drivers/hwtracing/coresight/coresight-etm4x-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/kernel.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/device.h>
  12 #include <linux/io.h>
  13 #include <linux/err.h>
  14 #include <linux/fs.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/smp.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/stat.h>
  20 #include <linux/clk.h>
  21 #include <linux/cpu.h>
  22 #include <linux/cpu_pm.h>
  23 #include <linux/coresight.h>
  24 #include <linux/coresight-pmu.h>
  25 #include <linux/pm_wakeup.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/perf_event.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/property.h>
  32
  33 #include <asm/sections.h>
  34 #include <asm/sysreg.h>
  35 #include <asm/local.h>
  36 #include <asm/virt.h>
  37
  38 #include "coresight-etm4x.h"
  39 #include "coresight-etm-perf.h"
  40
  41 static int boot_enable;
  42 module_param(boot_enable, int, 0444);
  43 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
  44
  45 #define PARAM_PM_SAVE_FIRMWARE    0 /* save self-hosted state as per firmware */
  46 #define PARAM_PM_SAVE_NEVER       1 /* never save any state */
  47 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
  48
  49 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
  50 module_param(pm_save_enable, int, 0444);
  51 MODULE_PARM_DESC(pm_save_enable,
  52         "Save/restore state on power down: 1 = never, 2 = self-hosted");
  53
  54 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  55 static void etm4_set_default_config(struct etmv4_config *config);
  56 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  57                                   struct perf_event *event);
  58 static u64 etm4_get_access_type(struct etmv4_config *config);
  59
  60 static enum cpuhp_state hp_online;
  61
  62 /*
  63  * Check if TRCSSPCICRn(i) is implemented for a given instance.
  64  *
  65  * TRCSSPCICRn is implemented only if :
  66  *      TRCSSPCICR<n> is present only if all of the following are true:
  67  *              TRCIDR4.NUMSSCC > n.
  68  *              TRCIDR4.NUMPC > 0b0000 .
  69  *              TRCSSCSR<n>.PC == 0b1
  70  */
  71 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
  72 {
  73         return (n < drvdata->nr_ss_cmp) &&
  74                drvdata->nr_pe &&
  75                (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
  76 }
  77
  78 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
  79 {
  80         u64 res = 0;
  81
  82         switch (offset) {
  83         ETM4x_READ_SYSREG_CASES(res)
  84         default :
  85                 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
  86                          offset);
  87         }
  88
  89         if (!_relaxed)
  90                 __iormb(res);   /* Imitate the !relaxed I/O helpers */
  91
  92         return res;
  93 }
  94
  95 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
  96 {
  97         if (!_relaxed)
  98                 __iowmb();      /* Imitate the !relaxed I/O helpers */
  99         if (!_64bit)
 100                 val &= GENMASK(31, 0);
 101
 102         switch (offset) {
 103         ETM4x_WRITE_SYSREG_CASES(val)
 104         default :
 105                 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
 106                         offset);
 107         }
 108 }
 109
 110 static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa)
 111 {
 112         /* Writing 0 to TRCOSLAR unlocks the trace registers */
 113         etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
 114         drvdata->os_unlock = true;
 115         isb();
 116 }
 117
 118 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
 119 {
 120         if (!WARN_ON(!drvdata->csdev))
 121                 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
 122
 123 }
 124
 125 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
 126 {
 127         if (WARN_ON(!drvdata->csdev))
 128                 return;
 129
 130         /* Writing 0x1 to TRCOSLAR locks the trace registers */
 131         etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
 132         drvdata->os_unlock = false;
 133         isb();
 134 }
 135
 136 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
 137                          struct csdev_access *csa)
 138 {
 139         /* Software Lock is only accessible via memory mapped interface */
 140         if (csa->io_mem)
 141                 CS_LOCK(csa->base);
 142 }
 143
 144 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
 145                            struct csdev_access *csa)
 146 {
 147         if (csa->io_mem)
 148                 CS_UNLOCK(csa->base);
 149 }
 150
 151 static bool etm4_arch_supported(u8 arch)
 152 {
 153         /* Mask out the minor version number */
 154         switch (arch & 0xf0) {
 155         case ETM_ARCH_V4:
 156                 break;
 157         default:
 158                 return false;
 159         }
 160         return true;
 161 }
 162
 163 static int etm4_cpu_id(struct coresight_device *csdev)
 164 {
 165         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 166
 167         return drvdata->cpu;
 168 }
 169
 170 static int etm4_trace_id(struct coresight_device *csdev)
 171 {
 172         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 173
 174         return drvdata->trcid;
 175 }
 176
 177 struct etm4_enable_arg {
 178         struct etmv4_drvdata *drvdata;
 179         int rc;
 180 };
 181
 182 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
 183
 184 #define HISI_HIP08_AMBA_ID              0x000b6d01
 185 #define ETM4_AMBA_MASK                  0xfffff
 186 #define HISI_HIP08_CORE_COMMIT_MASK     0x3000
 187 #define HISI_HIP08_CORE_COMMIT_SHIFT    12
 188 #define HISI_HIP08_CORE_COMMIT_FULL     0b00
 189 #define HISI_HIP08_CORE_COMMIT_LVL_1    0b01
 190 #define HISI_HIP08_CORE_COMMIT_REG      sys_reg(3, 1, 15, 2, 5)
 191
 192 struct etm4_arch_features {
 193         void (*arch_callback)(bool enable);
 194 };
 195
 196 static bool etm4_hisi_match_pid(unsigned int id)
 197 {
 198         return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
 199 }
 200
 201 static void etm4_hisi_config_core_commit(bool enable)
 202 {
 203         u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
 204                     HISI_HIP08_CORE_COMMIT_FULL;
 205         u64 val;
 206
 207         /*
 208          * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
 209          * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
 210          * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
 211          * speed(minimun value). So bit 12 and 13 should be cleared together.
 212          */
 213         val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
 214         val &= ~HISI_HIP08_CORE_COMMIT_MASK;
 215         val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
 216         write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
 217 }
 218
 219 static struct etm4_arch_features etm4_features[] = {
 220         [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
 221                 .arch_callback = etm4_hisi_config_core_commit,
 222         },
 223         {},
 224 };
 225
 226 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 227 {
 228         struct etm4_arch_features *ftr;
 229         int bit;
 230
 231         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 232                 ftr = &etm4_features[bit];
 233
 234                 if (ftr->arch_callback)
 235                         ftr->arch_callback(true);
 236         }
 237 }
 238
 239 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 240 {
 241         struct etm4_arch_features *ftr;
 242         int bit;
 243
 244         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 245                 ftr = &etm4_features[bit];
 246
 247                 if (ftr->arch_callback)
 248                         ftr->arch_callback(false);
 249         }
 250 }
 251
 252 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 253                                       unsigned int id)
 254 {
 255         if (etm4_hisi_match_pid(id))
 256                 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
 257 }
 258 #else
 259 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 260 {
 261 }
 262
 263 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 264 {
 265 }
 266
 267 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 268                                      unsigned int id)
 269 {
 270 }
 271 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
 272
 273 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 274 {
 275         int i, rc;
 276         struct etmv4_config *config = &drvdata->config;
 277         struct coresight_device *csdev = drvdata->csdev;
 278         struct device *etm_dev = &csdev->dev;
 279         struct csdev_access *csa = &csdev->access;
 280
 281
 282         etm4_cs_unlock(drvdata, csa);
 283         etm4_enable_arch_specific(drvdata);
 284
 285         etm4_os_unlock(drvdata);
 286
 287         rc = coresight_claim_device_unlocked(csdev);
 288         if (rc)
 289                 goto done;
 290
 291         /* Disable the trace unit before programming trace registers */
 292         etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
 293
 294         /* wait for TRCSTATR.IDLE to go up */
 295         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 296                 dev_err(etm_dev,
 297                         "timeout while waiting for Idle Trace Status\n");
 298         if (drvdata->nr_pe)
 299                 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
 300         etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
 301         /* nothing specific implemented */
 302         etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
 303         etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
 304         etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
 305         etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
 306         etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
 307         etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
 308         etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
 309         etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
 310         etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
 311         etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
 312         etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
 313         etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
 314         if (drvdata->nr_pe_cmp)
 315                 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
 316         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 317                 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
 318         etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
 319         etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
 320         etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
 321         for (i = 0; i < drvdata->nr_cntr; i++) {
 322                 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
 323                 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
 324                 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
 325         }
 326
 327         /*
 328          * Resource selector pair 0 is always implemented and reserved.  As
 329          * such start at 2.
 330          */
 331         for (i = 2; i < drvdata->nr_resource * 2; i++)
 332                 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
 333
 334         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 335                 /* always clear status bit on restart if using single-shot */
 336                 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
 337                         config->ss_status[i] &= ~BIT(31);
 338                 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
 339                 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
 340                 if (etm4x_sspcicrn_present(drvdata, i))
 341                         etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
 342         }
 343         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 344                 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
 345                 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
 346         }
 347         for (i = 0; i < drvdata->numcidc; i++)
 348                 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
 349         etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
 350         if (drvdata->numcidc > 4)
 351                 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
 352
 353         for (i = 0; i < drvdata->numvmidc; i++)
 354                 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
 355         etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
 356         if (drvdata->numvmidc > 4)
 357                 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
 358
 359         if (!drvdata->skip_power_up) {
 360                 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
 361
 362                 /*
 363                  * Request to keep the trace unit powered and also
 364                  * emulation of powerdown
 365                  */
 366                 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
 367         }
 368
 369         /* Enable the trace unit */
 370         etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
 371
 372         /* wait for TRCSTATR.IDLE to go back down to '0' */
 373         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 374                 dev_err(etm_dev,
 375                         "timeout while waiting for Idle Trace Status\n");
 376
 377         /*
 378          * As recommended by section 4.3.7 ("Synchronization when using the
 379          * memory-mapped interface") of ARM IHI 0064D
 380          */
 381         dsb(sy);
 382         isb();
 383
 384 done:
 385         etm4_cs_lock(drvdata, csa);
 386
 387         dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
 388                 drvdata->cpu, rc);
 389         return rc;
 390 }
 391
 392 static void etm4_enable_hw_smp_call(void *info)
 393 {
 394         struct etm4_enable_arg *arg = info;
 395
 396         if (WARN_ON(!arg))
 397                 return;
 398         arg->rc = etm4_enable_hw(arg->drvdata);
 399 }
 400
 401 /*
 402  * The goal of function etm4_config_timestamp_event() is to configure a
 403  * counter that will tell the tracer to emit a timestamp packet when it
 404  * reaches zero.  This is done in order to get a more fine grained idea
 405  * of when instructions are executed so that they can be correlated
 406  * with execution on other CPUs.
 407  *
 408  * To do this the counter itself is configured to self reload and
 409  * TRCRSCTLR1 (always true) used to get the counter to decrement.  From
 410  * there a resource selector is configured with the counter and the
 411  * timestamp control register to use the resource selector to trigger the
 412  * event that will insert a timestamp packet in the stream.
 413  */
 414 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
 415 {
 416         int ctridx, ret = -EINVAL;
 417         int counter, rselector;
 418         u32 val = 0;
 419         struct etmv4_config *config = &drvdata->config;
 420
 421         /* No point in trying if we don't have at least one counter */
 422         if (!drvdata->nr_cntr)
 423                 goto out;
 424
 425         /* Find a counter that hasn't been initialised */
 426         for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
 427                 if (config->cntr_val[ctridx] == 0)
 428                         break;
 429
 430         /* All the counters have been configured already, bail out */
 431         if (ctridx == drvdata->nr_cntr) {
 432                 pr_debug("%s: no available counter found\n", __func__);
 433                 ret = -ENOSPC;
 434                 goto out;
 435         }
 436
 437         /*
 438          * Searching for an available resource selector to use, starting at
 439          * '2' since every implementation has at least 2 resource selector.
 440          * ETMIDR4 gives the number of resource selector _pairs_,
 441          * hence multiply by 2.
 442          */
 443         for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
 444                 if (!config->res_ctrl[rselector])
 445                         break;
 446
 447         if (rselector == drvdata->nr_resource * 2) {
 448                 pr_debug("%s: no available resource selector found\n",
 449                          __func__);
 450                 ret = -ENOSPC;
 451                 goto out;
 452         }
 453
 454         /* Remember what counter we used */
 455         counter = 1 << ctridx;
 456
 457         /*
 458          * Initialise original and reload counter value to the smallest
 459          * possible value in order to get as much precision as we can.
 460          */
 461         config->cntr_val[ctridx] = 1;
 462         config->cntrldvr[ctridx] = 1;
 463
 464         /* Set the trace counter control register */
 465         val =  0x1 << 16        |  /* Bit 16, reload counter automatically */
 466                0x0 << 7         |  /* Select single resource selector */
 467                0x1;                /* Resource selector 1, i.e always true */
 468
 469         config->cntr_ctrl[ctridx] = val;
 470
 471         val = 0x2 << 16         | /* Group 0b0010 - Counter and sequencers */
 472               counter << 0;       /* Counter to use */
 473
 474         config->res_ctrl[rselector] = val;
 475
 476         val = 0x0 << 7          | /* Select single resource selector */
 477               rselector;          /* Resource selector */
 478
 479         config->ts_ctrl = val;
 480
 481         ret = 0;
 482 out:
 483         return ret;
 484 }
 485
 486 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
 487                                    struct perf_event *event)
 488 {
 489         int ret = 0;
 490         struct etmv4_config *config = &drvdata->config;
 491         struct perf_event_attr *attr = &event->attr;
 492
 493         if (!attr) {
 494                 ret = -EINVAL;
 495                 goto out;
 496         }
 497
 498         /* Clear configuration from previous run */
 499         memset(config, 0, sizeof(struct etmv4_config));
 500
 501         if (attr->exclude_kernel)
 502                 config->mode = ETM_MODE_EXCL_KERN;
 503
 504         if (attr->exclude_user)
 505                 config->mode = ETM_MODE_EXCL_USER;
 506
 507         /* Always start from the default config */
 508         etm4_set_default_config(config);
 509
 510         /* Configure filters specified on the perf cmd line, if any. */
 511         ret = etm4_set_event_filters(drvdata, event);
 512         if (ret)
 513                 goto out;
 514
 515         /* Go from generic option to ETMv4 specifics */
 516         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 517                 config->cfg |= BIT(4);
 518                 /* TRM: Must program this for cycacc to work */
 519                 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
 520         }
 521         if (attr->config & BIT(ETM_OPT_TS)) {
 522                 /*
 523                  * Configure timestamps to be emitted at regular intervals in
 524                  * order to correlate instructions executed on different CPUs
 525                  * (CPU-wide trace scenarios).
 526                  */
 527                 ret = etm4_config_timestamp_event(drvdata);
 528
 529                 /*
 530                  * No need to go further if timestamp intervals can't
 531                  * be configured.
 532                  */
 533                 if (ret)
 534                         goto out;
 535
 536                 /* bit[11], Global timestamp tracing bit */
 537                 config->cfg |= BIT(11);
 538         }
 539
 540         if (attr->config & BIT(ETM_OPT_CTXTID))
 541                 /* bit[6], Context ID tracing bit */
 542                 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
 543
 544         /* return stack - enable if selected and supported */
 545         if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
 546                 /* bit[12], Return stack enable bit */
 547                 config->cfg |= BIT(12);
 548
 549 out:
 550         return ret;
 551 }
 552
 553 static int etm4_enable_perf(struct coresight_device *csdev,
 554                             struct perf_event *event)
 555 {
 556         int ret = 0;
 557         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 558
 559         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 560                 ret = -EINVAL;
 561                 goto out;
 562         }
 563
 564         /* Configure the tracer based on the session's specifics */
 565         ret = etm4_parse_event_config(drvdata, event);
 566         if (ret)
 567                 goto out;
 568         /* And enable it */
 569         ret = etm4_enable_hw(drvdata);
 570
 571 out:
 572         return ret;
 573 }
 574
 575 static int etm4_enable_sysfs(struct coresight_device *csdev)
 576 {
 577         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 578         struct etm4_enable_arg arg = { };
 579         int ret;
 580
 581         spin_lock(&drvdata->spinlock);
 582
 583         /*
 584          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 585          * ensures that register writes occur when cpu is powered.
 586          */
 587         arg.drvdata = drvdata;
 588         ret = smp_call_function_single(drvdata->cpu,
 589                                        etm4_enable_hw_smp_call, &arg, 1);
 590         if (!ret)
 591                 ret = arg.rc;
 592         if (!ret)
 593                 drvdata->sticky_enable = true;
 594         spin_unlock(&drvdata->spinlock);
 595
 596         if (!ret)
 597                 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
 598         return ret;
 599 }
 600
 601 static int etm4_enable(struct coresight_device *csdev,
 602                        struct perf_event *event, u32 mode)
 603 {
 604         int ret;
 605         u32 val;
 606         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 607
 608         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 609
 610         /* Someone is already using the tracer */
 611         if (val)
 612                 return -EBUSY;
 613
 614         switch (mode) {
 615         case CS_MODE_SYSFS:
 616                 ret = etm4_enable_sysfs(csdev);
 617                 break;
 618         case CS_MODE_PERF:
 619                 ret = etm4_enable_perf(csdev, event);
 620                 break;
 621         default:
 622                 ret = -EINVAL;
 623         }
 624
 625         /* The tracer didn't start */
 626         if (ret)
 627                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 628
 629         return ret;
 630 }
 631
 632 static void etm4_disable_hw(void *info)
 633 {
 634         u32 control;
 635         struct etmv4_drvdata *drvdata = info;
 636         struct etmv4_config *config = &drvdata->config;
 637         struct coresight_device *csdev = drvdata->csdev;
 638         struct device *etm_dev = &csdev->dev;
 639         struct csdev_access *csa = &csdev->access;
 640         int i;
 641
 642         etm4_cs_unlock(drvdata, csa);
 643         etm4_disable_arch_specific(drvdata);
 644
 645         if (!drvdata->skip_power_up) {
 646                 /* power can be removed from the trace unit now */
 647                 control = etm4x_relaxed_read32(csa, TRCPDCR);
 648                 control &= ~TRCPDCR_PU;
 649                 etm4x_relaxed_write32(csa, control, TRCPDCR);
 650         }
 651
 652         control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
 653
 654         /* EN, bit[0] Trace unit enable bit */
 655         control &= ~0x1;
 656
 657         /*
 658          * Make sure everything completes before disabling, as recommended
 659          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 660          * SSTATUS") of ARM IHI 0064D
 661          */
 662         dsb(sy);
 663         isb();
 664         etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
 665
 666         /* wait for TRCSTATR.PMSTABLE to go to '1' */
 667         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
 668                 dev_err(etm_dev,
 669                         "timeout while waiting for PM stable Trace Status\n");
 670
 671         /* read the status of the single shot comparators */
 672         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 673                 config->ss_status[i] =
 674                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
 675         }
 676
 677         /* read back the current counter values */
 678         for (i = 0; i < drvdata->nr_cntr; i++) {
 679                 config->cntr_val[i] =
 680                         etm4x_relaxed_read32(csa, TRCCNTVRn(i));
 681         }
 682
 683         coresight_disclaim_device_unlocked(csdev);
 684         etm4_cs_lock(drvdata, csa);
 685
 686         dev_dbg(&drvdata->csdev->dev,
 687                 "cpu: %d disable smp call done\n", drvdata->cpu);
 688 }
 689
 690 static int etm4_disable_perf(struct coresight_device *csdev,
 691                              struct perf_event *event)
 692 {
 693         u32 control;
 694         struct etm_filters *filters = event->hw.addr_filters;
 695         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 696
 697         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 698                 return -EINVAL;
 699
 700         etm4_disable_hw(drvdata);
 701
 702         /*
 703          * Check if the start/stop logic was active when the unit was stopped.
 704          * That way we can re-enable the start/stop logic when the process is
 705          * scheduled again.  Configuration of the start/stop logic happens in
 706          * function etm4_set_event_filters().
 707          */
 708         control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
 709         /* TRCVICTLR::SSSTATUS, bit[9] */
 710         filters->ssstatus = (control & BIT(9));
 711
 712         return 0;
 713 }
 714
 715 static void etm4_disable_sysfs(struct coresight_device *csdev)
 716 {
 717         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 718
 719         /*
 720          * Taking hotplug lock here protects from clocks getting disabled
 721          * with tracing being left on (crash scenario) if user disable occurs
 722          * after cpu online mask indicates the cpu is offline but before the
 723          * DYING hotplug callback is serviced by the ETM driver.
 724          */
 725         cpus_read_lock();
 726         spin_lock(&drvdata->spinlock);
 727
 728         /*
 729          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 730          * ensures that register writes occur when cpu is powered.
 731          */
 732         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 733
 734         spin_unlock(&drvdata->spinlock);
 735         cpus_read_unlock();
 736
 737         dev_dbg(&csdev->dev, "ETM tracing disabled\n");
 738 }
 739
 740 static void etm4_disable(struct coresight_device *csdev,
 741                          struct perf_event *event)
 742 {
 743         u32 mode;
 744         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 745
 746         /*
 747          * For as long as the tracer isn't disabled another entity can't
 748          * change its status.  As such we can read the status here without
 749          * fearing it will change under us.
 750          */
 751         mode = local_read(&drvdata->mode);
 752
 753         switch (mode) {
 754         case CS_MODE_DISABLED:
 755                 break;
 756         case CS_MODE_SYSFS:
 757                 etm4_disable_sysfs(csdev);
 758                 break;
 759         case CS_MODE_PERF:
 760                 etm4_disable_perf(csdev, event);
 761                 break;
 762         }
 763
 764         if (mode)
 765                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 766 }
 767
 768 static const struct coresight_ops_source etm4_source_ops = {
 769         .cpu_id         = etm4_cpu_id,
 770         .trace_id       = etm4_trace_id,
 771         .enable         = etm4_enable,
 772         .disable        = etm4_disable,
 773 };
 774
 775 static const struct coresight_ops etm4_cs_ops = {
 776         .source_ops     = &etm4_source_ops,
 777 };
 778
 779 static void etm4_init_arch_data(void *info)
 780 {
 781         u32 etmidr0;
 782         u32 etmidr1;
 783         u32 etmidr2;
 784         u32 etmidr3;
 785         u32 etmidr4;
 786         u32 etmidr5;
 787         struct etmv4_drvdata *drvdata = info;
 788         struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
 789         struct csdev_access *csa = &tmp_csa;
 790         int i;
 791
 792         /* Make sure all registers are accessible */
 793         etm4_os_unlock_csa(drvdata, csa);
 794         etm4_cs_unlock(drvdata, csa);
 795
 796         /* find all capabilities of the tracing unit */
 797         etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
 798
 799         /* INSTP0, bits[2:1] P0 tracing support field */
 800         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 801                 drvdata->instrp0 = true;
 802         else
 803                 drvdata->instrp0 = false;
 804
 805         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 806         if (BMVAL(etmidr0, 5, 5))
 807                 drvdata->trcbb = true;
 808         else
 809                 drvdata->trcbb = false;
 810
 811         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 812         if (BMVAL(etmidr0, 6, 6))
 813                 drvdata->trccond = true;
 814         else
 815                 drvdata->trccond = false;
 816
 817         /* TRCCCI, bit[7] Cycle counting instruction bit */
 818         if (BMVAL(etmidr0, 7, 7))
 819                 drvdata->trccci = true;
 820         else
 821                 drvdata->trccci = false;
 822
 823         /* RETSTACK, bit[9] Return stack bit */
 824         if (BMVAL(etmidr0, 9, 9))
 825                 drvdata->retstack = true;
 826         else
 827                 drvdata->retstack = false;
 828
 829         /* NUMEVENT, bits[11:10] Number of events field */
 830         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 831         /* QSUPP, bits[16:15] Q element support field */
 832         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 833         /* TSSIZE, bits[28:24] Global timestamp size field */
 834         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 835
 836         /* base architecture of trace unit */
 837         etmidr1 = etm4x_relaxed_read32(csa, TRCIDR1);
 838         /*
 839          * TRCARCHMIN, bits[7:4] architecture the minor version number
 840          * TRCARCHMAJ, bits[11:8] architecture major versin number
 841          */
 842         drvdata->arch = BMVAL(etmidr1, 4, 11);
 843         drvdata->config.arch = drvdata->arch;
 844
 845         /* maximum size of resources */
 846         etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
 847         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 848         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 849         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 850         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 851         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 852         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 853
 854         etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
 855         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 856         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 857         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 858         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 859         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 860         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 861
 862         /*
 863          * TRCERR, bit[24] whether a trace unit can trace a
 864          * system error exception.
 865          */
 866         if (BMVAL(etmidr3, 24, 24))
 867                 drvdata->trc_error = true;
 868         else
 869                 drvdata->trc_error = false;
 870
 871         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 872         if (BMVAL(etmidr3, 25, 25))
 873                 drvdata->syncpr = true;
 874         else
 875                 drvdata->syncpr = false;
 876
 877         /* STALLCTL, bit[26] is stall control implemented? */
 878         if (BMVAL(etmidr3, 26, 26))
 879                 drvdata->stallctl = true;
 880         else
 881                 drvdata->stallctl = false;
 882
 883         /* SYSSTALL, bit[27] implementation can support stall control? */
 884         if (BMVAL(etmidr3, 27, 27))
 885                 drvdata->sysstall = true;
 886         else
 887                 drvdata->sysstall = false;
 888
 889         /*
 890          * NUMPROC - the number of PEs available for tracing, 5bits
 891          *         = TRCIDR3.bits[13:12]bits[30:28]
 892          *  bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
 893          *  bits[3:0] = TRCIDR3.bits[30:28]
 894          */
 895         drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30);
 896
 897         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 898         if (BMVAL(etmidr3, 31, 31))
 899                 drvdata->nooverflow = true;
 900         else
 901                 drvdata->nooverflow = false;
 902
 903         /* number of resources trace unit supports */
 904         etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
 905         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 906         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 907         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 908         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 909         /*
 910          * NUMRSPAIR, bits[19:16]
 911          * The number of resource pairs conveyed by the HW starts at 0, i.e a
 912          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
 913          * As such add 1 to the value of NUMRSPAIR for a better representation.
 914          *
 915          * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
 916          * the default TRUE and FALSE resource selectors are omitted.
 917          * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
 918          */
 919         drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
 920         if ((drvdata->arch < ETM4X_ARCH_4V3) || (drvdata->nr_resource > 0))
 921                 drvdata->nr_resource += 1;
 922         /*
 923          * NUMSSCC, bits[23:20] the number of single-shot
 924          * comparator control for tracing. Read any status regs as these
 925          * also contain RO capability data.
 926          */
 927         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 928         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 929                 drvdata->config.ss_status[i] =
 930                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
 931         }
 932         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 933         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 934         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 935         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 936
 937         etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
 938         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 939         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 940         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 941         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 942         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 943         if (BMVAL(etmidr5, 22, 22))
 944                 drvdata->atbtrig = true;
 945         else
 946                 drvdata->atbtrig = false;
 947         /*
 948          * LPOVERRIDE, bit[23] implementation supports
 949          * low-power state override
 950          */
 951         if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up))
 952                 drvdata->lpoverride = true;
 953         else
 954                 drvdata->lpoverride = false;
 955         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 956         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 957         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 958         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
 959         etm4_cs_lock(drvdata, csa);
 960 }
 961
 962 /* Set ELx trace filter access in the TRCVICTLR register */
 963 static void etm4_set_victlr_access(struct etmv4_config *config)
 964 {
 965         u64 access_type;
 966
 967         config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK | ETM_EXLEVEL_NS_VICTLR_MASK);
 968
 969         /*
 970          * TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering
 971          * bits in vinst_ctrl, same bit pattern as TRCACATRn values returned by
 972          * etm4_get_access_type() but with a relative shift in this register.
 973          */
 974         access_type = etm4_get_access_type(config) << ETM_EXLEVEL_LSHIFT_TRCVICTLR;
 975         config->vinst_ctrl |= (u32)access_type;
 976 }
 977
 978 static void etm4_set_default_config(struct etmv4_config *config)
 979 {
 980         /* disable all events tracing */
 981         config->eventctrl0 = 0x0;
 982         config->eventctrl1 = 0x0;
 983
 984         /* disable stalling */
 985         config->stall_ctrl = 0x0;
 986
 987         /* enable trace synchronization every 4096 bytes, if available */
 988         config->syncfreq = 0xC;
 989
 990         /* disable timestamp event */
 991         config->ts_ctrl = 0x0;
 992
 993         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
 994         config->vinst_ctrl = BIT(0);
 995
 996         /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
 997         etm4_set_victlr_access(config);
 998 }
 999
1000 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1001 {
1002         u64 access_type = 0;
1003
1004         /*
1005          * EXLEVEL_NS, bits[15:12]
1006          * The Exception levels are:
1007          *   Bit[12] Exception level 0 - Application
1008          *   Bit[13] Exception level 1 - OS
1009          *   Bit[14] Exception level 2 - Hypervisor
1010          *   Bit[15] Never implemented
1011          */
1012         if (!is_kernel_in_hyp_mode()) {
1013                 /* Stay away from hypervisor mode for non-VHE */
1014                 access_type =  ETM_EXLEVEL_NS_HYP;
1015                 if (config->mode & ETM_MODE_EXCL_KERN)
1016                         access_type |= ETM_EXLEVEL_NS_OS;
1017         } else if (config->mode & ETM_MODE_EXCL_KERN) {
1018                 access_type = ETM_EXLEVEL_NS_HYP;
1019         }
1020
1021         if (config->mode & ETM_MODE_EXCL_USER)
1022                 access_type |= ETM_EXLEVEL_NS_APP;
1023
1024         return access_type;
1025 }
1026
1027 static u64 etm4_get_access_type(struct etmv4_config *config)
1028 {
1029         u64 access_type = etm4_get_ns_access_type(config);
1030         u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
1031
1032         /*
1033          * EXLEVEL_S, bits[11:8], don't trace anything happening
1034          * in secure state.
1035          */
1036         access_type |= (ETM_EXLEVEL_S_APP       |
1037                         ETM_EXLEVEL_S_OS        |
1038                         s_hyp                   |
1039                         ETM_EXLEVEL_S_MON);
1040
1041         return access_type;
1042 }
1043
1044 static void etm4_set_comparator_filter(struct etmv4_config *config,
1045                                        u64 start, u64 stop, int comparator)
1046 {
1047         u64 access_type = etm4_get_access_type(config);
1048
1049         /* First half of default address comparator */
1050         config->addr_val[comparator] = start;
1051         config->addr_acc[comparator] = access_type;
1052         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1053
1054         /* Second half of default address comparator */
1055         config->addr_val[comparator + 1] = stop;
1056         config->addr_acc[comparator + 1] = access_type;
1057         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1058
1059         /*
1060          * Configure the ViewInst function to include this address range
1061          * comparator.
1062          *
1063          * @comparator is divided by two since it is the index in the
1064          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1065          * address range comparator _pairs_.
1066          *
1067          * Therefore:
1068          *      index 0 -> compatator pair 0
1069          *      index 2 -> comparator pair 1
1070          *      index 4 -> comparator pair 2
1071          *      ...
1072          *      index 14 -> comparator pair 7
1073          */
1074         config->viiectlr |= BIT(comparator / 2);
1075 }
1076
1077 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1078                                        u64 address, int comparator,
1079                                        enum etm_addr_type type)
1080 {
1081         int shift;
1082         u64 access_type = etm4_get_access_type(config);
1083
1084         /* Configure the comparator */
1085         config->addr_val[comparator] = address;
1086         config->addr_acc[comparator] = access_type;
1087         config->addr_type[comparator] = type;
1088
1089         /*
1090          * Configure ViewInst Start-Stop control register.
1091          * Addresses configured to start tracing go from bit 0 to n-1,
1092          * while those configured to stop tracing from 16 to 16 + n-1.
1093          */
1094         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1095         config->vissctlr |= BIT(shift + comparator);
1096 }
1097
1098 static void etm4_set_default_filter(struct etmv4_config *config)
1099 {
1100         /* Trace everything 'default' filter achieved by no filtering */
1101         config->viiectlr = 0x0;
1102
1103         /*
1104          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1105          * in the started state
1106          */
1107         config->vinst_ctrl |= BIT(9);
1108         config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1109
1110         /* No start-stop filtering for ViewInst */
1111         config->vissctlr = 0x0;
1112 }
1113
1114 static void etm4_set_default(struct etmv4_config *config)
1115 {
1116         if (WARN_ON_ONCE(!config))
1117                 return;
1118
1119         /*
1120          * Make default initialisation trace everything
1121          *
1122          * This is done by a minimum default config sufficient to enable
1123          * full instruction trace - with a default filter for trace all
1124          * achieved by having no filtering.
1125          */
1126         etm4_set_default_config(config);
1127         etm4_set_default_filter(config);
1128 }
1129
1130 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1131 {
1132         int nr_comparator, index = 0;
1133         struct etmv4_config *config = &drvdata->config;
1134
1135         /*
1136          * nr_addr_cmp holds the number of comparator _pair_, so time 2
1137          * for the total number of comparators.
1138          */
1139         nr_comparator = drvdata->nr_addr_cmp * 2;
1140
1141         /* Go through the tally of comparators looking for a free one. */
1142         while (index < nr_comparator) {
1143                 switch (type) {
1144                 case ETM_ADDR_TYPE_RANGE:
1145                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1146                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1147                                 return index;
1148
1149                         /* Address range comparators go in pairs */
1150                         index += 2;
1151                         break;
1152                 case ETM_ADDR_TYPE_START:
1153                 case ETM_ADDR_TYPE_STOP:
1154                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1155                                 return index;
1156
1157                         /* Start/stop address can have odd indexes */
1158                         index += 1;
1159                         break;
1160                 default:
1161                         return -EINVAL;
1162                 }
1163         }
1164
1165         /* If we are here all the comparators have been used. */
1166         return -ENOSPC;
1167 }
1168
1169 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1170                                   struct perf_event *event)
1171 {
1172         int i, comparator, ret = 0;
1173         u64 address;
1174         struct etmv4_config *config = &drvdata->config;
1175         struct etm_filters *filters = event->hw.addr_filters;
1176
1177         if (!filters)
1178                 goto default_filter;
1179
1180         /* Sync events with what Perf got */
1181         perf_event_addr_filters_sync(event);
1182
1183         /*
1184          * If there are no filters to deal with simply go ahead with
1185          * the default filter, i.e the entire address range.
1186          */
1187         if (!filters->nr_filters)
1188                 goto default_filter;
1189
1190         for (i = 0; i < filters->nr_filters; i++) {
1191                 struct etm_filter *filter = &filters->etm_filter[i];
1192                 enum etm_addr_type type = filter->type;
1193
1194                 /* See if a comparator is free. */
1195                 comparator = etm4_get_next_comparator(drvdata, type);
1196                 if (comparator < 0) {
1197                         ret = comparator;
1198                         goto out;
1199                 }
1200
1201                 switch (type) {
1202                 case ETM_ADDR_TYPE_RANGE:
1203                         etm4_set_comparator_filter(config,
1204                                                    filter->start_addr,
1205                                                    filter->stop_addr,
1206                                                    comparator);
1207                         /*
1208                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1209                          * in the started state
1210                          */
1211                         config->vinst_ctrl |= BIT(9);
1212
1213                         /* No start-stop filtering for ViewInst */
1214                         config->vissctlr = 0x0;
1215                         break;
1216                 case ETM_ADDR_TYPE_START:
1217                 case ETM_ADDR_TYPE_STOP:
1218                         /* Get the right start or stop address */
1219                         address = (type == ETM_ADDR_TYPE_START ?
1220                                    filter->start_addr :
1221                                    filter->stop_addr);
1222
1223                         /* Configure comparator */
1224                         etm4_set_start_stop_filter(config, address,
1225                                                    comparator, type);
1226
1227                         /*
1228                          * If filters::ssstatus == 1, trace acquisition was
1229                          * started but the process was yanked away before the
1230                          * the stop address was hit.  As such the start/stop
1231                          * logic needs to be re-started so that tracing can
1232                          * resume where it left.
1233                          *
1234                          * The start/stop logic status when a process is
1235                          * scheduled out is checked in function
1236                          * etm4_disable_perf().
1237                          */
1238                         if (filters->ssstatus)
1239                                 config->vinst_ctrl |= BIT(9);
1240
1241                         /* No include/exclude filtering for ViewInst */
1242                         config->viiectlr = 0x0;
1243                         break;
1244                 default:
1245                         ret = -EINVAL;
1246                         goto out;
1247                 }
1248         }
1249
1250         goto out;
1251
1252
1253 default_filter:
1254         etm4_set_default_filter(config);
1255
1256 out:
1257         return ret;
1258 }
1259
1260 void etm4_config_trace_mode(struct etmv4_config *config)
1261 {
1262         u32 mode;
1263
1264         mode = config->mode;
1265         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1266
1267         /* excluding kernel AND user space doesn't make sense */
1268         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1269
1270         /* nothing to do if neither flags are set */
1271         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1272                 return;
1273
1274         etm4_set_victlr_access(config);
1275 }
1276
1277 static int etm4_online_cpu(unsigned int cpu)
1278 {
1279         if (!etmdrvdata[cpu])
1280                 return 0;
1281
1282         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1283                 coresight_enable(etmdrvdata[cpu]->csdev);
1284         return 0;
1285 }
1286
1287 static int etm4_starting_cpu(unsigned int cpu)
1288 {
1289         if (!etmdrvdata[cpu])
1290                 return 0;
1291
1292         spin_lock(&etmdrvdata[cpu]->spinlock);
1293         if (!etmdrvdata[cpu]->os_unlock)
1294                 etm4_os_unlock(etmdrvdata[cpu]);
1295
1296         if (local_read(&etmdrvdata[cpu]->mode))
1297                 etm4_enable_hw(etmdrvdata[cpu]);
1298         spin_unlock(&etmdrvdata[cpu]->spinlock);
1299         return 0;
1300 }
1301
1302 static int etm4_dying_cpu(unsigned int cpu)
1303 {
1304         if (!etmdrvdata[cpu])
1305                 return 0;
1306
1307         spin_lock(&etmdrvdata[cpu]->spinlock);
1308         if (local_read(&etmdrvdata[cpu]->mode))
1309                 etm4_disable_hw(etmdrvdata[cpu]);
1310         spin_unlock(&etmdrvdata[cpu]->spinlock);
1311         return 0;
1312 }
1313
1314 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1315 {
1316         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1317 }
1318
1319 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1320 {
1321         int i, ret = 0;
1322         struct etmv4_save_state *state;
1323         struct coresight_device *csdev = drvdata->csdev;
1324         struct csdev_access *csa;
1325         struct device *etm_dev;
1326
1327         if (WARN_ON(!csdev))
1328                 return -ENODEV;
1329
1330         etm_dev = &csdev->dev;
1331         csa = &csdev->access;
1332
1333         /*
1334          * As recommended by 3.4.1 ("The procedure when powering down the PE")
1335          * of ARM IHI 0064D
1336          */
1337         dsb(sy);
1338         isb();
1339
1340         etm4_cs_unlock(drvdata, csa);
1341         /* Lock the OS lock to disable trace and external debugger access */
1342         etm4_os_lock(drvdata);
1343
1344         /* wait for TRCSTATR.PMSTABLE to go up */
1345         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1346                 dev_err(etm_dev,
1347                         "timeout while waiting for PM Stable Status\n");
1348                 etm4_os_unlock(drvdata);
1349                 ret = -EBUSY;
1350                 goto out;
1351         }
1352
1353         state = drvdata->save_state;
1354
1355         state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1356         if (drvdata->nr_pe)
1357                 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1358         state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1359         state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1360         state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1361         state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1362         state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1363         state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1364         state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1365         state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1366         state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1367         state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1368         state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1369
1370         state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1371         state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1372         state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1373         if (drvdata->nr_pe_cmp)
1374                 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1375         state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1376         state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1377         state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1378
1379         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1380                 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1381
1382         state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1383         state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1384         state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1385
1386         for (i = 0; i < drvdata->nr_cntr; i++) {
1387                 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1388                 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1389                 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1390         }
1391
1392         for (i = 0; i < drvdata->nr_resource * 2; i++)
1393                 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1394
1395         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1396                 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1397                 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1398                 if (etm4x_sspcicrn_present(drvdata, i))
1399                         state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1400         }
1401
1402         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1403                 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1404                 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1405         }
1406
1407         /*
1408          * Data trace stream is architecturally prohibited for A profile cores
1409          * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1410          * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1411          * unit") of ARM IHI 0064D.
1412          */
1413
1414         for (i = 0; i < drvdata->numcidc; i++)
1415                 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1416
1417         for (i = 0; i < drvdata->numvmidc; i++)
1418                 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1419
1420         state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1421         if (drvdata->numcidc > 4)
1422                 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1423
1424         state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1425         if (drvdata->numvmidc > 4)
1426                 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1427
1428         state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1429
1430         if (!drvdata->skip_power_up)
1431                 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1432
1433         /* wait for TRCSTATR.IDLE to go up */
1434         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1435                 dev_err(etm_dev,
1436                         "timeout while waiting for Idle Trace Status\n");
1437                 etm4_os_unlock(drvdata);
1438                 ret = -EBUSY;
1439                 goto out;
1440         }
1441
1442         drvdata->state_needs_restore = true;
1443
1444         /*
1445          * Power can be removed from the trace unit now. We do this to
1446          * potentially save power on systems that respect the TRCPDCR_PU
1447          * despite requesting software to save/restore state.
1448          */
1449         if (!drvdata->skip_power_up)
1450                 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1451                                       TRCPDCR);
1452 out:
1453         etm4_cs_lock(drvdata, csa);
1454         return ret;
1455 }
1456
1457 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1458 {
1459         int i;
1460         struct etmv4_save_state *state = drvdata->save_state;
1461         struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1462         struct csdev_access *csa = &tmp_csa;
1463
1464         etm4_cs_unlock(drvdata, csa);
1465         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1466
1467         etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1468         if (drvdata->nr_pe)
1469                 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1470         etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1471         etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1472         etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1473         etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1474         etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1475         etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1476         etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1477         etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1478         etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1479         etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1480         etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1481
1482         etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1483         etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1484         etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1485         if (drvdata->nr_pe_cmp)
1486                 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1487         etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1488         etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1489         etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1490
1491         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1492                 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1493
1494         etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1495         etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1496         etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1497
1498         for (i = 0; i < drvdata->nr_cntr; i++) {
1499                 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1500                 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1501                 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1502         }
1503
1504         for (i = 0; i < drvdata->nr_resource * 2; i++)
1505                 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1506
1507         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1508                 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1509                 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1510                 if (etm4x_sspcicrn_present(drvdata, i))
1511                         etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1512         }
1513
1514         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1515                 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1516                 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1517         }
1518
1519         for (i = 0; i < drvdata->numcidc; i++)
1520                 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1521
1522         for (i = 0; i < drvdata->numvmidc; i++)
1523                 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1524
1525         etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1526         if (drvdata->numcidc > 4)
1527                 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1528
1529         etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1530         if (drvdata->numvmidc > 4)
1531                 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1532
1533         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1534
1535         if (!drvdata->skip_power_up)
1536                 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1537
1538         drvdata->state_needs_restore = false;
1539
1540         /*
1541          * As recommended by section 4.3.7 ("Synchronization when using the
1542          * memory-mapped interface") of ARM IHI 0064D
1543          */
1544         dsb(sy);
1545         isb();
1546
1547         /* Unlock the OS lock to re-enable trace and external debug access */
1548         etm4_os_unlock(drvdata);
1549         etm4_cs_lock(drvdata, csa);
1550 }
1551
1552 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1553                               void *v)
1554 {
1555         struct etmv4_drvdata *drvdata;
1556         unsigned int cpu = smp_processor_id();
1557
1558         if (!etmdrvdata[cpu])
1559                 return NOTIFY_OK;
1560
1561         drvdata = etmdrvdata[cpu];
1562
1563         if (!drvdata->save_state)
1564                 return NOTIFY_OK;
1565
1566         if (WARN_ON_ONCE(drvdata->cpu != cpu))
1567                 return NOTIFY_BAD;
1568
1569         switch (cmd) {
1570         case CPU_PM_ENTER:
1571                 /* save the state if self-hosted coresight is in use */
1572                 if (local_read(&drvdata->mode))
1573                         if (etm4_cpu_save(drvdata))
1574                                 return NOTIFY_BAD;
1575                 break;
1576         case CPU_PM_EXIT:
1577         case CPU_PM_ENTER_FAILED:
1578                 if (drvdata->state_needs_restore)
1579                         etm4_cpu_restore(drvdata);
1580                 break;
1581         default:
1582                 return NOTIFY_DONE;
1583         }
1584
1585         return NOTIFY_OK;
1586 }
1587
1588 static struct notifier_block etm4_cpu_pm_nb = {
1589         .notifier_call = etm4_cpu_pm_notify,
1590 };
1591
1592 /* Setup PM. Deals with error conditions and counts */
1593 static int __init etm4_pm_setup(void)
1594 {
1595         int ret;
1596
1597         ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1598         if (ret)
1599                 return ret;
1600
1601         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1602                                         "arm/coresight4:starting",
1603                                         etm4_starting_cpu, etm4_dying_cpu);
1604
1605         if (ret)
1606                 goto unregister_notifier;
1607
1608         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1609                                         "arm/coresight4:online",
1610                                         etm4_online_cpu, NULL);
1611
1612         /* HP dyn state ID returned in ret on success */
1613         if (ret > 0) {
1614                 hp_online = ret;
1615                 return 0;
1616         }
1617
1618         /* failed dyn state - remove others */
1619         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1620
1621 unregister_notifier:
1622         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1623         return ret;
1624 }
1625
1626 static void etm4_pm_clear(void)
1627 {
1628         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1629         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1630         if (hp_online) {
1631                 cpuhp_remove_state_nocalls(hp_online);
1632                 hp_online = 0;
1633         }
1634 }
1635
1636 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
1637 {
1638         int ret;
1639         void __iomem *base;
1640         struct device *dev = &adev->dev;
1641         struct coresight_platform_data *pdata = NULL;
1642         struct etmv4_drvdata *drvdata;
1643         struct resource *res = &adev->res;
1644         struct coresight_desc desc = { 0 };
1645
1646         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1647         if (!drvdata)
1648                 return -ENOMEM;
1649
1650         dev_set_drvdata(dev, drvdata);
1651
1652         if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1653                 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1654                                PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1655
1656         if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1657                 drvdata->save_state = devm_kmalloc(dev,
1658                                 sizeof(struct etmv4_save_state), GFP_KERNEL);
1659                 if (!drvdata->save_state)
1660                         return -ENOMEM;
1661         }
1662
1663         if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1664                 drvdata->skip_power_up = true;
1665
1666         /* Validity for the resource is already checked by the AMBA core */
1667         base = devm_ioremap_resource(dev, res);
1668         if (IS_ERR(base))
1669                 return PTR_ERR(base);
1670
1671         drvdata->base = base;
1672         desc.access = CSDEV_ACCESS_IOMEM(base);
1673
1674         spin_lock_init(&drvdata->spinlock);
1675
1676         drvdata->cpu = coresight_get_cpu(dev);
1677         if (drvdata->cpu < 0)
1678                 return drvdata->cpu;
1679
1680         desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
1681         if (!desc.name)
1682                 return -ENOMEM;
1683
1684         if (smp_call_function_single(drvdata->cpu,
1685                                 etm4_init_arch_data,  drvdata, 1))
1686                 dev_err(dev, "ETM arch init failed\n");
1687
1688         if (etm4_arch_supported(drvdata->arch) == false)
1689                 return -EINVAL;
1690
1691         etm4_init_trace_id(drvdata);
1692         etm4_set_default(&drvdata->config);
1693
1694         pdata = coresight_get_platform_data(dev);
1695         if (IS_ERR(pdata))
1696                 return PTR_ERR(pdata);
1697
1698         adev->dev.platform_data = pdata;
1699
1700         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1701         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1702         desc.ops = &etm4_cs_ops;
1703         desc.pdata = pdata;
1704         desc.dev = dev;
1705         desc.groups = coresight_etmv4_groups;
1706         drvdata->csdev = coresight_register(&desc);
1707         if (IS_ERR(drvdata->csdev))
1708                 return PTR_ERR(drvdata->csdev);
1709
1710         ret = etm_perf_symlink(drvdata->csdev, true);
1711         if (ret) {
1712                 coresight_unregister(drvdata->csdev);
1713                 return ret;
1714         }
1715
1716         etmdrvdata[drvdata->cpu] = drvdata;
1717
1718         pm_runtime_put(&adev->dev);
1719         dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
1720                  drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
1721
1722         if (boot_enable) {
1723                 coresight_enable(drvdata->csdev);
1724                 drvdata->boot_enable = true;
1725         }
1726
1727         etm4_check_arch_features(drvdata, id->id);
1728
1729         return 0;
1730 }
1731
1732 static struct amba_cs_uci_id uci_id_etm4[] = {
1733         {
1734                 /*  ETMv4 UCI data */
1735                 .devarch        = ETM_DEVARCH_ETMv4x_ARCH,
1736                 .devarch_mask   = ETM_DEVARCH_ID_MASK,
1737                 .devtype        = 0x00000013,
1738         }
1739 };
1740
1741 static void clear_etmdrvdata(void *info)
1742 {
1743         int cpu = *(int *)info;
1744
1745         etmdrvdata[cpu] = NULL;
1746 }
1747
1748 static int etm4_remove(struct amba_device *adev)
1749 {
1750         struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
1751
1752         etm_perf_symlink(drvdata->csdev, false);
1753
1754         /*
1755          * Taking hotplug lock here to avoid racing between etm4_remove and
1756          * CPU hotplug call backs.
1757          */
1758         cpus_read_lock();
1759         /*
1760          * The readers for etmdrvdata[] are CPU hotplug call backs
1761          * and PM notification call backs. Change etmdrvdata[i] on
1762          * CPU i ensures these call backs has consistent view
1763          * inside one call back function.
1764          */
1765         if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
1766                 etmdrvdata[drvdata->cpu] = NULL;
1767
1768         cpus_read_unlock();
1769
1770         coresight_unregister(drvdata->csdev);
1771
1772         return 0;
1773 }
1774
1775 static const struct amba_id etm4_ids[] = {
1776         CS_AMBA_ID(0x000bb95d),                 /* Cortex-A53 */
1777         CS_AMBA_ID(0x000bb95e),                 /* Cortex-A57 */
1778         CS_AMBA_ID(0x000bb95a),                 /* Cortex-A72 */
1779         CS_AMBA_ID(0x000bb959),                 /* Cortex-A73 */
1780         CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
1781         CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
1782         CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
1783         CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
1784         CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
1785         CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
1786         CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
1787         CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
1788         CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
1789         CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
1790         CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
1791         CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
1792         CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
1793         {},
1794 };
1795
1796 MODULE_DEVICE_TABLE(amba, etm4_ids);
1797
1798 static struct amba_driver etm4x_driver = {
1799         .drv = {
1800                 .name   = "coresight-etm4x",
1801                 .owner  = THIS_MODULE,
1802                 .suppress_bind_attrs = true,
1803         },
1804         .probe          = etm4_probe,
1805         .remove         = etm4_remove,
1806         .id_table       = etm4_ids,
1807 };
1808
1809 static int __init etm4x_init(void)
1810 {
1811         int ret;
1812
1813         ret = etm4_pm_setup();
1814
1815         /* etm4_pm_setup() does its own cleanup - exit on error */
1816         if (ret)
1817                 return ret;
1818
1819         ret = amba_driver_register(&etm4x_driver);
1820         if (ret) {
1821                 pr_err("Error registering etm4x driver\n");
1822                 etm4_pm_clear();
1823         }
1824
1825         return ret;
1826 }
1827
1828 static void __exit etm4x_exit(void)
1829 {
1830         amba_driver_unregister(&etm4x_driver);
1831         etm4_pm_clear();
1832 }
1833
1834 module_init(etm4x_init);
1835 module_exit(etm4x_exit);
1836
1837 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1838 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
1839 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
1840 MODULE_LICENSE("GPL v2");