1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
6 #include <linux/bitops.h>
7 #include <linux/kernel.h>
8 #include <linux/moduleparam.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/device.h>
13 #include <linux/err.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/smp.h>
18 #include <linux/sysfs.h>
19 #include <linux/stat.h>
20 #include <linux/clk.h>
21 #include <linux/cpu.h>
22 #include <linux/cpu_pm.h>
23 #include <linux/coresight.h>
24 #include <linux/coresight-pmu.h>
25 #include <linux/pm_wakeup.h>
26 #include <linux/amba/bus.h>
27 #include <linux/seq_file.h>
28 #include <linux/uaccess.h>
29 #include <linux/perf_event.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/property.h>
33 #include <asm/sections.h>
34 #include <asm/sysreg.h>
35 #include <asm/local.h>
38 #include "coresight-etm4x.h"
39 #include "coresight-etm-perf.h"
41 static int boot_enable;
42 module_param(boot_enable, int, 0444);
43 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
45 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
46 #define PARAM_PM_SAVE_NEVER 1 /* never save any state */
47 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
49 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
50 module_param(pm_save_enable, int, 0444);
51 MODULE_PARM_DESC(pm_save_enable,
52 "Save/restore state on power down: 1 = never, 2 = self-hosted");
54 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
55 static void etm4_set_default_config(struct etmv4_config *config);
56 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
57 struct perf_event *event);
58 static u64 etm4_get_access_type(struct etmv4_config *config);
60 static enum cpuhp_state hp_online;
63 * Check if TRCSSPCICRn(i) is implemented for a given instance.
65 * TRCSSPCICRn is implemented only if :
66 * TRCSSPCICR<n> is present only if all of the following are true:
67 * TRCIDR4.NUMSSCC > n.
68 * TRCIDR4.NUMPC > 0b0000 .
69 * TRCSSCSR<n>.PC == 0b1
71 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
73 return (n < drvdata->nr_ss_cmp) &&
75 (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
78 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
83 ETM4x_READ_SYSREG_CASES(res)
85 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
90 __iormb(res); /* Imitate the !relaxed I/O helpers */
95 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
98 __iowmb(); /* Imitate the !relaxed I/O helpers */
100 val &= GENMASK(31, 0);
103 ETM4x_WRITE_SYSREG_CASES(val)
105 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
110 static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa)
112 /* Writing 0 to TRCOSLAR unlocks the trace registers */
113 etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
114 drvdata->os_unlock = true;
118 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
120 if (!WARN_ON(!drvdata->csdev))
121 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
125 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
127 if (WARN_ON(!drvdata->csdev))
130 /* Writing 0x1 to TRCOSLAR locks the trace registers */
131 etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
132 drvdata->os_unlock = false;
136 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
137 struct csdev_access *csa)
139 /* Software Lock is only accessible via memory mapped interface */
144 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
145 struct csdev_access *csa)
148 CS_UNLOCK(csa->base);
151 static bool etm4_arch_supported(u8 arch)
153 /* Mask out the minor version number */
154 switch (arch & 0xf0) {
163 static int etm4_cpu_id(struct coresight_device *csdev)
165 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
170 static int etm4_trace_id(struct coresight_device *csdev)
172 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
174 return drvdata->trcid;
177 struct etm4_enable_arg {
178 struct etmv4_drvdata *drvdata;
182 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
184 #define HISI_HIP08_AMBA_ID 0x000b6d01
185 #define ETM4_AMBA_MASK 0xfffff
186 #define HISI_HIP08_CORE_COMMIT_MASK 0x3000
187 #define HISI_HIP08_CORE_COMMIT_SHIFT 12
188 #define HISI_HIP08_CORE_COMMIT_FULL 0b00
189 #define HISI_HIP08_CORE_COMMIT_LVL_1 0b01
190 #define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5)
192 struct etm4_arch_features {
193 void (*arch_callback)(bool enable);
196 static bool etm4_hisi_match_pid(unsigned int id)
198 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
201 static void etm4_hisi_config_core_commit(bool enable)
203 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
204 HISI_HIP08_CORE_COMMIT_FULL;
208 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
209 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
210 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
211 * speed(minimun value). So bit 12 and 13 should be cleared together.
213 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
214 val &= ~HISI_HIP08_CORE_COMMIT_MASK;
215 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
216 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
219 static struct etm4_arch_features etm4_features[] = {
220 [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
221 .arch_callback = etm4_hisi_config_core_commit,
226 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
228 struct etm4_arch_features *ftr;
231 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
232 ftr = &etm4_features[bit];
234 if (ftr->arch_callback)
235 ftr->arch_callback(true);
239 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
241 struct etm4_arch_features *ftr;
244 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
245 ftr = &etm4_features[bit];
247 if (ftr->arch_callback)
248 ftr->arch_callback(false);
252 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
255 if (etm4_hisi_match_pid(id))
256 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
259 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
263 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
267 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
271 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
273 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
276 struct etmv4_config *config = &drvdata->config;
277 struct coresight_device *csdev = drvdata->csdev;
278 struct device *etm_dev = &csdev->dev;
279 struct csdev_access *csa = &csdev->access;
282 etm4_cs_unlock(drvdata, csa);
283 etm4_enable_arch_specific(drvdata);
285 etm4_os_unlock(drvdata);
287 rc = coresight_claim_device_unlocked(csdev);
291 /* Disable the trace unit before programming trace registers */
292 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
294 /* wait for TRCSTATR.IDLE to go up */
295 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
297 "timeout while waiting for Idle Trace Status\n");
299 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
300 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
301 /* nothing specific implemented */
302 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
303 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
304 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
305 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
306 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
307 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
308 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
309 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
310 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
311 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
312 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
313 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
314 if (drvdata->nr_pe_cmp)
315 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
316 for (i = 0; i < drvdata->nrseqstate - 1; i++)
317 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
318 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
319 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
320 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
321 for (i = 0; i < drvdata->nr_cntr; i++) {
322 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
323 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
324 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
328 * Resource selector pair 0 is always implemented and reserved. As
331 for (i = 2; i < drvdata->nr_resource * 2; i++)
332 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
334 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
335 /* always clear status bit on restart if using single-shot */
336 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
337 config->ss_status[i] &= ~BIT(31);
338 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
339 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
340 if (etm4x_sspcicrn_present(drvdata, i))
341 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
343 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
344 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
345 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
347 for (i = 0; i < drvdata->numcidc; i++)
348 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
349 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
350 if (drvdata->numcidc > 4)
351 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
353 for (i = 0; i < drvdata->numvmidc; i++)
354 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
355 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
356 if (drvdata->numvmidc > 4)
357 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
359 if (!drvdata->skip_power_up) {
360 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
363 * Request to keep the trace unit powered and also
364 * emulation of powerdown
366 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
369 /* Enable the trace unit */
370 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
372 /* wait for TRCSTATR.IDLE to go back down to '0' */
373 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
375 "timeout while waiting for Idle Trace Status\n");
378 * As recommended by section 4.3.7 ("Synchronization when using the
379 * memory-mapped interface") of ARM IHI 0064D
385 etm4_cs_lock(drvdata, csa);
387 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
392 static void etm4_enable_hw_smp_call(void *info)
394 struct etm4_enable_arg *arg = info;
398 arg->rc = etm4_enable_hw(arg->drvdata);
402 * The goal of function etm4_config_timestamp_event() is to configure a
403 * counter that will tell the tracer to emit a timestamp packet when it
404 * reaches zero. This is done in order to get a more fine grained idea
405 * of when instructions are executed so that they can be correlated
406 * with execution on other CPUs.
408 * To do this the counter itself is configured to self reload and
409 * TRCRSCTLR1 (always true) used to get the counter to decrement. From
410 * there a resource selector is configured with the counter and the
411 * timestamp control register to use the resource selector to trigger the
412 * event that will insert a timestamp packet in the stream.
414 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
416 int ctridx, ret = -EINVAL;
417 int counter, rselector;
419 struct etmv4_config *config = &drvdata->config;
421 /* No point in trying if we don't have at least one counter */
422 if (!drvdata->nr_cntr)
425 /* Find a counter that hasn't been initialised */
426 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
427 if (config->cntr_val[ctridx] == 0)
430 /* All the counters have been configured already, bail out */
431 if (ctridx == drvdata->nr_cntr) {
432 pr_debug("%s: no available counter found\n", __func__);
438 * Searching for an available resource selector to use, starting at
439 * '2' since every implementation has at least 2 resource selector.
440 * ETMIDR4 gives the number of resource selector _pairs_,
441 * hence multiply by 2.
443 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
444 if (!config->res_ctrl[rselector])
447 if (rselector == drvdata->nr_resource * 2) {
448 pr_debug("%s: no available resource selector found\n",
454 /* Remember what counter we used */
455 counter = 1 << ctridx;
458 * Initialise original and reload counter value to the smallest
459 * possible value in order to get as much precision as we can.
461 config->cntr_val[ctridx] = 1;
462 config->cntrldvr[ctridx] = 1;
464 /* Set the trace counter control register */
465 val = 0x1 << 16 | /* Bit 16, reload counter automatically */
466 0x0 << 7 | /* Select single resource selector */
467 0x1; /* Resource selector 1, i.e always true */
469 config->cntr_ctrl[ctridx] = val;
471 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */
472 counter << 0; /* Counter to use */
474 config->res_ctrl[rselector] = val;
476 val = 0x0 << 7 | /* Select single resource selector */
477 rselector; /* Resource selector */
479 config->ts_ctrl = val;
486 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
487 struct perf_event *event)
490 struct etmv4_config *config = &drvdata->config;
491 struct perf_event_attr *attr = &event->attr;
498 /* Clear configuration from previous run */
499 memset(config, 0, sizeof(struct etmv4_config));
501 if (attr->exclude_kernel)
502 config->mode = ETM_MODE_EXCL_KERN;
504 if (attr->exclude_user)
505 config->mode = ETM_MODE_EXCL_USER;
507 /* Always start from the default config */
508 etm4_set_default_config(config);
510 /* Configure filters specified on the perf cmd line, if any. */
511 ret = etm4_set_event_filters(drvdata, event);
515 /* Go from generic option to ETMv4 specifics */
516 if (attr->config & BIT(ETM_OPT_CYCACC)) {
517 config->cfg |= BIT(4);
518 /* TRM: Must program this for cycacc to work */
519 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
521 if (attr->config & BIT(ETM_OPT_TS)) {
523 * Configure timestamps to be emitted at regular intervals in
524 * order to correlate instructions executed on different CPUs
525 * (CPU-wide trace scenarios).
527 ret = etm4_config_timestamp_event(drvdata);
530 * No need to go further if timestamp intervals can't
536 /* bit[11], Global timestamp tracing bit */
537 config->cfg |= BIT(11);
540 if (attr->config & BIT(ETM_OPT_CTXTID))
541 /* bit[6], Context ID tracing bit */
542 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
544 /* return stack - enable if selected and supported */
545 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
546 /* bit[12], Return stack enable bit */
547 config->cfg |= BIT(12);
553 static int etm4_enable_perf(struct coresight_device *csdev,
554 struct perf_event *event)
557 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
559 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
564 /* Configure the tracer based on the session's specifics */
565 ret = etm4_parse_event_config(drvdata, event);
569 ret = etm4_enable_hw(drvdata);
575 static int etm4_enable_sysfs(struct coresight_device *csdev)
577 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
578 struct etm4_enable_arg arg = { };
581 spin_lock(&drvdata->spinlock);
584 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
585 * ensures that register writes occur when cpu is powered.
587 arg.drvdata = drvdata;
588 ret = smp_call_function_single(drvdata->cpu,
589 etm4_enable_hw_smp_call, &arg, 1);
593 drvdata->sticky_enable = true;
594 spin_unlock(&drvdata->spinlock);
597 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
601 static int etm4_enable(struct coresight_device *csdev,
602 struct perf_event *event, u32 mode)
606 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
608 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
610 /* Someone is already using the tracer */
616 ret = etm4_enable_sysfs(csdev);
619 ret = etm4_enable_perf(csdev, event);
625 /* The tracer didn't start */
627 local_set(&drvdata->mode, CS_MODE_DISABLED);
632 static void etm4_disable_hw(void *info)
635 struct etmv4_drvdata *drvdata = info;
636 struct etmv4_config *config = &drvdata->config;
637 struct coresight_device *csdev = drvdata->csdev;
638 struct device *etm_dev = &csdev->dev;
639 struct csdev_access *csa = &csdev->access;
642 etm4_cs_unlock(drvdata, csa);
643 etm4_disable_arch_specific(drvdata);
645 if (!drvdata->skip_power_up) {
646 /* power can be removed from the trace unit now */
647 control = etm4x_relaxed_read32(csa, TRCPDCR);
648 control &= ~TRCPDCR_PU;
649 etm4x_relaxed_write32(csa, control, TRCPDCR);
652 control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
654 /* EN, bit[0] Trace unit enable bit */
658 * Make sure everything completes before disabling, as recommended
659 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
660 * SSTATUS") of ARM IHI 0064D
664 etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
666 /* wait for TRCSTATR.PMSTABLE to go to '1' */
667 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
669 "timeout while waiting for PM stable Trace Status\n");
671 /* read the status of the single shot comparators */
672 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
673 config->ss_status[i] =
674 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
677 /* read back the current counter values */
678 for (i = 0; i < drvdata->nr_cntr; i++) {
679 config->cntr_val[i] =
680 etm4x_relaxed_read32(csa, TRCCNTVRn(i));
683 coresight_disclaim_device_unlocked(csdev);
684 etm4_cs_lock(drvdata, csa);
686 dev_dbg(&drvdata->csdev->dev,
687 "cpu: %d disable smp call done\n", drvdata->cpu);
690 static int etm4_disable_perf(struct coresight_device *csdev,
691 struct perf_event *event)
694 struct etm_filters *filters = event->hw.addr_filters;
695 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
697 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
700 etm4_disable_hw(drvdata);
703 * Check if the start/stop logic was active when the unit was stopped.
704 * That way we can re-enable the start/stop logic when the process is
705 * scheduled again. Configuration of the start/stop logic happens in
706 * function etm4_set_event_filters().
708 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
709 /* TRCVICTLR::SSSTATUS, bit[9] */
710 filters->ssstatus = (control & BIT(9));
715 static void etm4_disable_sysfs(struct coresight_device *csdev)
717 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
720 * Taking hotplug lock here protects from clocks getting disabled
721 * with tracing being left on (crash scenario) if user disable occurs
722 * after cpu online mask indicates the cpu is offline but before the
723 * DYING hotplug callback is serviced by the ETM driver.
726 spin_lock(&drvdata->spinlock);
729 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
730 * ensures that register writes occur when cpu is powered.
732 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
734 spin_unlock(&drvdata->spinlock);
737 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
740 static void etm4_disable(struct coresight_device *csdev,
741 struct perf_event *event)
744 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
747 * For as long as the tracer isn't disabled another entity can't
748 * change its status. As such we can read the status here without
749 * fearing it will change under us.
751 mode = local_read(&drvdata->mode);
754 case CS_MODE_DISABLED:
757 etm4_disable_sysfs(csdev);
760 etm4_disable_perf(csdev, event);
765 local_set(&drvdata->mode, CS_MODE_DISABLED);
768 static const struct coresight_ops_source etm4_source_ops = {
769 .cpu_id = etm4_cpu_id,
770 .trace_id = etm4_trace_id,
771 .enable = etm4_enable,
772 .disable = etm4_disable,
775 static const struct coresight_ops etm4_cs_ops = {
776 .source_ops = &etm4_source_ops,
779 static void etm4_init_arch_data(void *info)
787 struct etmv4_drvdata *drvdata = info;
788 struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
789 struct csdev_access *csa = &tmp_csa;
792 /* Make sure all registers are accessible */
793 etm4_os_unlock_csa(drvdata, csa);
794 etm4_cs_unlock(drvdata, csa);
796 /* find all capabilities of the tracing unit */
797 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
799 /* INSTP0, bits[2:1] P0 tracing support field */
800 if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
801 drvdata->instrp0 = true;
803 drvdata->instrp0 = false;
805 /* TRCBB, bit[5] Branch broadcast tracing support bit */
806 if (BMVAL(etmidr0, 5, 5))
807 drvdata->trcbb = true;
809 drvdata->trcbb = false;
811 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
812 if (BMVAL(etmidr0, 6, 6))
813 drvdata->trccond = true;
815 drvdata->trccond = false;
817 /* TRCCCI, bit[7] Cycle counting instruction bit */
818 if (BMVAL(etmidr0, 7, 7))
819 drvdata->trccci = true;
821 drvdata->trccci = false;
823 /* RETSTACK, bit[9] Return stack bit */
824 if (BMVAL(etmidr0, 9, 9))
825 drvdata->retstack = true;
827 drvdata->retstack = false;
829 /* NUMEVENT, bits[11:10] Number of events field */
830 drvdata->nr_event = BMVAL(etmidr0, 10, 11);
831 /* QSUPP, bits[16:15] Q element support field */
832 drvdata->q_support = BMVAL(etmidr0, 15, 16);
833 /* TSSIZE, bits[28:24] Global timestamp size field */
834 drvdata->ts_size = BMVAL(etmidr0, 24, 28);
836 /* base architecture of trace unit */
837 etmidr1 = etm4x_relaxed_read32(csa, TRCIDR1);
839 * TRCARCHMIN, bits[7:4] architecture the minor version number
840 * TRCARCHMAJ, bits[11:8] architecture major versin number
842 drvdata->arch = BMVAL(etmidr1, 4, 11);
844 /* maximum size of resources */
845 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
846 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
847 drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
848 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
849 drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
850 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
851 drvdata->ccsize = BMVAL(etmidr2, 25, 28);
853 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
854 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
855 drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
856 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
857 drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
858 drvdata->config.s_ex_level = drvdata->s_ex_level;
859 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
860 drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
863 * TRCERR, bit[24] whether a trace unit can trace a
864 * system error exception.
866 if (BMVAL(etmidr3, 24, 24))
867 drvdata->trc_error = true;
869 drvdata->trc_error = false;
871 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
872 if (BMVAL(etmidr3, 25, 25))
873 drvdata->syncpr = true;
875 drvdata->syncpr = false;
877 /* STALLCTL, bit[26] is stall control implemented? */
878 if (BMVAL(etmidr3, 26, 26))
879 drvdata->stallctl = true;
881 drvdata->stallctl = false;
883 /* SYSSTALL, bit[27] implementation can support stall control? */
884 if (BMVAL(etmidr3, 27, 27))
885 drvdata->sysstall = true;
887 drvdata->sysstall = false;
890 * NUMPROC - the number of PEs available for tracing, 5bits
891 * = TRCIDR3.bits[13:12]bits[30:28]
892 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
893 * bits[3:0] = TRCIDR3.bits[30:28]
895 drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30);
897 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
898 if (BMVAL(etmidr3, 31, 31))
899 drvdata->nooverflow = true;
901 drvdata->nooverflow = false;
903 /* number of resources trace unit supports */
904 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
905 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
906 drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
907 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
908 drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
910 * NUMRSPAIR, bits[19:16]
911 * The number of resource pairs conveyed by the HW starts at 0, i.e a
912 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
913 * As such add 1 to the value of NUMRSPAIR for a better representation.
915 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
916 * the default TRUE and FALSE resource selectors are omitted.
917 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
919 drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
920 if ((drvdata->arch < ETM4X_ARCH_4V3) || (drvdata->nr_resource > 0))
921 drvdata->nr_resource += 1;
923 * NUMSSCC, bits[23:20] the number of single-shot
924 * comparator control for tracing. Read any status regs as these
925 * also contain RO capability data.
927 drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
928 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
929 drvdata->config.ss_status[i] =
930 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
932 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
933 drvdata->numcidc = BMVAL(etmidr4, 24, 27);
934 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
935 drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
937 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
938 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
939 drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
940 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
941 drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
942 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
943 if (BMVAL(etmidr5, 22, 22))
944 drvdata->atbtrig = true;
946 drvdata->atbtrig = false;
948 * LPOVERRIDE, bit[23] implementation supports
949 * low-power state override
951 if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up))
952 drvdata->lpoverride = true;
954 drvdata->lpoverride = false;
955 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
956 drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
957 /* NUMCNTR, bits[30:28] number of counters available for tracing */
958 drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
959 etm4_cs_lock(drvdata, csa);
962 /* Set ELx trace filter access in the TRCVICTLR register */
963 static void etm4_set_victlr_access(struct etmv4_config *config)
967 config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK | ETM_EXLEVEL_NS_VICTLR_MASK);
970 * TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering
971 * bits in vinst_ctrl, same bit pattern as TRCACATRn values returned by
972 * etm4_get_access_type() but with a relative shift in this register.
974 access_type = etm4_get_access_type(config) << ETM_EXLEVEL_LSHIFT_TRCVICTLR;
975 config->vinst_ctrl |= (u32)access_type;
978 static void etm4_set_default_config(struct etmv4_config *config)
980 /* disable all events tracing */
981 config->eventctrl0 = 0x0;
982 config->eventctrl1 = 0x0;
984 /* disable stalling */
985 config->stall_ctrl = 0x0;
987 /* enable trace synchronization every 4096 bytes, if available */
988 config->syncfreq = 0xC;
990 /* disable timestamp event */
991 config->ts_ctrl = 0x0;
993 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
994 config->vinst_ctrl = BIT(0);
996 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
997 etm4_set_victlr_access(config);
1000 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1002 u64 access_type = 0;
1005 * EXLEVEL_NS, bits[15:12]
1006 * The Exception levels are:
1007 * Bit[12] Exception level 0 - Application
1008 * Bit[13] Exception level 1 - OS
1009 * Bit[14] Exception level 2 - Hypervisor
1010 * Bit[15] Never implemented
1012 if (!is_kernel_in_hyp_mode()) {
1013 /* Stay away from hypervisor mode for non-VHE */
1014 access_type = ETM_EXLEVEL_NS_HYP;
1015 if (config->mode & ETM_MODE_EXCL_KERN)
1016 access_type |= ETM_EXLEVEL_NS_OS;
1017 } else if (config->mode & ETM_MODE_EXCL_KERN) {
1018 access_type = ETM_EXLEVEL_NS_HYP;
1021 if (config->mode & ETM_MODE_EXCL_USER)
1022 access_type |= ETM_EXLEVEL_NS_APP;
1027 static u64 etm4_get_access_type(struct etmv4_config *config)
1029 u64 access_type = etm4_get_ns_access_type(config);
1031 /* All supported secure ELs are excluded */
1032 access_type |= (u64)config->s_ex_level << TRCACATR_EXLEVEL_SHIFT;
1037 static void etm4_set_comparator_filter(struct etmv4_config *config,
1038 u64 start, u64 stop, int comparator)
1040 u64 access_type = etm4_get_access_type(config);
1042 /* First half of default address comparator */
1043 config->addr_val[comparator] = start;
1044 config->addr_acc[comparator] = access_type;
1045 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1047 /* Second half of default address comparator */
1048 config->addr_val[comparator + 1] = stop;
1049 config->addr_acc[comparator + 1] = access_type;
1050 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1053 * Configure the ViewInst function to include this address range
1056 * @comparator is divided by two since it is the index in the
1057 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1058 * address range comparator _pairs_.
1061 * index 0 -> compatator pair 0
1062 * index 2 -> comparator pair 1
1063 * index 4 -> comparator pair 2
1065 * index 14 -> comparator pair 7
1067 config->viiectlr |= BIT(comparator / 2);
1070 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1071 u64 address, int comparator,
1072 enum etm_addr_type type)
1075 u64 access_type = etm4_get_access_type(config);
1077 /* Configure the comparator */
1078 config->addr_val[comparator] = address;
1079 config->addr_acc[comparator] = access_type;
1080 config->addr_type[comparator] = type;
1083 * Configure ViewInst Start-Stop control register.
1084 * Addresses configured to start tracing go from bit 0 to n-1,
1085 * while those configured to stop tracing from 16 to 16 + n-1.
1087 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1088 config->vissctlr |= BIT(shift + comparator);
1091 static void etm4_set_default_filter(struct etmv4_config *config)
1093 /* Trace everything 'default' filter achieved by no filtering */
1094 config->viiectlr = 0x0;
1097 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1098 * in the started state
1100 config->vinst_ctrl |= BIT(9);
1101 config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1103 /* No start-stop filtering for ViewInst */
1104 config->vissctlr = 0x0;
1107 static void etm4_set_default(struct etmv4_config *config)
1109 if (WARN_ON_ONCE(!config))
1113 * Make default initialisation trace everything
1115 * This is done by a minimum default config sufficient to enable
1116 * full instruction trace - with a default filter for trace all
1117 * achieved by having no filtering.
1119 etm4_set_default_config(config);
1120 etm4_set_default_filter(config);
1123 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1125 int nr_comparator, index = 0;
1126 struct etmv4_config *config = &drvdata->config;
1129 * nr_addr_cmp holds the number of comparator _pair_, so time 2
1130 * for the total number of comparators.
1132 nr_comparator = drvdata->nr_addr_cmp * 2;
1134 /* Go through the tally of comparators looking for a free one. */
1135 while (index < nr_comparator) {
1137 case ETM_ADDR_TYPE_RANGE:
1138 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1139 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1142 /* Address range comparators go in pairs */
1145 case ETM_ADDR_TYPE_START:
1146 case ETM_ADDR_TYPE_STOP:
1147 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1150 /* Start/stop address can have odd indexes */
1158 /* If we are here all the comparators have been used. */
1162 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1163 struct perf_event *event)
1165 int i, comparator, ret = 0;
1167 struct etmv4_config *config = &drvdata->config;
1168 struct etm_filters *filters = event->hw.addr_filters;
1171 goto default_filter;
1173 /* Sync events with what Perf got */
1174 perf_event_addr_filters_sync(event);
1177 * If there are no filters to deal with simply go ahead with
1178 * the default filter, i.e the entire address range.
1180 if (!filters->nr_filters)
1181 goto default_filter;
1183 for (i = 0; i < filters->nr_filters; i++) {
1184 struct etm_filter *filter = &filters->etm_filter[i];
1185 enum etm_addr_type type = filter->type;
1187 /* See if a comparator is free. */
1188 comparator = etm4_get_next_comparator(drvdata, type);
1189 if (comparator < 0) {
1195 case ETM_ADDR_TYPE_RANGE:
1196 etm4_set_comparator_filter(config,
1201 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1202 * in the started state
1204 config->vinst_ctrl |= BIT(9);
1206 /* No start-stop filtering for ViewInst */
1207 config->vissctlr = 0x0;
1209 case ETM_ADDR_TYPE_START:
1210 case ETM_ADDR_TYPE_STOP:
1211 /* Get the right start or stop address */
1212 address = (type == ETM_ADDR_TYPE_START ?
1213 filter->start_addr :
1216 /* Configure comparator */
1217 etm4_set_start_stop_filter(config, address,
1221 * If filters::ssstatus == 1, trace acquisition was
1222 * started but the process was yanked away before the
1223 * the stop address was hit. As such the start/stop
1224 * logic needs to be re-started so that tracing can
1225 * resume where it left.
1227 * The start/stop logic status when a process is
1228 * scheduled out is checked in function
1229 * etm4_disable_perf().
1231 if (filters->ssstatus)
1232 config->vinst_ctrl |= BIT(9);
1234 /* No include/exclude filtering for ViewInst */
1235 config->viiectlr = 0x0;
1247 etm4_set_default_filter(config);
1253 void etm4_config_trace_mode(struct etmv4_config *config)
1257 mode = config->mode;
1258 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1260 /* excluding kernel AND user space doesn't make sense */
1261 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1263 /* nothing to do if neither flags are set */
1264 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1267 etm4_set_victlr_access(config);
1270 static int etm4_online_cpu(unsigned int cpu)
1272 if (!etmdrvdata[cpu])
1275 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1276 coresight_enable(etmdrvdata[cpu]->csdev);
1280 static int etm4_starting_cpu(unsigned int cpu)
1282 if (!etmdrvdata[cpu])
1285 spin_lock(&etmdrvdata[cpu]->spinlock);
1286 if (!etmdrvdata[cpu]->os_unlock)
1287 etm4_os_unlock(etmdrvdata[cpu]);
1289 if (local_read(&etmdrvdata[cpu]->mode))
1290 etm4_enable_hw(etmdrvdata[cpu]);
1291 spin_unlock(&etmdrvdata[cpu]->spinlock);
1295 static int etm4_dying_cpu(unsigned int cpu)
1297 if (!etmdrvdata[cpu])
1300 spin_lock(&etmdrvdata[cpu]->spinlock);
1301 if (local_read(&etmdrvdata[cpu]->mode))
1302 etm4_disable_hw(etmdrvdata[cpu]);
1303 spin_unlock(&etmdrvdata[cpu]->spinlock);
1307 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1309 drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1312 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1315 struct etmv4_save_state *state;
1316 struct coresight_device *csdev = drvdata->csdev;
1317 struct csdev_access *csa;
1318 struct device *etm_dev;
1320 if (WARN_ON(!csdev))
1323 etm_dev = &csdev->dev;
1324 csa = &csdev->access;
1327 * As recommended by 3.4.1 ("The procedure when powering down the PE")
1333 etm4_cs_unlock(drvdata, csa);
1334 /* Lock the OS lock to disable trace and external debugger access */
1335 etm4_os_lock(drvdata);
1337 /* wait for TRCSTATR.PMSTABLE to go up */
1338 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1340 "timeout while waiting for PM Stable Status\n");
1341 etm4_os_unlock(drvdata);
1346 state = drvdata->save_state;
1348 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1350 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1351 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1352 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1353 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1354 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1355 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1356 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1357 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1358 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1359 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1360 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1361 state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1363 state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1364 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1365 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1366 if (drvdata->nr_pe_cmp)
1367 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1368 state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1369 state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1370 state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1372 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1373 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1375 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1376 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1377 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1379 for (i = 0; i < drvdata->nr_cntr; i++) {
1380 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1381 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1382 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1385 for (i = 0; i < drvdata->nr_resource * 2; i++)
1386 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1388 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1389 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1390 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1391 if (etm4x_sspcicrn_present(drvdata, i))
1392 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1395 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1396 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1397 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1401 * Data trace stream is architecturally prohibited for A profile cores
1402 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1403 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1404 * unit") of ARM IHI 0064D.
1407 for (i = 0; i < drvdata->numcidc; i++)
1408 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1410 for (i = 0; i < drvdata->numvmidc; i++)
1411 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1413 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1414 if (drvdata->numcidc > 4)
1415 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1417 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1418 if (drvdata->numvmidc > 4)
1419 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1421 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1423 if (!drvdata->skip_power_up)
1424 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1426 /* wait for TRCSTATR.IDLE to go up */
1427 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1429 "timeout while waiting for Idle Trace Status\n");
1430 etm4_os_unlock(drvdata);
1435 drvdata->state_needs_restore = true;
1438 * Power can be removed from the trace unit now. We do this to
1439 * potentially save power on systems that respect the TRCPDCR_PU
1440 * despite requesting software to save/restore state.
1442 if (!drvdata->skip_power_up)
1443 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1446 etm4_cs_lock(drvdata, csa);
1450 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1453 struct etmv4_save_state *state = drvdata->save_state;
1454 struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1455 struct csdev_access *csa = &tmp_csa;
1457 etm4_cs_unlock(drvdata, csa);
1458 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1460 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1462 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1463 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1464 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1465 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1466 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1467 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1468 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1469 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1470 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1471 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1472 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1473 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1475 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1476 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1477 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1478 if (drvdata->nr_pe_cmp)
1479 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1480 etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1481 etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1482 etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1484 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1485 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1487 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1488 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1489 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1491 for (i = 0; i < drvdata->nr_cntr; i++) {
1492 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1493 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1494 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1497 for (i = 0; i < drvdata->nr_resource * 2; i++)
1498 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1500 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1501 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1502 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1503 if (etm4x_sspcicrn_present(drvdata, i))
1504 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1507 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1508 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1509 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1512 for (i = 0; i < drvdata->numcidc; i++)
1513 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1515 for (i = 0; i < drvdata->numvmidc; i++)
1516 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1518 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1519 if (drvdata->numcidc > 4)
1520 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1522 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1523 if (drvdata->numvmidc > 4)
1524 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1526 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1528 if (!drvdata->skip_power_up)
1529 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1531 drvdata->state_needs_restore = false;
1534 * As recommended by section 4.3.7 ("Synchronization when using the
1535 * memory-mapped interface") of ARM IHI 0064D
1540 /* Unlock the OS lock to re-enable trace and external debug access */
1541 etm4_os_unlock(drvdata);
1542 etm4_cs_lock(drvdata, csa);
1545 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1548 struct etmv4_drvdata *drvdata;
1549 unsigned int cpu = smp_processor_id();
1551 if (!etmdrvdata[cpu])
1554 drvdata = etmdrvdata[cpu];
1556 if (!drvdata->save_state)
1559 if (WARN_ON_ONCE(drvdata->cpu != cpu))
1564 /* save the state if self-hosted coresight is in use */
1565 if (local_read(&drvdata->mode))
1566 if (etm4_cpu_save(drvdata))
1570 case CPU_PM_ENTER_FAILED:
1571 if (drvdata->state_needs_restore)
1572 etm4_cpu_restore(drvdata);
1581 static struct notifier_block etm4_cpu_pm_nb = {
1582 .notifier_call = etm4_cpu_pm_notify,
1585 /* Setup PM. Deals with error conditions and counts */
1586 static int __init etm4_pm_setup(void)
1590 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1594 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1595 "arm/coresight4:starting",
1596 etm4_starting_cpu, etm4_dying_cpu);
1599 goto unregister_notifier;
1601 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1602 "arm/coresight4:online",
1603 etm4_online_cpu, NULL);
1605 /* HP dyn state ID returned in ret on success */
1611 /* failed dyn state - remove others */
1612 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1614 unregister_notifier:
1615 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1619 static void etm4_pm_clear(void)
1621 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1622 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1624 cpuhp_remove_state_nocalls(hp_online);
1629 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
1633 struct device *dev = &adev->dev;
1634 struct coresight_platform_data *pdata = NULL;
1635 struct etmv4_drvdata *drvdata;
1636 struct resource *res = &adev->res;
1637 struct coresight_desc desc = { 0 };
1639 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1643 dev_set_drvdata(dev, drvdata);
1645 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1646 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1647 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1649 if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1650 drvdata->save_state = devm_kmalloc(dev,
1651 sizeof(struct etmv4_save_state), GFP_KERNEL);
1652 if (!drvdata->save_state)
1656 if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1657 drvdata->skip_power_up = true;
1659 /* Validity for the resource is already checked by the AMBA core */
1660 base = devm_ioremap_resource(dev, res);
1662 return PTR_ERR(base);
1664 drvdata->base = base;
1665 desc.access = CSDEV_ACCESS_IOMEM(base);
1667 spin_lock_init(&drvdata->spinlock);
1669 drvdata->cpu = coresight_get_cpu(dev);
1670 if (drvdata->cpu < 0)
1671 return drvdata->cpu;
1673 desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
1677 if (smp_call_function_single(drvdata->cpu,
1678 etm4_init_arch_data, drvdata, 1))
1679 dev_err(dev, "ETM arch init failed\n");
1681 if (etm4_arch_supported(drvdata->arch) == false)
1684 etm4_init_trace_id(drvdata);
1685 etm4_set_default(&drvdata->config);
1687 pdata = coresight_get_platform_data(dev);
1689 return PTR_ERR(pdata);
1691 adev->dev.platform_data = pdata;
1693 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1694 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1695 desc.ops = &etm4_cs_ops;
1698 desc.groups = coresight_etmv4_groups;
1699 drvdata->csdev = coresight_register(&desc);
1700 if (IS_ERR(drvdata->csdev))
1701 return PTR_ERR(drvdata->csdev);
1703 ret = etm_perf_symlink(drvdata->csdev, true);
1705 coresight_unregister(drvdata->csdev);
1709 etmdrvdata[drvdata->cpu] = drvdata;
1711 pm_runtime_put(&adev->dev);
1712 dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
1713 drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
1716 coresight_enable(drvdata->csdev);
1717 drvdata->boot_enable = true;
1720 etm4_check_arch_features(drvdata, id->id);
1725 static struct amba_cs_uci_id uci_id_etm4[] = {
1727 /* ETMv4 UCI data */
1728 .devarch = ETM_DEVARCH_ETMv4x_ARCH,
1729 .devarch_mask = ETM_DEVARCH_ID_MASK,
1730 .devtype = 0x00000013,
1734 static void clear_etmdrvdata(void *info)
1736 int cpu = *(int *)info;
1738 etmdrvdata[cpu] = NULL;
1741 static int etm4_remove(struct amba_device *adev)
1743 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
1745 etm_perf_symlink(drvdata->csdev, false);
1748 * Taking hotplug lock here to avoid racing between etm4_remove and
1749 * CPU hotplug call backs.
1753 * The readers for etmdrvdata[] are CPU hotplug call backs
1754 * and PM notification call backs. Change etmdrvdata[i] on
1755 * CPU i ensures these call backs has consistent view
1756 * inside one call back function.
1758 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
1759 etmdrvdata[drvdata->cpu] = NULL;
1763 coresight_unregister(drvdata->csdev);
1768 static const struct amba_id etm4_ids[] = {
1769 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
1770 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
1771 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
1772 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
1773 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
1774 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
1775 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
1776 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
1777 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
1778 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
1779 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
1780 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
1781 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
1782 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
1783 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
1784 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
1785 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
1789 MODULE_DEVICE_TABLE(amba, etm4_ids);
1791 static struct amba_driver etm4x_driver = {
1793 .name = "coresight-etm4x",
1794 .owner = THIS_MODULE,
1795 .suppress_bind_attrs = true,
1797 .probe = etm4_probe,
1798 .remove = etm4_remove,
1799 .id_table = etm4_ids,
1802 static int __init etm4x_init(void)
1806 ret = etm4_pm_setup();
1808 /* etm4_pm_setup() does its own cleanup - exit on error */
1812 ret = amba_driver_register(&etm4x_driver);
1814 pr_err("Error registering etm4x driver\n");
1821 static void __exit etm4x_exit(void)
1823 amba_driver_unregister(&etm4x_driver);
1827 module_init(etm4x_init);
1828 module_exit(etm4x_exit);
1830 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1831 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
1832 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
1833 MODULE_LICENSE("GPL v2");