drivers/hwtracing/coresight/coresight-etm4x-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/kernel.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/device.h>
  12 #include <linux/io.h>
  13 #include <linux/err.h>
  14 #include <linux/fs.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/smp.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/stat.h>
  20 #include <linux/clk.h>
  21 #include <linux/cpu.h>
  22 #include <linux/cpu_pm.h>
  23 #include <linux/coresight.h>
  24 #include <linux/coresight-pmu.h>
  25 #include <linux/pm_wakeup.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/perf_event.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/property.h>
  33
  34 #include <asm/barrier.h>
  35 #include <asm/sections.h>
  36 #include <asm/sysreg.h>
  37 #include <asm/local.h>
  38 #include <asm/virt.h>
  39
  40 #include "coresight-etm4x.h"
  41 #include "coresight-etm-perf.h"
  42
  43 static int boot_enable;
  44 module_param(boot_enable, int, 0444);
  45 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
  46
  47 #define PARAM_PM_SAVE_FIRMWARE    0 /* save self-hosted state as per firmware */
  48 #define PARAM_PM_SAVE_NEVER       1 /* never save any state */
  49 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
  50
  51 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
  52 module_param(pm_save_enable, int, 0444);
  53 MODULE_PARM_DESC(pm_save_enable,
  54         "Save/restore state on power down: 1 = never, 2 = self-hosted");
  55
  56 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  57 static void etm4_set_default_config(struct etmv4_config *config);
  58 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  59                                   struct perf_event *event);
  60 static u64 etm4_get_access_type(struct etmv4_config *config);
  61
  62 static enum cpuhp_state hp_online;
  63
  64 struct etm4_init_arg {
  65         unsigned int            pid;
  66         struct etmv4_drvdata    *drvdata;
  67         struct csdev_access     *csa;
  68 };
  69
  70 /*
  71  * Check if TRCSSPCICRn(i) is implemented for a given instance.
  72  *
  73  * TRCSSPCICRn is implemented only if :
  74  *      TRCSSPCICR<n> is present only if all of the following are true:
  75  *              TRCIDR4.NUMSSCC > n.
  76  *              TRCIDR4.NUMPC > 0b0000 .
  77  *              TRCSSCSR<n>.PC == 0b1
  78  */
  79 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
  80 {
  81         return (n < drvdata->nr_ss_cmp) &&
  82                drvdata->nr_pe &&
  83                (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
  84 }
  85
  86 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
  87 {
  88         u64 res = 0;
  89
  90         switch (offset) {
  91         ETM4x_READ_SYSREG_CASES(res)
  92         default :
  93                 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
  94                          offset);
  95         }
  96
  97         if (!_relaxed)
  98                 __iormb(res);   /* Imitate the !relaxed I/O helpers */
  99
 100         return res;
 101 }
 102
 103 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
 104 {
 105         if (!_relaxed)
 106                 __iowmb();      /* Imitate the !relaxed I/O helpers */
 107         if (!_64bit)
 108                 val &= GENMASK(31, 0);
 109
 110         switch (offset) {
 111         ETM4x_WRITE_SYSREG_CASES(val)
 112         default :
 113                 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
 114                         offset);
 115         }
 116 }
 117
 118 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
 119 {
 120         u64 res = 0;
 121
 122         switch (offset) {
 123         ETE_READ_CASES(res)
 124         default :
 125                 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
 126                                     offset);
 127         }
 128
 129         if (!_relaxed)
 130                 __iormb(res);   /* Imitate the !relaxed I/O helpers */
 131
 132         return res;
 133 }
 134
 135 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
 136 {
 137         if (!_relaxed)
 138                 __iowmb();      /* Imitate the !relaxed I/O helpers */
 139         if (!_64bit)
 140                 val &= GENMASK(31, 0);
 141
 142         switch (offset) {
 143         ETE_WRITE_CASES(val)
 144         default :
 145                 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
 146                                     offset);
 147         }
 148 }
 149
 150 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
 151                                struct csdev_access *csa)
 152 {
 153         u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
 154
 155         drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
 156 }
 157
 158 static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
 159                               struct csdev_access *csa, u32 val)
 160 {
 161         val = !!val;
 162
 163         switch (drvdata->os_lock_model) {
 164         case ETM_OSLOCK_PRESENT:
 165                 etm4x_relaxed_write32(csa, val, TRCOSLAR);
 166                 break;
 167         case ETM_OSLOCK_PE:
 168                 write_sysreg_s(val, SYS_OSLAR_EL1);
 169                 break;
 170         default:
 171                 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
 172                              smp_processor_id(), drvdata->os_lock_model);
 173                 fallthrough;
 174         case ETM_OSLOCK_NI:
 175                 return;
 176         }
 177         isb();
 178 }
 179
 180 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
 181                                       struct csdev_access *csa)
 182 {
 183         WARN_ON(drvdata->cpu != smp_processor_id());
 184
 185         /* Writing 0 to OS Lock unlocks the trace unit registers */
 186         etm_write_os_lock(drvdata, csa, 0x0);
 187         drvdata->os_unlock = true;
 188 }
 189
 190 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
 191 {
 192         if (!WARN_ON(!drvdata->csdev))
 193                 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
 194 }
 195
 196 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
 197 {
 198         if (WARN_ON(!drvdata->csdev))
 199                 return;
 200         /* Writing 0x1 to OS Lock locks the trace registers */
 201         etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
 202         drvdata->os_unlock = false;
 203 }
 204
 205 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
 206                          struct csdev_access *csa)
 207 {
 208         /* Software Lock is only accessible via memory mapped interface */
 209         if (csa->io_mem)
 210                 CS_LOCK(csa->base);
 211 }
 212
 213 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
 214                            struct csdev_access *csa)
 215 {
 216         if (csa->io_mem)
 217                 CS_UNLOCK(csa->base);
 218 }
 219
 220 static int etm4_cpu_id(struct coresight_device *csdev)
 221 {
 222         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 223
 224         return drvdata->cpu;
 225 }
 226
 227 static int etm4_trace_id(struct coresight_device *csdev)
 228 {
 229         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 230
 231         return drvdata->trcid;
 232 }
 233
 234 struct etm4_enable_arg {
 235         struct etmv4_drvdata *drvdata;
 236         int rc;
 237 };
 238
 239 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
 240
 241 #define HISI_HIP08_AMBA_ID              0x000b6d01
 242 #define ETM4_AMBA_MASK                  0xfffff
 243 #define HISI_HIP08_CORE_COMMIT_MASK     0x3000
 244 #define HISI_HIP08_CORE_COMMIT_SHIFT    12
 245 #define HISI_HIP08_CORE_COMMIT_FULL     0b00
 246 #define HISI_HIP08_CORE_COMMIT_LVL_1    0b01
 247 #define HISI_HIP08_CORE_COMMIT_REG      sys_reg(3, 1, 15, 2, 5)
 248
 249 struct etm4_arch_features {
 250         void (*arch_callback)(bool enable);
 251 };
 252
 253 static bool etm4_hisi_match_pid(unsigned int id)
 254 {
 255         return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
 256 }
 257
 258 static void etm4_hisi_config_core_commit(bool enable)
 259 {
 260         u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
 261                     HISI_HIP08_CORE_COMMIT_FULL;
 262         u64 val;
 263
 264         /*
 265          * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
 266          * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
 267          * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
 268          * speed(minimun value). So bit 12 and 13 should be cleared together.
 269          */
 270         val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
 271         val &= ~HISI_HIP08_CORE_COMMIT_MASK;
 272         val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
 273         write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
 274 }
 275
 276 static struct etm4_arch_features etm4_features[] = {
 277         [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
 278                 .arch_callback = etm4_hisi_config_core_commit,
 279         },
 280         {},
 281 };
 282
 283 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 284 {
 285         struct etm4_arch_features *ftr;
 286         int bit;
 287
 288         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 289                 ftr = &etm4_features[bit];
 290
 291                 if (ftr->arch_callback)
 292                         ftr->arch_callback(true);
 293         }
 294 }
 295
 296 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 297 {
 298         struct etm4_arch_features *ftr;
 299         int bit;
 300
 301         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 302                 ftr = &etm4_features[bit];
 303
 304                 if (ftr->arch_callback)
 305                         ftr->arch_callback(false);
 306         }
 307 }
 308
 309 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 310                                       unsigned int id)
 311 {
 312         if (etm4_hisi_match_pid(id))
 313                 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
 314 }
 315 #else
 316 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 317 {
 318 }
 319
 320 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 321 {
 322 }
 323
 324 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 325                                      unsigned int id)
 326 {
 327 }
 328 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
 329
 330 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 331 {
 332         int i, rc;
 333         struct etmv4_config *config = &drvdata->config;
 334         struct coresight_device *csdev = drvdata->csdev;
 335         struct device *etm_dev = &csdev->dev;
 336         struct csdev_access *csa = &csdev->access;
 337
 338
 339         etm4_cs_unlock(drvdata, csa);
 340         etm4_enable_arch_specific(drvdata);
 341
 342         etm4_os_unlock(drvdata);
 343
 344         rc = coresight_claim_device_unlocked(csdev);
 345         if (rc)
 346                 goto done;
 347
 348         /* Disable the trace unit before programming trace registers */
 349         etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
 350
 351         /*
 352          * If we use system instructions, we need to synchronize the
 353          * write to the TRCPRGCTLR, before accessing the TRCSTATR.
 354          * See ARM IHI0064F, section
 355          * "4.3.7 Synchronization of register updates"
 356          */
 357         if (!csa->io_mem)
 358                 isb();
 359
 360         /* wait for TRCSTATR.IDLE to go up */
 361         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 362                 dev_err(etm_dev,
 363                         "timeout while waiting for Idle Trace Status\n");
 364         if (drvdata->nr_pe)
 365                 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
 366         etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
 367         /* nothing specific implemented */
 368         etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
 369         etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
 370         etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
 371         if (drvdata->stallctl)
 372                 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
 373         etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
 374         etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
 375         etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
 376         etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
 377         etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
 378         etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
 379         etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
 380         etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
 381         if (drvdata->nr_pe_cmp)
 382                 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
 383         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 384                 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
 385         etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
 386         etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
 387         etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
 388         for (i = 0; i < drvdata->nr_cntr; i++) {
 389                 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
 390                 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
 391                 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
 392         }
 393
 394         /*
 395          * Resource selector pair 0 is always implemented and reserved.  As
 396          * such start at 2.
 397          */
 398         for (i = 2; i < drvdata->nr_resource * 2; i++)
 399                 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
 400
 401         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 402                 /* always clear status bit on restart if using single-shot */
 403                 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
 404                         config->ss_status[i] &= ~BIT(31);
 405                 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
 406                 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
 407                 if (etm4x_sspcicrn_present(drvdata, i))
 408                         etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
 409         }
 410         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 411                 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
 412                 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
 413         }
 414         for (i = 0; i < drvdata->numcidc; i++)
 415                 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
 416         etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
 417         if (drvdata->numcidc > 4)
 418                 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
 419
 420         for (i = 0; i < drvdata->numvmidc; i++)
 421                 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
 422         etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
 423         if (drvdata->numvmidc > 4)
 424                 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
 425
 426         if (!drvdata->skip_power_up) {
 427                 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
 428
 429                 /*
 430                  * Request to keep the trace unit powered and also
 431                  * emulation of powerdown
 432                  */
 433                 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
 434         }
 435
 436         /*
 437          * ETE mandates that the TRCRSR is written to before
 438          * enabling it.
 439          */
 440         if (etm4x_is_ete(drvdata))
 441                 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
 442
 443         /* Enable the trace unit */
 444         etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
 445
 446         /* Synchronize the register updates for sysreg access */
 447         if (!csa->io_mem)
 448                 isb();
 449
 450         /* wait for TRCSTATR.IDLE to go back down to '0' */
 451         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 452                 dev_err(etm_dev,
 453                         "timeout while waiting for Idle Trace Status\n");
 454
 455         /*
 456          * As recommended by section 4.3.7 ("Synchronization when using the
 457          * memory-mapped interface") of ARM IHI 0064D
 458          */
 459         dsb(sy);
 460         isb();
 461
 462 done:
 463         etm4_cs_lock(drvdata, csa);
 464
 465         dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
 466                 drvdata->cpu, rc);
 467         return rc;
 468 }
 469
 470 static void etm4_enable_hw_smp_call(void *info)
 471 {
 472         struct etm4_enable_arg *arg = info;
 473
 474         if (WARN_ON(!arg))
 475                 return;
 476         arg->rc = etm4_enable_hw(arg->drvdata);
 477 }
 478
 479 /*
 480  * The goal of function etm4_config_timestamp_event() is to configure a
 481  * counter that will tell the tracer to emit a timestamp packet when it
 482  * reaches zero.  This is done in order to get a more fine grained idea
 483  * of when instructions are executed so that they can be correlated
 484  * with execution on other CPUs.
 485  *
 486  * To do this the counter itself is configured to self reload and
 487  * TRCRSCTLR1 (always true) used to get the counter to decrement.  From
 488  * there a resource selector is configured with the counter and the
 489  * timestamp control register to use the resource selector to trigger the
 490  * event that will insert a timestamp packet in the stream.
 491  */
 492 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
 493 {
 494         int ctridx, ret = -EINVAL;
 495         int counter, rselector;
 496         u32 val = 0;
 497         struct etmv4_config *config = &drvdata->config;
 498
 499         /* No point in trying if we don't have at least one counter */
 500         if (!drvdata->nr_cntr)
 501                 goto out;
 502
 503         /* Find a counter that hasn't been initialised */
 504         for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
 505                 if (config->cntr_val[ctridx] == 0)
 506                         break;
 507
 508         /* All the counters have been configured already, bail out */
 509         if (ctridx == drvdata->nr_cntr) {
 510                 pr_debug("%s: no available counter found\n", __func__);
 511                 ret = -ENOSPC;
 512                 goto out;
 513         }
 514
 515         /*
 516          * Searching for an available resource selector to use, starting at
 517          * '2' since every implementation has at least 2 resource selector.
 518          * ETMIDR4 gives the number of resource selector _pairs_,
 519          * hence multiply by 2.
 520          */
 521         for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
 522                 if (!config->res_ctrl[rselector])
 523                         break;
 524
 525         if (rselector == drvdata->nr_resource * 2) {
 526                 pr_debug("%s: no available resource selector found\n",
 527                          __func__);
 528                 ret = -ENOSPC;
 529                 goto out;
 530         }
 531
 532         /* Remember what counter we used */
 533         counter = 1 << ctridx;
 534
 535         /*
 536          * Initialise original and reload counter value to the smallest
 537          * possible value in order to get as much precision as we can.
 538          */
 539         config->cntr_val[ctridx] = 1;
 540         config->cntrldvr[ctridx] = 1;
 541
 542         /* Set the trace counter control register */
 543         val =  0x1 << 16        |  /* Bit 16, reload counter automatically */
 544                0x0 << 7         |  /* Select single resource selector */
 545                0x1;                /* Resource selector 1, i.e always true */
 546
 547         config->cntr_ctrl[ctridx] = val;
 548
 549         val = 0x2 << 16         | /* Group 0b0010 - Counter and sequencers */
 550               counter << 0;       /* Counter to use */
 551
 552         config->res_ctrl[rselector] = val;
 553
 554         val = 0x0 << 7          | /* Select single resource selector */
 555               rselector;          /* Resource selector */
 556
 557         config->ts_ctrl = val;
 558
 559         ret = 0;
 560 out:
 561         return ret;
 562 }
 563
 564 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
 565                                    struct perf_event *event)
 566 {
 567         int ret = 0;
 568         struct etmv4_config *config = &drvdata->config;
 569         struct perf_event_attr *attr = &event->attr;
 570
 571         if (!attr) {
 572                 ret = -EINVAL;
 573                 goto out;
 574         }
 575
 576         /* Clear configuration from previous run */
 577         memset(config, 0, sizeof(struct etmv4_config));
 578
 579         if (attr->exclude_kernel)
 580                 config->mode = ETM_MODE_EXCL_KERN;
 581
 582         if (attr->exclude_user)
 583                 config->mode = ETM_MODE_EXCL_USER;
 584
 585         /* Always start from the default config */
 586         etm4_set_default_config(config);
 587
 588         /* Configure filters specified on the perf cmd line, if any. */
 589         ret = etm4_set_event_filters(drvdata, event);
 590         if (ret)
 591                 goto out;
 592
 593         /* Go from generic option to ETMv4 specifics */
 594         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 595                 config->cfg |= BIT(4);
 596                 /* TRM: Must program this for cycacc to work */
 597                 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
 598         }
 599         if (attr->config & BIT(ETM_OPT_TS)) {
 600                 /*
 601                  * Configure timestamps to be emitted at regular intervals in
 602                  * order to correlate instructions executed on different CPUs
 603                  * (CPU-wide trace scenarios).
 604                  */
 605                 ret = etm4_config_timestamp_event(drvdata);
 606
 607                 /*
 608                  * No need to go further if timestamp intervals can't
 609                  * be configured.
 610                  */
 611                 if (ret)
 612                         goto out;
 613
 614                 /* bit[11], Global timestamp tracing bit */
 615                 config->cfg |= BIT(11);
 616         }
 617
 618         if (attr->config & BIT(ETM_OPT_CTXTID))
 619                 /* bit[6], Context ID tracing bit */
 620                 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
 621
 622         /*
 623          * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
 624          * for recording CONTEXTIDR_EL2.  Do not enable VMID tracing if the
 625          * kernel is not running in EL2.
 626          */
 627         if (attr->config & BIT(ETM_OPT_CTXTID2)) {
 628                 if (!is_kernel_in_hyp_mode()) {
 629                         ret = -EINVAL;
 630                         goto out;
 631                 }
 632                 config->cfg |= BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT);
 633         }
 634
 635         /* return stack - enable if selected and supported */
 636         if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
 637                 /* bit[12], Return stack enable bit */
 638                 config->cfg |= BIT(12);
 639
 640 out:
 641         return ret;
 642 }
 643
 644 static int etm4_enable_perf(struct coresight_device *csdev,
 645                             struct perf_event *event)
 646 {
 647         int ret = 0;
 648         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 649
 650         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 651                 ret = -EINVAL;
 652                 goto out;
 653         }
 654
 655         /* Configure the tracer based on the session's specifics */
 656         ret = etm4_parse_event_config(drvdata, event);
 657         if (ret)
 658                 goto out;
 659         /* And enable it */
 660         ret = etm4_enable_hw(drvdata);
 661
 662 out:
 663         return ret;
 664 }
 665
 666 static int etm4_enable_sysfs(struct coresight_device *csdev)
 667 {
 668         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 669         struct etm4_enable_arg arg = { };
 670         int ret;
 671
 672         spin_lock(&drvdata->spinlock);
 673
 674         /*
 675          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 676          * ensures that register writes occur when cpu is powered.
 677          */
 678         arg.drvdata = drvdata;
 679         ret = smp_call_function_single(drvdata->cpu,
 680                                        etm4_enable_hw_smp_call, &arg, 1);
 681         if (!ret)
 682                 ret = arg.rc;
 683         if (!ret)
 684                 drvdata->sticky_enable = true;
 685         spin_unlock(&drvdata->spinlock);
 686
 687         if (!ret)
 688                 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
 689         return ret;
 690 }
 691
 692 static int etm4_enable(struct coresight_device *csdev,
 693                        struct perf_event *event, u32 mode)
 694 {
 695         int ret;
 696         u32 val;
 697         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 698
 699         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 700
 701         /* Someone is already using the tracer */
 702         if (val)
 703                 return -EBUSY;
 704
 705         switch (mode) {
 706         case CS_MODE_SYSFS:
 707                 ret = etm4_enable_sysfs(csdev);
 708                 break;
 709         case CS_MODE_PERF:
 710                 ret = etm4_enable_perf(csdev, event);
 711                 break;
 712         default:
 713                 ret = -EINVAL;
 714         }
 715
 716         /* The tracer didn't start */
 717         if (ret)
 718                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 719
 720         return ret;
 721 }
 722
 723 static void etm4_disable_hw(void *info)
 724 {
 725         u32 control;
 726         u64 trfcr;
 727         struct etmv4_drvdata *drvdata = info;
 728         struct etmv4_config *config = &drvdata->config;
 729         struct coresight_device *csdev = drvdata->csdev;
 730         struct device *etm_dev = &csdev->dev;
 731         struct csdev_access *csa = &csdev->access;
 732         int i;
 733
 734         etm4_cs_unlock(drvdata, csa);
 735         etm4_disable_arch_specific(drvdata);
 736
 737         if (!drvdata->skip_power_up) {
 738                 /* power can be removed from the trace unit now */
 739                 control = etm4x_relaxed_read32(csa, TRCPDCR);
 740                 control &= ~TRCPDCR_PU;
 741                 etm4x_relaxed_write32(csa, control, TRCPDCR);
 742         }
 743
 744         control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
 745
 746         /* EN, bit[0] Trace unit enable bit */
 747         control &= ~0x1;
 748
 749         /*
 750          * If the CPU supports v8.4 Trace filter Control,
 751          * set the ETM to trace prohibited region.
 752          */
 753         if (drvdata->trfc) {
 754                 trfcr = read_sysreg_s(SYS_TRFCR_EL1);
 755                 write_sysreg_s(trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE),
 756                                SYS_TRFCR_EL1);
 757                 isb();
 758         }
 759         /*
 760          * Make sure everything completes before disabling, as recommended
 761          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 762          * SSTATUS") of ARM IHI 0064D
 763          */
 764         dsb(sy);
 765         isb();
 766         /* Trace synchronization barrier, is a nop if not supported */
 767         tsb_csync();
 768         etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
 769
 770         /* wait for TRCSTATR.PMSTABLE to go to '1' */
 771         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
 772                 dev_err(etm_dev,
 773                         "timeout while waiting for PM stable Trace Status\n");
 774         if (drvdata->trfc)
 775                 write_sysreg_s(trfcr, SYS_TRFCR_EL1);
 776
 777         /* read the status of the single shot comparators */
 778         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 779                 config->ss_status[i] =
 780                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
 781         }
 782
 783         /* read back the current counter values */
 784         for (i = 0; i < drvdata->nr_cntr; i++) {
 785                 config->cntr_val[i] =
 786                         etm4x_relaxed_read32(csa, TRCCNTVRn(i));
 787         }
 788
 789         coresight_disclaim_device_unlocked(csdev);
 790         etm4_cs_lock(drvdata, csa);
 791
 792         dev_dbg(&drvdata->csdev->dev,
 793                 "cpu: %d disable smp call done\n", drvdata->cpu);
 794 }
 795
 796 static int etm4_disable_perf(struct coresight_device *csdev,
 797                              struct perf_event *event)
 798 {
 799         u32 control;
 800         struct etm_filters *filters = event->hw.addr_filters;
 801         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 802
 803         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 804                 return -EINVAL;
 805
 806         etm4_disable_hw(drvdata);
 807
 808         /*
 809          * Check if the start/stop logic was active when the unit was stopped.
 810          * That way we can re-enable the start/stop logic when the process is
 811          * scheduled again.  Configuration of the start/stop logic happens in
 812          * function etm4_set_event_filters().
 813          */
 814         control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
 815         /* TRCVICTLR::SSSTATUS, bit[9] */
 816         filters->ssstatus = (control & BIT(9));
 817
 818         return 0;
 819 }
 820
 821 static void etm4_disable_sysfs(struct coresight_device *csdev)
 822 {
 823         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 824
 825         /*
 826          * Taking hotplug lock here protects from clocks getting disabled
 827          * with tracing being left on (crash scenario) if user disable occurs
 828          * after cpu online mask indicates the cpu is offline but before the
 829          * DYING hotplug callback is serviced by the ETM driver.
 830          */
 831         cpus_read_lock();
 832         spin_lock(&drvdata->spinlock);
 833
 834         /*
 835          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 836          * ensures that register writes occur when cpu is powered.
 837          */
 838         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 839
 840         spin_unlock(&drvdata->spinlock);
 841         cpus_read_unlock();
 842
 843         dev_dbg(&csdev->dev, "ETM tracing disabled\n");
 844 }
 845
 846 static void etm4_disable(struct coresight_device *csdev,
 847                          struct perf_event *event)
 848 {
 849         u32 mode;
 850         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 851
 852         /*
 853          * For as long as the tracer isn't disabled another entity can't
 854          * change its status.  As such we can read the status here without
 855          * fearing it will change under us.
 856          */
 857         mode = local_read(&drvdata->mode);
 858
 859         switch (mode) {
 860         case CS_MODE_DISABLED:
 861                 break;
 862         case CS_MODE_SYSFS:
 863                 etm4_disable_sysfs(csdev);
 864                 break;
 865         case CS_MODE_PERF:
 866                 etm4_disable_perf(csdev, event);
 867                 break;
 868         }
 869
 870         if (mode)
 871                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 872 }
 873
 874 static const struct coresight_ops_source etm4_source_ops = {
 875         .cpu_id         = etm4_cpu_id,
 876         .trace_id       = etm4_trace_id,
 877         .enable         = etm4_enable,
 878         .disable        = etm4_disable,
 879 };
 880
 881 static const struct coresight_ops etm4_cs_ops = {
 882         .source_ops     = &etm4_source_ops,
 883 };
 884
 885 static inline bool cpu_supports_sysreg_trace(void)
 886 {
 887         u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
 888
 889         return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0;
 890 }
 891
 892 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
 893                                     struct csdev_access *csa)
 894 {
 895         u32 devarch;
 896
 897         if (!cpu_supports_sysreg_trace())
 898                 return false;
 899
 900         /*
 901          * ETMs implementing sysreg access must implement TRCDEVARCH.
 902          */
 903         devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
 904         switch (devarch & ETM_DEVARCH_ID_MASK) {
 905         case ETM_DEVARCH_ETMv4x_ARCH:
 906                 *csa = (struct csdev_access) {
 907                         .io_mem = false,
 908                         .read   = etm4x_sysreg_read,
 909                         .write  = etm4x_sysreg_write,
 910                 };
 911                 break;
 912         case ETM_DEVARCH_ETE_ARCH:
 913                 *csa = (struct csdev_access) {
 914                         .io_mem = false,
 915                         .read   = ete_sysreg_read,
 916                         .write  = ete_sysreg_write,
 917                 };
 918                 break;
 919         default:
 920                 return false;
 921         }
 922
 923         drvdata->arch = etm_devarch_to_arch(devarch);
 924         return true;
 925 }
 926
 927 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
 928                                    struct csdev_access *csa)
 929 {
 930         u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
 931         u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1);
 932
 933         /*
 934          * All ETMs must implement TRCDEVARCH to indicate that
 935          * the component is an ETMv4. To support any broken
 936          * implementations we fall back to TRCIDR1 check, which
 937          * is not really reliable.
 938          */
 939         if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) {
 940                 drvdata->arch = etm_devarch_to_arch(devarch);
 941         } else {
 942                 pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n",
 943                         smp_processor_id(), devarch);
 944
 945                 if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4)
 946                         return false;
 947                 drvdata->arch = etm_trcidr_to_arch(idr1);
 948         }
 949
 950         *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
 951         return true;
 952 }
 953
 954 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
 955                                    struct csdev_access *csa)
 956 {
 957         /*
 958          * Always choose the memory mapped io, if there is
 959          * a memory map to prevent sysreg access on broken
 960          * systems.
 961          */
 962         if (drvdata->base)
 963                 return etm4_init_iomem_access(drvdata, csa);
 964
 965         if (etm4_init_sysreg_access(drvdata, csa))
 966                 return true;
 967
 968         return false;
 969 }
 970
 971 static void cpu_enable_tracing(struct etmv4_drvdata *drvdata)
 972 {
 973         u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
 974         u64 trfcr;
 975
 976         if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT))
 977                 return;
 978
 979         drvdata->trfc = true;
 980         /*
 981          * If the CPU supports v8.4 SelfHosted Tracing, enable
 982          * tracing at the kernel EL and EL0, forcing to use the
 983          * virtual time as the timestamp.
 984          */
 985         trfcr = (TRFCR_ELx_TS_VIRTUAL |
 986                  TRFCR_ELx_ExTRE |
 987                  TRFCR_ELx_E0TRE);
 988
 989         /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
 990         if (is_kernel_in_hyp_mode())
 991                 trfcr |= TRFCR_EL2_CX;
 992
 993         write_sysreg_s(trfcr, SYS_TRFCR_EL1);
 994 }
 995
 996 static void etm4_init_arch_data(void *info)
 997 {
 998         u32 etmidr0;
 999         u32 etmidr2;
1000         u32 etmidr3;
1001         u32 etmidr4;
1002         u32 etmidr5;
1003         struct etm4_init_arg *init_arg = info;
1004         struct etmv4_drvdata *drvdata;
1005         struct csdev_access *csa;
1006         int i;
1007
1008         drvdata = init_arg->drvdata;
1009         csa = init_arg->csa;
1010
1011         /*
1012          * If we are unable to detect the access mechanism,
1013          * or unable to detect the trace unit type, fail
1014          * early.
1015          */
1016         if (!etm4_init_csdev_access(drvdata, csa))
1017                 return;
1018
1019         /* Detect the support for OS Lock before we actually use it */
1020         etm_detect_os_lock(drvdata, csa);
1021
1022         /* Make sure all registers are accessible */
1023         etm4_os_unlock_csa(drvdata, csa);
1024         etm4_cs_unlock(drvdata, csa);
1025
1026         etm4_check_arch_features(drvdata, init_arg->pid);
1027
1028         /* find all capabilities of the tracing unit */
1029         etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1030
1031         /* INSTP0, bits[2:1] P0 tracing support field */
1032         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
1033                 drvdata->instrp0 = true;
1034         else
1035                 drvdata->instrp0 = false;
1036
1037         /* TRCBB, bit[5] Branch broadcast tracing support bit */
1038         if (BMVAL(etmidr0, 5, 5))
1039                 drvdata->trcbb = true;
1040         else
1041                 drvdata->trcbb = false;
1042
1043         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1044         if (BMVAL(etmidr0, 6, 6))
1045                 drvdata->trccond = true;
1046         else
1047                 drvdata->trccond = false;
1048
1049         /* TRCCCI, bit[7] Cycle counting instruction bit */
1050         if (BMVAL(etmidr0, 7, 7))
1051                 drvdata->trccci = true;
1052         else
1053                 drvdata->trccci = false;
1054
1055         /* RETSTACK, bit[9] Return stack bit */
1056         if (BMVAL(etmidr0, 9, 9))
1057                 drvdata->retstack = true;
1058         else
1059                 drvdata->retstack = false;
1060
1061         /* NUMEVENT, bits[11:10] Number of events field */
1062         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
1063         /* QSUPP, bits[16:15] Q element support field */
1064         drvdata->q_support = BMVAL(etmidr0, 15, 16);
1065         /* TSSIZE, bits[28:24] Global timestamp size field */
1066         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
1067
1068         /* maximum size of resources */
1069         etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1070         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1071         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
1072         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1073         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
1074         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1075         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
1076
1077         etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1078         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1079         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
1080         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1081         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
1082         drvdata->config.s_ex_level = drvdata->s_ex_level;
1083         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1084         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
1085
1086         /*
1087          * TRCERR, bit[24] whether a trace unit can trace a
1088          * system error exception.
1089          */
1090         if (BMVAL(etmidr3, 24, 24))
1091                 drvdata->trc_error = true;
1092         else
1093                 drvdata->trc_error = false;
1094
1095         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1096         if (BMVAL(etmidr3, 25, 25))
1097                 drvdata->syncpr = true;
1098         else
1099                 drvdata->syncpr = false;
1100
1101         /* STALLCTL, bit[26] is stall control implemented? */
1102         if (BMVAL(etmidr3, 26, 26))
1103                 drvdata->stallctl = true;
1104         else
1105                 drvdata->stallctl = false;
1106
1107         /* SYSSTALL, bit[27] implementation can support stall control? */
1108         if (BMVAL(etmidr3, 27, 27))
1109                 drvdata->sysstall = true;
1110         else
1111                 drvdata->sysstall = false;
1112
1113         /*
1114          * NUMPROC - the number of PEs available for tracing, 5bits
1115          *         = TRCIDR3.bits[13:12]bits[30:28]
1116          *  bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1117          *  bits[3:0] = TRCIDR3.bits[30:28]
1118          */
1119         drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30);
1120
1121         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1122         if (BMVAL(etmidr3, 31, 31))
1123                 drvdata->nooverflow = true;
1124         else
1125                 drvdata->nooverflow = false;
1126
1127         /* number of resources trace unit supports */
1128         etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1129         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1130         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
1131         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1132         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
1133         /*
1134          * NUMRSPAIR, bits[19:16]
1135          * The number of resource pairs conveyed by the HW starts at 0, i.e a
1136          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1137          * As such add 1 to the value of NUMRSPAIR for a better representation.
1138          *
1139          * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1140          * the default TRUE and FALSE resource selectors are omitted.
1141          * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1142          */
1143         drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
1144         if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1145                 drvdata->nr_resource += 1;
1146         /*
1147          * NUMSSCC, bits[23:20] the number of single-shot
1148          * comparator control for tracing. Read any status regs as these
1149          * also contain RO capability data.
1150          */
1151         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
1152         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1153                 drvdata->config.ss_status[i] =
1154                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1155         }
1156         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1157         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
1158         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1159         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
1160
1161         etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1162         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1163         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
1164         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1165         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
1166         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1167         if (BMVAL(etmidr5, 22, 22))
1168                 drvdata->atbtrig = true;
1169         else
1170                 drvdata->atbtrig = false;
1171         /*
1172          * LPOVERRIDE, bit[23] implementation supports
1173          * low-power state override
1174          */
1175         if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up))
1176                 drvdata->lpoverride = true;
1177         else
1178                 drvdata->lpoverride = false;
1179         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1180         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
1181         /* NUMCNTR, bits[30:28] number of counters available for tracing */
1182         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
1183         etm4_cs_lock(drvdata, csa);
1184         cpu_enable_tracing(drvdata);
1185 }
1186
1187 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1188 {
1189         return etm4_get_access_type(config) << TRCVICTLR_EXLEVEL_SHIFT;
1190 }
1191
1192 /* Set ELx trace filter access in the TRCVICTLR register */
1193 static void etm4_set_victlr_access(struct etmv4_config *config)
1194 {
1195         config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1196         config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1197 }
1198
1199 static void etm4_set_default_config(struct etmv4_config *config)
1200 {
1201         /* disable all events tracing */
1202         config->eventctrl0 = 0x0;
1203         config->eventctrl1 = 0x0;
1204
1205         /* disable stalling */
1206         config->stall_ctrl = 0x0;
1207
1208         /* enable trace synchronization every 4096 bytes, if available */
1209         config->syncfreq = 0xC;
1210
1211         /* disable timestamp event */
1212         config->ts_ctrl = 0x0;
1213
1214         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1215         config->vinst_ctrl = BIT(0);
1216
1217         /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1218         etm4_set_victlr_access(config);
1219 }
1220
1221 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1222 {
1223         u64 access_type = 0;
1224
1225         /*
1226          * EXLEVEL_NS, for NonSecure Exception levels.
1227          * The mask here is a generic value and must be
1228          * shifted to the corresponding field for the registers
1229          */
1230         if (!is_kernel_in_hyp_mode()) {
1231                 /* Stay away from hypervisor mode for non-VHE */
1232                 access_type =  ETM_EXLEVEL_NS_HYP;
1233                 if (config->mode & ETM_MODE_EXCL_KERN)
1234                         access_type |= ETM_EXLEVEL_NS_OS;
1235         } else if (config->mode & ETM_MODE_EXCL_KERN) {
1236                 access_type = ETM_EXLEVEL_NS_HYP;
1237         }
1238
1239         if (config->mode & ETM_MODE_EXCL_USER)
1240                 access_type |= ETM_EXLEVEL_NS_APP;
1241
1242         return access_type;
1243 }
1244
1245 /*
1246  * Construct the exception level masks for a given config.
1247  * This must be shifted to the corresponding register field
1248  * for usage.
1249  */
1250 static u64 etm4_get_access_type(struct etmv4_config *config)
1251 {
1252         /* All Secure exception levels are excluded from the trace */
1253         return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1254 }
1255
1256 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1257 {
1258         return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1259 }
1260
1261 static void etm4_set_comparator_filter(struct etmv4_config *config,
1262                                        u64 start, u64 stop, int comparator)
1263 {
1264         u64 access_type = etm4_get_comparator_access_type(config);
1265
1266         /* First half of default address comparator */
1267         config->addr_val[comparator] = start;
1268         config->addr_acc[comparator] = access_type;
1269         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1270
1271         /* Second half of default address comparator */
1272         config->addr_val[comparator + 1] = stop;
1273         config->addr_acc[comparator + 1] = access_type;
1274         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1275
1276         /*
1277          * Configure the ViewInst function to include this address range
1278          * comparator.
1279          *
1280          * @comparator is divided by two since it is the index in the
1281          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1282          * address range comparator _pairs_.
1283          *
1284          * Therefore:
1285          *      index 0 -> compatator pair 0
1286          *      index 2 -> comparator pair 1
1287          *      index 4 -> comparator pair 2
1288          *      ...
1289          *      index 14 -> comparator pair 7
1290          */
1291         config->viiectlr |= BIT(comparator / 2);
1292 }
1293
1294 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1295                                        u64 address, int comparator,
1296                                        enum etm_addr_type type)
1297 {
1298         int shift;
1299         u64 access_type = etm4_get_comparator_access_type(config);
1300
1301         /* Configure the comparator */
1302         config->addr_val[comparator] = address;
1303         config->addr_acc[comparator] = access_type;
1304         config->addr_type[comparator] = type;
1305
1306         /*
1307          * Configure ViewInst Start-Stop control register.
1308          * Addresses configured to start tracing go from bit 0 to n-1,
1309          * while those configured to stop tracing from 16 to 16 + n-1.
1310          */
1311         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1312         config->vissctlr |= BIT(shift + comparator);
1313 }
1314
1315 static void etm4_set_default_filter(struct etmv4_config *config)
1316 {
1317         /* Trace everything 'default' filter achieved by no filtering */
1318         config->viiectlr = 0x0;
1319
1320         /*
1321          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1322          * in the started state
1323          */
1324         config->vinst_ctrl |= BIT(9);
1325         config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1326
1327         /* No start-stop filtering for ViewInst */
1328         config->vissctlr = 0x0;
1329 }
1330
1331 static void etm4_set_default(struct etmv4_config *config)
1332 {
1333         if (WARN_ON_ONCE(!config))
1334                 return;
1335
1336         /*
1337          * Make default initialisation trace everything
1338          *
1339          * This is done by a minimum default config sufficient to enable
1340          * full instruction trace - with a default filter for trace all
1341          * achieved by having no filtering.
1342          */
1343         etm4_set_default_config(config);
1344         etm4_set_default_filter(config);
1345 }
1346
1347 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1348 {
1349         int nr_comparator, index = 0;
1350         struct etmv4_config *config = &drvdata->config;
1351
1352         /*
1353          * nr_addr_cmp holds the number of comparator _pair_, so time 2
1354          * for the total number of comparators.
1355          */
1356         nr_comparator = drvdata->nr_addr_cmp * 2;
1357
1358         /* Go through the tally of comparators looking for a free one. */
1359         while (index < nr_comparator) {
1360                 switch (type) {
1361                 case ETM_ADDR_TYPE_RANGE:
1362                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1363                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1364                                 return index;
1365
1366                         /* Address range comparators go in pairs */
1367                         index += 2;
1368                         break;
1369                 case ETM_ADDR_TYPE_START:
1370                 case ETM_ADDR_TYPE_STOP:
1371                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1372                                 return index;
1373
1374                         /* Start/stop address can have odd indexes */
1375                         index += 1;
1376                         break;
1377                 default:
1378                         return -EINVAL;
1379                 }
1380         }
1381
1382         /* If we are here all the comparators have been used. */
1383         return -ENOSPC;
1384 }
1385
1386 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1387                                   struct perf_event *event)
1388 {
1389         int i, comparator, ret = 0;
1390         u64 address;
1391         struct etmv4_config *config = &drvdata->config;
1392         struct etm_filters *filters = event->hw.addr_filters;
1393
1394         if (!filters)
1395                 goto default_filter;
1396
1397         /* Sync events with what Perf got */
1398         perf_event_addr_filters_sync(event);
1399
1400         /*
1401          * If there are no filters to deal with simply go ahead with
1402          * the default filter, i.e the entire address range.
1403          */
1404         if (!filters->nr_filters)
1405                 goto default_filter;
1406
1407         for (i = 0; i < filters->nr_filters; i++) {
1408                 struct etm_filter *filter = &filters->etm_filter[i];
1409                 enum etm_addr_type type = filter->type;
1410
1411                 /* See if a comparator is free. */
1412                 comparator = etm4_get_next_comparator(drvdata, type);
1413                 if (comparator < 0) {
1414                         ret = comparator;
1415                         goto out;
1416                 }
1417
1418                 switch (type) {
1419                 case ETM_ADDR_TYPE_RANGE:
1420                         etm4_set_comparator_filter(config,
1421                                                    filter->start_addr,
1422                                                    filter->stop_addr,
1423                                                    comparator);
1424                         /*
1425                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1426                          * in the started state
1427                          */
1428                         config->vinst_ctrl |= BIT(9);
1429
1430                         /* No start-stop filtering for ViewInst */
1431                         config->vissctlr = 0x0;
1432                         break;
1433                 case ETM_ADDR_TYPE_START:
1434                 case ETM_ADDR_TYPE_STOP:
1435                         /* Get the right start or stop address */
1436                         address = (type == ETM_ADDR_TYPE_START ?
1437                                    filter->start_addr :
1438                                    filter->stop_addr);
1439
1440                         /* Configure comparator */
1441                         etm4_set_start_stop_filter(config, address,
1442                                                    comparator, type);
1443
1444                         /*
1445                          * If filters::ssstatus == 1, trace acquisition was
1446                          * started but the process was yanked away before the
1447                          * the stop address was hit.  As such the start/stop
1448                          * logic needs to be re-started so that tracing can
1449                          * resume where it left.
1450                          *
1451                          * The start/stop logic status when a process is
1452                          * scheduled out is checked in function
1453                          * etm4_disable_perf().
1454                          */
1455                         if (filters->ssstatus)
1456                                 config->vinst_ctrl |= BIT(9);
1457
1458                         /* No include/exclude filtering for ViewInst */
1459                         config->viiectlr = 0x0;
1460                         break;
1461                 default:
1462                         ret = -EINVAL;
1463                         goto out;
1464                 }
1465         }
1466
1467         goto out;
1468
1469
1470 default_filter:
1471         etm4_set_default_filter(config);
1472
1473 out:
1474         return ret;
1475 }
1476
1477 void etm4_config_trace_mode(struct etmv4_config *config)
1478 {
1479         u32 mode;
1480
1481         mode = config->mode;
1482         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1483
1484         /* excluding kernel AND user space doesn't make sense */
1485         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1486
1487         /* nothing to do if neither flags are set */
1488         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1489                 return;
1490
1491         etm4_set_victlr_access(config);
1492 }
1493
1494 static int etm4_online_cpu(unsigned int cpu)
1495 {
1496         if (!etmdrvdata[cpu])
1497                 return 0;
1498
1499         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1500                 coresight_enable(etmdrvdata[cpu]->csdev);
1501         return 0;
1502 }
1503
1504 static int etm4_starting_cpu(unsigned int cpu)
1505 {
1506         if (!etmdrvdata[cpu])
1507                 return 0;
1508
1509         spin_lock(&etmdrvdata[cpu]->spinlock);
1510         if (!etmdrvdata[cpu]->os_unlock)
1511                 etm4_os_unlock(etmdrvdata[cpu]);
1512
1513         if (local_read(&etmdrvdata[cpu]->mode))
1514                 etm4_enable_hw(etmdrvdata[cpu]);
1515         spin_unlock(&etmdrvdata[cpu]->spinlock);
1516         return 0;
1517 }
1518
1519 static int etm4_dying_cpu(unsigned int cpu)
1520 {
1521         if (!etmdrvdata[cpu])
1522                 return 0;
1523
1524         spin_lock(&etmdrvdata[cpu]->spinlock);
1525         if (local_read(&etmdrvdata[cpu]->mode))
1526                 etm4_disable_hw(etmdrvdata[cpu]);
1527         spin_unlock(&etmdrvdata[cpu]->spinlock);
1528         return 0;
1529 }
1530
1531 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1532 {
1533         drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1534 }
1535
1536 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1537 {
1538         int i, ret = 0;
1539         struct etmv4_save_state *state;
1540         struct coresight_device *csdev = drvdata->csdev;
1541         struct csdev_access *csa;
1542         struct device *etm_dev;
1543
1544         if (WARN_ON(!csdev))
1545                 return -ENODEV;
1546
1547         etm_dev = &csdev->dev;
1548         csa = &csdev->access;
1549
1550         /*
1551          * As recommended by 3.4.1 ("The procedure when powering down the PE")
1552          * of ARM IHI 0064D
1553          */
1554         dsb(sy);
1555         isb();
1556
1557         etm4_cs_unlock(drvdata, csa);
1558         /* Lock the OS lock to disable trace and external debugger access */
1559         etm4_os_lock(drvdata);
1560
1561         /* wait for TRCSTATR.PMSTABLE to go up */
1562         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1563                 dev_err(etm_dev,
1564                         "timeout while waiting for PM Stable Status\n");
1565                 etm4_os_unlock(drvdata);
1566                 ret = -EBUSY;
1567                 goto out;
1568         }
1569
1570         state = drvdata->save_state;
1571
1572         state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1573         if (drvdata->nr_pe)
1574                 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1575         state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1576         state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1577         state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1578         state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1579         if (drvdata->stallctl)
1580                 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1581         state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1582         state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1583         state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1584         state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1585         state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1586         state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1587
1588         state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1589         state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1590         state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1591         if (drvdata->nr_pe_cmp)
1592                 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1593         state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1594         state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1595         state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1596
1597         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1598                 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1599
1600         state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1601         state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1602         state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1603
1604         for (i = 0; i < drvdata->nr_cntr; i++) {
1605                 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1606                 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1607                 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1608         }
1609
1610         for (i = 0; i < drvdata->nr_resource * 2; i++)
1611                 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1612
1613         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1614                 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1615                 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1616                 if (etm4x_sspcicrn_present(drvdata, i))
1617                         state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1618         }
1619
1620         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1621                 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1622                 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1623         }
1624
1625         /*
1626          * Data trace stream is architecturally prohibited for A profile cores
1627          * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1628          * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1629          * unit") of ARM IHI 0064D.
1630          */
1631
1632         for (i = 0; i < drvdata->numcidc; i++)
1633                 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1634
1635         for (i = 0; i < drvdata->numvmidc; i++)
1636                 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1637
1638         state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1639         if (drvdata->numcidc > 4)
1640                 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1641
1642         state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1643         if (drvdata->numvmidc > 4)
1644                 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1645
1646         state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1647
1648         if (!drvdata->skip_power_up)
1649                 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1650
1651         /* wait for TRCSTATR.IDLE to go up */
1652         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1653                 dev_err(etm_dev,
1654                         "timeout while waiting for Idle Trace Status\n");
1655                 etm4_os_unlock(drvdata);
1656                 ret = -EBUSY;
1657                 goto out;
1658         }
1659
1660         drvdata->state_needs_restore = true;
1661
1662         /*
1663          * Power can be removed from the trace unit now. We do this to
1664          * potentially save power on systems that respect the TRCPDCR_PU
1665          * despite requesting software to save/restore state.
1666          */
1667         if (!drvdata->skip_power_up)
1668                 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1669                                       TRCPDCR);
1670 out:
1671         etm4_cs_lock(drvdata, csa);
1672         return ret;
1673 }
1674
1675 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1676 {
1677         int i;
1678         struct etmv4_save_state *state = drvdata->save_state;
1679         struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1680         struct csdev_access *csa = &tmp_csa;
1681
1682         etm4_cs_unlock(drvdata, csa);
1683         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1684
1685         etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1686         if (drvdata->nr_pe)
1687                 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1688         etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1689         etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1690         etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1691         etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1692         if (drvdata->stallctl)
1693                 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1694         etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1695         etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1696         etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1697         etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1698         etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1699         etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1700
1701         etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1702         etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1703         etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1704         if (drvdata->nr_pe_cmp)
1705                 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1706         etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1707         etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1708         etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1709
1710         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1711                 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1712
1713         etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1714         etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1715         etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1716
1717         for (i = 0; i < drvdata->nr_cntr; i++) {
1718                 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1719                 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1720                 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1721         }
1722
1723         for (i = 0; i < drvdata->nr_resource * 2; i++)
1724                 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1725
1726         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1727                 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1728                 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1729                 if (etm4x_sspcicrn_present(drvdata, i))
1730                         etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1731         }
1732
1733         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1734                 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1735                 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1736         }
1737
1738         for (i = 0; i < drvdata->numcidc; i++)
1739                 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1740
1741         for (i = 0; i < drvdata->numvmidc; i++)
1742                 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1743
1744         etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1745         if (drvdata->numcidc > 4)
1746                 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1747
1748         etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1749         if (drvdata->numvmidc > 4)
1750                 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1751
1752         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1753
1754         if (!drvdata->skip_power_up)
1755                 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1756
1757         drvdata->state_needs_restore = false;
1758
1759         /*
1760          * As recommended by section 4.3.7 ("Synchronization when using the
1761          * memory-mapped interface") of ARM IHI 0064D
1762          */
1763         dsb(sy);
1764         isb();
1765
1766         /* Unlock the OS lock to re-enable trace and external debug access */
1767         etm4_os_unlock(drvdata);
1768         etm4_cs_lock(drvdata, csa);
1769 }
1770
1771 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1772                               void *v)
1773 {
1774         struct etmv4_drvdata *drvdata;
1775         unsigned int cpu = smp_processor_id();
1776
1777         if (!etmdrvdata[cpu])
1778                 return NOTIFY_OK;
1779
1780         drvdata = etmdrvdata[cpu];
1781
1782         if (!drvdata->save_state)
1783                 return NOTIFY_OK;
1784
1785         if (WARN_ON_ONCE(drvdata->cpu != cpu))
1786                 return NOTIFY_BAD;
1787
1788         switch (cmd) {
1789         case CPU_PM_ENTER:
1790                 /* save the state if self-hosted coresight is in use */
1791                 if (local_read(&drvdata->mode))
1792                         if (etm4_cpu_save(drvdata))
1793                                 return NOTIFY_BAD;
1794                 break;
1795         case CPU_PM_EXIT:
1796         case CPU_PM_ENTER_FAILED:
1797                 if (drvdata->state_needs_restore)
1798                         etm4_cpu_restore(drvdata);
1799                 break;
1800         default:
1801                 return NOTIFY_DONE;
1802         }
1803
1804         return NOTIFY_OK;
1805 }
1806
1807 static struct notifier_block etm4_cpu_pm_nb = {
1808         .notifier_call = etm4_cpu_pm_notify,
1809 };
1810
1811 /* Setup PM. Deals with error conditions and counts */
1812 static int __init etm4_pm_setup(void)
1813 {
1814         int ret;
1815
1816         ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1817         if (ret)
1818                 return ret;
1819
1820         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1821                                         "arm/coresight4:starting",
1822                                         etm4_starting_cpu, etm4_dying_cpu);
1823
1824         if (ret)
1825                 goto unregister_notifier;
1826
1827         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1828                                         "arm/coresight4:online",
1829                                         etm4_online_cpu, NULL);
1830
1831         /* HP dyn state ID returned in ret on success */
1832         if (ret > 0) {
1833                 hp_online = ret;
1834                 return 0;
1835         }
1836
1837         /* failed dyn state - remove others */
1838         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1839
1840 unregister_notifier:
1841         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1842         return ret;
1843 }
1844
1845 static void etm4_pm_clear(void)
1846 {
1847         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1848         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1849         if (hp_online) {
1850                 cpuhp_remove_state_nocalls(hp_online);
1851                 hp_online = 0;
1852         }
1853 }
1854
1855 static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid)
1856 {
1857         int ret;
1858         struct coresight_platform_data *pdata = NULL;
1859         struct etmv4_drvdata *drvdata;
1860         struct coresight_desc desc = { 0 };
1861         struct etm4_init_arg init_arg = { 0 };
1862         u8 major, minor;
1863         char *type_name;
1864
1865         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1866         if (!drvdata)
1867                 return -ENOMEM;
1868
1869         dev_set_drvdata(dev, drvdata);
1870
1871         if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
1872                 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
1873                                PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
1874
1875         if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
1876                 drvdata->save_state = devm_kmalloc(dev,
1877                                 sizeof(struct etmv4_save_state), GFP_KERNEL);
1878                 if (!drvdata->save_state)
1879                         return -ENOMEM;
1880         }
1881
1882         drvdata->base = base;
1883
1884         spin_lock_init(&drvdata->spinlock);
1885
1886         drvdata->cpu = coresight_get_cpu(dev);
1887         if (drvdata->cpu < 0)
1888                 return drvdata->cpu;
1889
1890         init_arg.drvdata = drvdata;
1891         init_arg.csa = &desc.access;
1892         init_arg.pid = etm_pid;
1893
1894         if (smp_call_function_single(drvdata->cpu,
1895                                 etm4_init_arch_data,  &init_arg, 1))
1896                 dev_err(dev, "ETM arch init failed\n");
1897
1898         if (!drvdata->arch)
1899                 return -EINVAL;
1900
1901         /* TRCPDCR is not accessible with system instructions. */
1902         if (!desc.access.io_mem ||
1903             fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1904                 drvdata->skip_power_up = true;
1905
1906         major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
1907         minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
1908
1909         if (etm4x_is_ete(drvdata)) {
1910                 type_name = "ete";
1911                 /* ETE v1 has major version == 0b101. Adjust this for logging.*/
1912                 major -= 4;
1913         } else {
1914                 type_name = "etm";
1915         }
1916
1917         desc.name = devm_kasprintf(dev, GFP_KERNEL,
1918                                    "%s%d", type_name, drvdata->cpu);
1919         if (!desc.name)
1920                 return -ENOMEM;
1921
1922         etm4_init_trace_id(drvdata);
1923         etm4_set_default(&drvdata->config);
1924
1925         pdata = coresight_get_platform_data(dev);
1926         if (IS_ERR(pdata))
1927                 return PTR_ERR(pdata);
1928
1929         dev->platform_data = pdata;
1930
1931         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1932         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1933         desc.ops = &etm4_cs_ops;
1934         desc.pdata = pdata;
1935         desc.dev = dev;
1936         desc.groups = coresight_etmv4_groups;
1937         drvdata->csdev = coresight_register(&desc);
1938         if (IS_ERR(drvdata->csdev))
1939                 return PTR_ERR(drvdata->csdev);
1940
1941         ret = etm_perf_symlink(drvdata->csdev, true);
1942         if (ret) {
1943                 coresight_unregister(drvdata->csdev);
1944                 return ret;
1945         }
1946
1947         etmdrvdata[drvdata->cpu] = drvdata;
1948
1949         dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
1950                  drvdata->cpu, type_name, major, minor);
1951
1952         if (boot_enable) {
1953                 coresight_enable(drvdata->csdev);
1954                 drvdata->boot_enable = true;
1955         }
1956
1957         return 0;
1958 }
1959
1960 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
1961 {
1962         void __iomem *base;
1963         struct device *dev = &adev->dev;
1964         struct resource *res = &adev->res;
1965         int ret;
1966
1967         /* Validity for the resource is already checked by the AMBA core */
1968         base = devm_ioremap_resource(dev, res);
1969         if (IS_ERR(base))
1970                 return PTR_ERR(base);
1971
1972         ret = etm4_probe(dev, base, id->id);
1973         if (!ret)
1974                 pm_runtime_put(&adev->dev);
1975
1976         return ret;
1977 }
1978
1979 static int etm4_probe_platform_dev(struct platform_device *pdev)
1980 {
1981         int ret;
1982
1983         pm_runtime_get_noresume(&pdev->dev);
1984         pm_runtime_set_active(&pdev->dev);
1985         pm_runtime_enable(&pdev->dev);
1986
1987         /*
1988          * System register based devices could match the
1989          * HW by reading appropriate registers on the HW
1990          * and thus we could skip the PID.
1991          */
1992         ret = etm4_probe(&pdev->dev, NULL, 0);
1993
1994         pm_runtime_put(&pdev->dev);
1995         return ret;
1996 }
1997
1998 static struct amba_cs_uci_id uci_id_etm4[] = {
1999         {
2000                 /*  ETMv4 UCI data */
2001                 .devarch        = ETM_DEVARCH_ETMv4x_ARCH,
2002                 .devarch_mask   = ETM_DEVARCH_ID_MASK,
2003                 .devtype        = 0x00000013,
2004         }
2005 };
2006
2007 static void clear_etmdrvdata(void *info)
2008 {
2009         int cpu = *(int *)info;
2010
2011         etmdrvdata[cpu] = NULL;
2012 }
2013
2014 static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
2015 {
2016         etm_perf_symlink(drvdata->csdev, false);
2017         /*
2018          * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2019          * and CPU hotplug call backs.
2020          */
2021         cpus_read_lock();
2022         /*
2023          * The readers for etmdrvdata[] are CPU hotplug call backs
2024          * and PM notification call backs. Change etmdrvdata[i] on
2025          * CPU i ensures these call backs has consistent view
2026          * inside one call back function.
2027          */
2028         if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2029                 etmdrvdata[drvdata->cpu] = NULL;
2030
2031         cpus_read_unlock();
2032
2033         coresight_unregister(drvdata->csdev);
2034
2035         return 0;
2036 }
2037
2038 static void __exit etm4_remove_amba(struct amba_device *adev)
2039 {
2040         struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2041
2042         if (drvdata)
2043                 etm4_remove_dev(drvdata);
2044 }
2045
2046 static int __exit etm4_remove_platform_dev(struct platform_device *pdev)
2047 {
2048         int ret = 0;
2049         struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2050
2051         if (drvdata)
2052                 ret = etm4_remove_dev(drvdata);
2053         pm_runtime_disable(&pdev->dev);
2054         return ret;
2055 }
2056
2057 static const struct amba_id etm4_ids[] = {
2058         CS_AMBA_ID(0x000bb95d),                 /* Cortex-A53 */
2059         CS_AMBA_ID(0x000bb95e),                 /* Cortex-A57 */
2060         CS_AMBA_ID(0x000bb95a),                 /* Cortex-A72 */
2061         CS_AMBA_ID(0x000bb959),                 /* Cortex-A73 */
2062         CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2063         CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2064         CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2065         CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2066         CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2067         CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2068         CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2069         CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2070         CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2071         CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2072         CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2073         CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2074         CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2075         CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2076         {},
2077 };
2078
2079 MODULE_DEVICE_TABLE(amba, etm4_ids);
2080
2081 static struct amba_driver etm4x_amba_driver = {
2082         .drv = {
2083                 .name   = "coresight-etm4x",
2084                 .owner  = THIS_MODULE,
2085                 .suppress_bind_attrs = true,
2086         },
2087         .probe          = etm4_probe_amba,
2088         .remove         = etm4_remove_amba,
2089         .id_table       = etm4_ids,
2090 };
2091
2092 static const struct of_device_id etm4_sysreg_match[] = {
2093         { .compatible   = "arm,coresight-etm4x-sysreg" },
2094         { .compatible   = "arm,embedded-trace-extension" },
2095         {}
2096 };
2097
2098 static struct platform_driver etm4_platform_driver = {
2099         .probe          = etm4_probe_platform_dev,
2100         .remove         = etm4_remove_platform_dev,
2101         .driver                 = {
2102                 .name                   = "coresight-etm4x",
2103                 .of_match_table         = etm4_sysreg_match,
2104                 .suppress_bind_attrs    = true,
2105         },
2106 };
2107
2108 static int __init etm4x_init(void)
2109 {
2110         int ret;
2111
2112         ret = etm4_pm_setup();
2113
2114         /* etm4_pm_setup() does its own cleanup - exit on error */
2115         if (ret)
2116                 return ret;
2117
2118         ret = amba_driver_register(&etm4x_amba_driver);
2119         if (ret) {
2120                 pr_err("Error registering etm4x AMBA driver\n");
2121                 goto clear_pm;
2122         }
2123
2124         ret = platform_driver_register(&etm4_platform_driver);
2125         if (!ret)
2126                 return 0;
2127
2128         pr_err("Error registering etm4x platform driver\n");
2129         amba_driver_unregister(&etm4x_amba_driver);
2130
2131 clear_pm:
2132         etm4_pm_clear();
2133         return ret;
2134 }
2135
2136 static void __exit etm4x_exit(void)
2137 {
2138         amba_driver_unregister(&etm4x_amba_driver);
2139         platform_driver_unregister(&etm4_platform_driver);
2140         etm4_pm_clear();
2141 }
2142
2143 module_init(etm4x_init);
2144 module_exit(etm4x_exit);
2145
2146 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2147 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2148 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2149 MODULE_LICENSE("GPL v2");