drivers/hwtracing/coresight/coresight-etm4x-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/acpi.h>
   7 #include <linux/bitops.h>
   8 #include <linux/kernel.h>
   9 #include <linux/moduleparam.h>
  10 #include <linux/init.h>
  11 #include <linux/types.h>
  12 #include <linux/device.h>
  13 #include <linux/io.h>
  14 #include <linux/err.h>
  15 #include <linux/fs.h>
  16 #include <linux/slab.h>
  17 #include <linux/delay.h>
  18 #include <linux/smp.h>
  19 #include <linux/sysfs.h>
  20 #include <linux/stat.h>
  21 #include <linux/clk.h>
  22 #include <linux/cpu.h>
  23 #include <linux/cpu_pm.h>
  24 #include <linux/coresight.h>
  25 #include <linux/coresight-pmu.h>
  26 #include <linux/pm_wakeup.h>
  27 #include <linux/amba/bus.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/uaccess.h>
  30 #include <linux/perf_event.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/property.h>
  34 #include <linux/clk/clk-conf.h>
  35
  36 #include <asm/barrier.h>
  37 #include <asm/sections.h>
  38 #include <asm/sysreg.h>
  39 #include <asm/local.h>
  40 #include <asm/virt.h>
  41
  42 #include "coresight-etm4x.h"
  43 #include "coresight-etm-perf.h"
  44 #include "coresight-etm4x-cfg.h"
  45 #include "coresight-self-hosted-trace.h"
  46 #include "coresight-syscfg.h"
  47 #include "coresight-trace-id.h"
  48
  49 static int boot_enable;
  50 module_param(boot_enable, int, 0444);
  51 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
  52
  53 #define PARAM_PM_SAVE_FIRMWARE    0 /* save self-hosted state as per firmware */
  54 #define PARAM_PM_SAVE_NEVER       1 /* never save any state */
  55 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
  56
  57 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
  58 module_param(pm_save_enable, int, 0444);
  59 MODULE_PARM_DESC(pm_save_enable,
  60         "Save/restore state on power down: 1 = never, 2 = self-hosted");
  61
  62 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  63 static void etm4_set_default_config(struct etmv4_config *config);
  64 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
  65                                   struct perf_event *event);
  66 static u64 etm4_get_access_type(struct etmv4_config *config);
  67
  68 static enum cpuhp_state hp_online;
  69
  70 struct etm4_init_arg {
  71         struct device           *dev;
  72         struct csdev_access     *csa;
  73 };
  74
  75 static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe);
  76 static int etm4_probe_cpu(unsigned int cpu);
  77
  78 /*
  79  * Check if TRCSSPCICRn(i) is implemented for a given instance.
  80  *
  81  * TRCSSPCICRn is implemented only if :
  82  *      TRCSSPCICR<n> is present only if all of the following are true:
  83  *              TRCIDR4.NUMSSCC > n.
  84  *              TRCIDR4.NUMPC > 0b0000 .
  85  *              TRCSSCSR<n>.PC == 0b1
  86  */
  87 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
  88 {
  89         return (n < drvdata->nr_ss_cmp) &&
  90                drvdata->nr_pe &&
  91                (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
  92 }
  93
  94 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
  95 {
  96         u64 res = 0;
  97
  98         switch (offset) {
  99         ETM4x_READ_SYSREG_CASES(res)
 100         default :
 101                 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
 102                          offset);
 103         }
 104
 105         if (!_relaxed)
 106                 __io_ar(res);   /* Imitate the !relaxed I/O helpers */
 107
 108         return res;
 109 }
 110
 111 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
 112 {
 113         if (!_relaxed)
 114                 __io_bw();      /* Imitate the !relaxed I/O helpers */
 115         if (!_64bit)
 116                 val &= GENMASK(31, 0);
 117
 118         switch (offset) {
 119         ETM4x_WRITE_SYSREG_CASES(val)
 120         default :
 121                 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
 122                         offset);
 123         }
 124 }
 125
 126 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
 127 {
 128         u64 res = 0;
 129
 130         switch (offset) {
 131         ETE_READ_CASES(res)
 132         default :
 133                 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
 134                                     offset);
 135         }
 136
 137         if (!_relaxed)
 138                 __io_ar(res);   /* Imitate the !relaxed I/O helpers */
 139
 140         return res;
 141 }
 142
 143 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
 144 {
 145         if (!_relaxed)
 146                 __io_bw();      /* Imitate the !relaxed I/O helpers */
 147         if (!_64bit)
 148                 val &= GENMASK(31, 0);
 149
 150         switch (offset) {
 151         ETE_WRITE_CASES(val)
 152         default :
 153                 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
 154                                     offset);
 155         }
 156 }
 157
 158 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
 159                                struct csdev_access *csa)
 160 {
 161         u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
 162
 163         drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
 164 }
 165
 166 static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
 167                               struct csdev_access *csa, u32 val)
 168 {
 169         val = !!val;
 170
 171         switch (drvdata->os_lock_model) {
 172         case ETM_OSLOCK_PRESENT:
 173                 etm4x_relaxed_write32(csa, val, TRCOSLAR);
 174                 break;
 175         case ETM_OSLOCK_PE:
 176                 write_sysreg_s(val, SYS_OSLAR_EL1);
 177                 break;
 178         default:
 179                 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
 180                              smp_processor_id(), drvdata->os_lock_model);
 181                 fallthrough;
 182         case ETM_OSLOCK_NI:
 183                 return;
 184         }
 185         isb();
 186 }
 187
 188 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
 189                                       struct csdev_access *csa)
 190 {
 191         WARN_ON(drvdata->cpu != smp_processor_id());
 192
 193         /* Writing 0 to OS Lock unlocks the trace unit registers */
 194         etm_write_os_lock(drvdata, csa, 0x0);
 195         drvdata->os_unlock = true;
 196 }
 197
 198 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
 199 {
 200         if (!WARN_ON(!drvdata->csdev))
 201                 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
 202 }
 203
 204 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
 205 {
 206         if (WARN_ON(!drvdata->csdev))
 207                 return;
 208         /* Writing 0x1 to OS Lock locks the trace registers */
 209         etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
 210         drvdata->os_unlock = false;
 211 }
 212
 213 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
 214                          struct csdev_access *csa)
 215 {
 216         /* Software Lock is only accessible via memory mapped interface */
 217         if (csa->io_mem)
 218                 CS_LOCK(csa->base);
 219 }
 220
 221 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
 222                            struct csdev_access *csa)
 223 {
 224         if (csa->io_mem)
 225                 CS_UNLOCK(csa->base);
 226 }
 227
 228 static int etm4_cpu_id(struct coresight_device *csdev)
 229 {
 230         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 231
 232         return drvdata->cpu;
 233 }
 234
 235 int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata)
 236 {
 237         int trace_id;
 238
 239         /*
 240          * This will allocate a trace ID to the cpu,
 241          * or return the one currently allocated.
 242          * The trace id function has its own lock
 243          */
 244         trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
 245         if (IS_VALID_CS_TRACE_ID(trace_id))
 246                 drvdata->trcid = (u8)trace_id;
 247         else
 248                 dev_err(&drvdata->csdev->dev,
 249                         "Failed to allocate trace ID for %s on CPU%d\n",
 250                         dev_name(&drvdata->csdev->dev), drvdata->cpu);
 251         return trace_id;
 252 }
 253
 254 void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
 255 {
 256         coresight_trace_id_put_cpu_id(drvdata->cpu);
 257 }
 258
 259 struct etm4_enable_arg {
 260         struct etmv4_drvdata *drvdata;
 261         int rc;
 262 };
 263
 264 /*
 265  * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
 266  * When the CPU supports FEAT_TRF, we could move the ETM to a trace
 267  * prohibited state by filtering the Exception levels via TRFCR_EL1.
 268  */
 269 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
 270 {
 271         /* If the CPU doesn't support FEAT_TRF, nothing to do */
 272         if (!drvdata->trfcr)
 273                 return;
 274         cpu_prohibit_trace();
 275 }
 276
 277 /*
 278  * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
 279  * as configured by the drvdata->config.mode for the current
 280  * session. Even though we have TRCVICTLR bits to filter the
 281  * trace in the ELs, it doesn't prevent the ETM from generating
 282  * a packet (e.g, TraceInfo) that might contain the addresses from
 283  * the excluded levels. Thus we use the additional controls provided
 284  * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
 285  * is generated for the excluded ELs.
 286  */
 287 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
 288 {
 289         u64 trfcr = drvdata->trfcr;
 290
 291         /* If the CPU doesn't support FEAT_TRF, nothing to do */
 292         if (!trfcr)
 293                 return;
 294
 295         if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
 296                 trfcr &= ~TRFCR_ELx_ExTRE;
 297         if (drvdata->config.mode & ETM_MODE_EXCL_USER)
 298                 trfcr &= ~TRFCR_ELx_E0TRE;
 299
 300         write_trfcr(trfcr);
 301 }
 302
 303 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
 304
 305 #define HISI_HIP08_AMBA_ID              0x000b6d01
 306 #define ETM4_AMBA_MASK                  0xfffff
 307 #define HISI_HIP08_CORE_COMMIT_MASK     0x3000
 308 #define HISI_HIP08_CORE_COMMIT_SHIFT    12
 309 #define HISI_HIP08_CORE_COMMIT_FULL     0b00
 310 #define HISI_HIP08_CORE_COMMIT_LVL_1    0b01
 311 #define HISI_HIP08_CORE_COMMIT_REG      sys_reg(3, 1, 15, 2, 5)
 312
 313 struct etm4_arch_features {
 314         void (*arch_callback)(bool enable);
 315 };
 316
 317 static bool etm4_hisi_match_pid(unsigned int id)
 318 {
 319         return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
 320 }
 321
 322 static void etm4_hisi_config_core_commit(bool enable)
 323 {
 324         u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
 325                     HISI_HIP08_CORE_COMMIT_FULL;
 326         u64 val;
 327
 328         /*
 329          * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
 330          * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
 331          * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
 332          * speed(minimun value). So bit 12 and 13 should be cleared together.
 333          */
 334         val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
 335         val &= ~HISI_HIP08_CORE_COMMIT_MASK;
 336         val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
 337         write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
 338 }
 339
 340 static struct etm4_arch_features etm4_features[] = {
 341         [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
 342                 .arch_callback = etm4_hisi_config_core_commit,
 343         },
 344         {},
 345 };
 346
 347 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 348 {
 349         struct etm4_arch_features *ftr;
 350         int bit;
 351
 352         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 353                 ftr = &etm4_features[bit];
 354
 355                 if (ftr->arch_callback)
 356                         ftr->arch_callback(true);
 357         }
 358 }
 359
 360 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 361 {
 362         struct etm4_arch_features *ftr;
 363         int bit;
 364
 365         for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
 366                 ftr = &etm4_features[bit];
 367
 368                 if (ftr->arch_callback)
 369                         ftr->arch_callback(false);
 370         }
 371 }
 372
 373 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 374                                      struct csdev_access *csa)
 375 {
 376         /*
 377          * TRCPIDR* registers are not required for ETMs with system
 378          * instructions. They must be identified by the MIDR+REVIDRs.
 379          * Skip the TRCPID checks for now.
 380          */
 381         if (!csa->io_mem)
 382                 return;
 383
 384         if (etm4_hisi_match_pid(coresight_get_pid(csa)))
 385                 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
 386 }
 387 #else
 388 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
 389 {
 390 }
 391
 392 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
 393 {
 394 }
 395
 396 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
 397                                      struct csdev_access *csa)
 398 {
 399 }
 400 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
 401
 402 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 403 {
 404         int i, rc;
 405         struct etmv4_config *config = &drvdata->config;
 406         struct coresight_device *csdev = drvdata->csdev;
 407         struct device *etm_dev = &csdev->dev;
 408         struct csdev_access *csa = &csdev->access;
 409
 410
 411         etm4_cs_unlock(drvdata, csa);
 412         etm4_enable_arch_specific(drvdata);
 413
 414         etm4_os_unlock(drvdata);
 415
 416         rc = coresight_claim_device_unlocked(csdev);
 417         if (rc)
 418                 goto done;
 419
 420         /* Disable the trace unit before programming trace registers */
 421         etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
 422
 423         /*
 424          * If we use system instructions, we need to synchronize the
 425          * write to the TRCPRGCTLR, before accessing the TRCSTATR.
 426          * See ARM IHI0064F, section
 427          * "4.3.7 Synchronization of register updates"
 428          */
 429         if (!csa->io_mem)
 430                 isb();
 431
 432         /* wait for TRCSTATR.IDLE to go up */
 433         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 434                 dev_err(etm_dev,
 435                         "timeout while waiting for Idle Trace Status\n");
 436         if (drvdata->nr_pe)
 437                 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
 438         etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
 439         /* nothing specific implemented */
 440         etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
 441         etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
 442         etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
 443         if (drvdata->stallctl)
 444                 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
 445         etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
 446         etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
 447         etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
 448         etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
 449         etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
 450         etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
 451         etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
 452         etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
 453         if (drvdata->nr_pe_cmp)
 454                 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
 455         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 456                 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
 457         if (drvdata->nrseqstate) {
 458                 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
 459                 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
 460         }
 461         etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
 462         for (i = 0; i < drvdata->nr_cntr; i++) {
 463                 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
 464                 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
 465                 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
 466         }
 467
 468         /*
 469          * Resource selector pair 0 is always implemented and reserved.  As
 470          * such start at 2.
 471          */
 472         for (i = 2; i < drvdata->nr_resource * 2; i++)
 473                 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
 474
 475         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 476                 /* always clear status bit on restart if using single-shot */
 477                 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
 478                         config->ss_status[i] &= ~TRCSSCSRn_STATUS;
 479                 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
 480                 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
 481                 if (etm4x_sspcicrn_present(drvdata, i))
 482                         etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
 483         }
 484         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
 485                 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
 486                 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
 487         }
 488         for (i = 0; i < drvdata->numcidc; i++)
 489                 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
 490         etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
 491         if (drvdata->numcidc > 4)
 492                 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
 493
 494         for (i = 0; i < drvdata->numvmidc; i++)
 495                 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
 496         etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
 497         if (drvdata->numvmidc > 4)
 498                 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
 499
 500         if (!drvdata->skip_power_up) {
 501                 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
 502
 503                 /*
 504                  * Request to keep the trace unit powered and also
 505                  * emulation of powerdown
 506                  */
 507                 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
 508         }
 509
 510         /*
 511          * ETE mandates that the TRCRSR is written to before
 512          * enabling it.
 513          */
 514         if (etm4x_is_ete(drvdata))
 515                 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
 516
 517         etm4x_allow_trace(drvdata);
 518         /* Enable the trace unit */
 519         etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
 520
 521         /* Synchronize the register updates for sysreg access */
 522         if (!csa->io_mem)
 523                 isb();
 524
 525         /* wait for TRCSTATR.IDLE to go back down to '0' */
 526         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 527                 dev_err(etm_dev,
 528                         "timeout while waiting for Idle Trace Status\n");
 529
 530         /*
 531          * As recommended by section 4.3.7 ("Synchronization when using the
 532          * memory-mapped interface") of ARM IHI 0064D
 533          */
 534         dsb(sy);
 535         isb();
 536
 537 done:
 538         etm4_cs_lock(drvdata, csa);
 539
 540         dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
 541                 drvdata->cpu, rc);
 542         return rc;
 543 }
 544
 545 static void etm4_enable_hw_smp_call(void *info)
 546 {
 547         struct etm4_enable_arg *arg = info;
 548
 549         if (WARN_ON(!arg))
 550                 return;
 551         arg->rc = etm4_enable_hw(arg->drvdata);
 552 }
 553
 554 /*
 555  * The goal of function etm4_config_timestamp_event() is to configure a
 556  * counter that will tell the tracer to emit a timestamp packet when it
 557  * reaches zero.  This is done in order to get a more fine grained idea
 558  * of when instructions are executed so that they can be correlated
 559  * with execution on other CPUs.
 560  *
 561  * To do this the counter itself is configured to self reload and
 562  * TRCRSCTLR1 (always true) used to get the counter to decrement.  From
 563  * there a resource selector is configured with the counter and the
 564  * timestamp control register to use the resource selector to trigger the
 565  * event that will insert a timestamp packet in the stream.
 566  */
 567 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
 568 {
 569         int ctridx, ret = -EINVAL;
 570         int counter, rselector;
 571         u32 val = 0;
 572         struct etmv4_config *config = &drvdata->config;
 573
 574         /* No point in trying if we don't have at least one counter */
 575         if (!drvdata->nr_cntr)
 576                 goto out;
 577
 578         /* Find a counter that hasn't been initialised */
 579         for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
 580                 if (config->cntr_val[ctridx] == 0)
 581                         break;
 582
 583         /* All the counters have been configured already, bail out */
 584         if (ctridx == drvdata->nr_cntr) {
 585                 pr_debug("%s: no available counter found\n", __func__);
 586                 ret = -ENOSPC;
 587                 goto out;
 588         }
 589
 590         /*
 591          * Searching for an available resource selector to use, starting at
 592          * '2' since every implementation has at least 2 resource selector.
 593          * ETMIDR4 gives the number of resource selector _pairs_,
 594          * hence multiply by 2.
 595          */
 596         for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
 597                 if (!config->res_ctrl[rselector])
 598                         break;
 599
 600         if (rselector == drvdata->nr_resource * 2) {
 601                 pr_debug("%s: no available resource selector found\n",
 602                          __func__);
 603                 ret = -ENOSPC;
 604                 goto out;
 605         }
 606
 607         /* Remember what counter we used */
 608         counter = 1 << ctridx;
 609
 610         /*
 611          * Initialise original and reload counter value to the smallest
 612          * possible value in order to get as much precision as we can.
 613          */
 614         config->cntr_val[ctridx] = 1;
 615         config->cntrldvr[ctridx] = 1;
 616
 617         /* Set the trace counter control register */
 618         val =  0x1 << 16        |  /* Bit 16, reload counter automatically */
 619                0x0 << 7         |  /* Select single resource selector */
 620                0x1;                /* Resource selector 1, i.e always true */
 621
 622         config->cntr_ctrl[ctridx] = val;
 623
 624         val = 0x2 << 16         | /* Group 0b0010 - Counter and sequencers */
 625               counter << 0;       /* Counter to use */
 626
 627         config->res_ctrl[rselector] = val;
 628
 629         val = 0x0 << 7          | /* Select single resource selector */
 630               rselector;          /* Resource selector */
 631
 632         config->ts_ctrl = val;
 633
 634         ret = 0;
 635 out:
 636         return ret;
 637 }
 638
 639 static int etm4_parse_event_config(struct coresight_device *csdev,
 640                                    struct perf_event *event)
 641 {
 642         int ret = 0;
 643         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 644         struct etmv4_config *config = &drvdata->config;
 645         struct perf_event_attr *attr = &event->attr;
 646         unsigned long cfg_hash;
 647         int preset, cc_threshold;
 648
 649         /* Clear configuration from previous run */
 650         memset(config, 0, sizeof(struct etmv4_config));
 651
 652         if (attr->exclude_kernel)
 653                 config->mode = ETM_MODE_EXCL_KERN;
 654
 655         if (attr->exclude_user)
 656                 config->mode = ETM_MODE_EXCL_USER;
 657
 658         /* Always start from the default config */
 659         etm4_set_default_config(config);
 660
 661         /* Configure filters specified on the perf cmd line, if any. */
 662         ret = etm4_set_event_filters(drvdata, event);
 663         if (ret)
 664                 goto out;
 665
 666         /* Go from generic option to ETMv4 specifics */
 667         if (attr->config & BIT(ETM_OPT_CYCACC)) {
 668                 config->cfg |= TRCCONFIGR_CCI;
 669                 /* TRM: Must program this for cycacc to work */
 670                 cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK;
 671                 if (!cc_threshold)
 672                         cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;
 673                 if (cc_threshold < drvdata->ccitmin)
 674                         cc_threshold = drvdata->ccitmin;
 675                 config->ccctlr = cc_threshold;
 676         }
 677         if (attr->config & BIT(ETM_OPT_TS)) {
 678                 /*
 679                  * Configure timestamps to be emitted at regular intervals in
 680                  * order to correlate instructions executed on different CPUs
 681                  * (CPU-wide trace scenarios).
 682                  */
 683                 ret = etm4_config_timestamp_event(drvdata);
 684
 685                 /*
 686                  * No need to go further if timestamp intervals can't
 687                  * be configured.
 688                  */
 689                 if (ret)
 690                         goto out;
 691
 692                 /* bit[11], Global timestamp tracing bit */
 693                 config->cfg |= TRCCONFIGR_TS;
 694         }
 695
 696         /* Only trace contextID when runs in root PID namespace */
 697         if ((attr->config & BIT(ETM_OPT_CTXTID)) &&
 698             task_is_in_init_pid_ns(current))
 699                 /* bit[6], Context ID tracing bit */
 700                 config->cfg |= TRCCONFIGR_CID;
 701
 702         /*
 703          * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
 704          * for recording CONTEXTIDR_EL2.  Do not enable VMID tracing if the
 705          * kernel is not running in EL2.
 706          */
 707         if (attr->config & BIT(ETM_OPT_CTXTID2)) {
 708                 if (!is_kernel_in_hyp_mode()) {
 709                         ret = -EINVAL;
 710                         goto out;
 711                 }
 712                 /* Only trace virtual contextID when runs in root PID namespace */
 713                 if (task_is_in_init_pid_ns(current))
 714                         config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT;
 715         }
 716
 717         /* return stack - enable if selected and supported */
 718         if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
 719                 /* bit[12], Return stack enable bit */
 720                 config->cfg |= TRCCONFIGR_RS;
 721
 722         /*
 723          * Set any selected configuration and preset.
 724          *
 725          * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
 726          * in the perf attributes defined in coresight-etm-perf.c.
 727          * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
 728          * A zero configid means no configuration active, preset = 0 means no preset selected.
 729          */
 730         if (attr->config2 & GENMASK_ULL(63, 32)) {
 731                 cfg_hash = (u32)(attr->config2 >> 32);
 732                 preset = attr->config & 0xF;
 733                 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
 734         }
 735
 736         /* branch broadcast - enable if selected and supported */
 737         if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
 738                 if (!drvdata->trcbb) {
 739                         /*
 740                          * Missing BB support could cause silent decode errors
 741                          * so fail to open if it's not supported.
 742                          */
 743                         ret = -EINVAL;
 744                         goto out;
 745                 } else {
 746                         config->cfg |= BIT(ETM4_CFG_BIT_BB);
 747                 }
 748         }
 749
 750 out:
 751         return ret;
 752 }
 753
 754 static int etm4_enable_perf(struct coresight_device *csdev,
 755                             struct perf_event *event)
 756 {
 757         int ret = 0, trace_id;
 758         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 759
 760         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
 761                 ret = -EINVAL;
 762                 goto out;
 763         }
 764
 765         /* Configure the tracer based on the session's specifics */
 766         ret = etm4_parse_event_config(csdev, event);
 767         if (ret)
 768                 goto out;
 769
 770         /*
 771          * perf allocates cpu ids as part of _setup_aux() - device needs to use
 772          * the allocated ID. This reads the current version without allocation.
 773          *
 774          * This does not use the trace id lock to prevent lock_dep issues
 775          * with perf locks - we know the ID cannot change until perf shuts down
 776          * the session
 777          */
 778         trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu);
 779         if (!IS_VALID_CS_TRACE_ID(trace_id)) {
 780                 dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
 781                         dev_name(&drvdata->csdev->dev), drvdata->cpu);
 782                 ret = -EINVAL;
 783                 goto out;
 784         }
 785         drvdata->trcid = (u8)trace_id;
 786
 787         /* And enable it */
 788         ret = etm4_enable_hw(drvdata);
 789
 790 out:
 791         return ret;
 792 }
 793
 794 static int etm4_enable_sysfs(struct coresight_device *csdev)
 795 {
 796         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 797         struct etm4_enable_arg arg = { };
 798         unsigned long cfg_hash;
 799         int ret, preset;
 800
 801         /* enable any config activated by configfs */
 802         cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
 803         if (cfg_hash) {
 804                 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
 805                 if (ret)
 806                         return ret;
 807         }
 808
 809         spin_lock(&drvdata->spinlock);
 810
 811         /* sysfs needs to read and allocate a trace ID */
 812         ret = etm4_read_alloc_trace_id(drvdata);
 813         if (ret < 0)
 814                 goto unlock_sysfs_enable;
 815
 816         /*
 817          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 818          * ensures that register writes occur when cpu is powered.
 819          */
 820         arg.drvdata = drvdata;
 821         ret = smp_call_function_single(drvdata->cpu,
 822                                        etm4_enable_hw_smp_call, &arg, 1);
 823         if (!ret)
 824                 ret = arg.rc;
 825         if (!ret)
 826                 drvdata->sticky_enable = true;
 827
 828         if (ret)
 829                 etm4_release_trace_id(drvdata);
 830
 831 unlock_sysfs_enable:
 832         spin_unlock(&drvdata->spinlock);
 833
 834         if (!ret)
 835                 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
 836         return ret;
 837 }
 838
 839 static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
 840                        enum cs_mode mode)
 841 {
 842         int ret;
 843         u32 val;
 844
 845         val = local_cmpxchg(&csdev->mode, CS_MODE_DISABLED, mode);
 846
 847         /* Someone is already using the tracer */
 848         if (val)
 849                 return -EBUSY;
 850
 851         switch (mode) {
 852         case CS_MODE_SYSFS:
 853                 ret = etm4_enable_sysfs(csdev);
 854                 break;
 855         case CS_MODE_PERF:
 856                 ret = etm4_enable_perf(csdev, event);
 857                 break;
 858         default:
 859                 ret = -EINVAL;
 860         }
 861
 862         /* The tracer didn't start */
 863         if (ret)
 864                 local_set(&csdev->mode, CS_MODE_DISABLED);
 865
 866         return ret;
 867 }
 868
 869 static void etm4_disable_hw(void *info)
 870 {
 871         u32 control;
 872         struct etmv4_drvdata *drvdata = info;
 873         struct etmv4_config *config = &drvdata->config;
 874         struct coresight_device *csdev = drvdata->csdev;
 875         struct device *etm_dev = &csdev->dev;
 876         struct csdev_access *csa = &csdev->access;
 877         int i;
 878
 879         etm4_cs_unlock(drvdata, csa);
 880         etm4_disable_arch_specific(drvdata);
 881
 882         if (!drvdata->skip_power_up) {
 883                 /* power can be removed from the trace unit now */
 884                 control = etm4x_relaxed_read32(csa, TRCPDCR);
 885                 control &= ~TRCPDCR_PU;
 886                 etm4x_relaxed_write32(csa, control, TRCPDCR);
 887         }
 888
 889         control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
 890
 891         /* EN, bit[0] Trace unit enable bit */
 892         control &= ~0x1;
 893
 894         /*
 895          * If the CPU supports v8.4 Trace filter Control,
 896          * set the ETM to trace prohibited region.
 897          */
 898         etm4x_prohibit_trace(drvdata);
 899         /*
 900          * Make sure everything completes before disabling, as recommended
 901          * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
 902          * SSTATUS") of ARM IHI 0064D
 903          */
 904         dsb(sy);
 905         isb();
 906         /* Trace synchronization barrier, is a nop if not supported */
 907         tsb_csync();
 908         etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
 909
 910         /* wait for TRCSTATR.PMSTABLE to go to '1' */
 911         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
 912                 dev_err(etm_dev,
 913                         "timeout while waiting for PM stable Trace Status\n");
 914         /* read the status of the single shot comparators */
 915         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 916                 config->ss_status[i] =
 917                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
 918         }
 919
 920         /* read back the current counter values */
 921         for (i = 0; i < drvdata->nr_cntr; i++) {
 922                 config->cntr_val[i] =
 923                         etm4x_relaxed_read32(csa, TRCCNTVRn(i));
 924         }
 925
 926         coresight_disclaim_device_unlocked(csdev);
 927         etm4_cs_lock(drvdata, csa);
 928
 929         dev_dbg(&drvdata->csdev->dev,
 930                 "cpu: %d disable smp call done\n", drvdata->cpu);
 931 }
 932
 933 static int etm4_disable_perf(struct coresight_device *csdev,
 934                              struct perf_event *event)
 935 {
 936         u32 control;
 937         struct etm_filters *filters = event->hw.addr_filters;
 938         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 939         struct perf_event_attr *attr = &event->attr;
 940
 941         if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
 942                 return -EINVAL;
 943
 944         etm4_disable_hw(drvdata);
 945         /*
 946          * The config_id occupies bits 63:32 of the config2 perf event attr
 947          * field. If this is non-zero then we will have enabled a config.
 948          */
 949         if (attr->config2 & GENMASK_ULL(63, 32))
 950                 cscfg_csdev_disable_active_config(csdev);
 951
 952         /*
 953          * Check if the start/stop logic was active when the unit was stopped.
 954          * That way we can re-enable the start/stop logic when the process is
 955          * scheduled again.  Configuration of the start/stop logic happens in
 956          * function etm4_set_event_filters().
 957          */
 958         control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
 959         /* TRCVICTLR::SSSTATUS, bit[9] */
 960         filters->ssstatus = (control & BIT(9));
 961
 962         /*
 963          * perf will release trace ids when _free_aux() is
 964          * called at the end of the session.
 965          */
 966
 967         return 0;
 968 }
 969
 970 static void etm4_disable_sysfs(struct coresight_device *csdev)
 971 {
 972         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 973
 974         /*
 975          * Taking hotplug lock here protects from clocks getting disabled
 976          * with tracing being left on (crash scenario) if user disable occurs
 977          * after cpu online mask indicates the cpu is offline but before the
 978          * DYING hotplug callback is serviced by the ETM driver.
 979          */
 980         cpus_read_lock();
 981         spin_lock(&drvdata->spinlock);
 982
 983         /*
 984          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 985          * ensures that register writes occur when cpu is powered.
 986          */
 987         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 988
 989         spin_unlock(&drvdata->spinlock);
 990         cpus_read_unlock();
 991
 992         /*
 993          * we only release trace IDs when resetting sysfs.
 994          * This permits sysfs users to read the trace ID after the trace
 995          * session has completed. This maintains operational behaviour with
 996          * prior trace id allocation method
 997          */
 998
 999         dev_dbg(&csdev->dev, "ETM tracing disabled\n");
1000 }
1001
1002 static void etm4_disable(struct coresight_device *csdev,
1003                          struct perf_event *event)
1004 {
1005         enum cs_mode mode;
1006
1007         /*
1008          * For as long as the tracer isn't disabled another entity can't
1009          * change its status.  As such we can read the status here without
1010          * fearing it will change under us.
1011          */
1012         mode = local_read(&csdev->mode);
1013
1014         switch (mode) {
1015         case CS_MODE_DISABLED:
1016                 break;
1017         case CS_MODE_SYSFS:
1018                 etm4_disable_sysfs(csdev);
1019                 break;
1020         case CS_MODE_PERF:
1021                 etm4_disable_perf(csdev, event);
1022                 break;
1023         }
1024
1025         if (mode)
1026                 local_set(&csdev->mode, CS_MODE_DISABLED);
1027 }
1028
1029 static const struct coresight_ops_source etm4_source_ops = {
1030         .cpu_id         = etm4_cpu_id,
1031         .enable         = etm4_enable,
1032         .disable        = etm4_disable,
1033 };
1034
1035 static const struct coresight_ops etm4_cs_ops = {
1036         .source_ops     = &etm4_source_ops,
1037 };
1038
1039 static inline bool cpu_supports_sysreg_trace(void)
1040 {
1041         u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
1042
1043         return ((dfr0 >> ID_AA64DFR0_EL1_TraceVer_SHIFT) & 0xfUL) > 0;
1044 }
1045
1046 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
1047                                     struct csdev_access *csa)
1048 {
1049         u32 devarch;
1050
1051         if (!cpu_supports_sysreg_trace())
1052                 return false;
1053
1054         /*
1055          * ETMs implementing sysreg access must implement TRCDEVARCH.
1056          */
1057         devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
1058         switch (devarch & ETM_DEVARCH_ID_MASK) {
1059         case ETM_DEVARCH_ETMv4x_ARCH:
1060                 *csa = (struct csdev_access) {
1061                         .io_mem = false,
1062                         .read   = etm4x_sysreg_read,
1063                         .write  = etm4x_sysreg_write,
1064                 };
1065                 break;
1066         case ETM_DEVARCH_ETE_ARCH:
1067                 *csa = (struct csdev_access) {
1068                         .io_mem = false,
1069                         .read   = ete_sysreg_read,
1070                         .write  = ete_sysreg_write,
1071                 };
1072                 break;
1073         default:
1074                 return false;
1075         }
1076
1077         drvdata->arch = etm_devarch_to_arch(devarch);
1078         return true;
1079 }
1080
1081 static bool is_devtype_cpu_trace(void __iomem *base)
1082 {
1083         u32 devtype = readl(base + TRCDEVTYPE);
1084
1085         return (devtype == CS_DEVTYPE_PE_TRACE);
1086 }
1087
1088 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
1089                                    struct csdev_access *csa)
1090 {
1091         u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
1092
1093         if (!is_coresight_device(drvdata->base) || !is_devtype_cpu_trace(drvdata->base))
1094                 return false;
1095
1096         /*
1097          * All ETMs must implement TRCDEVARCH to indicate that
1098          * the component is an ETMv4. Even though TRCIDR1 also
1099          * contains the information, it is part of the "Trace"
1100          * register and must be accessed with the OSLK cleared,
1101          * with MMIO. But we cannot touch the OSLK until we are
1102          * sure this is an ETM. So rely only on the TRCDEVARCH.
1103          */
1104         if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) {
1105                 pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n");
1106                 return false;
1107         }
1108
1109         drvdata->arch = etm_devarch_to_arch(devarch);
1110         *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1111         return true;
1112 }
1113
1114 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
1115                                    struct csdev_access *csa)
1116 {
1117         /*
1118          * Always choose the memory mapped io, if there is
1119          * a memory map to prevent sysreg access on broken
1120          * systems.
1121          */
1122         if (drvdata->base)
1123                 return etm4_init_iomem_access(drvdata, csa);
1124
1125         if (etm4_init_sysreg_access(drvdata, csa))
1126                 return true;
1127
1128         return false;
1129 }
1130
1131 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
1132 {
1133         u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
1134         u64 trfcr;
1135
1136         drvdata->trfcr = 0;
1137         if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT))
1138                 return;
1139
1140         /*
1141          * If the CPU supports v8.4 SelfHosted Tracing, enable
1142          * tracing at the kernel EL and EL0, forcing to use the
1143          * virtual time as the timestamp.
1144          */
1145         trfcr = (TRFCR_ELx_TS_VIRTUAL |
1146                  TRFCR_ELx_ExTRE |
1147                  TRFCR_ELx_E0TRE);
1148
1149         /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
1150         if (is_kernel_in_hyp_mode())
1151                 trfcr |= TRFCR_EL2_CX;
1152
1153         drvdata->trfcr = trfcr;
1154 }
1155
1156 /*
1157  * The following errata on applicable cpu ranges, affect the CCITMIN filed
1158  * in TCRIDR3 register. Software read for the field returns 0x100 limiting
1159  * the cycle threshold granularity, whereas the right value should have
1160  * been 0x4, which is well supported in the hardware.
1161  */
1162 static struct midr_range etm_wrong_ccitmin_cpus[] = {
1163         /* Erratum #1490853 - Cortex-A76 */
1164         MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0),
1165         /* Erratum #1490853 - Neoverse-N1 */
1166         MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0),
1167         /* Erratum #1491015 - Cortex-A77 */
1168         MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0),
1169         /* Erratum #1502854 - Cortex-X1 */
1170         MIDR_REV(MIDR_CORTEX_X1, 0, 0),
1171         /* Erratum #1619801 - Neoverse-V1 */
1172         MIDR_REV(MIDR_NEOVERSE_V1, 0, 0),
1173         {},
1174 };
1175
1176 static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)
1177 {
1178         /*
1179          * Erratum affected cpus will read 256 as the minimum
1180          * instruction trace cycle counting threshold whereas
1181          * the correct value should be 4 instead. Override the
1182          * recorded value for 'drvdata->ccitmin' to workaround
1183          * this problem.
1184          */
1185         if (is_midr_in_range_list(read_cpuid_id(), etm_wrong_ccitmin_cpus)) {
1186                 if (drvdata->ccitmin == 256)
1187                         drvdata->ccitmin = 4;
1188         }
1189 }
1190
1191 static void etm4_init_arch_data(void *info)
1192 {
1193         u32 etmidr0;
1194         u32 etmidr2;
1195         u32 etmidr3;
1196         u32 etmidr4;
1197         u32 etmidr5;
1198         struct etm4_init_arg *init_arg = info;
1199         struct etmv4_drvdata *drvdata;
1200         struct csdev_access *csa;
1201         int i;
1202
1203         drvdata = dev_get_drvdata(init_arg->dev);
1204         csa = init_arg->csa;
1205
1206         /*
1207          * If we are unable to detect the access mechanism,
1208          * or unable to detect the trace unit type, fail
1209          * early.
1210          */
1211         if (!etm4_init_csdev_access(drvdata, csa))
1212                 return;
1213
1214         /* Detect the support for OS Lock before we actually use it */
1215         etm_detect_os_lock(drvdata, csa);
1216
1217         /* Make sure all registers are accessible */
1218         etm4_os_unlock_csa(drvdata, csa);
1219         etm4_cs_unlock(drvdata, csa);
1220
1221         etm4_check_arch_features(drvdata, csa);
1222
1223         /* find all capabilities of the tracing unit */
1224         etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1225
1226         /* INSTP0, bits[2:1] P0 tracing support field */
1227         drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
1228         /* TRCBB, bit[5] Branch broadcast tracing support bit */
1229         drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
1230         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1231         drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
1232         /* TRCCCI, bit[7] Cycle counting instruction bit */
1233         drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
1234         /* RETSTACK, bit[9] Return stack bit */
1235         drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
1236         /* NUMEVENT, bits[11:10] Number of events field */
1237         drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
1238         /* QSUPP, bits[16:15] Q element support field */
1239         drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
1240         /* TSSIZE, bits[28:24] Global timestamp size field */
1241         drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
1242
1243         /* maximum size of resources */
1244         etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1245         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1246         drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
1247         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1248         drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
1249         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1250         drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
1251
1252         etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1253         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1254         drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
1255         etm4_fixup_wrong_ccitmin(drvdata);
1256
1257         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1258         drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
1259         drvdata->config.s_ex_level = drvdata->s_ex_level;
1260         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1261         drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
1262         /*
1263          * TRCERR, bit[24] whether a trace unit can trace a
1264          * system error exception.
1265          */
1266         drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
1267         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1268         drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
1269         /* STALLCTL, bit[26] is stall control implemented? */
1270         drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
1271         /* SYSSTALL, bit[27] implementation can support stall control? */
1272         drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
1273         /*
1274          * NUMPROC - the number of PEs available for tracing, 5bits
1275          *         = TRCIDR3.bits[13:12]bits[30:28]
1276          *  bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1277          *  bits[3:0] = TRCIDR3.bits[30:28]
1278          */
1279         drvdata->nr_pe =  (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
1280                            FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
1281         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1282         drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
1283
1284         /* number of resources trace unit supports */
1285         etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1286         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1287         drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
1288         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1289         drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
1290         /*
1291          * NUMRSPAIR, bits[19:16]
1292          * The number of resource pairs conveyed by the HW starts at 0, i.e a
1293          * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1294          * As such add 1 to the value of NUMRSPAIR for a better representation.
1295          *
1296          * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1297          * the default TRUE and FALSE resource selectors are omitted.
1298          * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1299          */
1300         drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
1301         if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1302                 drvdata->nr_resource += 1;
1303         /*
1304          * NUMSSCC, bits[23:20] the number of single-shot
1305          * comparator control for tracing. Read any status regs as these
1306          * also contain RO capability data.
1307          */
1308         drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
1309         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1310                 drvdata->config.ss_status[i] =
1311                         etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1312         }
1313         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1314         drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
1315         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1316         drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
1317
1318         etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1319         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1320         drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
1321         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1322         drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
1323         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1324         drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
1325         /*
1326          * LPOVERRIDE, bit[23] implementation supports
1327          * low-power state override
1328          */
1329         drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
1330         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1331         drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
1332         /* NUMCNTR, bits[30:28] number of counters available for tracing */
1333         drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
1334         etm4_cs_lock(drvdata, csa);
1335         cpu_detect_trace_filtering(drvdata);
1336 }
1337
1338 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1339 {
1340         return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
1341 }
1342
1343 /* Set ELx trace filter access in the TRCVICTLR register */
1344 static void etm4_set_victlr_access(struct etmv4_config *config)
1345 {
1346         config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1347         config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1348 }
1349
1350 static void etm4_set_default_config(struct etmv4_config *config)
1351 {
1352         /* disable all events tracing */
1353         config->eventctrl0 = 0x0;
1354         config->eventctrl1 = 0x0;
1355
1356         /* disable stalling */
1357         config->stall_ctrl = 0x0;
1358
1359         /* enable trace synchronization every 4096 bytes, if available */
1360         config->syncfreq = 0xC;
1361
1362         /* disable timestamp event */
1363         config->ts_ctrl = 0x0;
1364
1365         /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1366         config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
1367
1368         /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1369         etm4_set_victlr_access(config);
1370 }
1371
1372 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1373 {
1374         u64 access_type = 0;
1375
1376         /*
1377          * EXLEVEL_NS, for NonSecure Exception levels.
1378          * The mask here is a generic value and must be
1379          * shifted to the corresponding field for the registers
1380          */
1381         if (!is_kernel_in_hyp_mode()) {
1382                 /* Stay away from hypervisor mode for non-VHE */
1383                 access_type =  ETM_EXLEVEL_NS_HYP;
1384                 if (config->mode & ETM_MODE_EXCL_KERN)
1385                         access_type |= ETM_EXLEVEL_NS_OS;
1386         } else if (config->mode & ETM_MODE_EXCL_KERN) {
1387                 access_type = ETM_EXLEVEL_NS_HYP;
1388         }
1389
1390         if (config->mode & ETM_MODE_EXCL_USER)
1391                 access_type |= ETM_EXLEVEL_NS_APP;
1392
1393         return access_type;
1394 }
1395
1396 /*
1397  * Construct the exception level masks for a given config.
1398  * This must be shifted to the corresponding register field
1399  * for usage.
1400  */
1401 static u64 etm4_get_access_type(struct etmv4_config *config)
1402 {
1403         /* All Secure exception levels are excluded from the trace */
1404         return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1405 }
1406
1407 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1408 {
1409         return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1410 }
1411
1412 static void etm4_set_comparator_filter(struct etmv4_config *config,
1413                                        u64 start, u64 stop, int comparator)
1414 {
1415         u64 access_type = etm4_get_comparator_access_type(config);
1416
1417         /* First half of default address comparator */
1418         config->addr_val[comparator] = start;
1419         config->addr_acc[comparator] = access_type;
1420         config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1421
1422         /* Second half of default address comparator */
1423         config->addr_val[comparator + 1] = stop;
1424         config->addr_acc[comparator + 1] = access_type;
1425         config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1426
1427         /*
1428          * Configure the ViewInst function to include this address range
1429          * comparator.
1430          *
1431          * @comparator is divided by two since it is the index in the
1432          * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1433          * address range comparator _pairs_.
1434          *
1435          * Therefore:
1436          *      index 0 -> compatator pair 0
1437          *      index 2 -> comparator pair 1
1438          *      index 4 -> comparator pair 2
1439          *      ...
1440          *      index 14 -> comparator pair 7
1441          */
1442         config->viiectlr |= BIT(comparator / 2);
1443 }
1444
1445 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1446                                        u64 address, int comparator,
1447                                        enum etm_addr_type type)
1448 {
1449         int shift;
1450         u64 access_type = etm4_get_comparator_access_type(config);
1451
1452         /* Configure the comparator */
1453         config->addr_val[comparator] = address;
1454         config->addr_acc[comparator] = access_type;
1455         config->addr_type[comparator] = type;
1456
1457         /*
1458          * Configure ViewInst Start-Stop control register.
1459          * Addresses configured to start tracing go from bit 0 to n-1,
1460          * while those configured to stop tracing from 16 to 16 + n-1.
1461          */
1462         shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1463         config->vissctlr |= BIT(shift + comparator);
1464 }
1465
1466 static void etm4_set_default_filter(struct etmv4_config *config)
1467 {
1468         /* Trace everything 'default' filter achieved by no filtering */
1469         config->viiectlr = 0x0;
1470
1471         /*
1472          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1473          * in the started state
1474          */
1475         config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1476         config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1477
1478         /* No start-stop filtering for ViewInst */
1479         config->vissctlr = 0x0;
1480 }
1481
1482 static void etm4_set_default(struct etmv4_config *config)
1483 {
1484         if (WARN_ON_ONCE(!config))
1485                 return;
1486
1487         /*
1488          * Make default initialisation trace everything
1489          *
1490          * This is done by a minimum default config sufficient to enable
1491          * full instruction trace - with a default filter for trace all
1492          * achieved by having no filtering.
1493          */
1494         etm4_set_default_config(config);
1495         etm4_set_default_filter(config);
1496 }
1497
1498 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1499 {
1500         int nr_comparator, index = 0;
1501         struct etmv4_config *config = &drvdata->config;
1502
1503         /*
1504          * nr_addr_cmp holds the number of comparator _pair_, so time 2
1505          * for the total number of comparators.
1506          */
1507         nr_comparator = drvdata->nr_addr_cmp * 2;
1508
1509         /* Go through the tally of comparators looking for a free one. */
1510         while (index < nr_comparator) {
1511                 switch (type) {
1512                 case ETM_ADDR_TYPE_RANGE:
1513                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1514                             config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1515                                 return index;
1516
1517                         /* Address range comparators go in pairs */
1518                         index += 2;
1519                         break;
1520                 case ETM_ADDR_TYPE_START:
1521                 case ETM_ADDR_TYPE_STOP:
1522                         if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1523                                 return index;
1524
1525                         /* Start/stop address can have odd indexes */
1526                         index += 1;
1527                         break;
1528                 default:
1529                         return -EINVAL;
1530                 }
1531         }
1532
1533         /* If we are here all the comparators have been used. */
1534         return -ENOSPC;
1535 }
1536
1537 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1538                                   struct perf_event *event)
1539 {
1540         int i, comparator, ret = 0;
1541         u64 address;
1542         struct etmv4_config *config = &drvdata->config;
1543         struct etm_filters *filters = event->hw.addr_filters;
1544
1545         if (!filters)
1546                 goto default_filter;
1547
1548         /* Sync events with what Perf got */
1549         perf_event_addr_filters_sync(event);
1550
1551         /*
1552          * If there are no filters to deal with simply go ahead with
1553          * the default filter, i.e the entire address range.
1554          */
1555         if (!filters->nr_filters)
1556                 goto default_filter;
1557
1558         for (i = 0; i < filters->nr_filters; i++) {
1559                 struct etm_filter *filter = &filters->etm_filter[i];
1560                 enum etm_addr_type type = filter->type;
1561
1562                 /* See if a comparator is free. */
1563                 comparator = etm4_get_next_comparator(drvdata, type);
1564                 if (comparator < 0) {
1565                         ret = comparator;
1566                         goto out;
1567                 }
1568
1569                 switch (type) {
1570                 case ETM_ADDR_TYPE_RANGE:
1571                         etm4_set_comparator_filter(config,
1572                                                    filter->start_addr,
1573                                                    filter->stop_addr,
1574                                                    comparator);
1575                         /*
1576                          * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1577                          * in the started state
1578                          */
1579                         config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1580
1581                         /* No start-stop filtering for ViewInst */
1582                         config->vissctlr = 0x0;
1583                         break;
1584                 case ETM_ADDR_TYPE_START:
1585                 case ETM_ADDR_TYPE_STOP:
1586                         /* Get the right start or stop address */
1587                         address = (type == ETM_ADDR_TYPE_START ?
1588                                    filter->start_addr :
1589                                    filter->stop_addr);
1590
1591                         /* Configure comparator */
1592                         etm4_set_start_stop_filter(config, address,
1593                                                    comparator, type);
1594
1595                         /*
1596                          * If filters::ssstatus == 1, trace acquisition was
1597                          * started but the process was yanked away before the
1598                          * stop address was hit.  As such the start/stop
1599                          * logic needs to be re-started so that tracing can
1600                          * resume where it left.
1601                          *
1602                          * The start/stop logic status when a process is
1603                          * scheduled out is checked in function
1604                          * etm4_disable_perf().
1605                          */
1606                         if (filters->ssstatus)
1607                                 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1608
1609                         /* No include/exclude filtering for ViewInst */
1610                         config->viiectlr = 0x0;
1611                         break;
1612                 default:
1613                         ret = -EINVAL;
1614                         goto out;
1615                 }
1616         }
1617
1618         goto out;
1619
1620
1621 default_filter:
1622         etm4_set_default_filter(config);
1623
1624 out:
1625         return ret;
1626 }
1627
1628 void etm4_config_trace_mode(struct etmv4_config *config)
1629 {
1630         u32 mode;
1631
1632         mode = config->mode;
1633         mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1634
1635         /* excluding kernel AND user space doesn't make sense */
1636         WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1637
1638         /* nothing to do if neither flags are set */
1639         if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1640                 return;
1641
1642         etm4_set_victlr_access(config);
1643 }
1644
1645 static int etm4_online_cpu(unsigned int cpu)
1646 {
1647         if (!etmdrvdata[cpu])
1648                 return etm4_probe_cpu(cpu);
1649
1650         if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1651                 coresight_enable(etmdrvdata[cpu]->csdev);
1652         return 0;
1653 }
1654
1655 static int etm4_starting_cpu(unsigned int cpu)
1656 {
1657         if (!etmdrvdata[cpu])
1658                 return 0;
1659
1660         spin_lock(&etmdrvdata[cpu]->spinlock);
1661         if (!etmdrvdata[cpu]->os_unlock)
1662                 etm4_os_unlock(etmdrvdata[cpu]);
1663
1664         if (local_read(&etmdrvdata[cpu]->csdev->mode))
1665                 etm4_enable_hw(etmdrvdata[cpu]);
1666         spin_unlock(&etmdrvdata[cpu]->spinlock);
1667         return 0;
1668 }
1669
1670 static int etm4_dying_cpu(unsigned int cpu)
1671 {
1672         if (!etmdrvdata[cpu])
1673                 return 0;
1674
1675         spin_lock(&etmdrvdata[cpu]->spinlock);
1676         if (local_read(&etmdrvdata[cpu]->csdev->mode))
1677                 etm4_disable_hw(etmdrvdata[cpu]);
1678         spin_unlock(&etmdrvdata[cpu]->spinlock);
1679         return 0;
1680 }
1681
1682 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1683 {
1684         int i, ret = 0;
1685         struct etmv4_save_state *state;
1686         struct coresight_device *csdev = drvdata->csdev;
1687         struct csdev_access *csa;
1688         struct device *etm_dev;
1689
1690         if (WARN_ON(!csdev))
1691                 return -ENODEV;
1692
1693         etm_dev = &csdev->dev;
1694         csa = &csdev->access;
1695
1696         /*
1697          * As recommended by 3.4.1 ("The procedure when powering down the PE")
1698          * of ARM IHI 0064D
1699          */
1700         dsb(sy);
1701         isb();
1702
1703         etm4_cs_unlock(drvdata, csa);
1704         /* Lock the OS lock to disable trace and external debugger access */
1705         etm4_os_lock(drvdata);
1706
1707         /* wait for TRCSTATR.PMSTABLE to go up */
1708         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1709                 dev_err(etm_dev,
1710                         "timeout while waiting for PM Stable Status\n");
1711                 etm4_os_unlock(drvdata);
1712                 ret = -EBUSY;
1713                 goto out;
1714         }
1715
1716         state = drvdata->save_state;
1717
1718         state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1719         if (drvdata->nr_pe)
1720                 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1721         state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1722         state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1723         state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1724         state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1725         if (drvdata->stallctl)
1726                 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1727         state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1728         state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1729         state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1730         state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1731         state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1732         state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1733
1734         state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1735         state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1736         state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1737         if (drvdata->nr_pe_cmp)
1738                 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1739         state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1740         state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1741         state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1742
1743         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1744                 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1745
1746         if (drvdata->nrseqstate) {
1747                 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1748                 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1749         }
1750         state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1751
1752         for (i = 0; i < drvdata->nr_cntr; i++) {
1753                 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1754                 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1755                 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1756         }
1757
1758         for (i = 0; i < drvdata->nr_resource * 2; i++)
1759                 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1760
1761         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1762                 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1763                 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1764                 if (etm4x_sspcicrn_present(drvdata, i))
1765                         state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1766         }
1767
1768         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1769                 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1770                 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1771         }
1772
1773         /*
1774          * Data trace stream is architecturally prohibited for A profile cores
1775          * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1776          * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1777          * unit") of ARM IHI 0064D.
1778          */
1779
1780         for (i = 0; i < drvdata->numcidc; i++)
1781                 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1782
1783         for (i = 0; i < drvdata->numvmidc; i++)
1784                 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1785
1786         state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1787         if (drvdata->numcidc > 4)
1788                 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1789
1790         state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1791         if (drvdata->numvmidc > 4)
1792                 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1793
1794         state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1795
1796         if (!drvdata->skip_power_up)
1797                 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1798
1799         /* wait for TRCSTATR.IDLE to go up */
1800         if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1801                 dev_err(etm_dev,
1802                         "timeout while waiting for Idle Trace Status\n");
1803                 etm4_os_unlock(drvdata);
1804                 ret = -EBUSY;
1805                 goto out;
1806         }
1807
1808         drvdata->state_needs_restore = true;
1809
1810         /*
1811          * Power can be removed from the trace unit now. We do this to
1812          * potentially save power on systems that respect the TRCPDCR_PU
1813          * despite requesting software to save/restore state.
1814          */
1815         if (!drvdata->skip_power_up)
1816                 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1817                                       TRCPDCR);
1818 out:
1819         etm4_cs_lock(drvdata, csa);
1820         return ret;
1821 }
1822
1823 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1824 {
1825         int ret = 0;
1826
1827         /* Save the TRFCR irrespective of whether the ETM is ON */
1828         if (drvdata->trfcr)
1829                 drvdata->save_trfcr = read_trfcr();
1830         /*
1831          * Save and restore the ETM Trace registers only if
1832          * the ETM is active.
1833          */
1834         if (local_read(&drvdata->csdev->mode) && drvdata->save_state)
1835                 ret = __etm4_cpu_save(drvdata);
1836         return ret;
1837 }
1838
1839 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1840 {
1841         int i;
1842         struct etmv4_save_state *state = drvdata->save_state;
1843         struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1844         struct csdev_access *csa = &tmp_csa;
1845
1846         etm4_cs_unlock(drvdata, csa);
1847         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1848
1849         etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1850         if (drvdata->nr_pe)
1851                 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1852         etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1853         etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1854         etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1855         etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1856         if (drvdata->stallctl)
1857                 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1858         etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1859         etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1860         etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1861         etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1862         etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1863         etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1864
1865         etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1866         etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1867         etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1868         if (drvdata->nr_pe_cmp)
1869                 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1870         etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1871         etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1872         etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1873
1874         for (i = 0; i < drvdata->nrseqstate - 1; i++)
1875                 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1876
1877         if (drvdata->nrseqstate) {
1878                 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1879                 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1880         }
1881         etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1882
1883         for (i = 0; i < drvdata->nr_cntr; i++) {
1884                 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1885                 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1886                 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1887         }
1888
1889         for (i = 0; i < drvdata->nr_resource * 2; i++)
1890                 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1891
1892         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1893                 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1894                 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1895                 if (etm4x_sspcicrn_present(drvdata, i))
1896                         etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1897         }
1898
1899         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1900                 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1901                 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1902         }
1903
1904         for (i = 0; i < drvdata->numcidc; i++)
1905                 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1906
1907         for (i = 0; i < drvdata->numvmidc; i++)
1908                 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1909
1910         etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1911         if (drvdata->numcidc > 4)
1912                 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1913
1914         etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1915         if (drvdata->numvmidc > 4)
1916                 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1917
1918         etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1919
1920         if (!drvdata->skip_power_up)
1921                 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1922
1923         drvdata->state_needs_restore = false;
1924
1925         /*
1926          * As recommended by section 4.3.7 ("Synchronization when using the
1927          * memory-mapped interface") of ARM IHI 0064D
1928          */
1929         dsb(sy);
1930         isb();
1931
1932         /* Unlock the OS lock to re-enable trace and external debug access */
1933         etm4_os_unlock(drvdata);
1934         etm4_cs_lock(drvdata, csa);
1935 }
1936
1937 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1938 {
1939         if (drvdata->trfcr)
1940                 write_trfcr(drvdata->save_trfcr);
1941         if (drvdata->state_needs_restore)
1942                 __etm4_cpu_restore(drvdata);
1943 }
1944
1945 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1946                               void *v)
1947 {
1948         struct etmv4_drvdata *drvdata;
1949         unsigned int cpu = smp_processor_id();
1950
1951         if (!etmdrvdata[cpu])
1952                 return NOTIFY_OK;
1953
1954         drvdata = etmdrvdata[cpu];
1955
1956         if (WARN_ON_ONCE(drvdata->cpu != cpu))
1957                 return NOTIFY_BAD;
1958
1959         switch (cmd) {
1960         case CPU_PM_ENTER:
1961                 if (etm4_cpu_save(drvdata))
1962                         return NOTIFY_BAD;
1963                 break;
1964         case CPU_PM_EXIT:
1965         case CPU_PM_ENTER_FAILED:
1966                 etm4_cpu_restore(drvdata);
1967                 break;
1968         default:
1969                 return NOTIFY_DONE;
1970         }
1971
1972         return NOTIFY_OK;
1973 }
1974
1975 static struct notifier_block etm4_cpu_pm_nb = {
1976         .notifier_call = etm4_cpu_pm_notify,
1977 };
1978
1979 /* Setup PM. Deals with error conditions and counts */
1980 static int __init etm4_pm_setup(void)
1981 {
1982         int ret;
1983
1984         ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1985         if (ret)
1986                 return ret;
1987
1988         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1989                                         "arm/coresight4:starting",
1990                                         etm4_starting_cpu, etm4_dying_cpu);
1991
1992         if (ret)
1993                 goto unregister_notifier;
1994
1995         ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1996                                         "arm/coresight4:online",
1997                                         etm4_online_cpu, NULL);
1998
1999         /* HP dyn state ID returned in ret on success */
2000         if (ret > 0) {
2001                 hp_online = ret;
2002                 return 0;
2003         }
2004
2005         /* failed dyn state - remove others */
2006         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
2007
2008 unregister_notifier:
2009         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
2010         return ret;
2011 }
2012
2013 static void etm4_pm_clear(void)
2014 {
2015         cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
2016         cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
2017         if (hp_online) {
2018                 cpuhp_remove_state_nocalls(hp_online);
2019                 hp_online = 0;
2020         }
2021 }
2022
2023 static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg)
2024 {
2025         int ret;
2026         struct coresight_platform_data *pdata = NULL;
2027         struct device *dev = init_arg->dev;
2028         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2029         struct coresight_desc desc = { 0 };
2030         u8 major, minor;
2031         char *type_name;
2032
2033         if (!drvdata)
2034                 return -EINVAL;
2035
2036         desc.access = *init_arg->csa;
2037
2038         if (!drvdata->arch)
2039                 return -EINVAL;
2040
2041         /* TRCPDCR is not accessible with system instructions. */
2042         if (!desc.access.io_mem ||
2043             fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
2044                 drvdata->skip_power_up = true;
2045
2046         major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
2047         minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
2048
2049         if (etm4x_is_ete(drvdata)) {
2050                 type_name = "ete";
2051                 /* ETE v1 has major version == 0b101. Adjust this for logging.*/
2052                 major -= 4;
2053         } else {
2054                 type_name = "etm";
2055         }
2056
2057         desc.name = devm_kasprintf(dev, GFP_KERNEL,
2058                                    "%s%d", type_name, drvdata->cpu);
2059         if (!desc.name)
2060                 return -ENOMEM;
2061
2062         etm4_set_default(&drvdata->config);
2063
2064         pdata = coresight_get_platform_data(dev);
2065         if (IS_ERR(pdata))
2066                 return PTR_ERR(pdata);
2067
2068         dev->platform_data = pdata;
2069
2070         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
2071         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
2072         desc.ops = &etm4_cs_ops;
2073         desc.pdata = pdata;
2074         desc.dev = dev;
2075         desc.groups = coresight_etmv4_groups;
2076         drvdata->csdev = coresight_register(&desc);
2077         if (IS_ERR(drvdata->csdev))
2078                 return PTR_ERR(drvdata->csdev);
2079
2080         ret = etm_perf_symlink(drvdata->csdev, true);
2081         if (ret) {
2082                 coresight_unregister(drvdata->csdev);
2083                 return ret;
2084         }
2085
2086         /* register with config infrastructure & load any current features */
2087         ret = etm4_cscfg_register(drvdata->csdev);
2088         if (ret) {
2089                 coresight_unregister(drvdata->csdev);
2090                 return ret;
2091         }
2092
2093         etmdrvdata[drvdata->cpu] = drvdata;
2094
2095         dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
2096                  drvdata->cpu, type_name, major, minor);
2097
2098         if (boot_enable) {
2099                 coresight_enable(drvdata->csdev);
2100                 drvdata->boot_enable = true;
2101         }
2102
2103         return 0;
2104 }
2105
2106 static int etm4_probe(struct device *dev)
2107 {
2108         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2109         struct csdev_access access = { 0 };
2110         struct etm4_init_arg init_arg = { 0 };
2111         struct etm4_init_arg *delayed;
2112
2113         if (WARN_ON(!drvdata))
2114                 return -ENOMEM;
2115
2116         if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
2117                 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
2118                                PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
2119
2120         if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
2121                 drvdata->save_state = devm_kmalloc(dev,
2122                                 sizeof(struct etmv4_save_state), GFP_KERNEL);
2123                 if (!drvdata->save_state)
2124                         return -ENOMEM;
2125         }
2126
2127         spin_lock_init(&drvdata->spinlock);
2128
2129         drvdata->cpu = coresight_get_cpu(dev);
2130         if (drvdata->cpu < 0)
2131                 return drvdata->cpu;
2132
2133         init_arg.dev = dev;
2134         init_arg.csa = &access;
2135
2136         /*
2137          * Serialize against CPUHP callbacks to avoid race condition
2138          * between the smp call and saving the delayed probe.
2139          */
2140         cpus_read_lock();
2141         if (smp_call_function_single(drvdata->cpu,
2142                                 etm4_init_arch_data,  &init_arg, 1)) {
2143                 /* The CPU was offline, try again once it comes online. */
2144                 delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL);
2145                 if (!delayed) {
2146                         cpus_read_unlock();
2147                         return -ENOMEM;
2148                 }
2149
2150                 *delayed = init_arg;
2151
2152                 per_cpu(delayed_probe, drvdata->cpu) = delayed;
2153
2154                 cpus_read_unlock();
2155                 return 0;
2156         }
2157         cpus_read_unlock();
2158
2159         return etm4_add_coresight_dev(&init_arg);
2160 }
2161
2162 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
2163 {
2164         struct etmv4_drvdata *drvdata;
2165         void __iomem *base;
2166         struct device *dev = &adev->dev;
2167         struct resource *res = &adev->res;
2168         int ret;
2169
2170         /* Validity for the resource is already checked by the AMBA core */
2171         base = devm_ioremap_resource(dev, res);
2172         if (IS_ERR(base))
2173                 return PTR_ERR(base);
2174
2175         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
2176         if (!drvdata)
2177                 return -ENOMEM;
2178
2179         drvdata->base = base;
2180         dev_set_drvdata(dev, drvdata);
2181         ret = etm4_probe(dev);
2182         if (!ret)
2183                 pm_runtime_put(&adev->dev);
2184
2185         return ret;
2186 }
2187
2188 static int etm4_probe_platform_dev(struct platform_device *pdev)
2189 {
2190         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2191         struct etmv4_drvdata *drvdata;
2192         int ret;
2193
2194         drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
2195         if (!drvdata)
2196                 return -ENOMEM;
2197
2198         drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev);
2199         if (IS_ERR(drvdata->pclk))
2200                 return -ENODEV;
2201
2202         if (res) {
2203                 drvdata->base = devm_ioremap_resource(&pdev->dev, res);
2204                 if (IS_ERR(drvdata->base)) {
2205                         clk_put(drvdata->pclk);
2206                         return PTR_ERR(drvdata->base);
2207                 }
2208         }
2209
2210         dev_set_drvdata(&pdev->dev, drvdata);
2211         pm_runtime_get_noresume(&pdev->dev);
2212         pm_runtime_set_active(&pdev->dev);
2213         pm_runtime_enable(&pdev->dev);
2214
2215         ret = etm4_probe(&pdev->dev);
2216
2217         pm_runtime_put(&pdev->dev);
2218         return ret;
2219 }
2220
2221 static int etm4_probe_cpu(unsigned int cpu)
2222 {
2223         int ret;
2224         struct etm4_init_arg init_arg;
2225         struct csdev_access access = { 0 };
2226         struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe);
2227
2228         if (!iap)
2229                 return 0;
2230
2231         init_arg = *iap;
2232         devm_kfree(init_arg.dev, iap);
2233         *this_cpu_ptr(&delayed_probe) = NULL;
2234
2235         ret = pm_runtime_resume_and_get(init_arg.dev);
2236         if (ret < 0) {
2237                 dev_err(init_arg.dev, "Failed to get PM runtime!\n");
2238                 return 0;
2239         }
2240
2241         init_arg.csa = &access;
2242         etm4_init_arch_data(&init_arg);
2243
2244         etm4_add_coresight_dev(&init_arg);
2245
2246         pm_runtime_put(init_arg.dev);
2247         return 0;
2248 }
2249
2250 static struct amba_cs_uci_id uci_id_etm4[] = {
2251         {
2252                 /*  ETMv4 UCI data */
2253                 .devarch        = ETM_DEVARCH_ETMv4x_ARCH,
2254                 .devarch_mask   = ETM_DEVARCH_ID_MASK,
2255                 .devtype        = CS_DEVTYPE_PE_TRACE,
2256         }
2257 };
2258
2259 static void clear_etmdrvdata(void *info)
2260 {
2261         int cpu = *(int *)info;
2262
2263         etmdrvdata[cpu] = NULL;
2264         per_cpu(delayed_probe, cpu) = NULL;
2265 }
2266
2267 static void etm4_remove_dev(struct etmv4_drvdata *drvdata)
2268 {
2269         bool had_delayed_probe;
2270         /*
2271          * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2272          * and CPU hotplug call backs.
2273          */
2274         cpus_read_lock();
2275
2276         had_delayed_probe = per_cpu(delayed_probe, drvdata->cpu);
2277
2278         /*
2279          * The readers for etmdrvdata[] are CPU hotplug call backs
2280          * and PM notification call backs. Change etmdrvdata[i] on
2281          * CPU i ensures these call backs has consistent view
2282          * inside one call back function.
2283          */
2284         if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2285                 clear_etmdrvdata(&drvdata->cpu);
2286
2287         cpus_read_unlock();
2288
2289         if (!had_delayed_probe) {
2290                 etm_perf_symlink(drvdata->csdev, false);
2291                 cscfg_unregister_csdev(drvdata->csdev);
2292                 coresight_unregister(drvdata->csdev);
2293         }
2294 }
2295
2296 static void etm4_remove_amba(struct amba_device *adev)
2297 {
2298         struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2299
2300         if (drvdata)
2301                 etm4_remove_dev(drvdata);
2302 }
2303
2304 static void etm4_remove_platform_dev(struct platform_device *pdev)
2305 {
2306         struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2307
2308         if (drvdata)
2309                 etm4_remove_dev(drvdata);
2310         pm_runtime_disable(&pdev->dev);
2311
2312         if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
2313                 clk_put(drvdata->pclk);
2314 }
2315
2316 static const struct amba_id etm4_ids[] = {
2317         CS_AMBA_ID(0x000bb95d),                 /* Cortex-A53 */
2318         CS_AMBA_ID(0x000bb95e),                 /* Cortex-A57 */
2319         CS_AMBA_ID(0x000bb95a),                 /* Cortex-A72 */
2320         CS_AMBA_ID(0x000bb959),                 /* Cortex-A73 */
2321         CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2322         CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2323         CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2324         CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2325         CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2326         CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2327         CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2328         CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2329         CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2330         CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2331         CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2332         CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */
2333         CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2334         CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2335         CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2336         /*
2337          * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new
2338          * CPUs to the list here.
2339          */
2340         CS_AMBA_MATCH_ALL_UCI(uci_id_etm4),
2341         {},
2342 };
2343
2344 MODULE_DEVICE_TABLE(amba, etm4_ids);
2345
2346 static struct amba_driver etm4x_amba_driver = {
2347         .drv = {
2348                 .name   = "coresight-etm4x",
2349                 .owner  = THIS_MODULE,
2350                 .suppress_bind_attrs = true,
2351         },
2352         .probe          = etm4_probe_amba,
2353         .remove         = etm4_remove_amba,
2354         .id_table       = etm4_ids,
2355 };
2356
2357 #ifdef CONFIG_PM
2358 static int etm4_runtime_suspend(struct device *dev)
2359 {
2360         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2361
2362         if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2363                 clk_disable_unprepare(drvdata->pclk);
2364
2365         return 0;
2366 }
2367
2368 static int etm4_runtime_resume(struct device *dev)
2369 {
2370         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2371
2372         if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2373                 clk_prepare_enable(drvdata->pclk);
2374
2375         return 0;
2376 }
2377 #endif
2378
2379 static const struct dev_pm_ops etm4_dev_pm_ops = {
2380         SET_RUNTIME_PM_OPS(etm4_runtime_suspend, etm4_runtime_resume, NULL)
2381 };
2382
2383 static const struct of_device_id etm4_sysreg_match[] = {
2384         { .compatible   = "arm,coresight-etm4x-sysreg" },
2385         { .compatible   = "arm,embedded-trace-extension" },
2386         {}
2387 };
2388
2389 #ifdef CONFIG_ACPI
2390 static const struct acpi_device_id etm4x_acpi_ids[] = {
2391         {"ARMHC500", 0, 0, 0}, /* ARM CoreSight ETM4x */
2392         {}
2393 };
2394 MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids);
2395 #endif
2396
2397 static struct platform_driver etm4_platform_driver = {
2398         .probe          = etm4_probe_platform_dev,
2399         .remove_new     = etm4_remove_platform_dev,
2400         .driver                 = {
2401                 .name                   = "coresight-etm4x",
2402                 .of_match_table         = etm4_sysreg_match,
2403                 .acpi_match_table       = ACPI_PTR(etm4x_acpi_ids),
2404                 .suppress_bind_attrs    = true,
2405                 .pm                     = &etm4_dev_pm_ops,
2406         },
2407 };
2408
2409 static int __init etm4x_init(void)
2410 {
2411         int ret;
2412
2413         ret = etm4_pm_setup();
2414
2415         /* etm4_pm_setup() does its own cleanup - exit on error */
2416         if (ret)
2417                 return ret;
2418
2419         ret = amba_driver_register(&etm4x_amba_driver);
2420         if (ret) {
2421                 pr_err("Error registering etm4x AMBA driver\n");
2422                 goto clear_pm;
2423         }
2424
2425         ret = platform_driver_register(&etm4_platform_driver);
2426         if (!ret)
2427                 return 0;
2428
2429         pr_err("Error registering etm4x platform driver\n");
2430         amba_driver_unregister(&etm4x_amba_driver);
2431
2432 clear_pm:
2433         etm4_pm_clear();
2434         return ret;
2435 }
2436
2437 static void __exit etm4x_exit(void)
2438 {
2439         amba_driver_unregister(&etm4x_amba_driver);
2440         platform_driver_unregister(&etm4_platform_driver);
2441         etm4_pm_clear();
2442 }
2443
2444 module_init(etm4x_init);
2445 module_exit(etm4x_exit);
2446
2447 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2448 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2449 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2450 MODULE_LICENSE("GPL v2");