1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
6 #include <linux/acpi.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/moduleparam.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/device.h>
14 #include <linux/err.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/smp.h>
19 #include <linux/sysfs.h>
20 #include <linux/stat.h>
21 #include <linux/clk.h>
22 #include <linux/cpu.h>
23 #include <linux/cpu_pm.h>
24 #include <linux/coresight.h>
25 #include <linux/coresight-pmu.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/amba/bus.h>
28 #include <linux/seq_file.h>
29 #include <linux/uaccess.h>
30 #include <linux/perf_event.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/property.h>
34 #include <linux/clk/clk-conf.h>
36 #include <asm/barrier.h>
37 #include <asm/sections.h>
38 #include <asm/sysreg.h>
39 #include <asm/local.h>
42 #include "coresight-etm4x.h"
43 #include "coresight-etm-perf.h"
44 #include "coresight-etm4x-cfg.h"
45 #include "coresight-self-hosted-trace.h"
46 #include "coresight-syscfg.h"
47 #include "coresight-trace-id.h"
49 static int boot_enable;
50 module_param(boot_enable, int, 0444);
51 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
53 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
54 #define PARAM_PM_SAVE_NEVER 1 /* never save any state */
55 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
57 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
58 module_param(pm_save_enable, int, 0444);
59 MODULE_PARM_DESC(pm_save_enable,
60 "Save/restore state on power down: 1 = never, 2 = self-hosted");
62 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
63 static void etm4_set_default_config(struct etmv4_config *config);
64 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
65 struct perf_event *event);
66 static u64 etm4_get_access_type(struct etmv4_config *config);
68 static enum cpuhp_state hp_online;
70 struct etm4_init_arg {
72 struct csdev_access *csa;
75 static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe);
76 static int etm4_probe_cpu(unsigned int cpu);
79 * Check if TRCSSPCICRn(i) is implemented for a given instance.
81 * TRCSSPCICRn is implemented only if :
82 * TRCSSPCICR<n> is present only if all of the following are true:
83 * TRCIDR4.NUMSSCC > n.
84 * TRCIDR4.NUMPC > 0b0000 .
85 * TRCSSCSR<n>.PC == 0b1
87 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
89 return (n < drvdata->nr_ss_cmp) &&
91 (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
94 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
99 ETM4x_READ_SYSREG_CASES(res)
101 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
106 __io_ar(res); /* Imitate the !relaxed I/O helpers */
111 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
114 __io_bw(); /* Imitate the !relaxed I/O helpers */
116 val &= GENMASK(31, 0);
119 ETM4x_WRITE_SYSREG_CASES(val)
121 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
126 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
133 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
138 __io_ar(res); /* Imitate the !relaxed I/O helpers */
143 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
146 __io_bw(); /* Imitate the !relaxed I/O helpers */
148 val &= GENMASK(31, 0);
153 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
158 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
159 struct csdev_access *csa)
161 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
163 drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
166 static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
167 struct csdev_access *csa, u32 val)
171 switch (drvdata->os_lock_model) {
172 case ETM_OSLOCK_PRESENT:
173 etm4x_relaxed_write32(csa, val, TRCOSLAR);
176 write_sysreg_s(val, SYS_OSLAR_EL1);
179 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
180 smp_processor_id(), drvdata->os_lock_model);
188 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
189 struct csdev_access *csa)
191 WARN_ON(drvdata->cpu != smp_processor_id());
193 /* Writing 0 to OS Lock unlocks the trace unit registers */
194 etm_write_os_lock(drvdata, csa, 0x0);
195 drvdata->os_unlock = true;
198 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
200 if (!WARN_ON(!drvdata->csdev))
201 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
204 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
206 if (WARN_ON(!drvdata->csdev))
208 /* Writing 0x1 to OS Lock locks the trace registers */
209 etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
210 drvdata->os_unlock = false;
213 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
214 struct csdev_access *csa)
216 /* Software Lock is only accessible via memory mapped interface */
221 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
222 struct csdev_access *csa)
225 CS_UNLOCK(csa->base);
228 static int etm4_cpu_id(struct coresight_device *csdev)
230 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
235 int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata)
240 * This will allocate a trace ID to the cpu,
241 * or return the one currently allocated.
242 * The trace id function has its own lock
244 trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
245 if (IS_VALID_CS_TRACE_ID(trace_id))
246 drvdata->trcid = (u8)trace_id;
248 dev_err(&drvdata->csdev->dev,
249 "Failed to allocate trace ID for %s on CPU%d\n",
250 dev_name(&drvdata->csdev->dev), drvdata->cpu);
254 void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
256 coresight_trace_id_put_cpu_id(drvdata->cpu);
259 struct etm4_enable_arg {
260 struct etmv4_drvdata *drvdata;
265 * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
266 * When the CPU supports FEAT_TRF, we could move the ETM to a trace
267 * prohibited state by filtering the Exception levels via TRFCR_EL1.
269 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
271 /* If the CPU doesn't support FEAT_TRF, nothing to do */
274 cpu_prohibit_trace();
278 * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
279 * as configured by the drvdata->config.mode for the current
280 * session. Even though we have TRCVICTLR bits to filter the
281 * trace in the ELs, it doesn't prevent the ETM from generating
282 * a packet (e.g, TraceInfo) that might contain the addresses from
283 * the excluded levels. Thus we use the additional controls provided
284 * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
285 * is generated for the excluded ELs.
287 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
289 u64 trfcr = drvdata->trfcr;
291 /* If the CPU doesn't support FEAT_TRF, nothing to do */
295 if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
296 trfcr &= ~TRFCR_ELx_ExTRE;
297 if (drvdata->config.mode & ETM_MODE_EXCL_USER)
298 trfcr &= ~TRFCR_ELx_E0TRE;
303 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
305 #define HISI_HIP08_AMBA_ID 0x000b6d01
306 #define ETM4_AMBA_MASK 0xfffff
307 #define HISI_HIP08_CORE_COMMIT_MASK 0x3000
308 #define HISI_HIP08_CORE_COMMIT_SHIFT 12
309 #define HISI_HIP08_CORE_COMMIT_FULL 0b00
310 #define HISI_HIP08_CORE_COMMIT_LVL_1 0b01
311 #define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5)
313 struct etm4_arch_features {
314 void (*arch_callback)(bool enable);
317 static bool etm4_hisi_match_pid(unsigned int id)
319 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
322 static void etm4_hisi_config_core_commit(bool enable)
324 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
325 HISI_HIP08_CORE_COMMIT_FULL;
329 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
330 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
331 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
332 * speed(minimun value). So bit 12 and 13 should be cleared together.
334 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
335 val &= ~HISI_HIP08_CORE_COMMIT_MASK;
336 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
337 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
340 static struct etm4_arch_features etm4_features[] = {
341 [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
342 .arch_callback = etm4_hisi_config_core_commit,
347 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
349 struct etm4_arch_features *ftr;
352 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
353 ftr = &etm4_features[bit];
355 if (ftr->arch_callback)
356 ftr->arch_callback(true);
360 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
362 struct etm4_arch_features *ftr;
365 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
366 ftr = &etm4_features[bit];
368 if (ftr->arch_callback)
369 ftr->arch_callback(false);
373 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
374 struct csdev_access *csa)
377 * TRCPIDR* registers are not required for ETMs with system
378 * instructions. They must be identified by the MIDR+REVIDRs.
379 * Skip the TRCPID checks for now.
384 if (etm4_hisi_match_pid(coresight_get_pid(csa)))
385 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
388 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
392 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
396 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
397 struct csdev_access *csa)
400 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
402 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
405 struct etmv4_config *config = &drvdata->config;
406 struct coresight_device *csdev = drvdata->csdev;
407 struct device *etm_dev = &csdev->dev;
408 struct csdev_access *csa = &csdev->access;
411 etm4_cs_unlock(drvdata, csa);
412 etm4_enable_arch_specific(drvdata);
414 etm4_os_unlock(drvdata);
416 rc = coresight_claim_device_unlocked(csdev);
420 /* Disable the trace unit before programming trace registers */
421 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
424 * If we use system instructions, we need to synchronize the
425 * write to the TRCPRGCTLR, before accessing the TRCSTATR.
426 * See ARM IHI0064F, section
427 * "4.3.7 Synchronization of register updates"
432 /* wait for TRCSTATR.IDLE to go up */
433 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
435 "timeout while waiting for Idle Trace Status\n");
437 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
438 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
439 /* nothing specific implemented */
440 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
441 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
442 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
443 if (drvdata->stallctl)
444 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
445 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
446 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
447 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
448 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
449 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
450 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
451 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
452 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
453 if (drvdata->nr_pe_cmp)
454 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
455 for (i = 0; i < drvdata->nrseqstate - 1; i++)
456 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
457 if (drvdata->nrseqstate) {
458 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
459 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
461 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
462 for (i = 0; i < drvdata->nr_cntr; i++) {
463 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
464 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
465 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
469 * Resource selector pair 0 is always implemented and reserved. As
472 for (i = 2; i < drvdata->nr_resource * 2; i++)
473 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
475 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
476 /* always clear status bit on restart if using single-shot */
477 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
478 config->ss_status[i] &= ~TRCSSCSRn_STATUS;
479 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
480 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
481 if (etm4x_sspcicrn_present(drvdata, i))
482 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
484 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
485 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
486 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
488 for (i = 0; i < drvdata->numcidc; i++)
489 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
490 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
491 if (drvdata->numcidc > 4)
492 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
494 for (i = 0; i < drvdata->numvmidc; i++)
495 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
496 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
497 if (drvdata->numvmidc > 4)
498 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
500 if (!drvdata->skip_power_up) {
501 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
504 * Request to keep the trace unit powered and also
505 * emulation of powerdown
507 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
511 * ETE mandates that the TRCRSR is written to before
514 if (etm4x_is_ete(drvdata))
515 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
517 etm4x_allow_trace(drvdata);
518 /* Enable the trace unit */
519 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
521 /* Synchronize the register updates for sysreg access */
525 /* wait for TRCSTATR.IDLE to go back down to '0' */
526 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
528 "timeout while waiting for Idle Trace Status\n");
531 * As recommended by section 4.3.7 ("Synchronization when using the
532 * memory-mapped interface") of ARM IHI 0064D
538 etm4_cs_lock(drvdata, csa);
540 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
545 static void etm4_enable_hw_smp_call(void *info)
547 struct etm4_enable_arg *arg = info;
551 arg->rc = etm4_enable_hw(arg->drvdata);
555 * The goal of function etm4_config_timestamp_event() is to configure a
556 * counter that will tell the tracer to emit a timestamp packet when it
557 * reaches zero. This is done in order to get a more fine grained idea
558 * of when instructions are executed so that they can be correlated
559 * with execution on other CPUs.
561 * To do this the counter itself is configured to self reload and
562 * TRCRSCTLR1 (always true) used to get the counter to decrement. From
563 * there a resource selector is configured with the counter and the
564 * timestamp control register to use the resource selector to trigger the
565 * event that will insert a timestamp packet in the stream.
567 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
569 int ctridx, ret = -EINVAL;
570 int counter, rselector;
572 struct etmv4_config *config = &drvdata->config;
574 /* No point in trying if we don't have at least one counter */
575 if (!drvdata->nr_cntr)
578 /* Find a counter that hasn't been initialised */
579 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
580 if (config->cntr_val[ctridx] == 0)
583 /* All the counters have been configured already, bail out */
584 if (ctridx == drvdata->nr_cntr) {
585 pr_debug("%s: no available counter found\n", __func__);
591 * Searching for an available resource selector to use, starting at
592 * '2' since every implementation has at least 2 resource selector.
593 * ETMIDR4 gives the number of resource selector _pairs_,
594 * hence multiply by 2.
596 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
597 if (!config->res_ctrl[rselector])
600 if (rselector == drvdata->nr_resource * 2) {
601 pr_debug("%s: no available resource selector found\n",
607 /* Remember what counter we used */
608 counter = 1 << ctridx;
611 * Initialise original and reload counter value to the smallest
612 * possible value in order to get as much precision as we can.
614 config->cntr_val[ctridx] = 1;
615 config->cntrldvr[ctridx] = 1;
617 /* Set the trace counter control register */
618 val = 0x1 << 16 | /* Bit 16, reload counter automatically */
619 0x0 << 7 | /* Select single resource selector */
620 0x1; /* Resource selector 1, i.e always true */
622 config->cntr_ctrl[ctridx] = val;
624 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */
625 counter << 0; /* Counter to use */
627 config->res_ctrl[rselector] = val;
629 val = 0x0 << 7 | /* Select single resource selector */
630 rselector; /* Resource selector */
632 config->ts_ctrl = val;
639 static int etm4_parse_event_config(struct coresight_device *csdev,
640 struct perf_event *event)
643 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
644 struct etmv4_config *config = &drvdata->config;
645 struct perf_event_attr *attr = &event->attr;
646 unsigned long cfg_hash;
649 /* Clear configuration from previous run */
650 memset(config, 0, sizeof(struct etmv4_config));
652 if (attr->exclude_kernel)
653 config->mode = ETM_MODE_EXCL_KERN;
655 if (attr->exclude_user)
656 config->mode = ETM_MODE_EXCL_USER;
658 /* Always start from the default config */
659 etm4_set_default_config(config);
661 /* Configure filters specified on the perf cmd line, if any. */
662 ret = etm4_set_event_filters(drvdata, event);
666 /* Go from generic option to ETMv4 specifics */
667 if (attr->config & BIT(ETM_OPT_CYCACC)) {
668 config->cfg |= TRCCONFIGR_CCI;
669 /* TRM: Must program this for cycacc to work */
670 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
672 if (attr->config & BIT(ETM_OPT_TS)) {
674 * Configure timestamps to be emitted at regular intervals in
675 * order to correlate instructions executed on different CPUs
676 * (CPU-wide trace scenarios).
678 ret = etm4_config_timestamp_event(drvdata);
681 * No need to go further if timestamp intervals can't
687 /* bit[11], Global timestamp tracing bit */
688 config->cfg |= TRCCONFIGR_TS;
691 /* Only trace contextID when runs in root PID namespace */
692 if ((attr->config & BIT(ETM_OPT_CTXTID)) &&
693 task_is_in_init_pid_ns(current))
694 /* bit[6], Context ID tracing bit */
695 config->cfg |= TRCCONFIGR_CID;
698 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
699 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the
700 * kernel is not running in EL2.
702 if (attr->config & BIT(ETM_OPT_CTXTID2)) {
703 if (!is_kernel_in_hyp_mode()) {
707 /* Only trace virtual contextID when runs in root PID namespace */
708 if (task_is_in_init_pid_ns(current))
709 config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT;
712 /* return stack - enable if selected and supported */
713 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
714 /* bit[12], Return stack enable bit */
715 config->cfg |= TRCCONFIGR_RS;
718 * Set any selected configuration and preset.
720 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
721 * in the perf attributes defined in coresight-etm-perf.c.
722 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
723 * A zero configid means no configuration active, preset = 0 means no preset selected.
725 if (attr->config2 & GENMASK_ULL(63, 32)) {
726 cfg_hash = (u32)(attr->config2 >> 32);
727 preset = attr->config & 0xF;
728 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
731 /* branch broadcast - enable if selected and supported */
732 if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
733 if (!drvdata->trcbb) {
735 * Missing BB support could cause silent decode errors
736 * so fail to open if it's not supported.
741 config->cfg |= BIT(ETM4_CFG_BIT_BB);
749 static int etm4_enable_perf(struct coresight_device *csdev,
750 struct perf_event *event)
752 int ret = 0, trace_id;
753 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
755 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
760 /* Configure the tracer based on the session's specifics */
761 ret = etm4_parse_event_config(csdev, event);
766 * perf allocates cpu ids as part of _setup_aux() - device needs to use
767 * the allocated ID. This reads the current version without allocation.
769 * This does not use the trace id lock to prevent lock_dep issues
770 * with perf locks - we know the ID cannot change until perf shuts down
773 trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu);
774 if (!IS_VALID_CS_TRACE_ID(trace_id)) {
775 dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
776 dev_name(&drvdata->csdev->dev), drvdata->cpu);
780 drvdata->trcid = (u8)trace_id;
783 ret = etm4_enable_hw(drvdata);
789 static int etm4_enable_sysfs(struct coresight_device *csdev)
791 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
792 struct etm4_enable_arg arg = { };
793 unsigned long cfg_hash;
796 /* enable any config activated by configfs */
797 cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
799 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
804 spin_lock(&drvdata->spinlock);
806 /* sysfs needs to read and allocate a trace ID */
807 ret = etm4_read_alloc_trace_id(drvdata);
809 goto unlock_sysfs_enable;
812 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
813 * ensures that register writes occur when cpu is powered.
815 arg.drvdata = drvdata;
816 ret = smp_call_function_single(drvdata->cpu,
817 etm4_enable_hw_smp_call, &arg, 1);
821 drvdata->sticky_enable = true;
824 etm4_release_trace_id(drvdata);
827 spin_unlock(&drvdata->spinlock);
830 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
834 static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
839 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
841 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
843 /* Someone is already using the tracer */
849 ret = etm4_enable_sysfs(csdev);
852 ret = etm4_enable_perf(csdev, event);
858 /* The tracer didn't start */
860 local_set(&drvdata->mode, CS_MODE_DISABLED);
865 static void etm4_disable_hw(void *info)
868 struct etmv4_drvdata *drvdata = info;
869 struct etmv4_config *config = &drvdata->config;
870 struct coresight_device *csdev = drvdata->csdev;
871 struct device *etm_dev = &csdev->dev;
872 struct csdev_access *csa = &csdev->access;
875 etm4_cs_unlock(drvdata, csa);
876 etm4_disable_arch_specific(drvdata);
878 if (!drvdata->skip_power_up) {
879 /* power can be removed from the trace unit now */
880 control = etm4x_relaxed_read32(csa, TRCPDCR);
881 control &= ~TRCPDCR_PU;
882 etm4x_relaxed_write32(csa, control, TRCPDCR);
885 control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
887 /* EN, bit[0] Trace unit enable bit */
891 * If the CPU supports v8.4 Trace filter Control,
892 * set the ETM to trace prohibited region.
894 etm4x_prohibit_trace(drvdata);
896 * Make sure everything completes before disabling, as recommended
897 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
898 * SSTATUS") of ARM IHI 0064D
902 /* Trace synchronization barrier, is a nop if not supported */
904 etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
906 /* wait for TRCSTATR.PMSTABLE to go to '1' */
907 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
909 "timeout while waiting for PM stable Trace Status\n");
910 /* read the status of the single shot comparators */
911 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
912 config->ss_status[i] =
913 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
916 /* read back the current counter values */
917 for (i = 0; i < drvdata->nr_cntr; i++) {
918 config->cntr_val[i] =
919 etm4x_relaxed_read32(csa, TRCCNTVRn(i));
922 coresight_disclaim_device_unlocked(csdev);
923 etm4_cs_lock(drvdata, csa);
925 dev_dbg(&drvdata->csdev->dev,
926 "cpu: %d disable smp call done\n", drvdata->cpu);
929 static int etm4_disable_perf(struct coresight_device *csdev,
930 struct perf_event *event)
933 struct etm_filters *filters = event->hw.addr_filters;
934 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
935 struct perf_event_attr *attr = &event->attr;
937 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
940 etm4_disable_hw(drvdata);
942 * The config_id occupies bits 63:32 of the config2 perf event attr
943 * field. If this is non-zero then we will have enabled a config.
945 if (attr->config2 & GENMASK_ULL(63, 32))
946 cscfg_csdev_disable_active_config(csdev);
949 * Check if the start/stop logic was active when the unit was stopped.
950 * That way we can re-enable the start/stop logic when the process is
951 * scheduled again. Configuration of the start/stop logic happens in
952 * function etm4_set_event_filters().
954 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
955 /* TRCVICTLR::SSSTATUS, bit[9] */
956 filters->ssstatus = (control & BIT(9));
959 * perf will release trace ids when _free_aux() is
960 * called at the end of the session.
966 static void etm4_disable_sysfs(struct coresight_device *csdev)
968 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
971 * Taking hotplug lock here protects from clocks getting disabled
972 * with tracing being left on (crash scenario) if user disable occurs
973 * after cpu online mask indicates the cpu is offline but before the
974 * DYING hotplug callback is serviced by the ETM driver.
977 spin_lock(&drvdata->spinlock);
980 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
981 * ensures that register writes occur when cpu is powered.
983 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
985 spin_unlock(&drvdata->spinlock);
989 * we only release trace IDs when resetting sysfs.
990 * This permits sysfs users to read the trace ID after the trace
991 * session has completed. This maintains operational behaviour with
992 * prior trace id allocation method
995 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
998 static void etm4_disable(struct coresight_device *csdev,
999 struct perf_event *event)
1002 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
1005 * For as long as the tracer isn't disabled another entity can't
1006 * change its status. As such we can read the status here without
1007 * fearing it will change under us.
1009 mode = local_read(&drvdata->mode);
1012 case CS_MODE_DISABLED:
1015 etm4_disable_sysfs(csdev);
1018 etm4_disable_perf(csdev, event);
1023 local_set(&drvdata->mode, CS_MODE_DISABLED);
1026 static const struct coresight_ops_source etm4_source_ops = {
1027 .cpu_id = etm4_cpu_id,
1028 .enable = etm4_enable,
1029 .disable = etm4_disable,
1032 static const struct coresight_ops etm4_cs_ops = {
1033 .source_ops = &etm4_source_ops,
1036 static inline bool cpu_supports_sysreg_trace(void)
1038 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
1040 return ((dfr0 >> ID_AA64DFR0_EL1_TraceVer_SHIFT) & 0xfUL) > 0;
1043 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
1044 struct csdev_access *csa)
1048 if (!cpu_supports_sysreg_trace())
1052 * ETMs implementing sysreg access must implement TRCDEVARCH.
1054 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
1055 switch (devarch & ETM_DEVARCH_ID_MASK) {
1056 case ETM_DEVARCH_ETMv4x_ARCH:
1057 *csa = (struct csdev_access) {
1059 .read = etm4x_sysreg_read,
1060 .write = etm4x_sysreg_write,
1063 case ETM_DEVARCH_ETE_ARCH:
1064 *csa = (struct csdev_access) {
1066 .read = ete_sysreg_read,
1067 .write = ete_sysreg_write,
1074 drvdata->arch = etm_devarch_to_arch(devarch);
1078 static bool is_devtype_cpu_trace(void __iomem *base)
1080 u32 devtype = readl(base + TRCDEVTYPE);
1082 return (devtype == CS_DEVTYPE_PE_TRACE);
1085 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
1086 struct csdev_access *csa)
1088 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
1090 if (!is_coresight_device(drvdata->base) || !is_devtype_cpu_trace(drvdata->base))
1094 * All ETMs must implement TRCDEVARCH to indicate that
1095 * the component is an ETMv4. Even though TRCIDR1 also
1096 * contains the information, it is part of the "Trace"
1097 * register and must be accessed with the OSLK cleared,
1098 * with MMIO. But we cannot touch the OSLK until we are
1099 * sure this is an ETM. So rely only on the TRCDEVARCH.
1101 if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) {
1102 pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n");
1106 drvdata->arch = etm_devarch_to_arch(devarch);
1107 *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1111 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
1112 struct csdev_access *csa)
1115 * Always choose the memory mapped io, if there is
1116 * a memory map to prevent sysreg access on broken
1120 return etm4_init_iomem_access(drvdata, csa);
1122 if (etm4_init_sysreg_access(drvdata, csa))
1128 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
1130 u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
1134 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT))
1138 * If the CPU supports v8.4 SelfHosted Tracing, enable
1139 * tracing at the kernel EL and EL0, forcing to use the
1140 * virtual time as the timestamp.
1142 trfcr = (TRFCR_ELx_TS_VIRTUAL |
1146 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
1147 if (is_kernel_in_hyp_mode())
1148 trfcr |= TRFCR_EL2_CX;
1150 drvdata->trfcr = trfcr;
1153 static void etm4_init_arch_data(void *info)
1160 struct etm4_init_arg *init_arg = info;
1161 struct etmv4_drvdata *drvdata;
1162 struct csdev_access *csa;
1165 drvdata = dev_get_drvdata(init_arg->dev);
1166 csa = init_arg->csa;
1169 * If we are unable to detect the access mechanism,
1170 * or unable to detect the trace unit type, fail
1173 if (!etm4_init_csdev_access(drvdata, csa))
1176 /* Detect the support for OS Lock before we actually use it */
1177 etm_detect_os_lock(drvdata, csa);
1179 /* Make sure all registers are accessible */
1180 etm4_os_unlock_csa(drvdata, csa);
1181 etm4_cs_unlock(drvdata, csa);
1183 etm4_check_arch_features(drvdata, csa);
1185 /* find all capabilities of the tracing unit */
1186 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1188 /* INSTP0, bits[2:1] P0 tracing support field */
1189 drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
1190 /* TRCBB, bit[5] Branch broadcast tracing support bit */
1191 drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
1192 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1193 drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
1194 /* TRCCCI, bit[7] Cycle counting instruction bit */
1195 drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
1196 /* RETSTACK, bit[9] Return stack bit */
1197 drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
1198 /* NUMEVENT, bits[11:10] Number of events field */
1199 drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
1200 /* QSUPP, bits[16:15] Q element support field */
1201 drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
1202 /* TSSIZE, bits[28:24] Global timestamp size field */
1203 drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
1205 /* maximum size of resources */
1206 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1207 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1208 drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
1209 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1210 drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
1211 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1212 drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
1214 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1215 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1216 drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
1217 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1218 drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
1219 drvdata->config.s_ex_level = drvdata->s_ex_level;
1220 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1221 drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
1223 * TRCERR, bit[24] whether a trace unit can trace a
1224 * system error exception.
1226 drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
1227 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1228 drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
1229 /* STALLCTL, bit[26] is stall control implemented? */
1230 drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
1231 /* SYSSTALL, bit[27] implementation can support stall control? */
1232 drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
1234 * NUMPROC - the number of PEs available for tracing, 5bits
1235 * = TRCIDR3.bits[13:12]bits[30:28]
1236 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1237 * bits[3:0] = TRCIDR3.bits[30:28]
1239 drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
1240 FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
1241 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1242 drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
1244 /* number of resources trace unit supports */
1245 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1246 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1247 drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
1248 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1249 drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
1251 * NUMRSPAIR, bits[19:16]
1252 * The number of resource pairs conveyed by the HW starts at 0, i.e a
1253 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1254 * As such add 1 to the value of NUMRSPAIR for a better representation.
1256 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1257 * the default TRUE and FALSE resource selectors are omitted.
1258 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1260 drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
1261 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1262 drvdata->nr_resource += 1;
1264 * NUMSSCC, bits[23:20] the number of single-shot
1265 * comparator control for tracing. Read any status regs as these
1266 * also contain RO capability data.
1268 drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
1269 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1270 drvdata->config.ss_status[i] =
1271 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1273 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1274 drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
1275 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1276 drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
1278 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1279 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1280 drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
1281 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1282 drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
1283 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1284 drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
1286 * LPOVERRIDE, bit[23] implementation supports
1287 * low-power state override
1289 drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
1290 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1291 drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
1292 /* NUMCNTR, bits[30:28] number of counters available for tracing */
1293 drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
1294 etm4_cs_lock(drvdata, csa);
1295 cpu_detect_trace_filtering(drvdata);
1298 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1300 return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
1303 /* Set ELx trace filter access in the TRCVICTLR register */
1304 static void etm4_set_victlr_access(struct etmv4_config *config)
1306 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1307 config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1310 static void etm4_set_default_config(struct etmv4_config *config)
1312 /* disable all events tracing */
1313 config->eventctrl0 = 0x0;
1314 config->eventctrl1 = 0x0;
1316 /* disable stalling */
1317 config->stall_ctrl = 0x0;
1319 /* enable trace synchronization every 4096 bytes, if available */
1320 config->syncfreq = 0xC;
1322 /* disable timestamp event */
1323 config->ts_ctrl = 0x0;
1325 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1326 config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
1328 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1329 etm4_set_victlr_access(config);
1332 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1334 u64 access_type = 0;
1337 * EXLEVEL_NS, for NonSecure Exception levels.
1338 * The mask here is a generic value and must be
1339 * shifted to the corresponding field for the registers
1341 if (!is_kernel_in_hyp_mode()) {
1342 /* Stay away from hypervisor mode for non-VHE */
1343 access_type = ETM_EXLEVEL_NS_HYP;
1344 if (config->mode & ETM_MODE_EXCL_KERN)
1345 access_type |= ETM_EXLEVEL_NS_OS;
1346 } else if (config->mode & ETM_MODE_EXCL_KERN) {
1347 access_type = ETM_EXLEVEL_NS_HYP;
1350 if (config->mode & ETM_MODE_EXCL_USER)
1351 access_type |= ETM_EXLEVEL_NS_APP;
1357 * Construct the exception level masks for a given config.
1358 * This must be shifted to the corresponding register field
1361 static u64 etm4_get_access_type(struct etmv4_config *config)
1363 /* All Secure exception levels are excluded from the trace */
1364 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1367 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1369 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1372 static void etm4_set_comparator_filter(struct etmv4_config *config,
1373 u64 start, u64 stop, int comparator)
1375 u64 access_type = etm4_get_comparator_access_type(config);
1377 /* First half of default address comparator */
1378 config->addr_val[comparator] = start;
1379 config->addr_acc[comparator] = access_type;
1380 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1382 /* Second half of default address comparator */
1383 config->addr_val[comparator + 1] = stop;
1384 config->addr_acc[comparator + 1] = access_type;
1385 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1388 * Configure the ViewInst function to include this address range
1391 * @comparator is divided by two since it is the index in the
1392 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1393 * address range comparator _pairs_.
1396 * index 0 -> compatator pair 0
1397 * index 2 -> comparator pair 1
1398 * index 4 -> comparator pair 2
1400 * index 14 -> comparator pair 7
1402 config->viiectlr |= BIT(comparator / 2);
1405 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1406 u64 address, int comparator,
1407 enum etm_addr_type type)
1410 u64 access_type = etm4_get_comparator_access_type(config);
1412 /* Configure the comparator */
1413 config->addr_val[comparator] = address;
1414 config->addr_acc[comparator] = access_type;
1415 config->addr_type[comparator] = type;
1418 * Configure ViewInst Start-Stop control register.
1419 * Addresses configured to start tracing go from bit 0 to n-1,
1420 * while those configured to stop tracing from 16 to 16 + n-1.
1422 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1423 config->vissctlr |= BIT(shift + comparator);
1426 static void etm4_set_default_filter(struct etmv4_config *config)
1428 /* Trace everything 'default' filter achieved by no filtering */
1429 config->viiectlr = 0x0;
1432 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1433 * in the started state
1435 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1436 config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1438 /* No start-stop filtering for ViewInst */
1439 config->vissctlr = 0x0;
1442 static void etm4_set_default(struct etmv4_config *config)
1444 if (WARN_ON_ONCE(!config))
1448 * Make default initialisation trace everything
1450 * This is done by a minimum default config sufficient to enable
1451 * full instruction trace - with a default filter for trace all
1452 * achieved by having no filtering.
1454 etm4_set_default_config(config);
1455 etm4_set_default_filter(config);
1458 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1460 int nr_comparator, index = 0;
1461 struct etmv4_config *config = &drvdata->config;
1464 * nr_addr_cmp holds the number of comparator _pair_, so time 2
1465 * for the total number of comparators.
1467 nr_comparator = drvdata->nr_addr_cmp * 2;
1469 /* Go through the tally of comparators looking for a free one. */
1470 while (index < nr_comparator) {
1472 case ETM_ADDR_TYPE_RANGE:
1473 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1474 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1477 /* Address range comparators go in pairs */
1480 case ETM_ADDR_TYPE_START:
1481 case ETM_ADDR_TYPE_STOP:
1482 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1485 /* Start/stop address can have odd indexes */
1493 /* If we are here all the comparators have been used. */
1497 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1498 struct perf_event *event)
1500 int i, comparator, ret = 0;
1502 struct etmv4_config *config = &drvdata->config;
1503 struct etm_filters *filters = event->hw.addr_filters;
1506 goto default_filter;
1508 /* Sync events with what Perf got */
1509 perf_event_addr_filters_sync(event);
1512 * If there are no filters to deal with simply go ahead with
1513 * the default filter, i.e the entire address range.
1515 if (!filters->nr_filters)
1516 goto default_filter;
1518 for (i = 0; i < filters->nr_filters; i++) {
1519 struct etm_filter *filter = &filters->etm_filter[i];
1520 enum etm_addr_type type = filter->type;
1522 /* See if a comparator is free. */
1523 comparator = etm4_get_next_comparator(drvdata, type);
1524 if (comparator < 0) {
1530 case ETM_ADDR_TYPE_RANGE:
1531 etm4_set_comparator_filter(config,
1536 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1537 * in the started state
1539 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1541 /* No start-stop filtering for ViewInst */
1542 config->vissctlr = 0x0;
1544 case ETM_ADDR_TYPE_START:
1545 case ETM_ADDR_TYPE_STOP:
1546 /* Get the right start or stop address */
1547 address = (type == ETM_ADDR_TYPE_START ?
1548 filter->start_addr :
1551 /* Configure comparator */
1552 etm4_set_start_stop_filter(config, address,
1556 * If filters::ssstatus == 1, trace acquisition was
1557 * started but the process was yanked away before the
1558 * stop address was hit. As such the start/stop
1559 * logic needs to be re-started so that tracing can
1560 * resume where it left.
1562 * The start/stop logic status when a process is
1563 * scheduled out is checked in function
1564 * etm4_disable_perf().
1566 if (filters->ssstatus)
1567 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1569 /* No include/exclude filtering for ViewInst */
1570 config->viiectlr = 0x0;
1582 etm4_set_default_filter(config);
1588 void etm4_config_trace_mode(struct etmv4_config *config)
1592 mode = config->mode;
1593 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1595 /* excluding kernel AND user space doesn't make sense */
1596 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1598 /* nothing to do if neither flags are set */
1599 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1602 etm4_set_victlr_access(config);
1605 static int etm4_online_cpu(unsigned int cpu)
1607 if (!etmdrvdata[cpu])
1608 return etm4_probe_cpu(cpu);
1610 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1611 coresight_enable(etmdrvdata[cpu]->csdev);
1615 static int etm4_starting_cpu(unsigned int cpu)
1617 if (!etmdrvdata[cpu])
1620 spin_lock(&etmdrvdata[cpu]->spinlock);
1621 if (!etmdrvdata[cpu]->os_unlock)
1622 etm4_os_unlock(etmdrvdata[cpu]);
1624 if (local_read(&etmdrvdata[cpu]->mode))
1625 etm4_enable_hw(etmdrvdata[cpu]);
1626 spin_unlock(&etmdrvdata[cpu]->spinlock);
1630 static int etm4_dying_cpu(unsigned int cpu)
1632 if (!etmdrvdata[cpu])
1635 spin_lock(&etmdrvdata[cpu]->spinlock);
1636 if (local_read(&etmdrvdata[cpu]->mode))
1637 etm4_disable_hw(etmdrvdata[cpu]);
1638 spin_unlock(&etmdrvdata[cpu]->spinlock);
1642 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1645 struct etmv4_save_state *state;
1646 struct coresight_device *csdev = drvdata->csdev;
1647 struct csdev_access *csa;
1648 struct device *etm_dev;
1650 if (WARN_ON(!csdev))
1653 etm_dev = &csdev->dev;
1654 csa = &csdev->access;
1657 * As recommended by 3.4.1 ("The procedure when powering down the PE")
1663 etm4_cs_unlock(drvdata, csa);
1664 /* Lock the OS lock to disable trace and external debugger access */
1665 etm4_os_lock(drvdata);
1667 /* wait for TRCSTATR.PMSTABLE to go up */
1668 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1670 "timeout while waiting for PM Stable Status\n");
1671 etm4_os_unlock(drvdata);
1676 state = drvdata->save_state;
1678 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1680 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1681 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1682 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1683 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1684 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1685 if (drvdata->stallctl)
1686 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1687 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1688 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1689 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1690 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1691 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1692 state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1694 state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1695 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1696 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1697 if (drvdata->nr_pe_cmp)
1698 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1699 state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1700 state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1701 state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1703 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1704 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1706 if (drvdata->nrseqstate) {
1707 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1708 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1710 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1712 for (i = 0; i < drvdata->nr_cntr; i++) {
1713 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1714 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1715 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1718 for (i = 0; i < drvdata->nr_resource * 2; i++)
1719 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1721 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1722 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1723 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1724 if (etm4x_sspcicrn_present(drvdata, i))
1725 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1728 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1729 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1730 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1734 * Data trace stream is architecturally prohibited for A profile cores
1735 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1736 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1737 * unit") of ARM IHI 0064D.
1740 for (i = 0; i < drvdata->numcidc; i++)
1741 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1743 for (i = 0; i < drvdata->numvmidc; i++)
1744 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1746 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1747 if (drvdata->numcidc > 4)
1748 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1750 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1751 if (drvdata->numvmidc > 4)
1752 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1754 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1756 if (!drvdata->skip_power_up)
1757 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1759 /* wait for TRCSTATR.IDLE to go up */
1760 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1762 "timeout while waiting for Idle Trace Status\n");
1763 etm4_os_unlock(drvdata);
1768 drvdata->state_needs_restore = true;
1771 * Power can be removed from the trace unit now. We do this to
1772 * potentially save power on systems that respect the TRCPDCR_PU
1773 * despite requesting software to save/restore state.
1775 if (!drvdata->skip_power_up)
1776 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1779 etm4_cs_lock(drvdata, csa);
1783 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1787 /* Save the TRFCR irrespective of whether the ETM is ON */
1789 drvdata->save_trfcr = read_trfcr();
1791 * Save and restore the ETM Trace registers only if
1792 * the ETM is active.
1794 if (local_read(&drvdata->mode) && drvdata->save_state)
1795 ret = __etm4_cpu_save(drvdata);
1799 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1802 struct etmv4_save_state *state = drvdata->save_state;
1803 struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1804 struct csdev_access *csa = &tmp_csa;
1806 etm4_cs_unlock(drvdata, csa);
1807 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1809 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1811 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1812 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1813 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1814 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1815 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1816 if (drvdata->stallctl)
1817 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1818 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1819 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1820 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1821 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1822 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1823 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1825 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1826 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1827 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1828 if (drvdata->nr_pe_cmp)
1829 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1830 etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1831 etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1832 etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1834 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1835 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1837 if (drvdata->nrseqstate) {
1838 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1839 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1841 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1843 for (i = 0; i < drvdata->nr_cntr; i++) {
1844 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1845 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1846 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1849 for (i = 0; i < drvdata->nr_resource * 2; i++)
1850 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1852 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1853 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1854 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1855 if (etm4x_sspcicrn_present(drvdata, i))
1856 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1859 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1860 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1861 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1864 for (i = 0; i < drvdata->numcidc; i++)
1865 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1867 for (i = 0; i < drvdata->numvmidc; i++)
1868 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1870 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1871 if (drvdata->numcidc > 4)
1872 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1874 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1875 if (drvdata->numvmidc > 4)
1876 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1878 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1880 if (!drvdata->skip_power_up)
1881 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1883 drvdata->state_needs_restore = false;
1886 * As recommended by section 4.3.7 ("Synchronization when using the
1887 * memory-mapped interface") of ARM IHI 0064D
1892 /* Unlock the OS lock to re-enable trace and external debug access */
1893 etm4_os_unlock(drvdata);
1894 etm4_cs_lock(drvdata, csa);
1897 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1900 write_trfcr(drvdata->save_trfcr);
1901 if (drvdata->state_needs_restore)
1902 __etm4_cpu_restore(drvdata);
1905 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1908 struct etmv4_drvdata *drvdata;
1909 unsigned int cpu = smp_processor_id();
1911 if (!etmdrvdata[cpu])
1914 drvdata = etmdrvdata[cpu];
1916 if (WARN_ON_ONCE(drvdata->cpu != cpu))
1921 if (etm4_cpu_save(drvdata))
1925 case CPU_PM_ENTER_FAILED:
1926 etm4_cpu_restore(drvdata);
1935 static struct notifier_block etm4_cpu_pm_nb = {
1936 .notifier_call = etm4_cpu_pm_notify,
1939 /* Setup PM. Deals with error conditions and counts */
1940 static int __init etm4_pm_setup(void)
1944 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1948 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1949 "arm/coresight4:starting",
1950 etm4_starting_cpu, etm4_dying_cpu);
1953 goto unregister_notifier;
1955 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1956 "arm/coresight4:online",
1957 etm4_online_cpu, NULL);
1959 /* HP dyn state ID returned in ret on success */
1965 /* failed dyn state - remove others */
1966 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1968 unregister_notifier:
1969 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1973 static void etm4_pm_clear(void)
1975 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
1976 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1978 cpuhp_remove_state_nocalls(hp_online);
1983 static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg)
1986 struct coresight_platform_data *pdata = NULL;
1987 struct device *dev = init_arg->dev;
1988 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
1989 struct coresight_desc desc = { 0 };
1996 desc.access = *init_arg->csa;
2001 /* TRCPDCR is not accessible with system instructions. */
2002 if (!desc.access.io_mem ||
2003 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
2004 drvdata->skip_power_up = true;
2006 major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
2007 minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
2009 if (etm4x_is_ete(drvdata)) {
2011 /* ETE v1 has major version == 0b101. Adjust this for logging.*/
2017 desc.name = devm_kasprintf(dev, GFP_KERNEL,
2018 "%s%d", type_name, drvdata->cpu);
2022 etm4_set_default(&drvdata->config);
2024 pdata = coresight_get_platform_data(dev);
2026 return PTR_ERR(pdata);
2028 dev->platform_data = pdata;
2030 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
2031 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
2032 desc.ops = &etm4_cs_ops;
2035 desc.groups = coresight_etmv4_groups;
2036 drvdata->csdev = coresight_register(&desc);
2037 if (IS_ERR(drvdata->csdev))
2038 return PTR_ERR(drvdata->csdev);
2040 ret = etm_perf_symlink(drvdata->csdev, true);
2042 coresight_unregister(drvdata->csdev);
2046 /* register with config infrastructure & load any current features */
2047 ret = etm4_cscfg_register(drvdata->csdev);
2049 coresight_unregister(drvdata->csdev);
2053 etmdrvdata[drvdata->cpu] = drvdata;
2055 dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
2056 drvdata->cpu, type_name, major, minor);
2059 coresight_enable(drvdata->csdev);
2060 drvdata->boot_enable = true;
2066 static int etm4_probe(struct device *dev)
2068 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2069 struct csdev_access access = { 0 };
2070 struct etm4_init_arg init_arg = { 0 };
2071 struct etm4_init_arg *delayed;
2073 if (WARN_ON(!drvdata))
2076 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
2077 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
2078 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
2080 if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
2081 drvdata->save_state = devm_kmalloc(dev,
2082 sizeof(struct etmv4_save_state), GFP_KERNEL);
2083 if (!drvdata->save_state)
2087 spin_lock_init(&drvdata->spinlock);
2089 drvdata->cpu = coresight_get_cpu(dev);
2090 if (drvdata->cpu < 0)
2091 return drvdata->cpu;
2094 init_arg.csa = &access;
2097 * Serialize against CPUHP callbacks to avoid race condition
2098 * between the smp call and saving the delayed probe.
2101 if (smp_call_function_single(drvdata->cpu,
2102 etm4_init_arch_data, &init_arg, 1)) {
2103 /* The CPU was offline, try again once it comes online. */
2104 delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL);
2110 *delayed = init_arg;
2112 per_cpu(delayed_probe, drvdata->cpu) = delayed;
2119 return etm4_add_coresight_dev(&init_arg);
2122 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
2124 struct etmv4_drvdata *drvdata;
2126 struct device *dev = &adev->dev;
2127 struct resource *res = &adev->res;
2130 /* Validity for the resource is already checked by the AMBA core */
2131 base = devm_ioremap_resource(dev, res);
2133 return PTR_ERR(base);
2135 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
2139 drvdata->base = base;
2140 dev_set_drvdata(dev, drvdata);
2141 ret = etm4_probe(dev);
2143 pm_runtime_put(&adev->dev);
2148 static int etm4_probe_platform_dev(struct platform_device *pdev)
2150 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2151 struct etmv4_drvdata *drvdata;
2154 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
2158 drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev);
2159 if (IS_ERR(drvdata->pclk))
2163 drvdata->base = devm_ioremap_resource(&pdev->dev, res);
2164 if (IS_ERR(drvdata->base)) {
2165 clk_put(drvdata->pclk);
2166 return PTR_ERR(drvdata->base);
2170 dev_set_drvdata(&pdev->dev, drvdata);
2171 pm_runtime_get_noresume(&pdev->dev);
2172 pm_runtime_set_active(&pdev->dev);
2173 pm_runtime_enable(&pdev->dev);
2175 ret = etm4_probe(&pdev->dev);
2177 pm_runtime_put(&pdev->dev);
2181 static int etm4_probe_cpu(unsigned int cpu)
2184 struct etm4_init_arg init_arg;
2185 struct csdev_access access = { 0 };
2186 struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe);
2192 devm_kfree(init_arg.dev, iap);
2193 *this_cpu_ptr(&delayed_probe) = NULL;
2195 ret = pm_runtime_resume_and_get(init_arg.dev);
2197 dev_err(init_arg.dev, "Failed to get PM runtime!\n");
2201 init_arg.csa = &access;
2202 etm4_init_arch_data(&init_arg);
2204 etm4_add_coresight_dev(&init_arg);
2206 pm_runtime_put(init_arg.dev);
2210 static struct amba_cs_uci_id uci_id_etm4[] = {
2212 /* ETMv4 UCI data */
2213 .devarch = ETM_DEVARCH_ETMv4x_ARCH,
2214 .devarch_mask = ETM_DEVARCH_ID_MASK,
2215 .devtype = CS_DEVTYPE_PE_TRACE,
2219 static void clear_etmdrvdata(void *info)
2221 int cpu = *(int *)info;
2223 etmdrvdata[cpu] = NULL;
2224 per_cpu(delayed_probe, cpu) = NULL;
2227 static void __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
2229 bool had_delayed_probe;
2231 * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2232 * and CPU hotplug call backs.
2236 had_delayed_probe = per_cpu(delayed_probe, drvdata->cpu);
2239 * The readers for etmdrvdata[] are CPU hotplug call backs
2240 * and PM notification call backs. Change etmdrvdata[i] on
2241 * CPU i ensures these call backs has consistent view
2242 * inside one call back function.
2244 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2245 clear_etmdrvdata(&drvdata->cpu);
2249 if (!had_delayed_probe) {
2250 etm_perf_symlink(drvdata->csdev, false);
2251 cscfg_unregister_csdev(drvdata->csdev);
2252 coresight_unregister(drvdata->csdev);
2256 static void __exit etm4_remove_amba(struct amba_device *adev)
2258 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2261 etm4_remove_dev(drvdata);
2264 static int __exit etm4_remove_platform_dev(struct platform_device *pdev)
2266 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2269 etm4_remove_dev(drvdata);
2270 pm_runtime_disable(&pdev->dev);
2272 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
2273 clk_put(drvdata->pclk);
2278 static const struct amba_id etm4_ids[] = {
2279 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
2280 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
2281 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
2282 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
2283 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2284 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2285 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2286 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2287 CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2288 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2289 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2290 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2291 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2292 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2293 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2294 CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */
2295 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2296 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2297 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2299 * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new
2300 * CPUs to the list here.
2302 CS_AMBA_MATCH_ALL_UCI(uci_id_etm4),
2306 MODULE_DEVICE_TABLE(amba, etm4_ids);
2308 static struct amba_driver etm4x_amba_driver = {
2310 .name = "coresight-etm4x",
2311 .owner = THIS_MODULE,
2312 .suppress_bind_attrs = true,
2314 .probe = etm4_probe_amba,
2315 .remove = etm4_remove_amba,
2316 .id_table = etm4_ids,
2320 static int etm4_runtime_suspend(struct device *dev)
2322 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2324 if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2325 clk_disable_unprepare(drvdata->pclk);
2330 static int etm4_runtime_resume(struct device *dev)
2332 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2334 if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2335 clk_prepare_enable(drvdata->pclk);
2341 static const struct dev_pm_ops etm4_dev_pm_ops = {
2342 SET_RUNTIME_PM_OPS(etm4_runtime_suspend, etm4_runtime_resume, NULL)
2345 static const struct of_device_id etm4_sysreg_match[] = {
2346 { .compatible = "arm,coresight-etm4x-sysreg" },
2347 { .compatible = "arm,embedded-trace-extension" },
2352 static const struct acpi_device_id etm4x_acpi_ids[] = {
2353 {"ARMHC500", 0}, /* ARM CoreSight ETM4x */
2356 MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids);
2359 static struct platform_driver etm4_platform_driver = {
2360 .probe = etm4_probe_platform_dev,
2361 .remove = etm4_remove_platform_dev,
2363 .name = "coresight-etm4x",
2364 .of_match_table = etm4_sysreg_match,
2365 .acpi_match_table = ACPI_PTR(etm4x_acpi_ids),
2366 .suppress_bind_attrs = true,
2367 .pm = &etm4_dev_pm_ops,
2371 static int __init etm4x_init(void)
2375 ret = etm4_pm_setup();
2377 /* etm4_pm_setup() does its own cleanup - exit on error */
2381 ret = amba_driver_register(&etm4x_amba_driver);
2383 pr_err("Error registering etm4x AMBA driver\n");
2387 ret = platform_driver_register(&etm4_platform_driver);
2391 pr_err("Error registering etm4x platform driver\n");
2392 amba_driver_unregister(&etm4x_amba_driver);
2399 static void __exit etm4x_exit(void)
2401 amba_driver_unregister(&etm4x_amba_driver);
2402 platform_driver_unregister(&etm4_platform_driver);
2406 module_init(etm4x_init);
2407 module_exit(etm4x_exit);
2409 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2410 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2411 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2412 MODULE_LICENSE("GPL v2");