drivers/hwmon/nct7904.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * nct7904.c - driver for Nuvoton NCT7904D.
   4  *
   5  * Copyright (c) 2015 Kontron
   6  * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>
   7  *
   8  * Copyright (c) 2019 Advantech
   9  * Author: Amy.Shih <amy.shih@advantech.com.tw>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/device.h>
  14 #include <linux/init.h>
  15 #include <linux/i2c.h>
  16 #include <linux/mutex.h>
  17 #include <linux/hwmon.h>
  18
  19 #define VENDOR_ID_REG           0x7A    /* Any bank */
  20 #define NUVOTON_ID              0x50
  21 #define CHIP_ID_REG             0x7B    /* Any bank */
  22 #define NCT7904_ID              0xC5
  23 #define DEVICE_ID_REG           0x7C    /* Any bank */
  24
  25 #define BANK_SEL_REG            0xFF
  26 #define BANK_0                  0x00
  27 #define BANK_1                  0x01
  28 #define BANK_2                  0x02
  29 #define BANK_3                  0x03
  30 #define BANK_4                  0x04
  31 #define BANK_MAX                0x04
  32
  33 #define FANIN_MAX               12      /* Counted from 1 */
  34 #define VSEN_MAX                21      /* VSEN1..14, 3VDD, VBAT, V3VSB,
  35                                            LTD (not a voltage), VSEN17..19 */
  36 #define FANCTL_MAX              4       /* Counted from 1 */
  37 #define TCPU_MAX                8       /* Counted from 1 */
  38 #define TEMP_MAX                4       /* Counted from 1 */
  39
  40 #define VT_ADC_CTRL0_REG        0x20    /* Bank 0 */
  41 #define VT_ADC_CTRL1_REG        0x21    /* Bank 0 */
  42 #define VT_ADC_CTRL2_REG        0x22    /* Bank 0 */
  43 #define FANIN_CTRL0_REG         0x24
  44 #define FANIN_CTRL1_REG         0x25
  45 #define DTS_T_CTRL0_REG         0x26
  46 #define DTS_T_CTRL1_REG         0x27
  47 #define VT_ADC_MD_REG           0x2E
  48
  49 #define VSEN1_HV_LL_REG         0x02    /* Bank 1; 2 regs (HV/LV) per sensor */
  50 #define VSEN1_LV_LL_REG         0x03    /* Bank 1; 2 regs (HV/LV) per sensor */
  51 #define VSEN1_HV_HL_REG         0x00    /* Bank 1; 2 regs (HV/LV) per sensor */
  52 #define VSEN1_LV_HL_REG         0x01    /* Bank 1; 2 regs (HV/LV) per sensor */
  53 #define SMI_STS1_REG            0xC1    /* Bank 0; SMI Status Register */
  54 #define SMI_STS3_REG            0xC3    /* Bank 0; SMI Status Register */
  55 #define SMI_STS5_REG            0xC5    /* Bank 0; SMI Status Register */
  56 #define SMI_STS7_REG            0xC7    /* Bank 0; SMI Status Register */
  57 #define SMI_STS8_REG            0xC8    /* Bank 0; SMI Status Register */
  58
  59 #define VSEN1_HV_REG            0x40    /* Bank 0; 2 regs (HV/LV) per sensor */
  60 #define TEMP_CH1_HV_REG         0x42    /* Bank 0; same as VSEN2_HV */
  61 #define LTD_HV_REG              0x62    /* Bank 0; 2 regs in VSEN range */
  62 #define LTD_HV_HL_REG           0x44    /* Bank 1; 1 reg for LTD */
  63 #define LTD_LV_HL_REG           0x45    /* Bank 1; 1 reg for LTD */
  64 #define LTD_HV_LL_REG           0x46    /* Bank 1; 1 reg for LTD */
  65 #define LTD_LV_LL_REG           0x47    /* Bank 1; 1 reg for LTD */
  66 #define TEMP_CH1_CH_REG         0x05    /* Bank 1; 1 reg for LTD */
  67 #define TEMP_CH1_W_REG          0x06    /* Bank 1; 1 reg for LTD */
  68 #define TEMP_CH1_WH_REG         0x07    /* Bank 1; 1 reg for LTD */
  69 #define TEMP_CH1_C_REG          0x04    /* Bank 1; 1 reg per sensor */
  70 #define DTS_T_CPU1_C_REG        0x90    /* Bank 1; 1 reg per sensor */
  71 #define DTS_T_CPU1_CH_REG       0x91    /* Bank 1; 1 reg per sensor */
  72 #define DTS_T_CPU1_W_REG        0x92    /* Bank 1; 1 reg per sensor */
  73 #define DTS_T_CPU1_WH_REG       0x93    /* Bank 1; 1 reg per sensor */
  74 #define FANIN1_HV_REG           0x80    /* Bank 0; 2 regs (HV/LV) per sensor */
  75 #define FANIN1_HV_HL_REG        0x60    /* Bank 1; 2 regs (HV/LV) per sensor */
  76 #define FANIN1_LV_HL_REG        0x61    /* Bank 1; 2 regs (HV/LV) per sensor */
  77 #define T_CPU1_HV_REG           0xA0    /* Bank 0; 2 regs (HV/LV) per sensor */
  78
  79 #define PRTS_REG                0x03    /* Bank 2 */
  80 #define PFE_REG                 0x00    /* Bank 2; PECI Function Enable */
  81 #define TSI_CTRL_REG            0x50    /* Bank 2; TSI Control Register */
  82 #define FANCTL1_FMR_REG         0x00    /* Bank 3; 1 reg per channel */
  83 #define FANCTL1_OUT_REG         0x10    /* Bank 3; 1 reg per channel */
  84
  85 #define ENABLE_TSI      BIT(1)
  86
  87 static const unsigned short normal_i2c[] = {
  88         0x2d, 0x2e, I2C_CLIENT_END
  89 };
  90
  91 struct nct7904_data {
  92         struct i2c_client *client;
  93         struct mutex bank_lock;
  94         int bank_sel;
  95         u32 fanin_mask;
  96         u32 vsen_mask;
  97         u32 tcpu_mask;
  98         u8 fan_mode[FANCTL_MAX];
  99         u8 enable_dts;
 100         u8 has_dts;
 101         u8 temp_mode; /* 0: TR mode, 1: TD mode */
 102         u8 fan_alarm[2];
 103         u8 vsen_alarm[3];
 104 };
 105
 106 /* Access functions */
 107 static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank)
 108 {
 109         int ret;
 110
 111         mutex_lock(&data->bank_lock);
 112         if (data->bank_sel == bank)
 113                 return 0;
 114         ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank);
 115         if (ret == 0)
 116                 data->bank_sel = bank;
 117         else
 118                 data->bank_sel = -1;
 119         return ret;
 120 }
 121
 122 static inline void nct7904_bank_release(struct nct7904_data *data)
 123 {
 124         mutex_unlock(&data->bank_lock);
 125 }
 126
 127 /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */
 128 static int nct7904_read_reg(struct nct7904_data *data,
 129                             unsigned int bank, unsigned int reg)
 130 {
 131         struct i2c_client *client = data->client;
 132         int ret;
 133
 134         ret = nct7904_bank_lock(data, bank);
 135         if (ret == 0)
 136                 ret = i2c_smbus_read_byte_data(client, reg);
 137
 138         nct7904_bank_release(data);
 139         return ret;
 140 }
 141
 142 /*
 143  * Read 2-byte register. Returns register in big-endian format or
 144  * -ERRNO on error.
 145  */
 146 static int nct7904_read_reg16(struct nct7904_data *data,
 147                               unsigned int bank, unsigned int reg)
 148 {
 149         struct i2c_client *client = data->client;
 150         int ret, hi;
 151
 152         ret = nct7904_bank_lock(data, bank);
 153         if (ret == 0) {
 154                 ret = i2c_smbus_read_byte_data(client, reg);
 155                 if (ret >= 0) {
 156                         hi = ret;
 157                         ret = i2c_smbus_read_byte_data(client, reg + 1);
 158                         if (ret >= 0)
 159                                 ret |= hi << 8;
 160                 }
 161         }
 162
 163         nct7904_bank_release(data);
 164         return ret;
 165 }
 166
 167 /* Write 1-byte register. Returns 0 or -ERRNO on error. */
 168 static int nct7904_write_reg(struct nct7904_data *data,
 169                              unsigned int bank, unsigned int reg, u8 val)
 170 {
 171         struct i2c_client *client = data->client;
 172         int ret;
 173
 174         ret = nct7904_bank_lock(data, bank);
 175         if (ret == 0)
 176                 ret = i2c_smbus_write_byte_data(client, reg, val);
 177
 178         nct7904_bank_release(data);
 179         return ret;
 180 }
 181
 182 static int nct7904_read_fan(struct device *dev, u32 attr, int channel,
 183                             long *val)
 184 {
 185         struct nct7904_data *data = dev_get_drvdata(dev);
 186         unsigned int cnt, rpm;
 187         int ret;
 188
 189         switch (attr) {
 190         case hwmon_fan_input:
 191                 ret = nct7904_read_reg16(data, BANK_0,
 192                                          FANIN1_HV_REG + channel * 2);
 193                 if (ret < 0)
 194                         return ret;
 195                 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
 196                 if (cnt == 0x1fff)
 197                         rpm = 0;
 198                 else
 199                         rpm = 1350000 / cnt;
 200                 *val = rpm;
 201                 return 0;
 202         case hwmon_fan_min:
 203                 ret = nct7904_read_reg16(data, BANK_1,
 204                                          FANIN1_HV_HL_REG + channel * 2);
 205                 if (ret < 0)
 206                         return ret;
 207                 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
 208                 if (cnt == 0x1fff)
 209                         rpm = 0;
 210                 else
 211                         rpm = 1350000 / cnt;
 212                 *val = rpm;
 213                 return 0;
 214         case hwmon_fan_alarm:
 215                 ret = nct7904_read_reg(data, BANK_0,
 216                                        SMI_STS5_REG + (channel >> 3));
 217                 if (ret < 0)
 218                         return ret;
 219                 if (!data->fan_alarm[channel >> 3])
 220                         data->fan_alarm[channel >> 3] = ret & 0xff;
 221                 else
 222                         /* If there is new alarm showing up */
 223                         data->fan_alarm[channel >> 3] |= (ret & 0xff);
 224                 *val = (data->fan_alarm[channel >> 3] >> (channel & 0x07)) & 1;
 225                 /* Needs to clean the alarm if alarm existing */
 226                 if (*val)
 227                         data->fan_alarm[channel >> 3] ^= 1 << (channel & 0x07);
 228                 return 0;
 229         default:
 230                 return -EOPNOTSUPP;
 231         }
 232 }
 233
 234 static umode_t nct7904_fan_is_visible(const void *_data, u32 attr, int channel)
 235 {
 236         const struct nct7904_data *data = _data;
 237
 238         switch (attr) {
 239         case hwmon_fan_input:
 240         case hwmon_fan_alarm:
 241                 if (data->fanin_mask & (1 << channel))
 242                         return 0444;
 243                 break;
 244         case hwmon_fan_min:
 245                 if (data->fanin_mask & (1 << channel))
 246                         return 0644;
 247                 break;
 248         default:
 249                 break;
 250         }
 251
 252         return 0;
 253 }
 254
 255 static u8 nct7904_chan_to_index[] = {
 256         0,      /* Not used */
 257         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
 258         18, 19, 20, 16
 259 };
 260
 261 static int nct7904_read_in(struct device *dev, u32 attr, int channel,
 262                            long *val)
 263 {
 264         struct nct7904_data *data = dev_get_drvdata(dev);
 265         int ret, volt, index;
 266
 267         index = nct7904_chan_to_index[channel];
 268
 269         switch (attr) {
 270         case hwmon_in_input:
 271                 ret = nct7904_read_reg16(data, BANK_0,
 272                                          VSEN1_HV_REG + index * 2);
 273                 if (ret < 0)
 274                         return ret;
 275                 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
 276                 if (index < 14)
 277                         volt *= 2; /* 0.002V scale */
 278                 else
 279                         volt *= 6; /* 0.006V scale */
 280                 *val = volt;
 281                 return 0;
 282         case hwmon_in_min:
 283                 ret = nct7904_read_reg16(data, BANK_1,
 284                                          VSEN1_HV_LL_REG + index * 4);
 285                 if (ret < 0)
 286                         return ret;
 287                 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
 288                 if (index < 14)
 289                         volt *= 2; /* 0.002V scale */
 290                 else
 291                         volt *= 6; /* 0.006V scale */
 292                 *val = volt;
 293                 return 0;
 294         case hwmon_in_max:
 295                 ret = nct7904_read_reg16(data, BANK_1,
 296                                          VSEN1_HV_HL_REG + index * 4);
 297                 if (ret < 0)
 298                         return ret;
 299                 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
 300                 if (index < 14)
 301                         volt *= 2; /* 0.002V scale */
 302                 else
 303                         volt *= 6; /* 0.006V scale */
 304                 *val = volt;
 305                 return 0;
 306         case hwmon_in_alarm:
 307                 ret = nct7904_read_reg(data, BANK_0,
 308                                        SMI_STS1_REG + (index >> 3));
 309                 if (ret < 0)
 310                         return ret;
 311                 if (!data->vsen_alarm[index >> 3])
 312                         data->vsen_alarm[index >> 3] = ret & 0xff;
 313                 else
 314                         /* If there is new alarm showing up */
 315                         data->vsen_alarm[index >> 3] |= (ret & 0xff);
 316                 *val = (data->vsen_alarm[index >> 3] >> (index & 0x07)) & 1;
 317                 /* Needs to clean the alarm if alarm existing */
 318                 if (*val)
 319                         data->vsen_alarm[index >> 3] ^= 1 << (index & 0x07);
 320                 return 0;
 321         default:
 322                 return -EOPNOTSUPP;
 323         }
 324 }
 325
 326 static umode_t nct7904_in_is_visible(const void *_data, u32 attr, int channel)
 327 {
 328         const struct nct7904_data *data = _data;
 329         int index = nct7904_chan_to_index[channel];
 330
 331         switch (attr) {
 332         case hwmon_in_input:
 333         case hwmon_in_alarm:
 334                 if (channel > 0 && (data->vsen_mask & BIT(index)))
 335                         return 0444;
 336                 break;
 337         case hwmon_in_min:
 338         case hwmon_in_max:
 339                 if (channel > 0 && (data->vsen_mask & BIT(index)))
 340                         return 0644;
 341                 break;
 342         default:
 343                 break;
 344         }
 345
 346         return 0;
 347 }
 348
 349 static int nct7904_read_temp(struct device *dev, u32 attr, int channel,
 350                              long *val)
 351 {
 352         struct nct7904_data *data = dev_get_drvdata(dev);
 353         int ret, temp;
 354         unsigned int reg1, reg2, reg3;
 355
 356         switch (attr) {
 357         case hwmon_temp_input:
 358                 if (channel == 4)
 359                         ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG);
 360                 else if (channel < 5)
 361                         ret = nct7904_read_reg16(data, BANK_0,
 362                                                  TEMP_CH1_HV_REG + channel * 4);
 363                 else
 364                         ret = nct7904_read_reg16(data, BANK_0,
 365                                                  T_CPU1_HV_REG + (channel - 5)
 366                                                  * 2);
 367                 if (ret < 0)
 368                         return ret;
 369                 temp = ((ret & 0xff00) >> 5) | (ret & 0x7);
 370                 *val = sign_extend32(temp, 10) * 125;
 371                 return 0;
 372         case hwmon_temp_alarm:
 373                 if (channel == 4) {
 374                         ret = nct7904_read_reg(data, BANK_0,
 375                                                SMI_STS3_REG);
 376                         if (ret < 0)
 377                                 return ret;
 378                         *val = (ret >> 1) & 1;
 379                 } else if (channel < 4) {
 380                         ret = nct7904_read_reg(data, BANK_0,
 381                                                SMI_STS1_REG);
 382                         if (ret < 0)
 383                                 return ret;
 384                         *val = (ret >> (((channel * 2) + 1) & 0x07)) & 1;
 385                 } else {
 386                         if ((channel - 5) < 4) {
 387                                 ret = nct7904_read_reg(data, BANK_0,
 388                                                        SMI_STS7_REG +
 389                                                        ((channel - 5) >> 3));
 390                                 if (ret < 0)
 391                                         return ret;
 392                                 *val = (ret >> ((channel - 5) & 0x07)) & 1;
 393                         } else {
 394                                 ret = nct7904_read_reg(data, BANK_0,
 395                                                        SMI_STS8_REG +
 396                                                        ((channel - 5) >> 3));
 397                                 if (ret < 0)
 398                                         return ret;
 399                                 *val = (ret >> (((channel - 5) & 0x07) - 4))
 400                                                         & 1;
 401                         }
 402                 }
 403                 return 0;
 404         case hwmon_temp_type:
 405                 if (channel < 5) {
 406                         if ((data->tcpu_mask >> channel) & 0x01) {
 407                                 if ((data->temp_mode >> channel) & 0x01)
 408                                         *val = 3; /* TD */
 409                                 else
 410                                         *val = 4; /* TR */
 411                         } else {
 412                                 *val = 0;
 413                         }
 414                 } else {
 415                         if ((data->has_dts >> (channel - 5)) & 0x01) {
 416                                 if (data->enable_dts & ENABLE_TSI)
 417                                         *val = 5; /* TSI */
 418                                 else
 419                                         *val = 6; /* PECI */
 420                         } else {
 421                                 *val = 0;
 422                         }
 423                 }
 424                 return 0;
 425         case hwmon_temp_max:
 426                 reg1 = LTD_HV_LL_REG;
 427                 reg2 = TEMP_CH1_W_REG;
 428                 reg3 = DTS_T_CPU1_W_REG;
 429                 break;
 430         case hwmon_temp_max_hyst:
 431                 reg1 = LTD_LV_LL_REG;
 432                 reg2 = TEMP_CH1_WH_REG;
 433                 reg3 = DTS_T_CPU1_WH_REG;
 434                 break;
 435         case hwmon_temp_crit:
 436                 reg1 = LTD_HV_HL_REG;
 437                 reg2 = TEMP_CH1_C_REG;
 438                 reg3 = DTS_T_CPU1_C_REG;
 439                 break;
 440         case hwmon_temp_crit_hyst:
 441                 reg1 = LTD_LV_HL_REG;
 442                 reg2 = TEMP_CH1_CH_REG;
 443                 reg3 = DTS_T_CPU1_CH_REG;
 444                 break;
 445         default:
 446                 return -EOPNOTSUPP;
 447         }
 448
 449         if (channel == 4)
 450                 ret = nct7904_read_reg(data, BANK_1, reg1);
 451         else if (channel < 5)
 452                 ret = nct7904_read_reg(data, BANK_1,
 453                                        reg2 + channel * 8);
 454         else
 455                 ret = nct7904_read_reg(data, BANK_1,
 456                                        reg3 + (channel - 5) * 4);
 457
 458         if (ret < 0)
 459                 return ret;
 460         *val = ret * 1000;
 461         return 0;
 462 }
 463
 464 static umode_t nct7904_temp_is_visible(const void *_data, u32 attr, int channel)
 465 {
 466         const struct nct7904_data *data = _data;
 467
 468         switch (attr) {
 469         case hwmon_temp_input:
 470         case hwmon_temp_alarm:
 471         case hwmon_temp_type:
 472                 if (channel < 5) {
 473                         if (data->tcpu_mask & BIT(channel))
 474                                 return 0444;
 475                 } else {
 476                         if (data->has_dts & BIT(channel - 5))
 477                                 return 0444;
 478                 }
 479                 break;
 480         case hwmon_temp_max:
 481         case hwmon_temp_max_hyst:
 482         case hwmon_temp_crit:
 483         case hwmon_temp_crit_hyst:
 484                 if (channel < 5) {
 485                         if (data->tcpu_mask & BIT(channel))
 486                                 return 0644;
 487                 } else {
 488                         if (data->has_dts & BIT(channel - 5))
 489                                 return 0644;
 490                 }
 491                 break;
 492         default:
 493                 break;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static int nct7904_read_pwm(struct device *dev, u32 attr, int channel,
 500                             long *val)
 501 {
 502         struct nct7904_data *data = dev_get_drvdata(dev);
 503         int ret;
 504
 505         switch (attr) {
 506         case hwmon_pwm_input:
 507                 ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel);
 508                 if (ret < 0)
 509                         return ret;
 510                 *val = ret;
 511                 return 0;
 512         case hwmon_pwm_enable:
 513                 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel);
 514                 if (ret < 0)
 515                         return ret;
 516
 517                 *val = ret ? 2 : 1;
 518                 return 0;
 519         default:
 520                 return -EOPNOTSUPP;
 521         }
 522 }
 523
 524 static int nct7904_write_temp(struct device *dev, u32 attr, int channel,
 525                               long val)
 526 {
 527         struct nct7904_data *data = dev_get_drvdata(dev);
 528         int ret;
 529         unsigned int reg1, reg2, reg3;
 530
 531         val = clamp_val(val / 1000, -128, 127);
 532
 533         switch (attr) {
 534         case hwmon_temp_max:
 535                 reg1 = LTD_HV_LL_REG;
 536                 reg2 = TEMP_CH1_W_REG;
 537                 reg3 = DTS_T_CPU1_W_REG;
 538                 break;
 539         case hwmon_temp_max_hyst:
 540                 reg1 = LTD_LV_LL_REG;
 541                 reg2 = TEMP_CH1_WH_REG;
 542                 reg3 = DTS_T_CPU1_WH_REG;
 543                 break;
 544         case hwmon_temp_crit:
 545                 reg1 = LTD_HV_HL_REG;
 546                 reg2 = TEMP_CH1_C_REG;
 547                 reg3 = DTS_T_CPU1_C_REG;
 548                 break;
 549         case hwmon_temp_crit_hyst:
 550                 reg1 = LTD_LV_HL_REG;
 551                 reg2 = TEMP_CH1_CH_REG;
 552                 reg3 = DTS_T_CPU1_CH_REG;
 553                 break;
 554         default:
 555                 return -EOPNOTSUPP;
 556         }
 557         if (channel == 4)
 558                 ret = nct7904_write_reg(data, BANK_1, reg1, val);
 559         else if (channel < 5)
 560                 ret = nct7904_write_reg(data, BANK_1,
 561                                         reg2 + channel * 8, val);
 562         else
 563                 ret = nct7904_write_reg(data, BANK_1,
 564                                         reg3 + (channel - 5) * 4, val);
 565
 566         return ret;
 567 }
 568
 569 static int nct7904_write_fan(struct device *dev, u32 attr, int channel,
 570                              long val)
 571 {
 572         struct nct7904_data *data = dev_get_drvdata(dev);
 573         int ret;
 574         u8 tmp;
 575
 576         switch (attr) {
 577         case hwmon_fan_min:
 578                 if (val <= 0)
 579                         return -EINVAL;
 580
 581                 val = clamp_val(DIV_ROUND_CLOSEST(1350000, val), 1, 0x1fff);
 582                 tmp = (val >> 5) & 0xff;
 583                 ret = nct7904_write_reg(data, BANK_1,
 584                                         FANIN1_HV_HL_REG + channel * 2, tmp);
 585                 if (ret < 0)
 586                         return ret;
 587                 tmp = val & 0x1f;
 588                 ret = nct7904_write_reg(data, BANK_1,
 589                                         FANIN1_LV_HL_REG + channel * 2, tmp);
 590                 return ret;
 591         default:
 592                 return -EOPNOTSUPP;
 593         }
 594 }
 595
 596 static int nct7904_write_in(struct device *dev, u32 attr, int channel,
 597                             long val)
 598 {
 599         struct nct7904_data *data = dev_get_drvdata(dev);
 600         int ret, index, tmp;
 601
 602         index = nct7904_chan_to_index[channel];
 603
 604         if (index < 14)
 605                 val = val / 2; /* 0.002V scale */
 606         else
 607                 val = val / 6; /* 0.006V scale */
 608
 609         val = clamp_val(val, 0, 0x7ff);
 610
 611         switch (attr) {
 612         case hwmon_in_min:
 613                 tmp = nct7904_read_reg(data, BANK_1,
 614                                        VSEN1_LV_LL_REG + index * 4);
 615                 if (tmp < 0)
 616                         return tmp;
 617                 tmp &= ~0x7;
 618                 tmp |= val & 0x7;
 619                 ret = nct7904_write_reg(data, BANK_1,
 620                                         VSEN1_LV_LL_REG + index * 4, tmp);
 621                 if (ret < 0)
 622                         return ret;
 623                 tmp = nct7904_read_reg(data, BANK_1,
 624                                        VSEN1_HV_LL_REG + index * 4);
 625                 if (tmp < 0)
 626                         return tmp;
 627                 tmp = (val >> 3) & 0xff;
 628                 ret = nct7904_write_reg(data, BANK_1,
 629                                         VSEN1_HV_LL_REG + index * 4, tmp);
 630                 return ret;
 631         case hwmon_in_max:
 632                 tmp = nct7904_read_reg(data, BANK_1,
 633                                        VSEN1_LV_HL_REG + index * 4);
 634                 if (tmp < 0)
 635                         return tmp;
 636                 tmp &= ~0x7;
 637                 tmp |= val & 0x7;
 638                 ret = nct7904_write_reg(data, BANK_1,
 639                                         VSEN1_LV_HL_REG + index * 4, tmp);
 640                 if (ret < 0)
 641                         return ret;
 642                 tmp = nct7904_read_reg(data, BANK_1,
 643                                        VSEN1_HV_HL_REG + index * 4);
 644                 if (tmp < 0)
 645                         return tmp;
 646                 tmp = (val >> 3) & 0xff;
 647                 ret = nct7904_write_reg(data, BANK_1,
 648                                         VSEN1_HV_HL_REG + index * 4, tmp);
 649                 return ret;
 650         default:
 651                 return -EOPNOTSUPP;
 652         }
 653 }
 654
 655 static int nct7904_write_pwm(struct device *dev, u32 attr, int channel,
 656                              long val)
 657 {
 658         struct nct7904_data *data = dev_get_drvdata(dev);
 659         int ret;
 660
 661         switch (attr) {
 662         case hwmon_pwm_input:
 663                 if (val < 0 || val > 255)
 664                         return -EINVAL;
 665                 ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel,
 666                                         val);
 667                 return ret;
 668         case hwmon_pwm_enable:
 669                 if (val < 1 || val > 2 ||
 670                     (val == 2 && !data->fan_mode[channel]))
 671                         return -EINVAL;
 672                 ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel,
 673                                         val == 2 ? data->fan_mode[channel] : 0);
 674                 return ret;
 675         default:
 676                 return -EOPNOTSUPP;
 677         }
 678 }
 679
 680 static umode_t nct7904_pwm_is_visible(const void *_data, u32 attr, int channel)
 681 {
 682         switch (attr) {
 683         case hwmon_pwm_input:
 684         case hwmon_pwm_enable:
 685                 return 0644;
 686         default:
 687                 return 0;
 688         }
 689 }
 690
 691 static int nct7904_read(struct device *dev, enum hwmon_sensor_types type,
 692                         u32 attr, int channel, long *val)
 693 {
 694         switch (type) {
 695         case hwmon_in:
 696                 return nct7904_read_in(dev, attr, channel, val);
 697         case hwmon_fan:
 698                 return nct7904_read_fan(dev, attr, channel, val);
 699         case hwmon_pwm:
 700                 return nct7904_read_pwm(dev, attr, channel, val);
 701         case hwmon_temp:
 702                 return nct7904_read_temp(dev, attr, channel, val);
 703         default:
 704                 return -EOPNOTSUPP;
 705         }
 706 }
 707
 708 static int nct7904_write(struct device *dev, enum hwmon_sensor_types type,
 709                          u32 attr, int channel, long val)
 710 {
 711         switch (type) {
 712         case hwmon_in:
 713                 return nct7904_write_in(dev, attr, channel, val);
 714         case hwmon_fan:
 715                 return nct7904_write_fan(dev, attr, channel, val);
 716         case hwmon_pwm:
 717                 return nct7904_write_pwm(dev, attr, channel, val);
 718         case hwmon_temp:
 719                 return nct7904_write_temp(dev, attr, channel, val);
 720         default:
 721                 return -EOPNOTSUPP;
 722         }
 723 }
 724
 725 static umode_t nct7904_is_visible(const void *data,
 726                                   enum hwmon_sensor_types type,
 727                                   u32 attr, int channel)
 728 {
 729         switch (type) {
 730         case hwmon_in:
 731                 return nct7904_in_is_visible(data, attr, channel);
 732         case hwmon_fan:
 733                 return nct7904_fan_is_visible(data, attr, channel);
 734         case hwmon_pwm:
 735                 return nct7904_pwm_is_visible(data, attr, channel);
 736         case hwmon_temp:
 737                 return nct7904_temp_is_visible(data, attr, channel);
 738         default:
 739                 return 0;
 740         }
 741 }
 742
 743 /* Return 0 if detection is successful, -ENODEV otherwise */
 744 static int nct7904_detect(struct i2c_client *client,
 745                           struct i2c_board_info *info)
 746 {
 747         struct i2c_adapter *adapter = client->adapter;
 748
 749         if (!i2c_check_functionality(adapter,
 750                                      I2C_FUNC_SMBUS_READ_BYTE |
 751                                      I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
 752                 return -ENODEV;
 753
 754         /* Determine the chip type. */
 755         if (i2c_smbus_read_byte_data(client, VENDOR_ID_REG) != NUVOTON_ID ||
 756             i2c_smbus_read_byte_data(client, CHIP_ID_REG) != NCT7904_ID ||
 757             (i2c_smbus_read_byte_data(client, DEVICE_ID_REG) & 0xf0) != 0x50 ||
 758             (i2c_smbus_read_byte_data(client, BANK_SEL_REG) & 0xf8) != 0x00)
 759                 return -ENODEV;
 760
 761         strlcpy(info->type, "nct7904", I2C_NAME_SIZE);
 762
 763         return 0;
 764 }
 765
 766 static const struct hwmon_channel_info *nct7904_info[] = {
 767         HWMON_CHANNEL_INFO(in,
 768                            /* dummy, skipped in is_visible */
 769                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 770                            HWMON_I_ALARM,
 771                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 772                            HWMON_I_ALARM,
 773                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 774                            HWMON_I_ALARM,
 775                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 776                            HWMON_I_ALARM,
 777                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 778                            HWMON_I_ALARM,
 779                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 780                            HWMON_I_ALARM,
 781                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 782                            HWMON_I_ALARM,
 783                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 784                            HWMON_I_ALARM,
 785                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 786                            HWMON_I_ALARM,
 787                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 788                            HWMON_I_ALARM,
 789                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 790                            HWMON_I_ALARM,
 791                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 792                            HWMON_I_ALARM,
 793                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 794                            HWMON_I_ALARM,
 795                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 796                            HWMON_I_ALARM,
 797                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 798                            HWMON_I_ALARM,
 799                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 800                            HWMON_I_ALARM,
 801                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 802                            HWMON_I_ALARM,
 803                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 804                            HWMON_I_ALARM,
 805                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 806                            HWMON_I_ALARM,
 807                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 808                            HWMON_I_ALARM,
 809                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 810                            HWMON_I_ALARM),
 811         HWMON_CHANNEL_INFO(fan,
 812                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 813                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 814                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 815                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 816                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 817                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 818                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 819                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM),
 820         HWMON_CHANNEL_INFO(pwm,
 821                            HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
 822                            HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
 823                            HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
 824                            HWMON_PWM_INPUT | HWMON_PWM_ENABLE),
 825         HWMON_CHANNEL_INFO(temp,
 826                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 827                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 828                            HWMON_T_CRIT_HYST,
 829                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 830                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 831                            HWMON_T_CRIT_HYST,
 832                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 833                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 834                            HWMON_T_CRIT_HYST,
 835                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 836                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 837                            HWMON_T_CRIT_HYST,
 838                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 839                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 840                            HWMON_T_CRIT_HYST,
 841                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 842                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 843                            HWMON_T_CRIT_HYST,
 844                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 845                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 846                            HWMON_T_CRIT_HYST,
 847                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 848                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 849                            HWMON_T_CRIT_HYST,
 850                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 851                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 852                            HWMON_T_CRIT_HYST),
 853         NULL
 854 };
 855
 856 static const struct hwmon_ops nct7904_hwmon_ops = {
 857         .is_visible = nct7904_is_visible,
 858         .read = nct7904_read,
 859         .write = nct7904_write,
 860 };
 861
 862 static const struct hwmon_chip_info nct7904_chip_info = {
 863         .ops = &nct7904_hwmon_ops,
 864         .info = nct7904_info,
 865 };
 866
 867 static int nct7904_probe(struct i2c_client *client,
 868                          const struct i2c_device_id *id)
 869 {
 870         struct nct7904_data *data;
 871         struct device *hwmon_dev;
 872         struct device *dev = &client->dev;
 873         int ret, i;
 874         u32 mask;
 875         u8 val, bit;
 876
 877         data = devm_kzalloc(dev, sizeof(struct nct7904_data), GFP_KERNEL);
 878         if (!data)
 879                 return -ENOMEM;
 880
 881         data->client = client;
 882         mutex_init(&data->bank_lock);
 883         data->bank_sel = -1;
 884
 885         /* Setup sensor groups. */
 886         /* FANIN attributes */
 887         ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG);
 888         if (ret < 0)
 889                 return ret;
 890         data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8);
 891
 892         /*
 893          * VSEN attributes
 894          *
 895          * Note: voltage sensors overlap with external temperature
 896          * sensors. So, if we ever decide to support the latter
 897          * we will have to adjust 'vsen_mask' accordingly.
 898          */
 899         mask = 0;
 900         ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG);
 901         if (ret >= 0)
 902                 mask = (ret >> 8) | ((ret & 0xff) << 8);
 903         ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
 904         if (ret >= 0)
 905                 mask |= (ret << 16);
 906         data->vsen_mask = mask;
 907
 908         /* CPU_TEMP attributes */
 909         ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG);
 910         if (ret < 0)
 911                 return ret;
 912
 913         if ((ret & 0x6) == 0x6)
 914                 data->tcpu_mask |= 1; /* TR1 */
 915         if ((ret & 0x18) == 0x18)
 916                 data->tcpu_mask |= 2; /* TR2 */
 917         if ((ret & 0x20) == 0x20)
 918                 data->tcpu_mask |= 4; /* TR3 */
 919         if ((ret & 0x80) == 0x80)
 920                 data->tcpu_mask |= 8; /* TR4 */
 921
 922         /* LTD */
 923         ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
 924         if (ret < 0)
 925                 return ret;
 926         if ((ret & 0x02) == 0x02)
 927                 data->tcpu_mask |= 0x10;
 928
 929         /* Multi-Function detecting for Volt and TR/TD */
 930         ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG);
 931         if (ret < 0)
 932                 return ret;
 933
 934         data->temp_mode = 0;
 935         for (i = 0; i < 4; i++) {
 936                 val = (ret >> (i * 2)) & 0x03;
 937                 bit = (1 << i);
 938                 if (val == 0) {
 939                         data->tcpu_mask &= ~bit;
 940                 } else {
 941                         if (val == 0x1 || val == 0x2)
 942                                 data->temp_mode |= bit;
 943                         data->vsen_mask &= ~(0x06 << (i * 2));
 944                 }
 945         }
 946
 947         /* PECI */
 948         ret = nct7904_read_reg(data, BANK_2, PFE_REG);
 949         if (ret < 0)
 950                 return ret;
 951         if (ret & 0x80) {
 952                 data->enable_dts = 1; /* Enable DTS & PECI */
 953         } else {
 954                 ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG);
 955                 if (ret < 0)
 956                         return ret;
 957                 if (ret & 0x80)
 958                         data->enable_dts = 0x3; /* Enable DTS & TSI */
 959         }
 960
 961         /* Check DTS enable status */
 962         if (data->enable_dts) {
 963                 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG);
 964                 if (ret < 0)
 965                         return ret;
 966                 data->has_dts = ret & 0xF;
 967                 if (data->enable_dts & ENABLE_TSI) {
 968                         ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG);
 969                         if (ret < 0)
 970                                 return ret;
 971                         data->has_dts |= (ret & 0xF) << 4;
 972                 }
 973         }
 974
 975         for (i = 0; i < FANCTL_MAX; i++) {
 976                 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i);
 977                 if (ret < 0)
 978                         return ret;
 979                 data->fan_mode[i] = ret;
 980         }
 981
 982         hwmon_dev =
 983                 devm_hwmon_device_register_with_info(dev, client->name, data,
 984                                                      &nct7904_chip_info, NULL);
 985         return PTR_ERR_OR_ZERO(hwmon_dev);
 986 }
 987
 988 static const struct i2c_device_id nct7904_id[] = {
 989         {"nct7904", 0},
 990         {}
 991 };
 992 MODULE_DEVICE_TABLE(i2c, nct7904_id);
 993
 994 static struct i2c_driver nct7904_driver = {
 995         .class = I2C_CLASS_HWMON,
 996         .driver = {
 997                 .name = "nct7904",
 998         },
 999         .probe = nct7904_probe,
1000         .id_table = nct7904_id,
1001         .detect = nct7904_detect,
1002         .address_list = normal_i2c,
1003 };
1004
1005 module_i2c_driver(nct7904_driver);
1006
1007 MODULE_AUTHOR("Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>");
1008 MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904");
1009 MODULE_LICENSE("GPL");