drivers/hwmon/nct7904.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * nct7904.c - driver for Nuvoton NCT7904D.
   4  *
   5  * Copyright (c) 2015 Kontron
   6  * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>
   7  *
   8  * Copyright (c) 2019 Advantech
   9  * Author: Amy.Shih <amy.shih@advantech.com.tw>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/device.h>
  14 #include <linux/init.h>
  15 #include <linux/i2c.h>
  16 #include <linux/mutex.h>
  17 #include <linux/hwmon.h>
  18
  19 #define VENDOR_ID_REG           0x7A    /* Any bank */
  20 #define NUVOTON_ID              0x50
  21 #define CHIP_ID_REG             0x7B    /* Any bank */
  22 #define NCT7904_ID              0xC5
  23 #define DEVICE_ID_REG           0x7C    /* Any bank */
  24
  25 #define BANK_SEL_REG            0xFF
  26 #define BANK_0                  0x00
  27 #define BANK_1                  0x01
  28 #define BANK_2                  0x02
  29 #define BANK_3                  0x03
  30 #define BANK_4                  0x04
  31 #define BANK_MAX                0x04
  32
  33 #define FANIN_MAX               12      /* Counted from 1 */
  34 #define VSEN_MAX                21      /* VSEN1..14, 3VDD, VBAT, V3VSB,
  35                                            LTD (not a voltage), VSEN17..19 */
  36 #define FANCTL_MAX              4       /* Counted from 1 */
  37 #define TCPU_MAX                8       /* Counted from 1 */
  38 #define TEMP_MAX                4       /* Counted from 1 */
  39
  40 #define VT_ADC_CTRL0_REG        0x20    /* Bank 0 */
  41 #define VT_ADC_CTRL1_REG        0x21    /* Bank 0 */
  42 #define VT_ADC_CTRL2_REG        0x22    /* Bank 0 */
  43 #define FANIN_CTRL0_REG         0x24
  44 #define FANIN_CTRL1_REG         0x25
  45 #define DTS_T_CTRL0_REG         0x26
  46 #define DTS_T_CTRL1_REG         0x27
  47 #define VT_ADC_MD_REG           0x2E
  48
  49 #define VSEN1_HV_LL_REG         0x02    /* Bank 1; 2 regs (HV/LV) per sensor */
  50 #define VSEN1_LV_LL_REG         0x03    /* Bank 1; 2 regs (HV/LV) per sensor */
  51 #define VSEN1_HV_HL_REG         0x00    /* Bank 1; 2 regs (HV/LV) per sensor */
  52 #define VSEN1_LV_HL_REG         0x01    /* Bank 1; 2 regs (HV/LV) per sensor */
  53 #define SMI_STS1_REG            0xC1    /* Bank 0; SMI Status Register */
  54 #define SMI_STS3_REG            0xC3    /* Bank 0; SMI Status Register */
  55 #define SMI_STS5_REG            0xC5    /* Bank 0; SMI Status Register */
  56 #define SMI_STS7_REG            0xC7    /* Bank 0; SMI Status Register */
  57 #define SMI_STS8_REG            0xC8    /* Bank 0; SMI Status Register */
  58
  59 #define VSEN1_HV_REG            0x40    /* Bank 0; 2 regs (HV/LV) per sensor */
  60 #define TEMP_CH1_HV_REG         0x42    /* Bank 0; same as VSEN2_HV */
  61 #define LTD_HV_REG              0x62    /* Bank 0; 2 regs in VSEN range */
  62 #define LTD_HV_HL_REG           0x44    /* Bank 1; 1 reg for LTD */
  63 #define LTD_LV_HL_REG           0x45    /* Bank 1; 1 reg for LTD */
  64 #define LTD_HV_LL_REG           0x46    /* Bank 1; 1 reg for LTD */
  65 #define LTD_LV_LL_REG           0x47    /* Bank 1; 1 reg for LTD */
  66 #define TEMP_CH1_CH_REG         0x05    /* Bank 1; 1 reg for LTD */
  67 #define TEMP_CH1_W_REG          0x06    /* Bank 1; 1 reg for LTD */
  68 #define TEMP_CH1_WH_REG         0x07    /* Bank 1; 1 reg for LTD */
  69 #define TEMP_CH1_C_REG          0x04    /* Bank 1; 1 reg per sensor */
  70 #define DTS_T_CPU1_C_REG        0x90    /* Bank 1; 1 reg per sensor */
  71 #define DTS_T_CPU1_CH_REG       0x91    /* Bank 1; 1 reg per sensor */
  72 #define DTS_T_CPU1_W_REG        0x92    /* Bank 1; 1 reg per sensor */
  73 #define DTS_T_CPU1_WH_REG       0x93    /* Bank 1; 1 reg per sensor */
  74 #define FANIN1_HV_REG           0x80    /* Bank 0; 2 regs (HV/LV) per sensor */
  75 #define FANIN1_HV_HL_REG        0x60    /* Bank 1; 2 regs (HV/LV) per sensor */
  76 #define FANIN1_LV_HL_REG        0x61    /* Bank 1; 2 regs (HV/LV) per sensor */
  77 #define T_CPU1_HV_REG           0xA0    /* Bank 0; 2 regs (HV/LV) per sensor */
  78
  79 #define PRTS_REG                0x03    /* Bank 2 */
  80 #define PFE_REG                 0x00    /* Bank 2; PECI Function Enable */
  81 #define TSI_CTRL_REG            0x50    /* Bank 2; TSI Control Register */
  82 #define FANCTL1_FMR_REG         0x00    /* Bank 3; 1 reg per channel */
  83 #define FANCTL1_OUT_REG         0x10    /* Bank 3; 1 reg per channel */
  84
  85 #define VOLT_MONITOR_MODE       0x0
  86 #define THERMAL_DIODE_MODE      0x1
  87 #define THERMISTOR_MODE         0x3
  88
  89 #define ENABLE_TSI      BIT(1)
  90
  91 static const unsigned short normal_i2c[] = {
  92         0x2d, 0x2e, I2C_CLIENT_END
  93 };
  94
  95 struct nct7904_data {
  96         struct i2c_client *client;
  97         struct mutex bank_lock;
  98         int bank_sel;
  99         u32 fanin_mask;
 100         u32 vsen_mask;
 101         u32 tcpu_mask;
 102         u8 fan_mode[FANCTL_MAX];
 103         u8 enable_dts;
 104         u8 has_dts;
 105         u8 temp_mode; /* 0: TR mode, 1: TD mode */
 106         u8 fan_alarm[2];
 107         u8 vsen_alarm[3];
 108 };
 109
 110 /* Access functions */
 111 static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank)
 112 {
 113         int ret;
 114
 115         mutex_lock(&data->bank_lock);
 116         if (data->bank_sel == bank)
 117                 return 0;
 118         ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank);
 119         if (ret == 0)
 120                 data->bank_sel = bank;
 121         else
 122                 data->bank_sel = -1;
 123         return ret;
 124 }
 125
 126 static inline void nct7904_bank_release(struct nct7904_data *data)
 127 {
 128         mutex_unlock(&data->bank_lock);
 129 }
 130
 131 /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */
 132 static int nct7904_read_reg(struct nct7904_data *data,
 133                             unsigned int bank, unsigned int reg)
 134 {
 135         struct i2c_client *client = data->client;
 136         int ret;
 137
 138         ret = nct7904_bank_lock(data, bank);
 139         if (ret == 0)
 140                 ret = i2c_smbus_read_byte_data(client, reg);
 141
 142         nct7904_bank_release(data);
 143         return ret;
 144 }
 145
 146 /*
 147  * Read 2-byte register. Returns register in big-endian format or
 148  * -ERRNO on error.
 149  */
 150 static int nct7904_read_reg16(struct nct7904_data *data,
 151                               unsigned int bank, unsigned int reg)
 152 {
 153         struct i2c_client *client = data->client;
 154         int ret, hi;
 155
 156         ret = nct7904_bank_lock(data, bank);
 157         if (ret == 0) {
 158                 ret = i2c_smbus_read_byte_data(client, reg);
 159                 if (ret >= 0) {
 160                         hi = ret;
 161                         ret = i2c_smbus_read_byte_data(client, reg + 1);
 162                         if (ret >= 0)
 163                                 ret |= hi << 8;
 164                 }
 165         }
 166
 167         nct7904_bank_release(data);
 168         return ret;
 169 }
 170
 171 /* Write 1-byte register. Returns 0 or -ERRNO on error. */
 172 static int nct7904_write_reg(struct nct7904_data *data,
 173                              unsigned int bank, unsigned int reg, u8 val)
 174 {
 175         struct i2c_client *client = data->client;
 176         int ret;
 177
 178         ret = nct7904_bank_lock(data, bank);
 179         if (ret == 0)
 180                 ret = i2c_smbus_write_byte_data(client, reg, val);
 181
 182         nct7904_bank_release(data);
 183         return ret;
 184 }
 185
 186 static int nct7904_read_fan(struct device *dev, u32 attr, int channel,
 187                             long *val)
 188 {
 189         struct nct7904_data *data = dev_get_drvdata(dev);
 190         unsigned int cnt, rpm;
 191         int ret;
 192
 193         switch (attr) {
 194         case hwmon_fan_input:
 195                 ret = nct7904_read_reg16(data, BANK_0,
 196                                          FANIN1_HV_REG + channel * 2);
 197                 if (ret < 0)
 198                         return ret;
 199                 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
 200                 if (cnt == 0x1fff)
 201                         rpm = 0;
 202                 else
 203                         rpm = 1350000 / cnt;
 204                 *val = rpm;
 205                 return 0;
 206         case hwmon_fan_min:
 207                 ret = nct7904_read_reg16(data, BANK_1,
 208                                          FANIN1_HV_HL_REG + channel * 2);
 209                 if (ret < 0)
 210                         return ret;
 211                 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
 212                 if (cnt == 0x1fff)
 213                         rpm = 0;
 214                 else
 215                         rpm = 1350000 / cnt;
 216                 *val = rpm;
 217                 return 0;
 218         case hwmon_fan_alarm:
 219                 ret = nct7904_read_reg(data, BANK_0,
 220                                        SMI_STS5_REG + (channel >> 3));
 221                 if (ret < 0)
 222                         return ret;
 223                 if (!data->fan_alarm[channel >> 3])
 224                         data->fan_alarm[channel >> 3] = ret & 0xff;
 225                 else
 226                         /* If there is new alarm showing up */
 227                         data->fan_alarm[channel >> 3] |= (ret & 0xff);
 228                 *val = (data->fan_alarm[channel >> 3] >> (channel & 0x07)) & 1;
 229                 /* Needs to clean the alarm if alarm existing */
 230                 if (*val)
 231                         data->fan_alarm[channel >> 3] ^= 1 << (channel & 0x07);
 232                 return 0;
 233         default:
 234                 return -EOPNOTSUPP;
 235         }
 236 }
 237
 238 static umode_t nct7904_fan_is_visible(const void *_data, u32 attr, int channel)
 239 {
 240         const struct nct7904_data *data = _data;
 241
 242         switch (attr) {
 243         case hwmon_fan_input:
 244         case hwmon_fan_alarm:
 245                 if (data->fanin_mask & (1 << channel))
 246                         return 0444;
 247                 break;
 248         case hwmon_fan_min:
 249                 if (data->fanin_mask & (1 << channel))
 250                         return 0644;
 251                 break;
 252         default:
 253                 break;
 254         }
 255
 256         return 0;
 257 }
 258
 259 static u8 nct7904_chan_to_index[] = {
 260         0,      /* Not used */
 261         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
 262         18, 19, 20, 16
 263 };
 264
 265 static int nct7904_read_in(struct device *dev, u32 attr, int channel,
 266                            long *val)
 267 {
 268         struct nct7904_data *data = dev_get_drvdata(dev);
 269         int ret, volt, index;
 270
 271         index = nct7904_chan_to_index[channel];
 272
 273         switch (attr) {
 274         case hwmon_in_input:
 275                 ret = nct7904_read_reg16(data, BANK_0,
 276                                          VSEN1_HV_REG + index * 2);
 277                 if (ret < 0)
 278                         return ret;
 279                 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
 280                 if (index < 14)
 281                         volt *= 2; /* 0.002V scale */
 282                 else
 283                         volt *= 6; /* 0.006V scale */
 284                 *val = volt;
 285                 return 0;
 286         case hwmon_in_min:
 287                 ret = nct7904_read_reg16(data, BANK_1,
 288                                          VSEN1_HV_LL_REG + index * 4);
 289                 if (ret < 0)
 290                         return ret;
 291                 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
 292                 if (index < 14)
 293                         volt *= 2; /* 0.002V scale */
 294                 else
 295                         volt *= 6; /* 0.006V scale */
 296                 *val = volt;
 297                 return 0;
 298         case hwmon_in_max:
 299                 ret = nct7904_read_reg16(data, BANK_1,
 300                                          VSEN1_HV_HL_REG + index * 4);
 301                 if (ret < 0)
 302                         return ret;
 303                 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
 304                 if (index < 14)
 305                         volt *= 2; /* 0.002V scale */
 306                 else
 307                         volt *= 6; /* 0.006V scale */
 308                 *val = volt;
 309                 return 0;
 310         case hwmon_in_alarm:
 311                 ret = nct7904_read_reg(data, BANK_0,
 312                                        SMI_STS1_REG + (index >> 3));
 313                 if (ret < 0)
 314                         return ret;
 315                 if (!data->vsen_alarm[index >> 3])
 316                         data->vsen_alarm[index >> 3] = ret & 0xff;
 317                 else
 318                         /* If there is new alarm showing up */
 319                         data->vsen_alarm[index >> 3] |= (ret & 0xff);
 320                 *val = (data->vsen_alarm[index >> 3] >> (index & 0x07)) & 1;
 321                 /* Needs to clean the alarm if alarm existing */
 322                 if (*val)
 323                         data->vsen_alarm[index >> 3] ^= 1 << (index & 0x07);
 324                 return 0;
 325         default:
 326                 return -EOPNOTSUPP;
 327         }
 328 }
 329
 330 static umode_t nct7904_in_is_visible(const void *_data, u32 attr, int channel)
 331 {
 332         const struct nct7904_data *data = _data;
 333         int index = nct7904_chan_to_index[channel];
 334
 335         switch (attr) {
 336         case hwmon_in_input:
 337         case hwmon_in_alarm:
 338                 if (channel > 0 && (data->vsen_mask & BIT(index)))
 339                         return 0444;
 340                 break;
 341         case hwmon_in_min:
 342         case hwmon_in_max:
 343                 if (channel > 0 && (data->vsen_mask & BIT(index)))
 344                         return 0644;
 345                 break;
 346         default:
 347                 break;
 348         }
 349
 350         return 0;
 351 }
 352
 353 static int nct7904_read_temp(struct device *dev, u32 attr, int channel,
 354                              long *val)
 355 {
 356         struct nct7904_data *data = dev_get_drvdata(dev);
 357         int ret, temp;
 358         unsigned int reg1, reg2, reg3;
 359
 360         switch (attr) {
 361         case hwmon_temp_input:
 362                 if (channel == 4)
 363                         ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG);
 364                 else if (channel < 5)
 365                         ret = nct7904_read_reg16(data, BANK_0,
 366                                                  TEMP_CH1_HV_REG + channel * 4);
 367                 else
 368                         ret = nct7904_read_reg16(data, BANK_0,
 369                                                  T_CPU1_HV_REG + (channel - 5)
 370                                                  * 2);
 371                 if (ret < 0)
 372                         return ret;
 373                 temp = ((ret & 0xff00) >> 5) | (ret & 0x7);
 374                 *val = sign_extend32(temp, 10) * 125;
 375                 return 0;
 376         case hwmon_temp_alarm:
 377                 if (channel == 4) {
 378                         ret = nct7904_read_reg(data, BANK_0,
 379                                                SMI_STS3_REG);
 380                         if (ret < 0)
 381                                 return ret;
 382                         *val = (ret >> 1) & 1;
 383                 } else if (channel < 4) {
 384                         ret = nct7904_read_reg(data, BANK_0,
 385                                                SMI_STS1_REG);
 386                         if (ret < 0)
 387                                 return ret;
 388                         *val = (ret >> (((channel * 2) + 1) & 0x07)) & 1;
 389                 } else {
 390                         if ((channel - 5) < 4) {
 391                                 ret = nct7904_read_reg(data, BANK_0,
 392                                                        SMI_STS7_REG +
 393                                                        ((channel - 5) >> 3));
 394                                 if (ret < 0)
 395                                         return ret;
 396                                 *val = (ret >> ((channel - 5) & 0x07)) & 1;
 397                         } else {
 398                                 ret = nct7904_read_reg(data, BANK_0,
 399                                                        SMI_STS8_REG +
 400                                                        ((channel - 5) >> 3));
 401                                 if (ret < 0)
 402                                         return ret;
 403                                 *val = (ret >> (((channel - 5) & 0x07) - 4))
 404                                                         & 1;
 405                         }
 406                 }
 407                 return 0;
 408         case hwmon_temp_type:
 409                 if (channel < 5) {
 410                         if ((data->tcpu_mask >> channel) & 0x01) {
 411                                 if ((data->temp_mode >> channel) & 0x01)
 412                                         *val = 3; /* TD */
 413                                 else
 414                                         *val = 4; /* TR */
 415                         } else {
 416                                 *val = 0;
 417                         }
 418                 } else {
 419                         if ((data->has_dts >> (channel - 5)) & 0x01) {
 420                                 if (data->enable_dts & ENABLE_TSI)
 421                                         *val = 5; /* TSI */
 422                                 else
 423                                         *val = 6; /* PECI */
 424                         } else {
 425                                 *val = 0;
 426                         }
 427                 }
 428                 return 0;
 429         case hwmon_temp_max:
 430                 reg1 = LTD_HV_LL_REG;
 431                 reg2 = TEMP_CH1_W_REG;
 432                 reg3 = DTS_T_CPU1_W_REG;
 433                 break;
 434         case hwmon_temp_max_hyst:
 435                 reg1 = LTD_LV_LL_REG;
 436                 reg2 = TEMP_CH1_WH_REG;
 437                 reg3 = DTS_T_CPU1_WH_REG;
 438                 break;
 439         case hwmon_temp_crit:
 440                 reg1 = LTD_HV_HL_REG;
 441                 reg2 = TEMP_CH1_C_REG;
 442                 reg3 = DTS_T_CPU1_C_REG;
 443                 break;
 444         case hwmon_temp_crit_hyst:
 445                 reg1 = LTD_LV_HL_REG;
 446                 reg2 = TEMP_CH1_CH_REG;
 447                 reg3 = DTS_T_CPU1_CH_REG;
 448                 break;
 449         default:
 450                 return -EOPNOTSUPP;
 451         }
 452
 453         if (channel == 4)
 454                 ret = nct7904_read_reg(data, BANK_1, reg1);
 455         else if (channel < 5)
 456                 ret = nct7904_read_reg(data, BANK_1,
 457                                        reg2 + channel * 8);
 458         else
 459                 ret = nct7904_read_reg(data, BANK_1,
 460                                        reg3 + (channel - 5) * 4);
 461
 462         if (ret < 0)
 463                 return ret;
 464         *val = ret * 1000;
 465         return 0;
 466 }
 467
 468 static umode_t nct7904_temp_is_visible(const void *_data, u32 attr, int channel)
 469 {
 470         const struct nct7904_data *data = _data;
 471
 472         switch (attr) {
 473         case hwmon_temp_input:
 474         case hwmon_temp_alarm:
 475         case hwmon_temp_type:
 476                 if (channel < 5) {
 477                         if (data->tcpu_mask & BIT(channel))
 478                                 return 0444;
 479                 } else {
 480                         if (data->has_dts & BIT(channel - 5))
 481                                 return 0444;
 482                 }
 483                 break;
 484         case hwmon_temp_max:
 485         case hwmon_temp_max_hyst:
 486         case hwmon_temp_crit:
 487         case hwmon_temp_crit_hyst:
 488                 if (channel < 5) {
 489                         if (data->tcpu_mask & BIT(channel))
 490                                 return 0644;
 491                 } else {
 492                         if (data->has_dts & BIT(channel - 5))
 493                                 return 0644;
 494                 }
 495                 break;
 496         default:
 497                 break;
 498         }
 499
 500         return 0;
 501 }
 502
 503 static int nct7904_read_pwm(struct device *dev, u32 attr, int channel,
 504                             long *val)
 505 {
 506         struct nct7904_data *data = dev_get_drvdata(dev);
 507         int ret;
 508
 509         switch (attr) {
 510         case hwmon_pwm_input:
 511                 ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel);
 512                 if (ret < 0)
 513                         return ret;
 514                 *val = ret;
 515                 return 0;
 516         case hwmon_pwm_enable:
 517                 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel);
 518                 if (ret < 0)
 519                         return ret;
 520
 521                 *val = ret ? 2 : 1;
 522                 return 0;
 523         default:
 524                 return -EOPNOTSUPP;
 525         }
 526 }
 527
 528 static int nct7904_write_temp(struct device *dev, u32 attr, int channel,
 529                               long val)
 530 {
 531         struct nct7904_data *data = dev_get_drvdata(dev);
 532         int ret;
 533         unsigned int reg1, reg2, reg3;
 534
 535         val = clamp_val(val / 1000, -128, 127);
 536
 537         switch (attr) {
 538         case hwmon_temp_max:
 539                 reg1 = LTD_HV_LL_REG;
 540                 reg2 = TEMP_CH1_W_REG;
 541                 reg3 = DTS_T_CPU1_W_REG;
 542                 break;
 543         case hwmon_temp_max_hyst:
 544                 reg1 = LTD_LV_LL_REG;
 545                 reg2 = TEMP_CH1_WH_REG;
 546                 reg3 = DTS_T_CPU1_WH_REG;
 547                 break;
 548         case hwmon_temp_crit:
 549                 reg1 = LTD_HV_HL_REG;
 550                 reg2 = TEMP_CH1_C_REG;
 551                 reg3 = DTS_T_CPU1_C_REG;
 552                 break;
 553         case hwmon_temp_crit_hyst:
 554                 reg1 = LTD_LV_HL_REG;
 555                 reg2 = TEMP_CH1_CH_REG;
 556                 reg3 = DTS_T_CPU1_CH_REG;
 557                 break;
 558         default:
 559                 return -EOPNOTSUPP;
 560         }
 561         if (channel == 4)
 562                 ret = nct7904_write_reg(data, BANK_1, reg1, val);
 563         else if (channel < 5)
 564                 ret = nct7904_write_reg(data, BANK_1,
 565                                         reg2 + channel * 8, val);
 566         else
 567                 ret = nct7904_write_reg(data, BANK_1,
 568                                         reg3 + (channel - 5) * 4, val);
 569
 570         return ret;
 571 }
 572
 573 static int nct7904_write_fan(struct device *dev, u32 attr, int channel,
 574                              long val)
 575 {
 576         struct nct7904_data *data = dev_get_drvdata(dev);
 577         int ret;
 578         u8 tmp;
 579
 580         switch (attr) {
 581         case hwmon_fan_min:
 582                 if (val <= 0)
 583                         return -EINVAL;
 584
 585                 val = clamp_val(DIV_ROUND_CLOSEST(1350000, val), 1, 0x1fff);
 586                 tmp = (val >> 5) & 0xff;
 587                 ret = nct7904_write_reg(data, BANK_1,
 588                                         FANIN1_HV_HL_REG + channel * 2, tmp);
 589                 if (ret < 0)
 590                         return ret;
 591                 tmp = val & 0x1f;
 592                 ret = nct7904_write_reg(data, BANK_1,
 593                                         FANIN1_LV_HL_REG + channel * 2, tmp);
 594                 return ret;
 595         default:
 596                 return -EOPNOTSUPP;
 597         }
 598 }
 599
 600 static int nct7904_write_in(struct device *dev, u32 attr, int channel,
 601                             long val)
 602 {
 603         struct nct7904_data *data = dev_get_drvdata(dev);
 604         int ret, index, tmp;
 605
 606         index = nct7904_chan_to_index[channel];
 607
 608         if (index < 14)
 609                 val = val / 2; /* 0.002V scale */
 610         else
 611                 val = val / 6; /* 0.006V scale */
 612
 613         val = clamp_val(val, 0, 0x7ff);
 614
 615         switch (attr) {
 616         case hwmon_in_min:
 617                 tmp = nct7904_read_reg(data, BANK_1,
 618                                        VSEN1_LV_LL_REG + index * 4);
 619                 if (tmp < 0)
 620                         return tmp;
 621                 tmp &= ~0x7;
 622                 tmp |= val & 0x7;
 623                 ret = nct7904_write_reg(data, BANK_1,
 624                                         VSEN1_LV_LL_REG + index * 4, tmp);
 625                 if (ret < 0)
 626                         return ret;
 627                 tmp = nct7904_read_reg(data, BANK_1,
 628                                        VSEN1_HV_LL_REG + index * 4);
 629                 if (tmp < 0)
 630                         return tmp;
 631                 tmp = (val >> 3) & 0xff;
 632                 ret = nct7904_write_reg(data, BANK_1,
 633                                         VSEN1_HV_LL_REG + index * 4, tmp);
 634                 return ret;
 635         case hwmon_in_max:
 636                 tmp = nct7904_read_reg(data, BANK_1,
 637                                        VSEN1_LV_HL_REG + index * 4);
 638                 if (tmp < 0)
 639                         return tmp;
 640                 tmp &= ~0x7;
 641                 tmp |= val & 0x7;
 642                 ret = nct7904_write_reg(data, BANK_1,
 643                                         VSEN1_LV_HL_REG + index * 4, tmp);
 644                 if (ret < 0)
 645                         return ret;
 646                 tmp = nct7904_read_reg(data, BANK_1,
 647                                        VSEN1_HV_HL_REG + index * 4);
 648                 if (tmp < 0)
 649                         return tmp;
 650                 tmp = (val >> 3) & 0xff;
 651                 ret = nct7904_write_reg(data, BANK_1,
 652                                         VSEN1_HV_HL_REG + index * 4, tmp);
 653                 return ret;
 654         default:
 655                 return -EOPNOTSUPP;
 656         }
 657 }
 658
 659 static int nct7904_write_pwm(struct device *dev, u32 attr, int channel,
 660                              long val)
 661 {
 662         struct nct7904_data *data = dev_get_drvdata(dev);
 663         int ret;
 664
 665         switch (attr) {
 666         case hwmon_pwm_input:
 667                 if (val < 0 || val > 255)
 668                         return -EINVAL;
 669                 ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel,
 670                                         val);
 671                 return ret;
 672         case hwmon_pwm_enable:
 673                 if (val < 1 || val > 2 ||
 674                     (val == 2 && !data->fan_mode[channel]))
 675                         return -EINVAL;
 676                 ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel,
 677                                         val == 2 ? data->fan_mode[channel] : 0);
 678                 return ret;
 679         default:
 680                 return -EOPNOTSUPP;
 681         }
 682 }
 683
 684 static umode_t nct7904_pwm_is_visible(const void *_data, u32 attr, int channel)
 685 {
 686         switch (attr) {
 687         case hwmon_pwm_input:
 688         case hwmon_pwm_enable:
 689                 return 0644;
 690         default:
 691                 return 0;
 692         }
 693 }
 694
 695 static int nct7904_read(struct device *dev, enum hwmon_sensor_types type,
 696                         u32 attr, int channel, long *val)
 697 {
 698         switch (type) {
 699         case hwmon_in:
 700                 return nct7904_read_in(dev, attr, channel, val);
 701         case hwmon_fan:
 702                 return nct7904_read_fan(dev, attr, channel, val);
 703         case hwmon_pwm:
 704                 return nct7904_read_pwm(dev, attr, channel, val);
 705         case hwmon_temp:
 706                 return nct7904_read_temp(dev, attr, channel, val);
 707         default:
 708                 return -EOPNOTSUPP;
 709         }
 710 }
 711
 712 static int nct7904_write(struct device *dev, enum hwmon_sensor_types type,
 713                          u32 attr, int channel, long val)
 714 {
 715         switch (type) {
 716         case hwmon_in:
 717                 return nct7904_write_in(dev, attr, channel, val);
 718         case hwmon_fan:
 719                 return nct7904_write_fan(dev, attr, channel, val);
 720         case hwmon_pwm:
 721                 return nct7904_write_pwm(dev, attr, channel, val);
 722         case hwmon_temp:
 723                 return nct7904_write_temp(dev, attr, channel, val);
 724         default:
 725                 return -EOPNOTSUPP;
 726         }
 727 }
 728
 729 static umode_t nct7904_is_visible(const void *data,
 730                                   enum hwmon_sensor_types type,
 731                                   u32 attr, int channel)
 732 {
 733         switch (type) {
 734         case hwmon_in:
 735                 return nct7904_in_is_visible(data, attr, channel);
 736         case hwmon_fan:
 737                 return nct7904_fan_is_visible(data, attr, channel);
 738         case hwmon_pwm:
 739                 return nct7904_pwm_is_visible(data, attr, channel);
 740         case hwmon_temp:
 741                 return nct7904_temp_is_visible(data, attr, channel);
 742         default:
 743                 return 0;
 744         }
 745 }
 746
 747 /* Return 0 if detection is successful, -ENODEV otherwise */
 748 static int nct7904_detect(struct i2c_client *client,
 749                           struct i2c_board_info *info)
 750 {
 751         struct i2c_adapter *adapter = client->adapter;
 752
 753         if (!i2c_check_functionality(adapter,
 754                                      I2C_FUNC_SMBUS_READ_BYTE |
 755                                      I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
 756                 return -ENODEV;
 757
 758         /* Determine the chip type. */
 759         if (i2c_smbus_read_byte_data(client, VENDOR_ID_REG) != NUVOTON_ID ||
 760             i2c_smbus_read_byte_data(client, CHIP_ID_REG) != NCT7904_ID ||
 761             (i2c_smbus_read_byte_data(client, DEVICE_ID_REG) & 0xf0) != 0x50 ||
 762             (i2c_smbus_read_byte_data(client, BANK_SEL_REG) & 0xf8) != 0x00)
 763                 return -ENODEV;
 764
 765         strlcpy(info->type, "nct7904", I2C_NAME_SIZE);
 766
 767         return 0;
 768 }
 769
 770 static const struct hwmon_channel_info *nct7904_info[] = {
 771         HWMON_CHANNEL_INFO(in,
 772                            /* dummy, skipped in is_visible */
 773                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 774                            HWMON_I_ALARM,
 775                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 776                            HWMON_I_ALARM,
 777                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 778                            HWMON_I_ALARM,
 779                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 780                            HWMON_I_ALARM,
 781                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 782                            HWMON_I_ALARM,
 783                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 784                            HWMON_I_ALARM,
 785                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 786                            HWMON_I_ALARM,
 787                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 788                            HWMON_I_ALARM,
 789                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 790                            HWMON_I_ALARM,
 791                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 792                            HWMON_I_ALARM,
 793                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 794                            HWMON_I_ALARM,
 795                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 796                            HWMON_I_ALARM,
 797                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 798                            HWMON_I_ALARM,
 799                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 800                            HWMON_I_ALARM,
 801                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 802                            HWMON_I_ALARM,
 803                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 804                            HWMON_I_ALARM,
 805                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 806                            HWMON_I_ALARM,
 807                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 808                            HWMON_I_ALARM,
 809                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 810                            HWMON_I_ALARM,
 811                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 812                            HWMON_I_ALARM,
 813                            HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
 814                            HWMON_I_ALARM),
 815         HWMON_CHANNEL_INFO(fan,
 816                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 817                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 818                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 819                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 820                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 821                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 822                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
 823                            HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM),
 824         HWMON_CHANNEL_INFO(pwm,
 825                            HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
 826                            HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
 827                            HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
 828                            HWMON_PWM_INPUT | HWMON_PWM_ENABLE),
 829         HWMON_CHANNEL_INFO(temp,
 830                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 831                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 832                            HWMON_T_CRIT_HYST,
 833                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 834                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 835                            HWMON_T_CRIT_HYST,
 836                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 837                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 838                            HWMON_T_CRIT_HYST,
 839                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 840                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 841                            HWMON_T_CRIT_HYST,
 842                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 843                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 844                            HWMON_T_CRIT_HYST,
 845                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 846                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 847                            HWMON_T_CRIT_HYST,
 848                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 849                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 850                            HWMON_T_CRIT_HYST,
 851                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 852                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 853                            HWMON_T_CRIT_HYST,
 854                            HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
 855                            HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
 856                            HWMON_T_CRIT_HYST),
 857         NULL
 858 };
 859
 860 static const struct hwmon_ops nct7904_hwmon_ops = {
 861         .is_visible = nct7904_is_visible,
 862         .read = nct7904_read,
 863         .write = nct7904_write,
 864 };
 865
 866 static const struct hwmon_chip_info nct7904_chip_info = {
 867         .ops = &nct7904_hwmon_ops,
 868         .info = nct7904_info,
 869 };
 870
 871 static int nct7904_probe(struct i2c_client *client,
 872                          const struct i2c_device_id *id)
 873 {
 874         struct nct7904_data *data;
 875         struct device *hwmon_dev;
 876         struct device *dev = &client->dev;
 877         int ret, i;
 878         u32 mask;
 879         u8 val, bit;
 880
 881         data = devm_kzalloc(dev, sizeof(struct nct7904_data), GFP_KERNEL);
 882         if (!data)
 883                 return -ENOMEM;
 884
 885         data->client = client;
 886         mutex_init(&data->bank_lock);
 887         data->bank_sel = -1;
 888
 889         /* Setup sensor groups. */
 890         /* FANIN attributes */
 891         ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG);
 892         if (ret < 0)
 893                 return ret;
 894         data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8);
 895
 896         /*
 897          * VSEN attributes
 898          *
 899          * Note: voltage sensors overlap with external temperature
 900          * sensors. So, if we ever decide to support the latter
 901          * we will have to adjust 'vsen_mask' accordingly.
 902          */
 903         mask = 0;
 904         ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG);
 905         if (ret >= 0)
 906                 mask = (ret >> 8) | ((ret & 0xff) << 8);
 907         ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
 908         if (ret >= 0)
 909                 mask |= (ret << 16);
 910         data->vsen_mask = mask;
 911
 912         /* CPU_TEMP attributes */
 913         ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG);
 914         if (ret < 0)
 915                 return ret;
 916
 917         if ((ret & 0x6) == 0x6)
 918                 data->tcpu_mask |= 1; /* TR1 */
 919         if ((ret & 0x18) == 0x18)
 920                 data->tcpu_mask |= 2; /* TR2 */
 921         if ((ret & 0x20) == 0x20)
 922                 data->tcpu_mask |= 4; /* TR3 */
 923         if ((ret & 0x80) == 0x80)
 924                 data->tcpu_mask |= 8; /* TR4 */
 925
 926         /* LTD */
 927         ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
 928         if (ret < 0)
 929                 return ret;
 930         if ((ret & 0x02) == 0x02)
 931                 data->tcpu_mask |= 0x10;
 932
 933         /* Multi-Function detecting for Volt and TR/TD */
 934         ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG);
 935         if (ret < 0)
 936                 return ret;
 937
 938         data->temp_mode = 0;
 939         for (i = 0; i < 4; i++) {
 940                 val = (ret >> (i * 2)) & 0x03;
 941                 bit = (1 << i);
 942                 if (val == VOLT_MONITOR_MODE) {
 943                         data->tcpu_mask &= ~bit;
 944                 } else if (val == THERMAL_DIODE_MODE && i < 2) {
 945                         data->temp_mode |= bit;
 946                         data->vsen_mask &= ~(0x06 << (i * 2));
 947                 } else if (val == THERMISTOR_MODE) {
 948                         data->vsen_mask &= ~(0x02 << (i * 2));
 949                 } else {
 950                         /* Reserved */
 951                         data->tcpu_mask &= ~bit;
 952                         data->vsen_mask &= ~(0x06 << (i * 2));
 953                 }
 954         }
 955
 956         /* PECI */
 957         ret = nct7904_read_reg(data, BANK_2, PFE_REG);
 958         if (ret < 0)
 959                 return ret;
 960         if (ret & 0x80) {
 961                 data->enable_dts = 1; /* Enable DTS & PECI */
 962         } else {
 963                 ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG);
 964                 if (ret < 0)
 965                         return ret;
 966                 if (ret & 0x80)
 967                         data->enable_dts = 0x3; /* Enable DTS & TSI */
 968         }
 969
 970         /* Check DTS enable status */
 971         if (data->enable_dts) {
 972                 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG);
 973                 if (ret < 0)
 974                         return ret;
 975                 data->has_dts = ret & 0xF;
 976                 if (data->enable_dts & ENABLE_TSI) {
 977                         ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG);
 978                         if (ret < 0)
 979                                 return ret;
 980                         data->has_dts |= (ret & 0xF) << 4;
 981                 }
 982         }
 983
 984         for (i = 0; i < FANCTL_MAX; i++) {
 985                 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i);
 986                 if (ret < 0)
 987                         return ret;
 988                 data->fan_mode[i] = ret;
 989         }
 990
 991         hwmon_dev =
 992                 devm_hwmon_device_register_with_info(dev, client->name, data,
 993                                                      &nct7904_chip_info, NULL);
 994         return PTR_ERR_OR_ZERO(hwmon_dev);
 995 }
 996
 997 static const struct i2c_device_id nct7904_id[] = {
 998         {"nct7904", 0},
 999         {}
1000 };
1001 MODULE_DEVICE_TABLE(i2c, nct7904_id);
1002
1003 static struct i2c_driver nct7904_driver = {
1004         .class = I2C_CLASS_HWMON,
1005         .driver = {
1006                 .name = "nct7904",
1007         },
1008         .probe = nct7904_probe,
1009         .id_table = nct7904_id,
1010         .detect = nct7904_detect,
1011         .address_list = normal_i2c,
1012 };
1013
1014 module_i2c_driver(nct7904_driver);
1015
1016 MODULE_AUTHOR("Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>");
1017 MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904");
1018 MODULE_LICENSE("GPL");