1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * nct7904.c - driver for Nuvoton NCT7904D.
5 * Copyright (c) 2015 Kontron
6 * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>
8 * Copyright (c) 2019 Advantech
9 * Author: Amy.Shih <amy.shih@advantech.com.tw>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/mutex.h>
17 #include <linux/hwmon.h>
19 #define VENDOR_ID_REG 0x7A /* Any bank */
20 #define NUVOTON_ID 0x50
21 #define CHIP_ID_REG 0x7B /* Any bank */
22 #define NCT7904_ID 0xC5
23 #define DEVICE_ID_REG 0x7C /* Any bank */
25 #define BANK_SEL_REG 0xFF
33 #define FANIN_MAX 12 /* Counted from 1 */
34 #define VSEN_MAX 21 /* VSEN1..14, 3VDD, VBAT, V3VSB,
35 LTD (not a voltage), VSEN17..19 */
36 #define FANCTL_MAX 4 /* Counted from 1 */
37 #define TCPU_MAX 8 /* Counted from 1 */
38 #define TEMP_MAX 4 /* Counted from 1 */
40 #define VT_ADC_CTRL0_REG 0x20 /* Bank 0 */
41 #define VT_ADC_CTRL1_REG 0x21 /* Bank 0 */
42 #define VT_ADC_CTRL2_REG 0x22 /* Bank 0 */
43 #define FANIN_CTRL0_REG 0x24
44 #define FANIN_CTRL1_REG 0x25
45 #define DTS_T_CTRL0_REG 0x26
46 #define DTS_T_CTRL1_REG 0x27
47 #define VT_ADC_MD_REG 0x2E
49 #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */
50 #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */
51 #define VSEN1_HV_HL_REG 0x00 /* Bank 1; 2 regs (HV/LV) per sensor */
52 #define VSEN1_LV_HL_REG 0x01 /* Bank 1; 2 regs (HV/LV) per sensor */
53 #define SMI_STS1_REG 0xC1 /* Bank 0; SMI Status Register */
54 #define SMI_STS3_REG 0xC3 /* Bank 0; SMI Status Register */
55 #define SMI_STS5_REG 0xC5 /* Bank 0; SMI Status Register */
56 #define SMI_STS7_REG 0xC7 /* Bank 0; SMI Status Register */
57 #define SMI_STS8_REG 0xC8 /* Bank 0; SMI Status Register */
59 #define VSEN1_HV_REG 0x40 /* Bank 0; 2 regs (HV/LV) per sensor */
60 #define TEMP_CH1_HV_REG 0x42 /* Bank 0; same as VSEN2_HV */
61 #define LTD_HV_REG 0x62 /* Bank 0; 2 regs in VSEN range */
62 #define LTD_HV_HL_REG 0x44 /* Bank 1; 1 reg for LTD */
63 #define LTD_LV_HL_REG 0x45 /* Bank 1; 1 reg for LTD */
64 #define LTD_HV_LL_REG 0x46 /* Bank 1; 1 reg for LTD */
65 #define LTD_LV_LL_REG 0x47 /* Bank 1; 1 reg for LTD */
66 #define TEMP_CH1_CH_REG 0x05 /* Bank 1; 1 reg for LTD */
67 #define TEMP_CH1_W_REG 0x06 /* Bank 1; 1 reg for LTD */
68 #define TEMP_CH1_WH_REG 0x07 /* Bank 1; 1 reg for LTD */
69 #define TEMP_CH1_C_REG 0x04 /* Bank 1; 1 reg per sensor */
70 #define DTS_T_CPU1_C_REG 0x90 /* Bank 1; 1 reg per sensor */
71 #define DTS_T_CPU1_CH_REG 0x91 /* Bank 1; 1 reg per sensor */
72 #define DTS_T_CPU1_W_REG 0x92 /* Bank 1; 1 reg per sensor */
73 #define DTS_T_CPU1_WH_REG 0x93 /* Bank 1; 1 reg per sensor */
74 #define FANIN1_HV_REG 0x80 /* Bank 0; 2 regs (HV/LV) per sensor */
75 #define FANIN1_HV_HL_REG 0x60 /* Bank 1; 2 regs (HV/LV) per sensor */
76 #define FANIN1_LV_HL_REG 0x61 /* Bank 1; 2 regs (HV/LV) per sensor */
77 #define T_CPU1_HV_REG 0xA0 /* Bank 0; 2 regs (HV/LV) per sensor */
79 #define PRTS_REG 0x03 /* Bank 2 */
80 #define PFE_REG 0x00 /* Bank 2; PECI Function Enable */
81 #define TSI_CTRL_REG 0x50 /* Bank 2; TSI Control Register */
82 #define FANCTL1_FMR_REG 0x00 /* Bank 3; 1 reg per channel */
83 #define FANCTL1_OUT_REG 0x10 /* Bank 3; 1 reg per channel */
85 #define ENABLE_TSI BIT(1)
87 static const unsigned short normal_i2c[] = {
88 0x2d, 0x2e, I2C_CLIENT_END
92 struct i2c_client *client;
93 struct mutex bank_lock;
98 u8 fan_mode[FANCTL_MAX];
101 u8 temp_mode; /* 0: TR mode, 1: TD mode */
106 /* Access functions */
107 static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank)
111 mutex_lock(&data->bank_lock);
112 if (data->bank_sel == bank)
114 ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank);
116 data->bank_sel = bank;
122 static inline void nct7904_bank_release(struct nct7904_data *data)
124 mutex_unlock(&data->bank_lock);
127 /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */
128 static int nct7904_read_reg(struct nct7904_data *data,
129 unsigned int bank, unsigned int reg)
131 struct i2c_client *client = data->client;
134 ret = nct7904_bank_lock(data, bank);
136 ret = i2c_smbus_read_byte_data(client, reg);
138 nct7904_bank_release(data);
143 * Read 2-byte register. Returns register in big-endian format or
146 static int nct7904_read_reg16(struct nct7904_data *data,
147 unsigned int bank, unsigned int reg)
149 struct i2c_client *client = data->client;
152 ret = nct7904_bank_lock(data, bank);
154 ret = i2c_smbus_read_byte_data(client, reg);
157 ret = i2c_smbus_read_byte_data(client, reg + 1);
163 nct7904_bank_release(data);
167 /* Write 1-byte register. Returns 0 or -ERRNO on error. */
168 static int nct7904_write_reg(struct nct7904_data *data,
169 unsigned int bank, unsigned int reg, u8 val)
171 struct i2c_client *client = data->client;
174 ret = nct7904_bank_lock(data, bank);
176 ret = i2c_smbus_write_byte_data(client, reg, val);
178 nct7904_bank_release(data);
182 static int nct7904_read_fan(struct device *dev, u32 attr, int channel,
185 struct nct7904_data *data = dev_get_drvdata(dev);
186 unsigned int cnt, rpm;
190 case hwmon_fan_input:
191 ret = nct7904_read_reg16(data, BANK_0,
192 FANIN1_HV_REG + channel * 2);
195 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
203 ret = nct7904_read_reg16(data, BANK_1,
204 FANIN1_HV_HL_REG + channel * 2);
207 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
214 case hwmon_fan_alarm:
215 ret = nct7904_read_reg(data, BANK_0,
216 SMI_STS5_REG + (channel >> 3));
219 if (!data->fan_alarm[channel >> 3])
220 data->fan_alarm[channel >> 3] = ret & 0xff;
222 /* If there is new alarm showing up */
223 data->fan_alarm[channel >> 3] |= (ret & 0xff);
224 *val = (data->fan_alarm[channel >> 3] >> (channel & 0x07)) & 1;
225 /* Needs to clean the alarm if alarm existing */
227 data->fan_alarm[channel >> 3] ^= 1 << (channel & 0x07);
234 static umode_t nct7904_fan_is_visible(const void *_data, u32 attr, int channel)
236 const struct nct7904_data *data = _data;
239 case hwmon_fan_input:
240 case hwmon_fan_alarm:
241 if (data->fanin_mask & (1 << channel))
245 if (data->fanin_mask & (1 << channel))
255 static u8 nct7904_chan_to_index[] = {
257 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
261 static int nct7904_read_in(struct device *dev, u32 attr, int channel,
264 struct nct7904_data *data = dev_get_drvdata(dev);
265 int ret, volt, index;
267 index = nct7904_chan_to_index[channel];
271 ret = nct7904_read_reg16(data, BANK_0,
272 VSEN1_HV_REG + index * 2);
275 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
277 volt *= 2; /* 0.002V scale */
279 volt *= 6; /* 0.006V scale */
283 ret = nct7904_read_reg16(data, BANK_1,
284 VSEN1_HV_LL_REG + index * 4);
287 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
289 volt *= 2; /* 0.002V scale */
291 volt *= 6; /* 0.006V scale */
295 ret = nct7904_read_reg16(data, BANK_1,
296 VSEN1_HV_HL_REG + index * 4);
299 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
301 volt *= 2; /* 0.002V scale */
303 volt *= 6; /* 0.006V scale */
307 ret = nct7904_read_reg(data, BANK_0,
308 SMI_STS1_REG + (index >> 3));
311 if (!data->vsen_alarm[index >> 3])
312 data->vsen_alarm[index >> 3] = ret & 0xff;
314 /* If there is new alarm showing up */
315 data->vsen_alarm[index >> 3] |= (ret & 0xff);
316 *val = (data->vsen_alarm[index >> 3] >> (index & 0x07)) & 1;
317 /* Needs to clean the alarm if alarm existing */
319 data->vsen_alarm[index >> 3] ^= 1 << (index & 0x07);
326 static umode_t nct7904_in_is_visible(const void *_data, u32 attr, int channel)
328 const struct nct7904_data *data = _data;
329 int index = nct7904_chan_to_index[channel];
334 if (channel > 0 && (data->vsen_mask & BIT(index)))
339 if (channel > 0 && (data->vsen_mask & BIT(index)))
349 static int nct7904_read_temp(struct device *dev, u32 attr, int channel,
352 struct nct7904_data *data = dev_get_drvdata(dev);
354 unsigned int reg1, reg2, reg3;
357 case hwmon_temp_input:
359 ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG);
360 else if (channel < 5)
361 ret = nct7904_read_reg16(data, BANK_0,
362 TEMP_CH1_HV_REG + channel * 4);
364 ret = nct7904_read_reg16(data, BANK_0,
365 T_CPU1_HV_REG + (channel - 5)
369 temp = ((ret & 0xff00) >> 5) | (ret & 0x7);
370 *val = sign_extend32(temp, 10) * 125;
372 case hwmon_temp_alarm:
374 ret = nct7904_read_reg(data, BANK_0,
378 *val = (ret >> 1) & 1;
379 } else if (channel < 4) {
380 ret = nct7904_read_reg(data, BANK_0,
384 *val = (ret >> (((channel * 2) + 1) & 0x07)) & 1;
386 if ((channel - 5) < 4) {
387 ret = nct7904_read_reg(data, BANK_0,
389 ((channel - 5) >> 3));
392 *val = (ret >> ((channel - 5) & 0x07)) & 1;
394 ret = nct7904_read_reg(data, BANK_0,
396 ((channel - 5) >> 3));
399 *val = (ret >> (((channel - 5) & 0x07) - 4))
404 case hwmon_temp_type:
406 if ((data->tcpu_mask >> channel) & 0x01) {
407 if ((data->temp_mode >> channel) & 0x01)
415 if ((data->has_dts >> (channel - 5)) & 0x01) {
416 if (data->enable_dts & ENABLE_TSI)
426 reg1 = LTD_HV_LL_REG;
427 reg2 = TEMP_CH1_W_REG;
428 reg3 = DTS_T_CPU1_W_REG;
430 case hwmon_temp_max_hyst:
431 reg1 = LTD_LV_LL_REG;
432 reg2 = TEMP_CH1_WH_REG;
433 reg3 = DTS_T_CPU1_WH_REG;
435 case hwmon_temp_crit:
436 reg1 = LTD_HV_HL_REG;
437 reg2 = TEMP_CH1_C_REG;
438 reg3 = DTS_T_CPU1_C_REG;
440 case hwmon_temp_crit_hyst:
441 reg1 = LTD_LV_HL_REG;
442 reg2 = TEMP_CH1_CH_REG;
443 reg3 = DTS_T_CPU1_CH_REG;
450 ret = nct7904_read_reg(data, BANK_1, reg1);
451 else if (channel < 5)
452 ret = nct7904_read_reg(data, BANK_1,
455 ret = nct7904_read_reg(data, BANK_1,
456 reg3 + (channel - 5) * 4);
464 static umode_t nct7904_temp_is_visible(const void *_data, u32 attr, int channel)
466 const struct nct7904_data *data = _data;
469 case hwmon_temp_input:
470 case hwmon_temp_alarm:
471 case hwmon_temp_type:
473 if (data->tcpu_mask & BIT(channel))
476 if (data->has_dts & BIT(channel - 5))
481 case hwmon_temp_max_hyst:
482 case hwmon_temp_crit:
483 case hwmon_temp_crit_hyst:
485 if (data->tcpu_mask & BIT(channel))
488 if (data->has_dts & BIT(channel - 5))
499 static int nct7904_read_pwm(struct device *dev, u32 attr, int channel,
502 struct nct7904_data *data = dev_get_drvdata(dev);
506 case hwmon_pwm_input:
507 ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel);
512 case hwmon_pwm_enable:
513 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel);
524 static int nct7904_write_temp(struct device *dev, u32 attr, int channel,
527 struct nct7904_data *data = dev_get_drvdata(dev);
529 unsigned int reg1, reg2, reg3;
531 val = clamp_val(val / 1000, -128, 127);
535 reg1 = LTD_HV_LL_REG;
536 reg2 = TEMP_CH1_W_REG;
537 reg3 = DTS_T_CPU1_W_REG;
539 case hwmon_temp_max_hyst:
540 reg1 = LTD_LV_LL_REG;
541 reg2 = TEMP_CH1_WH_REG;
542 reg3 = DTS_T_CPU1_WH_REG;
544 case hwmon_temp_crit:
545 reg1 = LTD_HV_HL_REG;
546 reg2 = TEMP_CH1_C_REG;
547 reg3 = DTS_T_CPU1_C_REG;
549 case hwmon_temp_crit_hyst:
550 reg1 = LTD_LV_HL_REG;
551 reg2 = TEMP_CH1_CH_REG;
552 reg3 = DTS_T_CPU1_CH_REG;
558 ret = nct7904_write_reg(data, BANK_1, reg1, val);
559 else if (channel < 5)
560 ret = nct7904_write_reg(data, BANK_1,
561 reg2 + channel * 8, val);
563 ret = nct7904_write_reg(data, BANK_1,
564 reg3 + (channel - 5) * 4, val);
569 static int nct7904_write_fan(struct device *dev, u32 attr, int channel,
572 struct nct7904_data *data = dev_get_drvdata(dev);
581 val = clamp_val(DIV_ROUND_CLOSEST(1350000, val), 1, 0x1fff);
582 tmp = (val >> 5) & 0xff;
583 ret = nct7904_write_reg(data, BANK_1,
584 FANIN1_HV_HL_REG + channel * 2, tmp);
588 ret = nct7904_write_reg(data, BANK_1,
589 FANIN1_LV_HL_REG + channel * 2, tmp);
596 static int nct7904_write_in(struct device *dev, u32 attr, int channel,
599 struct nct7904_data *data = dev_get_drvdata(dev);
602 index = nct7904_chan_to_index[channel];
605 val = val / 2; /* 0.002V scale */
607 val = val / 6; /* 0.006V scale */
609 val = clamp_val(val, 0, 0x7ff);
613 tmp = nct7904_read_reg(data, BANK_1,
614 VSEN1_LV_LL_REG + index * 4);
619 ret = nct7904_write_reg(data, BANK_1,
620 VSEN1_LV_LL_REG + index * 4, tmp);
623 tmp = nct7904_read_reg(data, BANK_1,
624 VSEN1_HV_LL_REG + index * 4);
627 tmp = (val >> 3) & 0xff;
628 ret = nct7904_write_reg(data, BANK_1,
629 VSEN1_HV_LL_REG + index * 4, tmp);
632 tmp = nct7904_read_reg(data, BANK_1,
633 VSEN1_LV_HL_REG + index * 4);
638 ret = nct7904_write_reg(data, BANK_1,
639 VSEN1_LV_HL_REG + index * 4, tmp);
642 tmp = nct7904_read_reg(data, BANK_1,
643 VSEN1_HV_HL_REG + index * 4);
646 tmp = (val >> 3) & 0xff;
647 ret = nct7904_write_reg(data, BANK_1,
648 VSEN1_HV_HL_REG + index * 4, tmp);
655 static int nct7904_write_pwm(struct device *dev, u32 attr, int channel,
658 struct nct7904_data *data = dev_get_drvdata(dev);
662 case hwmon_pwm_input:
663 if (val < 0 || val > 255)
665 ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel,
668 case hwmon_pwm_enable:
669 if (val < 1 || val > 2 ||
670 (val == 2 && !data->fan_mode[channel]))
672 ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel,
673 val == 2 ? data->fan_mode[channel] : 0);
680 static umode_t nct7904_pwm_is_visible(const void *_data, u32 attr, int channel)
683 case hwmon_pwm_input:
684 case hwmon_pwm_enable:
691 static int nct7904_read(struct device *dev, enum hwmon_sensor_types type,
692 u32 attr, int channel, long *val)
696 return nct7904_read_in(dev, attr, channel, val);
698 return nct7904_read_fan(dev, attr, channel, val);
700 return nct7904_read_pwm(dev, attr, channel, val);
702 return nct7904_read_temp(dev, attr, channel, val);
708 static int nct7904_write(struct device *dev, enum hwmon_sensor_types type,
709 u32 attr, int channel, long val)
713 return nct7904_write_in(dev, attr, channel, val);
715 return nct7904_write_fan(dev, attr, channel, val);
717 return nct7904_write_pwm(dev, attr, channel, val);
719 return nct7904_write_temp(dev, attr, channel, val);
725 static umode_t nct7904_is_visible(const void *data,
726 enum hwmon_sensor_types type,
727 u32 attr, int channel)
731 return nct7904_in_is_visible(data, attr, channel);
733 return nct7904_fan_is_visible(data, attr, channel);
735 return nct7904_pwm_is_visible(data, attr, channel);
737 return nct7904_temp_is_visible(data, attr, channel);
743 /* Return 0 if detection is successful, -ENODEV otherwise */
744 static int nct7904_detect(struct i2c_client *client,
745 struct i2c_board_info *info)
747 struct i2c_adapter *adapter = client->adapter;
749 if (!i2c_check_functionality(adapter,
750 I2C_FUNC_SMBUS_READ_BYTE |
751 I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
754 /* Determine the chip type. */
755 if (i2c_smbus_read_byte_data(client, VENDOR_ID_REG) != NUVOTON_ID ||
756 i2c_smbus_read_byte_data(client, CHIP_ID_REG) != NCT7904_ID ||
757 (i2c_smbus_read_byte_data(client, DEVICE_ID_REG) & 0xf0) != 0x50 ||
758 (i2c_smbus_read_byte_data(client, BANK_SEL_REG) & 0xf8) != 0x00)
761 strlcpy(info->type, "nct7904", I2C_NAME_SIZE);
766 static const struct hwmon_channel_info *nct7904_info[] = {
767 HWMON_CHANNEL_INFO(in,
768 /* dummy, skipped in is_visible */
769 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
771 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
773 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
775 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
777 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
779 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
781 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
783 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
785 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
787 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
789 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
791 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
793 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
795 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
797 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
799 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
801 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
803 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
805 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
807 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
809 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
811 HWMON_CHANNEL_INFO(fan,
812 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
813 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
814 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
815 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
816 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
817 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
818 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
819 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM),
820 HWMON_CHANNEL_INFO(pwm,
821 HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
822 HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
823 HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
824 HWMON_PWM_INPUT | HWMON_PWM_ENABLE),
825 HWMON_CHANNEL_INFO(temp,
826 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
827 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
829 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
830 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
832 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
833 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
835 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
836 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
838 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
839 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
841 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
842 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
844 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
845 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
847 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
848 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
850 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
851 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
856 static const struct hwmon_ops nct7904_hwmon_ops = {
857 .is_visible = nct7904_is_visible,
858 .read = nct7904_read,
859 .write = nct7904_write,
862 static const struct hwmon_chip_info nct7904_chip_info = {
863 .ops = &nct7904_hwmon_ops,
864 .info = nct7904_info,
867 static int nct7904_probe(struct i2c_client *client,
868 const struct i2c_device_id *id)
870 struct nct7904_data *data;
871 struct device *hwmon_dev;
872 struct device *dev = &client->dev;
877 data = devm_kzalloc(dev, sizeof(struct nct7904_data), GFP_KERNEL);
881 data->client = client;
882 mutex_init(&data->bank_lock);
885 /* Setup sensor groups. */
886 /* FANIN attributes */
887 ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG);
890 data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8);
895 * Note: voltage sensors overlap with external temperature
896 * sensors. So, if we ever decide to support the latter
897 * we will have to adjust 'vsen_mask' accordingly.
900 ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG);
902 mask = (ret >> 8) | ((ret & 0xff) << 8);
903 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
906 data->vsen_mask = mask;
908 /* CPU_TEMP attributes */
909 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG);
913 if ((ret & 0x6) == 0x6)
914 data->tcpu_mask |= 1; /* TR1 */
915 if ((ret & 0x18) == 0x18)
916 data->tcpu_mask |= 2; /* TR2 */
917 if ((ret & 0x20) == 0x20)
918 data->tcpu_mask |= 4; /* TR3 */
919 if ((ret & 0x80) == 0x80)
920 data->tcpu_mask |= 8; /* TR4 */
923 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
926 if ((ret & 0x02) == 0x02)
927 data->tcpu_mask |= 0x10;
929 /* Multi-Function detecting for Volt and TR/TD */
930 ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG);
935 for (i = 0; i < 4; i++) {
936 val = (ret >> (i * 2)) & 0x03;
939 data->tcpu_mask &= ~bit;
941 if (val == 0x1 || val == 0x2)
942 data->temp_mode |= bit;
943 data->vsen_mask &= ~(0x06 << (i * 2));
948 ret = nct7904_read_reg(data, BANK_2, PFE_REG);
952 data->enable_dts = 1; /* Enable DTS & PECI */
954 ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG);
958 data->enable_dts = 0x3; /* Enable DTS & TSI */
961 /* Check DTS enable status */
962 if (data->enable_dts) {
963 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG);
966 data->has_dts = ret & 0xF;
967 if (data->enable_dts & ENABLE_TSI) {
968 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG);
971 data->has_dts |= (ret & 0xF) << 4;
975 for (i = 0; i < FANCTL_MAX; i++) {
976 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i);
979 data->fan_mode[i] = ret;
983 devm_hwmon_device_register_with_info(dev, client->name, data,
984 &nct7904_chip_info, NULL);
985 return PTR_ERR_OR_ZERO(hwmon_dev);
988 static const struct i2c_device_id nct7904_id[] = {
992 MODULE_DEVICE_TABLE(i2c, nct7904_id);
994 static struct i2c_driver nct7904_driver = {
995 .class = I2C_CLASS_HWMON,
999 .probe = nct7904_probe,
1000 .id_table = nct7904_id,
1001 .detect = nct7904_detect,
1002 .address_list = normal_i2c,
1005 module_i2c_driver(nct7904_driver);
1007 MODULE_AUTHOR("Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>");
1008 MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904");
1009 MODULE_LICENSE("GPL");