1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * nct7904.c - driver for Nuvoton NCT7904D.
5 * Copyright (c) 2015 Kontron
6 * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>
8 * Copyright (c) 2019 Advantech
9 * Author: Amy.Shih <amy.shih@advantech.com.tw>
11 * Copyright (c) 2020 Advantech
12 * Author: Yuechao Zhao <yuechao.zhao@advantech.com.cn>
14 * Supports the following chips:
16 * Chip #vin #fan #pwm #temp #dts chip ID
17 * nct7904d 20 12 4 5 8 0xc5
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/init.h>
23 #include <linux/i2c.h>
24 #include <linux/mutex.h>
25 #include <linux/hwmon.h>
26 #include <linux/watchdog.h>
28 #define VENDOR_ID_REG 0x7A /* Any bank */
29 #define NUVOTON_ID 0x50
30 #define CHIP_ID_REG 0x7B /* Any bank */
31 #define NCT7904_ID 0xC5
32 #define DEVICE_ID_REG 0x7C /* Any bank */
34 #define BANK_SEL_REG 0xFF
42 #define FANIN_MAX 12 /* Counted from 1 */
43 #define VSEN_MAX 21 /* VSEN1..14, 3VDD, VBAT, V3VSB,
44 LTD (not a voltage), VSEN17..19 */
45 #define FANCTL_MAX 4 /* Counted from 1 */
46 #define TCPU_MAX 8 /* Counted from 1 */
47 #define TEMP_MAX 4 /* Counted from 1 */
48 #define SMI_STS_MAX 10 /* Counted from 1 */
50 #define VT_ADC_CTRL0_REG 0x20 /* Bank 0 */
51 #define VT_ADC_CTRL1_REG 0x21 /* Bank 0 */
52 #define VT_ADC_CTRL2_REG 0x22 /* Bank 0 */
53 #define FANIN_CTRL0_REG 0x24
54 #define FANIN_CTRL1_REG 0x25
55 #define DTS_T_CTRL0_REG 0x26
56 #define DTS_T_CTRL1_REG 0x27
57 #define VT_ADC_MD_REG 0x2E
59 #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */
60 #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */
61 #define VSEN1_HV_HL_REG 0x00 /* Bank 1; 2 regs (HV/LV) per sensor */
62 #define VSEN1_LV_HL_REG 0x01 /* Bank 1; 2 regs (HV/LV) per sensor */
63 #define SMI_STS1_REG 0xC1 /* Bank 0; SMI Status Register */
64 #define SMI_STS3_REG 0xC3 /* Bank 0; SMI Status Register */
65 #define SMI_STS5_REG 0xC5 /* Bank 0; SMI Status Register */
66 #define SMI_STS7_REG 0xC7 /* Bank 0; SMI Status Register */
67 #define SMI_STS8_REG 0xC8 /* Bank 0; SMI Status Register */
69 #define VSEN1_HV_REG 0x40 /* Bank 0; 2 regs (HV/LV) per sensor */
70 #define TEMP_CH1_HV_REG 0x42 /* Bank 0; same as VSEN2_HV */
71 #define LTD_HV_REG 0x62 /* Bank 0; 2 regs in VSEN range */
72 #define LTD_HV_HL_REG 0x44 /* Bank 1; 1 reg for LTD */
73 #define LTD_LV_HL_REG 0x45 /* Bank 1; 1 reg for LTD */
74 #define LTD_HV_LL_REG 0x46 /* Bank 1; 1 reg for LTD */
75 #define LTD_LV_LL_REG 0x47 /* Bank 1; 1 reg for LTD */
76 #define TEMP_CH1_CH_REG 0x05 /* Bank 1; 1 reg for LTD */
77 #define TEMP_CH1_W_REG 0x06 /* Bank 1; 1 reg for LTD */
78 #define TEMP_CH1_WH_REG 0x07 /* Bank 1; 1 reg for LTD */
79 #define TEMP_CH1_C_REG 0x04 /* Bank 1; 1 reg per sensor */
80 #define DTS_T_CPU1_C_REG 0x90 /* Bank 1; 1 reg per sensor */
81 #define DTS_T_CPU1_CH_REG 0x91 /* Bank 1; 1 reg per sensor */
82 #define DTS_T_CPU1_W_REG 0x92 /* Bank 1; 1 reg per sensor */
83 #define DTS_T_CPU1_WH_REG 0x93 /* Bank 1; 1 reg per sensor */
84 #define FANIN1_HV_REG 0x80 /* Bank 0; 2 regs (HV/LV) per sensor */
85 #define FANIN1_HV_HL_REG 0x60 /* Bank 1; 2 regs (HV/LV) per sensor */
86 #define FANIN1_LV_HL_REG 0x61 /* Bank 1; 2 regs (HV/LV) per sensor */
87 #define T_CPU1_HV_REG 0xA0 /* Bank 0; 2 regs (HV/LV) per sensor */
89 #define PRTS_REG 0x03 /* Bank 2 */
90 #define PFE_REG 0x00 /* Bank 2; PECI Function Enable */
91 #define TSI_CTRL_REG 0x50 /* Bank 2; TSI Control Register */
92 #define FANCTL1_FMR_REG 0x00 /* Bank 3; 1 reg per channel */
93 #define FANCTL1_OUT_REG 0x10 /* Bank 3; 1 reg per channel */
95 #define WDT_LOCK_REG 0xE0 /* W/O Lock Watchdog Register */
96 #define WDT_EN_REG 0xE1 /* R/O Watchdog Enable Register */
97 #define WDT_STS_REG 0xE2 /* R/O Watchdog Status Register */
98 #define WDT_TIMER_REG 0xE3 /* R/W Watchdog Timer Register */
99 #define WDT_SOFT_EN 0x55 /* Enable soft watchdog timer */
100 #define WDT_SOFT_DIS 0xAA /* Disable soft watchdog timer */
102 #define VOLT_MONITOR_MODE 0x0
103 #define THERMAL_DIODE_MODE 0x1
104 #define THERMISTOR_MODE 0x3
106 #define ENABLE_TSI BIT(1)
108 #define WATCHDOG_TIMEOUT 1 /* 1 minute default timeout */
110 /*The timeout range is 1-255 minutes*/
111 #define MIN_TIMEOUT (1 * 60)
112 #define MAX_TIMEOUT (255 * 60)
115 module_param(timeout, int, 0);
116 MODULE_PARM_DESC(timeout, "Watchdog timeout in minutes. 1 <= timeout <= 255, default="
117 __MODULE_STRING(WATCHDOG_TIMEOUT) ".");
119 static bool nowayout = WATCHDOG_NOWAYOUT;
120 module_param(nowayout, bool, 0);
121 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
122 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
124 static const unsigned short normal_i2c[] = {
125 0x2d, 0x2e, I2C_CLIENT_END
128 struct nct7904_data {
129 struct i2c_client *client;
130 struct watchdog_device wdt;
131 struct mutex bank_lock;
136 u8 fan_mode[FANCTL_MAX];
139 u8 temp_mode; /* 0: TR mode, 1: TD mode */
144 /* Access functions */
145 static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank)
149 mutex_lock(&data->bank_lock);
150 if (data->bank_sel == bank)
152 ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank);
154 data->bank_sel = bank;
160 static inline void nct7904_bank_release(struct nct7904_data *data)
162 mutex_unlock(&data->bank_lock);
165 /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */
166 static int nct7904_read_reg(struct nct7904_data *data,
167 unsigned int bank, unsigned int reg)
169 struct i2c_client *client = data->client;
172 ret = nct7904_bank_lock(data, bank);
174 ret = i2c_smbus_read_byte_data(client, reg);
176 nct7904_bank_release(data);
181 * Read 2-byte register. Returns register in big-endian format or
184 static int nct7904_read_reg16(struct nct7904_data *data,
185 unsigned int bank, unsigned int reg)
187 struct i2c_client *client = data->client;
190 ret = nct7904_bank_lock(data, bank);
192 ret = i2c_smbus_read_byte_data(client, reg);
195 ret = i2c_smbus_read_byte_data(client, reg + 1);
201 nct7904_bank_release(data);
205 /* Write 1-byte register. Returns 0 or -ERRNO on error. */
206 static int nct7904_write_reg(struct nct7904_data *data,
207 unsigned int bank, unsigned int reg, u8 val)
209 struct i2c_client *client = data->client;
212 ret = nct7904_bank_lock(data, bank);
214 ret = i2c_smbus_write_byte_data(client, reg, val);
216 nct7904_bank_release(data);
220 static int nct7904_read_fan(struct device *dev, u32 attr, int channel,
223 struct nct7904_data *data = dev_get_drvdata(dev);
224 unsigned int cnt, rpm;
228 case hwmon_fan_input:
229 ret = nct7904_read_reg16(data, BANK_0,
230 FANIN1_HV_REG + channel * 2);
233 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
234 if (cnt == 0 || cnt == 0x1fff)
241 ret = nct7904_read_reg16(data, BANK_1,
242 FANIN1_HV_HL_REG + channel * 2);
245 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
246 if (cnt == 0 || cnt == 0x1fff)
252 case hwmon_fan_alarm:
253 ret = nct7904_read_reg(data, BANK_0,
254 SMI_STS5_REG + (channel >> 3));
257 if (!data->fan_alarm[channel >> 3])
258 data->fan_alarm[channel >> 3] = ret & 0xff;
260 /* If there is new alarm showing up */
261 data->fan_alarm[channel >> 3] |= (ret & 0xff);
262 *val = (data->fan_alarm[channel >> 3] >> (channel & 0x07)) & 1;
263 /* Needs to clean the alarm if alarm existing */
265 data->fan_alarm[channel >> 3] ^= 1 << (channel & 0x07);
272 static umode_t nct7904_fan_is_visible(const void *_data, u32 attr, int channel)
274 const struct nct7904_data *data = _data;
277 case hwmon_fan_input:
278 case hwmon_fan_alarm:
279 if (data->fanin_mask & (1 << channel))
283 if (data->fanin_mask & (1 << channel))
293 static u8 nct7904_chan_to_index[] = {
295 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
299 static int nct7904_read_in(struct device *dev, u32 attr, int channel,
302 struct nct7904_data *data = dev_get_drvdata(dev);
303 int ret, volt, index;
305 index = nct7904_chan_to_index[channel];
309 ret = nct7904_read_reg16(data, BANK_0,
310 VSEN1_HV_REG + index * 2);
313 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
315 volt *= 2; /* 0.002V scale */
317 volt *= 6; /* 0.006V scale */
321 ret = nct7904_read_reg16(data, BANK_1,
322 VSEN1_HV_LL_REG + index * 4);
325 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
327 volt *= 2; /* 0.002V scale */
329 volt *= 6; /* 0.006V scale */
333 ret = nct7904_read_reg16(data, BANK_1,
334 VSEN1_HV_HL_REG + index * 4);
337 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
339 volt *= 2; /* 0.002V scale */
341 volt *= 6; /* 0.006V scale */
345 ret = nct7904_read_reg(data, BANK_0,
346 SMI_STS1_REG + (index >> 3));
349 if (!data->vsen_alarm[index >> 3])
350 data->vsen_alarm[index >> 3] = ret & 0xff;
352 /* If there is new alarm showing up */
353 data->vsen_alarm[index >> 3] |= (ret & 0xff);
354 *val = (data->vsen_alarm[index >> 3] >> (index & 0x07)) & 1;
355 /* Needs to clean the alarm if alarm existing */
357 data->vsen_alarm[index >> 3] ^= 1 << (index & 0x07);
364 static umode_t nct7904_in_is_visible(const void *_data, u32 attr, int channel)
366 const struct nct7904_data *data = _data;
367 int index = nct7904_chan_to_index[channel];
372 if (channel > 0 && (data->vsen_mask & BIT(index)))
377 if (channel > 0 && (data->vsen_mask & BIT(index)))
387 static int nct7904_read_temp(struct device *dev, u32 attr, int channel,
390 struct nct7904_data *data = dev_get_drvdata(dev);
392 unsigned int reg1, reg2, reg3;
396 case hwmon_temp_input:
398 ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG);
399 else if (channel < 5)
400 ret = nct7904_read_reg16(data, BANK_0,
401 TEMP_CH1_HV_REG + channel * 4);
403 ret = nct7904_read_reg16(data, BANK_0,
404 T_CPU1_HV_REG + (channel - 5)
408 temp = ((ret & 0xff00) >> 5) | (ret & 0x7);
409 *val = sign_extend32(temp, 10) * 125;
411 case hwmon_temp_alarm:
413 ret = nct7904_read_reg(data, BANK_0,
417 *val = (ret >> 1) & 1;
418 } else if (channel < 4) {
419 ret = nct7904_read_reg(data, BANK_0,
423 *val = (ret >> (((channel * 2) + 1) & 0x07)) & 1;
425 if ((channel - 5) < 4) {
426 ret = nct7904_read_reg(data, BANK_0,
428 ((channel - 5) >> 3));
431 *val = (ret >> ((channel - 5) & 0x07)) & 1;
433 ret = nct7904_read_reg(data, BANK_0,
435 ((channel - 5) >> 3));
438 *val = (ret >> (((channel - 5) & 0x07) - 4))
443 case hwmon_temp_type:
445 if ((data->tcpu_mask >> channel) & 0x01) {
446 if ((data->temp_mode >> channel) & 0x01)
454 if ((data->has_dts >> (channel - 5)) & 0x01) {
455 if (data->enable_dts & ENABLE_TSI)
465 reg1 = LTD_HV_LL_REG;
466 reg2 = TEMP_CH1_W_REG;
467 reg3 = DTS_T_CPU1_W_REG;
469 case hwmon_temp_max_hyst:
470 reg1 = LTD_LV_LL_REG;
471 reg2 = TEMP_CH1_WH_REG;
472 reg3 = DTS_T_CPU1_WH_REG;
474 case hwmon_temp_crit:
475 reg1 = LTD_HV_HL_REG;
476 reg2 = TEMP_CH1_C_REG;
477 reg3 = DTS_T_CPU1_C_REG;
479 case hwmon_temp_crit_hyst:
480 reg1 = LTD_LV_HL_REG;
481 reg2 = TEMP_CH1_CH_REG;
482 reg3 = DTS_T_CPU1_CH_REG;
489 ret = nct7904_read_reg(data, BANK_1, reg1);
490 else if (channel < 5)
491 ret = nct7904_read_reg(data, BANK_1,
494 ret = nct7904_read_reg(data, BANK_1,
495 reg3 + (channel - 5) * 4);
504 static umode_t nct7904_temp_is_visible(const void *_data, u32 attr, int channel)
506 const struct nct7904_data *data = _data;
509 case hwmon_temp_input:
510 case hwmon_temp_alarm:
511 case hwmon_temp_type:
513 if (data->tcpu_mask & BIT(channel))
516 if (data->has_dts & BIT(channel - 5))
521 case hwmon_temp_max_hyst:
522 case hwmon_temp_crit:
523 case hwmon_temp_crit_hyst:
525 if (data->tcpu_mask & BIT(channel))
528 if (data->has_dts & BIT(channel - 5))
539 static int nct7904_read_pwm(struct device *dev, u32 attr, int channel,
542 struct nct7904_data *data = dev_get_drvdata(dev);
546 case hwmon_pwm_input:
547 ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel);
552 case hwmon_pwm_enable:
553 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel);
564 static int nct7904_write_temp(struct device *dev, u32 attr, int channel,
567 struct nct7904_data *data = dev_get_drvdata(dev);
569 unsigned int reg1, reg2, reg3;
571 val = clamp_val(val / 1000, -128, 127);
575 reg1 = LTD_HV_LL_REG;
576 reg2 = TEMP_CH1_W_REG;
577 reg3 = DTS_T_CPU1_W_REG;
579 case hwmon_temp_max_hyst:
580 reg1 = LTD_LV_LL_REG;
581 reg2 = TEMP_CH1_WH_REG;
582 reg3 = DTS_T_CPU1_WH_REG;
584 case hwmon_temp_crit:
585 reg1 = LTD_HV_HL_REG;
586 reg2 = TEMP_CH1_C_REG;
587 reg3 = DTS_T_CPU1_C_REG;
589 case hwmon_temp_crit_hyst:
590 reg1 = LTD_LV_HL_REG;
591 reg2 = TEMP_CH1_CH_REG;
592 reg3 = DTS_T_CPU1_CH_REG;
598 ret = nct7904_write_reg(data, BANK_1, reg1, val);
599 else if (channel < 5)
600 ret = nct7904_write_reg(data, BANK_1,
601 reg2 + channel * 8, val);
603 ret = nct7904_write_reg(data, BANK_1,
604 reg3 + (channel - 5) * 4, val);
609 static int nct7904_write_fan(struct device *dev, u32 attr, int channel,
612 struct nct7904_data *data = dev_get_drvdata(dev);
621 val = clamp_val(DIV_ROUND_CLOSEST(1350000, val), 1, 0x1fff);
622 tmp = (val >> 5) & 0xff;
623 ret = nct7904_write_reg(data, BANK_1,
624 FANIN1_HV_HL_REG + channel * 2, tmp);
628 ret = nct7904_write_reg(data, BANK_1,
629 FANIN1_LV_HL_REG + channel * 2, tmp);
636 static int nct7904_write_in(struct device *dev, u32 attr, int channel,
639 struct nct7904_data *data = dev_get_drvdata(dev);
642 index = nct7904_chan_to_index[channel];
645 val = val / 2; /* 0.002V scale */
647 val = val / 6; /* 0.006V scale */
649 val = clamp_val(val, 0, 0x7ff);
653 tmp = nct7904_read_reg(data, BANK_1,
654 VSEN1_LV_LL_REG + index * 4);
659 ret = nct7904_write_reg(data, BANK_1,
660 VSEN1_LV_LL_REG + index * 4, tmp);
663 tmp = nct7904_read_reg(data, BANK_1,
664 VSEN1_HV_LL_REG + index * 4);
667 tmp = (val >> 3) & 0xff;
668 ret = nct7904_write_reg(data, BANK_1,
669 VSEN1_HV_LL_REG + index * 4, tmp);
672 tmp = nct7904_read_reg(data, BANK_1,
673 VSEN1_LV_HL_REG + index * 4);
678 ret = nct7904_write_reg(data, BANK_1,
679 VSEN1_LV_HL_REG + index * 4, tmp);
682 tmp = nct7904_read_reg(data, BANK_1,
683 VSEN1_HV_HL_REG + index * 4);
686 tmp = (val >> 3) & 0xff;
687 ret = nct7904_write_reg(data, BANK_1,
688 VSEN1_HV_HL_REG + index * 4, tmp);
695 static int nct7904_write_pwm(struct device *dev, u32 attr, int channel,
698 struct nct7904_data *data = dev_get_drvdata(dev);
702 case hwmon_pwm_input:
703 if (val < 0 || val > 255)
705 ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel,
708 case hwmon_pwm_enable:
709 if (val < 1 || val > 2 ||
710 (val == 2 && !data->fan_mode[channel]))
712 ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel,
713 val == 2 ? data->fan_mode[channel] : 0);
720 static umode_t nct7904_pwm_is_visible(const void *_data, u32 attr, int channel)
723 case hwmon_pwm_input:
724 case hwmon_pwm_enable:
731 static int nct7904_read(struct device *dev, enum hwmon_sensor_types type,
732 u32 attr, int channel, long *val)
736 return nct7904_read_in(dev, attr, channel, val);
738 return nct7904_read_fan(dev, attr, channel, val);
740 return nct7904_read_pwm(dev, attr, channel, val);
742 return nct7904_read_temp(dev, attr, channel, val);
748 static int nct7904_write(struct device *dev, enum hwmon_sensor_types type,
749 u32 attr, int channel, long val)
753 return nct7904_write_in(dev, attr, channel, val);
755 return nct7904_write_fan(dev, attr, channel, val);
757 return nct7904_write_pwm(dev, attr, channel, val);
759 return nct7904_write_temp(dev, attr, channel, val);
765 static umode_t nct7904_is_visible(const void *data,
766 enum hwmon_sensor_types type,
767 u32 attr, int channel)
771 return nct7904_in_is_visible(data, attr, channel);
773 return nct7904_fan_is_visible(data, attr, channel);
775 return nct7904_pwm_is_visible(data, attr, channel);
777 return nct7904_temp_is_visible(data, attr, channel);
783 /* Return 0 if detection is successful, -ENODEV otherwise */
784 static int nct7904_detect(struct i2c_client *client,
785 struct i2c_board_info *info)
787 struct i2c_adapter *adapter = client->adapter;
789 if (!i2c_check_functionality(adapter,
790 I2C_FUNC_SMBUS_READ_BYTE |
791 I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
794 /* Determine the chip type. */
795 if (i2c_smbus_read_byte_data(client, VENDOR_ID_REG) != NUVOTON_ID ||
796 i2c_smbus_read_byte_data(client, CHIP_ID_REG) != NCT7904_ID ||
797 (i2c_smbus_read_byte_data(client, DEVICE_ID_REG) & 0xf0) != 0x50 ||
798 (i2c_smbus_read_byte_data(client, BANK_SEL_REG) & 0xf8) != 0x00)
801 strlcpy(info->type, "nct7904", I2C_NAME_SIZE);
806 static const struct hwmon_channel_info *nct7904_info[] = {
807 HWMON_CHANNEL_INFO(in,
808 /* dummy, skipped in is_visible */
809 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
811 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
813 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
815 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
817 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
819 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
821 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
823 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
825 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
827 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
829 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
831 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
833 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
835 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
837 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
839 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
841 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
843 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
845 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
847 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
849 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
851 HWMON_CHANNEL_INFO(fan,
852 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
853 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
854 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
855 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
856 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
857 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
858 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
859 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
860 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
861 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
862 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
863 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM),
864 HWMON_CHANNEL_INFO(pwm,
865 HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
866 HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
867 HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
868 HWMON_PWM_INPUT | HWMON_PWM_ENABLE),
869 HWMON_CHANNEL_INFO(temp,
870 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
871 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
873 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
874 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
876 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
877 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
879 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
880 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
882 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
883 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
885 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
886 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
888 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
889 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
891 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
892 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
894 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
895 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
897 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
898 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
900 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
901 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
903 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
904 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
906 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
907 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
912 static const struct hwmon_ops nct7904_hwmon_ops = {
913 .is_visible = nct7904_is_visible,
914 .read = nct7904_read,
915 .write = nct7904_write,
918 static const struct hwmon_chip_info nct7904_chip_info = {
919 .ops = &nct7904_hwmon_ops,
920 .info = nct7904_info,
926 static int nct7904_wdt_start(struct watchdog_device *wdt)
928 struct nct7904_data *data = watchdog_get_drvdata(wdt);
930 /* Enable soft watchdog timer */
931 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
934 static int nct7904_wdt_stop(struct watchdog_device *wdt)
936 struct nct7904_data *data = watchdog_get_drvdata(wdt);
938 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
941 static int nct7904_wdt_set_timeout(struct watchdog_device *wdt,
942 unsigned int timeout)
944 struct nct7904_data *data = watchdog_get_drvdata(wdt);
946 * The NCT7904 is very special in watchdog function.
947 * Its minimum unit is minutes. And wdt->timeout needs
948 * to match the actual timeout selected. So, this needs
949 * to be: wdt->timeout = timeout / 60 * 60.
950 * For example, if the user configures a timeout of
951 * 119 seconds, the actual timeout will be 60 seconds.
952 * So, wdt->timeout must then be set to 60 seconds.
954 wdt->timeout = timeout / 60 * 60;
956 return nct7904_write_reg(data, BANK_0, WDT_TIMER_REG,
960 static int nct7904_wdt_ping(struct watchdog_device *wdt)
964 * NCT7904 does not support refreshing WDT_TIMER_REG register when
965 * the watchdog is active. Please disable watchdog before feeding
966 * the watchdog and enable it again.
968 struct nct7904_data *data = watchdog_get_drvdata(wdt);
971 /* Disable soft watchdog timer */
972 ret = nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
977 ret = nct7904_write_reg(data, BANK_0, WDT_TIMER_REG, wdt->timeout / 60);
981 /* Enable soft watchdog timer */
982 return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
985 static unsigned int nct7904_wdt_get_timeleft(struct watchdog_device *wdt)
987 struct nct7904_data *data = watchdog_get_drvdata(wdt);
990 ret = nct7904_read_reg(data, BANK_0, WDT_TIMER_REG);
997 static const struct watchdog_info nct7904_wdt_info = {
998 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
1000 .identity = "nct7904 watchdog",
1003 static const struct watchdog_ops nct7904_wdt_ops = {
1004 .owner = THIS_MODULE,
1005 .start = nct7904_wdt_start,
1006 .stop = nct7904_wdt_stop,
1007 .ping = nct7904_wdt_ping,
1008 .set_timeout = nct7904_wdt_set_timeout,
1009 .get_timeleft = nct7904_wdt_get_timeleft,
1012 static int nct7904_probe(struct i2c_client *client)
1014 struct nct7904_data *data;
1015 struct device *hwmon_dev;
1016 struct device *dev = &client->dev;
1021 data = devm_kzalloc(dev, sizeof(struct nct7904_data), GFP_KERNEL);
1025 data->client = client;
1026 mutex_init(&data->bank_lock);
1027 data->bank_sel = -1;
1029 /* Setup sensor groups. */
1030 /* FANIN attributes */
1031 ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG);
1034 data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8);
1039 * Note: voltage sensors overlap with external temperature
1040 * sensors. So, if we ever decide to support the latter
1041 * we will have to adjust 'vsen_mask' accordingly.
1044 ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG);
1046 mask = (ret >> 8) | ((ret & 0xff) << 8);
1047 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
1049 mask |= (ret << 16);
1050 data->vsen_mask = mask;
1052 /* CPU_TEMP attributes */
1053 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG);
1057 if ((ret & 0x6) == 0x6)
1058 data->tcpu_mask |= 1; /* TR1 */
1059 if ((ret & 0x18) == 0x18)
1060 data->tcpu_mask |= 2; /* TR2 */
1061 if ((ret & 0x20) == 0x20)
1062 data->tcpu_mask |= 4; /* TR3 */
1063 if ((ret & 0x80) == 0x80)
1064 data->tcpu_mask |= 8; /* TR4 */
1067 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
1070 if ((ret & 0x02) == 0x02)
1071 data->tcpu_mask |= 0x10;
1073 /* Multi-Function detecting for Volt and TR/TD */
1074 ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG);
1078 data->temp_mode = 0;
1079 for (i = 0; i < 4; i++) {
1080 val = (ret >> (i * 2)) & 0x03;
1082 if (val == VOLT_MONITOR_MODE) {
1083 data->tcpu_mask &= ~bit;
1084 } else if (val == THERMAL_DIODE_MODE && i < 2) {
1085 data->temp_mode |= bit;
1086 data->vsen_mask &= ~(0x06 << (i * 2));
1087 } else if (val == THERMISTOR_MODE) {
1088 data->vsen_mask &= ~(0x02 << (i * 2));
1091 data->tcpu_mask &= ~bit;
1092 data->vsen_mask &= ~(0x06 << (i * 2));
1097 ret = nct7904_read_reg(data, BANK_2, PFE_REG);
1101 data->enable_dts = 1; /* Enable DTS & PECI */
1103 ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG);
1107 data->enable_dts = 0x3; /* Enable DTS & TSI */
1110 /* Check DTS enable status */
1111 if (data->enable_dts) {
1112 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG);
1115 data->has_dts = ret & 0xF;
1116 if (data->enable_dts & ENABLE_TSI) {
1117 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG);
1120 data->has_dts |= (ret & 0xF) << 4;
1124 for (i = 0; i < FANCTL_MAX; i++) {
1125 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i);
1128 data->fan_mode[i] = ret;
1131 /* Read all of SMI status register to clear alarms */
1132 for (i = 0; i < SMI_STS_MAX; i++) {
1133 ret = nct7904_read_reg(data, BANK_0, SMI_STS1_REG + i);
1139 devm_hwmon_device_register_with_info(dev, client->name, data,
1140 &nct7904_chip_info, NULL);
1141 ret = PTR_ERR_OR_ZERO(hwmon_dev);
1145 /* Watchdog initialization */
1146 data->wdt.ops = &nct7904_wdt_ops;
1147 data->wdt.info = &nct7904_wdt_info;
1149 data->wdt.timeout = WATCHDOG_TIMEOUT * 60; /* Set default timeout */
1150 data->wdt.min_timeout = MIN_TIMEOUT;
1151 data->wdt.max_timeout = MAX_TIMEOUT;
1152 data->wdt.parent = &client->dev;
1154 watchdog_init_timeout(&data->wdt, timeout * 60, &client->dev);
1155 watchdog_set_nowayout(&data->wdt, nowayout);
1156 watchdog_set_drvdata(&data->wdt, data);
1158 watchdog_stop_on_unregister(&data->wdt);
1160 return devm_watchdog_register_device(dev, &data->wdt);
1163 static const struct i2c_device_id nct7904_id[] = {
1167 MODULE_DEVICE_TABLE(i2c, nct7904_id);
1169 static struct i2c_driver nct7904_driver = {
1170 .class = I2C_CLASS_HWMON,
1174 .probe_new = nct7904_probe,
1175 .id_table = nct7904_id,
1176 .detect = nct7904_detect,
1177 .address_list = normal_i2c,
1180 module_i2c_driver(nct7904_driver);
1182 MODULE_AUTHOR("Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>");
1183 MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904");
1184 MODULE_LICENSE("GPL");