2 * nct6775 - Driver for the hardware monitoring functionality of
3 * Nuvoton NCT677x Super-I/O chips
5 * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net>
7 * Derived from w83627ehf driver
8 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
9 * Copyright (C) 2006 Yuan Mu (Winbond),
10 * Rudolf Marek <r.marek@assembler.cz>
11 * David Hubbard <david.c.hubbard@gmail.com>
12 * Daniel J Blueman <daniel.blueman@gmail.com>
13 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
15 * Shamelessly ripped from the w83627hf driver
16 * Copyright (C) 2003 Mark Studebaker
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 * Supports the following chips:
35 * Chip #vin #fan #pwm #temp chip IDs man ID
36 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
37 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
38 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
39 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
40 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
41 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
42 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
43 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
44 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
46 * #temp lists the number of monitored temperature sources (first value) plus
47 * the number of directly connectable temperature sensors (second value).
50 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
52 #include <linux/module.h>
53 #include <linux/init.h>
54 #include <linux/slab.h>
55 #include <linux/jiffies.h>
56 #include <linux/platform_device.h>
57 #include <linux/hwmon.h>
58 #include <linux/hwmon-sysfs.h>
59 #include <linux/hwmon-vid.h>
60 #include <linux/err.h>
61 #include <linux/mutex.h>
62 #include <linux/acpi.h>
63 #include <linux/bitops.h>
64 #include <linux/dmi.h>
70 enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
73 /* used to set data->name = nct6775_device_names[data->sio_kind] */
74 static const char * const nct6775_device_names[] = {
86 static const char * const nct6775_sio_names[] __initconst = {
98 static unsigned short force_id;
99 module_param(force_id, ushort, 0);
100 MODULE_PARM_DESC(force_id, "Override the detected device ID");
102 static unsigned short fan_debounce;
103 module_param(fan_debounce, ushort, 0);
104 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
106 #define DRVNAME "nct6775"
109 * Super-I/O constants and functions
112 #define NCT6775_LD_ACPI 0x0a
113 #define NCT6775_LD_HWM 0x0b
114 #define NCT6775_LD_VID 0x0d
115 #define NCT6775_LD_12 0x12
117 #define SIO_REG_LDSEL 0x07 /* Logical device select */
118 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
119 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
120 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
122 #define SIO_NCT6106_ID 0xc450
123 #define SIO_NCT6775_ID 0xb470
124 #define SIO_NCT6776_ID 0xc330
125 #define SIO_NCT6779_ID 0xc560
126 #define SIO_NCT6791_ID 0xc800
127 #define SIO_NCT6792_ID 0xc910
128 #define SIO_NCT6793_ID 0xd120
129 #define SIO_NCT6795_ID 0xd350
130 #define SIO_NCT6796_ID 0xd420
131 #define SIO_ID_MASK 0xFFF0
133 enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
136 superio_outb(int ioreg, int reg, int val)
139 outb(val, ioreg + 1);
143 superio_inb(int ioreg, int reg)
146 return inb(ioreg + 1);
150 superio_select(int ioreg, int ld)
152 outb(SIO_REG_LDSEL, ioreg);
157 superio_enter(int ioreg)
160 * Try to reserve <ioreg> and <ioreg + 1> for exclusive access.
162 if (!request_muxed_region(ioreg, 2, DRVNAME))
172 superio_exit(int ioreg)
176 outb(0x02, ioreg + 1);
177 release_region(ioreg, 2);
184 #define IOREGION_ALIGNMENT (~7)
185 #define IOREGION_OFFSET 5
186 #define IOREGION_LENGTH 2
187 #define ADDR_REG_OFFSET 0
188 #define DATA_REG_OFFSET 1
190 #define NCT6775_REG_BANK 0x4E
191 #define NCT6775_REG_CONFIG 0x40
194 * Not currently used:
195 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
196 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
197 * REG_MAN_ID is at port 0x4f
198 * REG_CHIP_ID is at port 0x58
201 #define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/
202 #define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */
204 #define NUM_REG_ALARM 7 /* Max number of alarm registers */
205 #define NUM_REG_BEEP 5 /* Max number of beep registers */
209 #define TEMP_SOURCE_VIRTUAL 0x1f
211 /* Common and NCT6775 specific data */
213 /* Voltage min/max registers for nr=7..14 are in bank 5 */
215 static const u16 NCT6775_REG_IN_MAX[] = {
216 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
217 0x55c, 0x55e, 0x560, 0x562 };
218 static const u16 NCT6775_REG_IN_MIN[] = {
219 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
220 0x55d, 0x55f, 0x561, 0x563 };
221 static const u16 NCT6775_REG_IN[] = {
222 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
225 #define NCT6775_REG_VBAT 0x5D
226 #define NCT6775_REG_DIODE 0x5E
227 #define NCT6775_DIODE_MASK 0x02
229 #define NCT6775_REG_FANDIV1 0x506
230 #define NCT6775_REG_FANDIV2 0x507
232 #define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0
234 static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
236 /* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */
238 static const s8 NCT6775_ALARM_BITS[] = {
239 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
240 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
242 6, 7, 11, -1, -1, /* fan1..fan5 */
243 -1, -1, -1, /* unused */
244 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
245 12, -1 }; /* intrusion0, intrusion1 */
247 #define FAN_ALARM_BASE 16
248 #define TEMP_ALARM_BASE 24
249 #define INTRUSION_ALARM_BASE 30
251 static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
254 * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures,
257 static const s8 NCT6775_BEEP_BITS[] = {
258 0, 1, 2, 3, 8, 9, 10, 16, /* in0.. in7 */
259 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
260 21, /* global beep enable */
261 6, 7, 11, 28, -1, /* fan1..fan5 */
262 -1, -1, -1, /* unused */
263 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
264 12, -1 }; /* intrusion0, intrusion1 */
266 #define BEEP_ENABLE_BASE 15
268 static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
269 static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
271 /* DC or PWM output fan configuration */
272 static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
273 static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
275 /* Advanced Fan control, some values are common for all fans */
277 static const u16 NCT6775_REG_TARGET[] = {
278 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01, 0xb01 };
279 static const u16 NCT6775_REG_FAN_MODE[] = {
280 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02, 0xb02 };
281 static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
282 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03, 0xb03 };
283 static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
284 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04, 0xb04 };
285 static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
286 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05, 0xb05 };
287 static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
288 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06, 0xb06 };
289 static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
290 static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
292 static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
293 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07, 0xb07 };
294 static const u16 NCT6775_REG_PWM[] = {
295 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09, 0xb09 };
296 static const u16 NCT6775_REG_PWM_READ[] = {
297 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09, 0xb09 };
299 static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
300 static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
301 static const u16 NCT6775_REG_FAN_PULSES[] = { 0x641, 0x642, 0x643, 0x644, 0 };
302 static const u16 NCT6775_FAN_PULSE_SHIFT[] = { 0, 0, 0, 0, 0, 0 };
304 static const u16 NCT6775_REG_TEMP[] = {
305 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
307 static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
309 static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
310 0, 0x152, 0x252, 0x628, 0x629, 0x62A };
311 static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
312 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
313 static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
314 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
316 static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
317 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
319 static const u16 NCT6775_REG_TEMP_SEL[] = {
320 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00, 0xb00 };
322 static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
323 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
324 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
325 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
326 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
327 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
328 static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
329 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
330 static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
331 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
333 static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
335 static const u16 NCT6775_REG_AUTO_TEMP[] = {
336 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21, 0xb21 };
337 static const u16 NCT6775_REG_AUTO_PWM[] = {
338 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27, 0xb27 };
340 #define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p))
341 #define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p))
343 static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
345 static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
346 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35, 0xb35 };
347 static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
348 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38, 0xb38 };
350 static const char *const nct6775_temp_label[] = {
364 "PCH_CHIP_CPU_MAX_TEMP",
374 #define NCT6775_TEMP_MASK 0x001ffffe
376 static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
382 static const u16 NCT6775_REG_TEMP_CRIT[32] = {
393 /* NCT6776 specific data */
395 /* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */
396 #define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
397 #define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
399 static const s8 NCT6776_ALARM_BITS[] = {
400 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
401 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
403 6, 7, 11, 10, 23, /* fan1..fan5 */
404 -1, -1, -1, /* unused */
405 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
406 12, 9 }; /* intrusion0, intrusion1 */
408 static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
410 static const s8 NCT6776_BEEP_BITS[] = {
411 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
412 8, -1, -1, -1, -1, -1, -1, /* in8..in14 */
413 24, /* global beep enable */
414 25, 26, 27, 28, 29, /* fan1..fan5 */
415 -1, -1, -1, /* unused */
416 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
417 30, 31 }; /* intrusion0, intrusion1 */
419 static const u16 NCT6776_REG_TOLERANCE_H[] = {
420 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c, 0xb0c };
422 static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
423 static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
425 static const u16 NCT6776_REG_FAN_MIN[] = {
426 0x63a, 0x63c, 0x63e, 0x640, 0x642, 0x64a, 0x64c };
427 static const u16 NCT6776_REG_FAN_PULSES[] = {
428 0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0 };
430 static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
431 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
433 static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
434 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
436 static const char *const nct6776_temp_label[] = {
451 "PCH_CHIP_CPU_MAX_TEMP",
462 #define NCT6776_TEMP_MASK 0x007ffffe
464 static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
470 static const u16 NCT6776_REG_TEMP_CRIT[32] = {
475 /* NCT6779 specific data */
477 static const u16 NCT6779_REG_IN[] = {
478 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
479 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
481 static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
482 0x459, 0x45A, 0x45B, 0x568 };
484 static const s8 NCT6779_ALARM_BITS[] = {
485 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
486 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
488 6, 7, 11, 10, 23, /* fan1..fan5 */
489 -1, -1, -1, /* unused */
490 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
491 12, 9 }; /* intrusion0, intrusion1 */
493 static const s8 NCT6779_BEEP_BITS[] = {
494 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
495 8, 9, 10, 11, 12, 13, 14, /* in8..in14 */
496 24, /* global beep enable */
497 25, 26, 27, 28, 29, /* fan1..fan5 */
498 -1, -1, -1, /* unused */
499 16, 17, -1, -1, -1, -1, /* temp1..temp6 */
500 30, 31 }; /* intrusion0, intrusion1 */
502 static const u16 NCT6779_REG_FAN[] = {
503 0x4b0, 0x4b2, 0x4b4, 0x4b6, 0x4b8, 0x4ba, 0x660 };
504 static const u16 NCT6779_REG_FAN_PULSES[] = {
505 0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0 };
507 static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
508 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36, 0xb36 };
509 #define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01
510 static const u16 NCT6779_REG_CRITICAL_PWM[] = {
511 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37, 0xb37 };
513 static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
514 static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
515 static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
517 static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
519 static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
522 static const u16 NCT6779_REG_TEMP_OFFSET[] = {
523 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
525 static const char *const nct6779_temp_label[] = {
544 "PCH_CHIP_CPU_MAX_TEMP",
560 #define NCT6779_TEMP_MASK 0x07ffff7e
561 #define NCT6791_TEMP_MASK 0x87ffff7e
563 static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
564 = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
565 0, 0, 0, 0, 0, 0, 0, 0,
566 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
569 static const u16 NCT6779_REG_TEMP_CRIT[32] = {
574 /* NCT6791 specific data */
576 #define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
578 static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[NUM_FAN] = { 0, 0x239 };
579 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[NUM_FAN] = { 0, 0x23a };
580 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[NUM_FAN] = { 0, 0x23b };
581 static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[NUM_FAN] = { 0, 0x23c };
582 static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[NUM_FAN] = { 0, 0x23d };
583 static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[NUM_FAN] = { 0, 0x23e };
585 static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
586 0x459, 0x45A, 0x45B, 0x568, 0x45D };
588 static const s8 NCT6791_ALARM_BITS[] = {
589 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
590 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
592 6, 7, 11, 10, 23, 33, /* fan1..fan6 */
594 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
595 12, 9 }; /* intrusion0, intrusion1 */
597 /* NCT6792/NCT6793 specific data */
599 static const u16 NCT6792_REG_TEMP_MON[] = {
600 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
601 static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
602 0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
604 static const char *const nct6792_temp_label[] = {
623 "PCH_CHIP_CPU_MAX_TEMP",
632 "PECI Agent 0 Calibration",
633 "PECI Agent 1 Calibration",
639 #define NCT6792_TEMP_MASK 0x9fffff7e
641 static const char *const nct6793_temp_label[] = {
660 "PCH_CHIP_CPU_MAX_TEMP",
670 "PECI Agent 0 Calibration",
671 "PECI Agent 1 Calibration",
676 #define NCT6793_TEMP_MASK 0xbfff037e
678 static const char *const nct6795_temp_label[] = {
697 "PCH_CHIP_CPU_MAX_TEMP",
707 "PECI Agent 0 Calibration",
708 "PECI Agent 1 Calibration",
713 #define NCT6795_TEMP_MASK 0xbfffff7e
715 static const char *const nct6796_temp_label[] = {
734 "PCH_CHIP_CPU_MAX_TEMP",
744 "PECI Agent 0 Calibration",
745 "PECI Agent 1 Calibration",
750 #define NCT6796_TEMP_MASK 0xbfff03fe
752 /* NCT6102D/NCT6106D specific data */
754 #define NCT6106_REG_VBAT 0x318
755 #define NCT6106_REG_DIODE 0x319
756 #define NCT6106_DIODE_MASK 0x01
758 static const u16 NCT6106_REG_IN_MAX[] = {
759 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
760 static const u16 NCT6106_REG_IN_MIN[] = {
761 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
762 static const u16 NCT6106_REG_IN[] = {
763 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
765 static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
766 static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
767 static const u16 NCT6106_REG_TEMP_HYST[] = {
768 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
769 static const u16 NCT6106_REG_TEMP_OVER[] = {
770 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
771 static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
772 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
773 static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
774 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
775 static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
776 static const u16 NCT6106_REG_TEMP_CONFIG[] = {
777 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
779 static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
780 static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
781 static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6, 0, 0 };
782 static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4, 0, 0 };
784 static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
785 static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
786 static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
787 static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
788 static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
789 static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
790 static const u16 NCT6106_REG_TEMP_SOURCE[] = {
791 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
793 static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
794 static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
795 0x11b, 0x12b, 0x13b };
797 static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
798 #define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10
799 static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
801 static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
802 static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
803 static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
804 static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
805 static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
806 static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
808 static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
810 static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
811 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
812 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
813 static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x17c };
814 static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
815 static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
817 static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
818 static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
820 static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
821 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
823 static const s8 NCT6106_ALARM_BITS[] = {
824 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
825 9, -1, -1, -1, -1, -1, -1, /* in8..in14 */
827 32, 33, 34, -1, -1, /* fan1..fan5 */
828 -1, -1, -1, /* unused */
829 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
830 48, -1 /* intrusion0, intrusion1 */
833 static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
834 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
836 static const s8 NCT6106_BEEP_BITS[] = {
837 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
838 9, 10, 11, 12, -1, -1, -1, /* in8..in14 */
839 32, /* global beep enable */
840 24, 25, 26, 27, 28, /* fan1..fan5 */
841 -1, -1, -1, /* unused */
842 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
843 34, -1 /* intrusion0, intrusion1 */
846 static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
852 static const u16 NCT6106_REG_TEMP_CRIT[32] = {
857 static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
859 if (mode == 0 && pwm == 255)
864 static int pwm_enable_to_reg(enum pwm_enable mode)
875 /* 1 is DC mode, output in ms */
876 static unsigned int step_time_from_reg(u8 reg, u8 mode)
878 return mode ? 400 * reg : 100 * reg;
881 static u8 step_time_to_reg(unsigned int msec, u8 mode)
883 return clamp_val((mode ? (msec + 200) / 400 :
884 (msec + 50) / 100), 1, 255);
887 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
889 if (reg == 0 || reg == 255)
891 return 1350000U / (reg << divreg);
894 static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
896 if ((reg & 0xff1f) == 0xff1f)
899 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
904 return 1350000U / reg;
907 static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
909 if (reg == 0 || reg == 0xffff)
913 * Even though the registers are 16 bit wide, the fan divisor
916 return 1350000U / (reg << divreg);
919 static u16 fan_to_reg(u32 fan, unsigned int divreg)
924 return (1350000U / fan) >> divreg;
927 static inline unsigned int
934 * Some of the voltage inputs have internal scaling, the tables below
935 * contain 8 (the ADC LSB in mV) * scaling factor * 100
937 static const u16 scale_in[15] = {
938 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
942 static inline long in_from_reg(u8 reg, u8 nr)
944 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
947 static inline u8 in_to_reg(u32 val, u8 nr)
949 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
953 * Data structures and manipulation thereof
956 struct nct6775_data {
957 int addr; /* IO base of hw monitor block */
958 int sioreg; /* SIO register address */
962 const struct attribute_group *groups[6];
964 u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
965 * 3=temp_crit, 4=temp_lcrit
967 u8 temp_src[NUM_TEMP];
968 u16 reg_temp_config[NUM_TEMP];
969 const char * const *temp_label;
977 const s8 *ALARM_BITS;
981 const u16 *REG_IN_MINMAX[2];
983 const u16 *REG_TARGET;
985 const u16 *REG_FAN_MODE;
986 const u16 *REG_FAN_MIN;
987 const u16 *REG_FAN_PULSES;
988 const u16 *FAN_PULSE_SHIFT;
989 const u16 *REG_FAN_TIME[3];
991 const u16 *REG_TOLERANCE_H;
993 const u8 *REG_PWM_MODE;
994 const u8 *PWM_MODE_MASK;
996 const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
997 * [3]=pwm_max, [4]=pwm_step,
998 * [5]=weight_duty_step, [6]=weight_duty_base
1000 const u16 *REG_PWM_READ;
1002 const u16 *REG_CRITICAL_PWM_ENABLE;
1003 u8 CRITICAL_PWM_ENABLE_MASK;
1004 const u16 *REG_CRITICAL_PWM;
1006 const u16 *REG_AUTO_TEMP;
1007 const u16 *REG_AUTO_PWM;
1009 const u16 *REG_CRITICAL_TEMP;
1010 const u16 *REG_CRITICAL_TEMP_TOLERANCE;
1012 const u16 *REG_TEMP_SOURCE; /* temp register sources */
1013 const u16 *REG_TEMP_SEL;
1014 const u16 *REG_WEIGHT_TEMP_SEL;
1015 const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */
1017 const u16 *REG_TEMP_OFFSET;
1019 const u16 *REG_ALARM;
1020 const u16 *REG_BEEP;
1022 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
1023 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
1025 struct mutex update_lock;
1026 bool valid; /* true if following fields are valid */
1027 unsigned long last_updated; /* In jiffies */
1029 /* Register values */
1030 u8 bank; /* current register bank */
1031 u8 in_num; /* number of in inputs we have */
1032 u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */
1033 unsigned int rpm[NUM_FAN];
1034 u16 fan_min[NUM_FAN];
1035 u8 fan_pulses[NUM_FAN];
1036 u8 fan_div[NUM_FAN];
1038 u8 has_fan; /* some fan inputs can be disabled */
1039 u8 has_fan_min; /* some fans don't have min register */
1042 u8 num_temp_alarms; /* 2, 3, or 6 */
1043 u8 num_temp_beeps; /* 2, 3, or 6 */
1044 u8 temp_fixed_num; /* 3 or 6 */
1045 u8 temp_type[NUM_TEMP_FIXED];
1046 s8 temp_offset[NUM_TEMP_FIXED];
1047 s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1048 * 3=temp_crit, 4=temp_lcrit */
1052 u8 pwm_num; /* number of pwm */
1053 u8 pwm_mode[NUM_FAN]; /* 1->DC variable voltage,
1054 * 0->PWM variable duty cycle
1056 enum pwm_enable pwm_enable[NUM_FAN];
1059 * 2->thermal cruise mode (also called SmartFan I)
1060 * 3->fan speed cruise mode
1062 * 5->enhanced variable thermal cruise (SmartFan IV)
1064 u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1065 * [3]=pwm_max, [4]=pwm_step,
1066 * [5]=weight_duty_step, [6]=weight_duty_base
1069 u8 target_temp[NUM_FAN];
1070 u8 target_temp_mask;
1071 u32 target_speed[NUM_FAN];
1072 u32 target_speed_tolerance[NUM_FAN];
1073 u8 speed_tolerance_limit;
1075 u8 temp_tolerance[2][NUM_FAN];
1078 u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
1080 /* Automatic fan speed control registers */
1082 u8 auto_pwm[NUM_FAN][7];
1083 u8 auto_temp[NUM_FAN][7];
1084 u8 pwm_temp_sel[NUM_FAN];
1085 u8 pwm_weight_temp_sel[NUM_FAN];
1086 u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol,
1096 u16 have_temp_fixed;
1099 /* Remember extra register values over suspend/resume */
1106 struct nct6775_sio_data {
1111 struct sensor_device_template {
1112 struct device_attribute dev_attr;
1120 bool s2; /* true if both index and nr are used */
1123 struct sensor_device_attr_u {
1125 struct sensor_device_attribute a1;
1126 struct sensor_device_attribute_2 a2;
1131 #define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \
1132 .attr = {.name = _template, .mode = _mode }, \
1137 #define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1138 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1139 .u.index = _index, \
1142 #define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1144 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1145 .u.s.index = _index, \
1149 #define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1150 static struct sensor_device_template sensor_dev_template_##_name \
1151 = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \
1154 #define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \
1156 static struct sensor_device_template sensor_dev_template_##_name \
1157 = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1160 struct sensor_template_group {
1161 struct sensor_device_template **templates;
1162 umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1166 static struct attribute_group *
1167 nct6775_create_attr_group(struct device *dev,
1168 const struct sensor_template_group *tg,
1171 struct attribute_group *group;
1172 struct sensor_device_attr_u *su;
1173 struct sensor_device_attribute *a;
1174 struct sensor_device_attribute_2 *a2;
1175 struct attribute **attrs;
1176 struct sensor_device_template **t;
1180 return ERR_PTR(-EINVAL);
1183 for (count = 0; *t; t++, count++)
1187 return ERR_PTR(-EINVAL);
1189 group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1191 return ERR_PTR(-ENOMEM);
1193 attrs = devm_kzalloc(dev, sizeof(*attrs) * (repeat * count + 1),
1196 return ERR_PTR(-ENOMEM);
1198 su = devm_kzalloc(dev, sizeof(*su) * repeat * count,
1201 return ERR_PTR(-ENOMEM);
1203 group->attrs = attrs;
1204 group->is_visible = tg->is_visible;
1206 for (i = 0; i < repeat; i++) {
1208 while (*t != NULL) {
1209 snprintf(su->name, sizeof(su->name),
1210 (*t)->dev_attr.attr.name, tg->base + i);
1213 sysfs_attr_init(&a2->dev_attr.attr);
1214 a2->dev_attr.attr.name = su->name;
1215 a2->nr = (*t)->u.s.nr + i;
1216 a2->index = (*t)->u.s.index;
1217 a2->dev_attr.attr.mode =
1218 (*t)->dev_attr.attr.mode;
1219 a2->dev_attr.show = (*t)->dev_attr.show;
1220 a2->dev_attr.store = (*t)->dev_attr.store;
1221 *attrs = &a2->dev_attr.attr;
1224 sysfs_attr_init(&a->dev_attr.attr);
1225 a->dev_attr.attr.name = su->name;
1226 a->index = (*t)->u.index + i;
1227 a->dev_attr.attr.mode =
1228 (*t)->dev_attr.attr.mode;
1229 a->dev_attr.show = (*t)->dev_attr.show;
1230 a->dev_attr.store = (*t)->dev_attr.store;
1231 *attrs = &a->dev_attr.attr;
1242 static bool is_word_sized(struct nct6775_data *data, u16 reg)
1244 switch (data->kind) {
1246 return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1247 reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1248 reg == 0x111 || reg == 0x121 || reg == 0x131;
1250 return (((reg & 0xff00) == 0x100 ||
1251 (reg & 0xff00) == 0x200) &&
1252 ((reg & 0x00ff) == 0x50 ||
1253 (reg & 0x00ff) == 0x53 ||
1254 (reg & 0x00ff) == 0x55)) ||
1255 (reg & 0xfff0) == 0x630 ||
1256 reg == 0x640 || reg == 0x642 ||
1258 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1259 reg == 0x73 || reg == 0x75 || reg == 0x77;
1261 return (((reg & 0xff00) == 0x100 ||
1262 (reg & 0xff00) == 0x200) &&
1263 ((reg & 0x00ff) == 0x50 ||
1264 (reg & 0x00ff) == 0x53 ||
1265 (reg & 0x00ff) == 0x55)) ||
1266 (reg & 0xfff0) == 0x630 ||
1268 reg == 0x640 || reg == 0x642 ||
1269 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1270 reg == 0x73 || reg == 0x75 || reg == 0x77;
1277 return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
1278 ((reg & 0xfff0) == 0x4b0 && (reg & 0x000f) < 0x0b) ||
1280 reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1281 reg == 0x640 || reg == 0x642 || reg == 0x64a ||
1282 reg == 0x64c || reg == 0x660 ||
1283 reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
1284 reg == 0x7b || reg == 0x7d;
1290 * On older chips, only registers 0x50-0x5f are banked.
1291 * On more recent chips, all registers are banked.
1292 * Assume that is the case and set the bank number for each access.
1293 * Cache the bank number so it only needs to be set if it changes.
1295 static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1299 if (data->bank != bank) {
1300 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1301 outb_p(bank, data->addr + DATA_REG_OFFSET);
1306 static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1308 int res, word_sized = is_word_sized(data, reg);
1310 nct6775_set_bank(data, reg);
1311 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1312 res = inb_p(data->addr + DATA_REG_OFFSET);
1314 outb_p((reg & 0xff) + 1,
1315 data->addr + ADDR_REG_OFFSET);
1316 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1321 static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1323 int word_sized = is_word_sized(data, reg);
1325 nct6775_set_bank(data, reg);
1326 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1328 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1329 outb_p((reg & 0xff) + 1,
1330 data->addr + ADDR_REG_OFFSET);
1332 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
1336 /* We left-align 8-bit temperature values to make the code simpler */
1337 static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1341 res = nct6775_read_value(data, reg);
1342 if (!is_word_sized(data, reg))
1348 static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1350 if (!is_word_sized(data, reg))
1352 return nct6775_write_value(data, reg, value);
1355 /* This function assumes that the caller holds data->update_lock */
1356 static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1362 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1363 | (data->fan_div[0] & 0x7);
1364 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1367 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1368 | ((data->fan_div[1] << 4) & 0x70);
1369 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1372 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1373 | (data->fan_div[2] & 0x7);
1374 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1377 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1378 | ((data->fan_div[3] << 4) & 0x70);
1379 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1384 static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1386 if (data->kind == nct6775)
1387 nct6775_write_fan_div(data, nr);
1390 static void nct6775_update_fan_div(struct nct6775_data *data)
1394 i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1395 data->fan_div[0] = i & 0x7;
1396 data->fan_div[1] = (i & 0x70) >> 4;
1397 i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1398 data->fan_div[2] = i & 0x7;
1399 if (data->has_fan & BIT(3))
1400 data->fan_div[3] = (i & 0x70) >> 4;
1403 static void nct6775_update_fan_div_common(struct nct6775_data *data)
1405 if (data->kind == nct6775)
1406 nct6775_update_fan_div(data);
1409 static void nct6775_init_fan_div(struct nct6775_data *data)
1413 nct6775_update_fan_div_common(data);
1415 * For all fans, start with highest divider value if the divider
1416 * register is not initialized. This ensures that we get a
1417 * reading from the fan count register, even if it is not optimal.
1418 * We'll compute a better divider later on.
1420 for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
1421 if (!(data->has_fan & BIT(i)))
1423 if (data->fan_div[i] == 0) {
1424 data->fan_div[i] = 7;
1425 nct6775_write_fan_div_common(data, i);
1430 static void nct6775_init_fan_common(struct device *dev,
1431 struct nct6775_data *data)
1436 if (data->has_fan_div)
1437 nct6775_init_fan_div(data);
1440 * If fan_min is not set (0), set it to 0xff to disable it. This
1441 * prevents the unnecessary warning when fanX_min is reported as 0.
1443 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
1444 if (data->has_fan_min & BIT(i)) {
1445 reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1447 nct6775_write_value(data, data->REG_FAN_MIN[i],
1448 data->has_fan_div ? 0xff
1454 static void nct6775_select_fan_div(struct device *dev,
1455 struct nct6775_data *data, int nr, u16 reg)
1457 u8 fan_div = data->fan_div[nr];
1460 if (!data->has_fan_div)
1464 * If we failed to measure the fan speed, or the reported value is not
1465 * in the optimal range, and the clock divider can be modified,
1466 * let's try that for next time.
1468 if (reg == 0x00 && fan_div < 0x07)
1470 else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1473 if (fan_div != data->fan_div[nr]) {
1474 dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1475 nr + 1, div_from_reg(data->fan_div[nr]),
1476 div_from_reg(fan_div));
1478 /* Preserve min limit if possible */
1479 if (data->has_fan_min & BIT(nr)) {
1480 fan_min = data->fan_min[nr];
1481 if (fan_div > data->fan_div[nr]) {
1482 if (fan_min != 255 && fan_min > 1)
1485 if (fan_min != 255) {
1491 if (fan_min != data->fan_min[nr]) {
1492 data->fan_min[nr] = fan_min;
1493 nct6775_write_value(data, data->REG_FAN_MIN[nr],
1497 data->fan_div[nr] = fan_div;
1498 nct6775_write_fan_div_common(data, nr);
1502 static void nct6775_update_pwm(struct device *dev)
1504 struct nct6775_data *data = dev_get_drvdata(dev);
1506 int fanmodecfg, reg;
1509 for (i = 0; i < data->pwm_num; i++) {
1510 if (!(data->has_pwm & BIT(i)))
1513 duty_is_dc = data->REG_PWM_MODE[i] &&
1514 (nct6775_read_value(data, data->REG_PWM_MODE[i])
1515 & data->PWM_MODE_MASK[i]);
1516 data->pwm_mode[i] = !duty_is_dc;
1518 fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1519 for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1520 if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1522 = nct6775_read_value(data,
1523 data->REG_PWM[j][i]);
1527 data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1528 (fanmodecfg >> 4) & 7);
1530 if (!data->temp_tolerance[0][i] ||
1531 data->pwm_enable[i] != speed_cruise)
1532 data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1533 if (!data->target_speed_tolerance[i] ||
1534 data->pwm_enable[i] == speed_cruise) {
1535 u8 t = fanmodecfg & 0x0f;
1537 if (data->REG_TOLERANCE_H) {
1538 t |= (nct6775_read_value(data,
1539 data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1541 data->target_speed_tolerance[i] = t;
1544 data->temp_tolerance[1][i] =
1545 nct6775_read_value(data,
1546 data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1548 reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1549 data->pwm_temp_sel[i] = reg & 0x1f;
1550 /* If fan can stop, report floor as 0 */
1552 data->pwm[2][i] = 0;
1554 if (!data->REG_WEIGHT_TEMP_SEL[i])
1557 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1558 data->pwm_weight_temp_sel[i] = reg & 0x1f;
1559 /* If weight is disabled, report weight source as 0 */
1560 if (j == 1 && !(reg & 0x80))
1561 data->pwm_weight_temp_sel[i] = 0;
1563 /* Weight temp data */
1564 for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
1565 data->weight_temp[j][i]
1566 = nct6775_read_value(data,
1567 data->REG_WEIGHT_TEMP[j][i]);
1572 static void nct6775_update_pwm_limits(struct device *dev)
1574 struct nct6775_data *data = dev_get_drvdata(dev);
1579 for (i = 0; i < data->pwm_num; i++) {
1580 if (!(data->has_pwm & BIT(i)))
1583 for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
1584 data->fan_time[j][i] =
1585 nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1588 reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1589 /* Update only in matching mode or if never updated */
1590 if (!data->target_temp[i] ||
1591 data->pwm_enable[i] == thermal_cruise)
1592 data->target_temp[i] = reg_t & data->target_temp_mask;
1593 if (!data->target_speed[i] ||
1594 data->pwm_enable[i] == speed_cruise) {
1595 if (data->REG_TOLERANCE_H) {
1596 reg_t |= (nct6775_read_value(data,
1597 data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1599 data->target_speed[i] = reg_t;
1602 for (j = 0; j < data->auto_pwm_num; j++) {
1603 data->auto_pwm[i][j] =
1604 nct6775_read_value(data,
1605 NCT6775_AUTO_PWM(data, i, j));
1606 data->auto_temp[i][j] =
1607 nct6775_read_value(data,
1608 NCT6775_AUTO_TEMP(data, i, j));
1611 /* critical auto_pwm temperature data */
1612 data->auto_temp[i][data->auto_pwm_num] =
1613 nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1615 switch (data->kind) {
1617 reg = nct6775_read_value(data,
1618 NCT6775_REG_CRITICAL_ENAB[i]);
1619 data->auto_pwm[i][data->auto_pwm_num] =
1620 (reg & 0x02) ? 0xff : 0x00;
1623 data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1632 reg = nct6775_read_value(data,
1633 data->REG_CRITICAL_PWM_ENABLE[i]);
1634 if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1635 reg = nct6775_read_value(data,
1636 data->REG_CRITICAL_PWM[i]);
1639 data->auto_pwm[i][data->auto_pwm_num] = reg;
1645 static struct nct6775_data *nct6775_update_device(struct device *dev)
1647 struct nct6775_data *data = dev_get_drvdata(dev);
1650 mutex_lock(&data->update_lock);
1652 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1654 /* Fan clock dividers */
1655 nct6775_update_fan_div_common(data);
1657 /* Measured voltages and limits */
1658 for (i = 0; i < data->in_num; i++) {
1659 if (!(data->have_in & BIT(i)))
1662 data->in[i][0] = nct6775_read_value(data,
1664 data->in[i][1] = nct6775_read_value(data,
1665 data->REG_IN_MINMAX[0][i]);
1666 data->in[i][2] = nct6775_read_value(data,
1667 data->REG_IN_MINMAX[1][i]);
1670 /* Measured fan speeds and limits */
1671 for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1674 if (!(data->has_fan & BIT(i)))
1677 reg = nct6775_read_value(data, data->REG_FAN[i]);
1678 data->rpm[i] = data->fan_from_reg(reg,
1681 if (data->has_fan_min & BIT(i))
1682 data->fan_min[i] = nct6775_read_value(data,
1683 data->REG_FAN_MIN[i]);
1684 data->fan_pulses[i] =
1685 (nct6775_read_value(data, data->REG_FAN_PULSES[i])
1686 >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1688 nct6775_select_fan_div(dev, data, i, reg);
1691 nct6775_update_pwm(dev);
1692 nct6775_update_pwm_limits(dev);
1694 /* Measured temperatures and limits */
1695 for (i = 0; i < NUM_TEMP; i++) {
1696 if (!(data->have_temp & BIT(i)))
1698 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1699 if (data->reg_temp[j][i])
1701 = nct6775_read_temp(data,
1702 data->reg_temp[j][i]);
1704 if (i >= NUM_TEMP_FIXED ||
1705 !(data->have_temp_fixed & BIT(i)))
1707 data->temp_offset[i]
1708 = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1712 for (i = 0; i < NUM_REG_ALARM; i++) {
1715 if (!data->REG_ALARM[i])
1717 alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1718 data->alarms |= ((u64)alarm) << (i << 3);
1722 for (i = 0; i < NUM_REG_BEEP; i++) {
1725 if (!data->REG_BEEP[i])
1727 beep = nct6775_read_value(data, data->REG_BEEP[i]);
1728 data->beeps |= ((u64)beep) << (i << 3);
1731 data->last_updated = jiffies;
1735 mutex_unlock(&data->update_lock);
1740 * Sysfs callback functions
1743 show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1745 struct nct6775_data *data = nct6775_update_device(dev);
1746 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1747 int index = sattr->index;
1750 return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1754 store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1757 struct nct6775_data *data = dev_get_drvdata(dev);
1758 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1759 int index = sattr->index;
1764 err = kstrtoul(buf, 10, &val);
1767 mutex_lock(&data->update_lock);
1768 data->in[nr][index] = in_to_reg(val, nr);
1769 nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
1770 data->in[nr][index]);
1771 mutex_unlock(&data->update_lock);
1776 show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1778 struct nct6775_data *data = nct6775_update_device(dev);
1779 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1780 int nr = data->ALARM_BITS[sattr->index];
1782 return sprintf(buf, "%u\n",
1783 (unsigned int)((data->alarms >> nr) & 0x01));
1786 static int find_temp_source(struct nct6775_data *data, int index, int count)
1788 int source = data->temp_src[index];
1791 for (nr = 0; nr < count; nr++) {
1794 src = nct6775_read_value(data,
1795 data->REG_TEMP_SOURCE[nr]) & 0x1f;
1803 show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1805 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1806 struct nct6775_data *data = nct6775_update_device(dev);
1807 unsigned int alarm = 0;
1811 * For temperatures, there is no fixed mapping from registers to alarm
1812 * bits. Alarm bits are determined by the temperature source mapping.
1814 nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1816 int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
1818 alarm = (data->alarms >> bit) & 0x01;
1820 return sprintf(buf, "%u\n", alarm);
1824 show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1826 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1827 struct nct6775_data *data = nct6775_update_device(dev);
1828 int nr = data->BEEP_BITS[sattr->index];
1830 return sprintf(buf, "%u\n",
1831 (unsigned int)((data->beeps >> nr) & 0x01));
1835 store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1838 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1839 struct nct6775_data *data = dev_get_drvdata(dev);
1840 int nr = data->BEEP_BITS[sattr->index];
1841 int regindex = nr >> 3;
1845 err = kstrtoul(buf, 10, &val);
1851 mutex_lock(&data->update_lock);
1853 data->beeps |= (1ULL << nr);
1855 data->beeps &= ~(1ULL << nr);
1856 nct6775_write_value(data, data->REG_BEEP[regindex],
1857 (data->beeps >> (regindex << 3)) & 0xff);
1858 mutex_unlock(&data->update_lock);
1863 show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1865 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1866 struct nct6775_data *data = nct6775_update_device(dev);
1867 unsigned int beep = 0;
1871 * For temperatures, there is no fixed mapping from registers to beep
1872 * enable bits. Beep enable bits are determined by the temperature
1875 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1877 int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1879 beep = (data->beeps >> bit) & 0x01;
1881 return sprintf(buf, "%u\n", beep);
1885 store_temp_beep(struct device *dev, struct device_attribute *attr,
1886 const char *buf, size_t count)
1888 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1889 struct nct6775_data *data = dev_get_drvdata(dev);
1890 int nr, bit, regindex;
1894 err = kstrtoul(buf, 10, &val);
1900 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1904 bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1905 regindex = bit >> 3;
1907 mutex_lock(&data->update_lock);
1909 data->beeps |= (1ULL << bit);
1911 data->beeps &= ~(1ULL << bit);
1912 nct6775_write_value(data, data->REG_BEEP[regindex],
1913 (data->beeps >> (regindex << 3)) & 0xff);
1914 mutex_unlock(&data->update_lock);
1919 static umode_t nct6775_in_is_visible(struct kobject *kobj,
1920 struct attribute *attr, int index)
1922 struct device *dev = container_of(kobj, struct device, kobj);
1923 struct nct6775_data *data = dev_get_drvdata(dev);
1924 int in = index / 5; /* voltage index */
1926 if (!(data->have_in & BIT(in)))
1932 SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
1933 SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
1934 SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
1936 SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
1937 store_in_reg, 0, 1);
1938 SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
1939 store_in_reg, 0, 2);
1942 * nct6775_in_is_visible uses the index into the following array
1943 * to determine if attributes should be created or not.
1944 * Any change in order or content must be matched.
1946 static struct sensor_device_template *nct6775_attributes_in_template[] = {
1947 &sensor_dev_template_in_input,
1948 &sensor_dev_template_in_alarm,
1949 &sensor_dev_template_in_beep,
1950 &sensor_dev_template_in_min,
1951 &sensor_dev_template_in_max,
1955 static const struct sensor_template_group nct6775_in_template_group = {
1956 .templates = nct6775_attributes_in_template,
1957 .is_visible = nct6775_in_is_visible,
1961 show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1963 struct nct6775_data *data = nct6775_update_device(dev);
1964 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1965 int nr = sattr->index;
1967 return sprintf(buf, "%d\n", data->rpm[nr]);
1971 show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1973 struct nct6775_data *data = nct6775_update_device(dev);
1974 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1975 int nr = sattr->index;
1977 return sprintf(buf, "%d\n",
1978 data->fan_from_reg_min(data->fan_min[nr],
1979 data->fan_div[nr]));
1983 show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
1985 struct nct6775_data *data = nct6775_update_device(dev);
1986 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1987 int nr = sattr->index;
1989 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
1993 store_fan_min(struct device *dev, struct device_attribute *attr,
1994 const char *buf, size_t count)
1996 struct nct6775_data *data = dev_get_drvdata(dev);
1997 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1998 int nr = sattr->index;
2004 err = kstrtoul(buf, 10, &val);
2008 mutex_lock(&data->update_lock);
2009 if (!data->has_fan_div) {
2010 /* NCT6776F or NCT6779D; we know this is a 13 bit register */
2016 val = 1350000U / val;
2017 val = (val & 0x1f) | ((val << 3) & 0xff00);
2019 data->fan_min[nr] = val;
2020 goto write_min; /* Leave fan divider alone */
2023 /* No min limit, alarm disabled */
2024 data->fan_min[nr] = 255;
2025 new_div = data->fan_div[nr]; /* No change */
2026 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
2029 reg = 1350000U / val;
2030 if (reg >= 128 * 255) {
2032 * Speed below this value cannot possibly be represented,
2033 * even with the highest divider (128)
2035 data->fan_min[nr] = 254;
2036 new_div = 7; /* 128 == BIT(7) */
2038 "fan%u low limit %lu below minimum %u, set to minimum\n",
2039 nr + 1, val, data->fan_from_reg_min(254, 7));
2042 * Speed above this value cannot possibly be represented,
2043 * even with the lowest divider (1)
2045 data->fan_min[nr] = 1;
2046 new_div = 0; /* 1 == BIT(0) */
2048 "fan%u low limit %lu above maximum %u, set to maximum\n",
2049 nr + 1, val, data->fan_from_reg_min(1, 0));
2052 * Automatically pick the best divider, i.e. the one such
2053 * that the min limit will correspond to a register value
2054 * in the 96..192 range
2057 while (reg > 192 && new_div < 7) {
2061 data->fan_min[nr] = reg;
2066 * Write both the fan clock divider (if it changed) and the new
2067 * fan min (unconditionally)
2069 if (new_div != data->fan_div[nr]) {
2070 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2071 nr + 1, div_from_reg(data->fan_div[nr]),
2072 div_from_reg(new_div));
2073 data->fan_div[nr] = new_div;
2074 nct6775_write_fan_div_common(data, nr);
2075 /* Give the chip time to sample a new speed value */
2076 data->last_updated = jiffies;
2080 nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2081 mutex_unlock(&data->update_lock);
2087 show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2089 struct nct6775_data *data = nct6775_update_device(dev);
2090 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2091 int p = data->fan_pulses[sattr->index];
2093 return sprintf(buf, "%d\n", p ? : 4);
2097 store_fan_pulses(struct device *dev, struct device_attribute *attr,
2098 const char *buf, size_t count)
2100 struct nct6775_data *data = dev_get_drvdata(dev);
2101 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2102 int nr = sattr->index;
2107 err = kstrtoul(buf, 10, &val);
2114 mutex_lock(&data->update_lock);
2115 data->fan_pulses[nr] = val & 3;
2116 reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2117 reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2118 reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2119 nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
2120 mutex_unlock(&data->update_lock);
2125 static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2126 struct attribute *attr, int index)
2128 struct device *dev = container_of(kobj, struct device, kobj);
2129 struct nct6775_data *data = dev_get_drvdata(dev);
2130 int fan = index / 6; /* fan index */
2131 int nr = index % 6; /* attribute index */
2133 if (!(data->has_fan & BIT(fan)))
2136 if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2138 if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
2140 if (nr == 3 && !data->REG_FAN_PULSES[fan])
2142 if (nr == 4 && !(data->has_fan_min & BIT(fan)))
2144 if (nr == 5 && data->kind != nct6775)
2150 SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2151 SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2153 SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2154 store_beep, FAN_ALARM_BASE);
2155 SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2156 store_fan_pulses, 0);
2157 SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2159 SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2162 * nct6775_fan_is_visible uses the index into the following array
2163 * to determine if attributes should be created or not.
2164 * Any change in order or content must be matched.
2166 static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2167 &sensor_dev_template_fan_input,
2168 &sensor_dev_template_fan_alarm, /* 1 */
2169 &sensor_dev_template_fan_beep, /* 2 */
2170 &sensor_dev_template_fan_pulses,
2171 &sensor_dev_template_fan_min, /* 4 */
2172 &sensor_dev_template_fan_div, /* 5 */
2176 static const struct sensor_template_group nct6775_fan_template_group = {
2177 .templates = nct6775_attributes_fan_template,
2178 .is_visible = nct6775_fan_is_visible,
2183 show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2185 struct nct6775_data *data = nct6775_update_device(dev);
2186 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2187 int nr = sattr->index;
2189 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2193 show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2195 struct nct6775_data *data = nct6775_update_device(dev);
2196 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2198 int index = sattr->index;
2200 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2204 store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2207 struct nct6775_data *data = dev_get_drvdata(dev);
2208 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2210 int index = sattr->index;
2214 err = kstrtol(buf, 10, &val);
2218 mutex_lock(&data->update_lock);
2219 data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2220 nct6775_write_temp(data, data->reg_temp[index][nr],
2221 data->temp[index][nr]);
2222 mutex_unlock(&data->update_lock);
2227 show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2229 struct nct6775_data *data = nct6775_update_device(dev);
2230 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2232 return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2236 store_temp_offset(struct device *dev, struct device_attribute *attr,
2237 const char *buf, size_t count)
2239 struct nct6775_data *data = dev_get_drvdata(dev);
2240 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2241 int nr = sattr->index;
2245 err = kstrtol(buf, 10, &val);
2249 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2251 mutex_lock(&data->update_lock);
2252 data->temp_offset[nr] = val;
2253 nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2254 mutex_unlock(&data->update_lock);
2260 show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2262 struct nct6775_data *data = nct6775_update_device(dev);
2263 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2264 int nr = sattr->index;
2266 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2270 store_temp_type(struct device *dev, struct device_attribute *attr,
2271 const char *buf, size_t count)
2273 struct nct6775_data *data = nct6775_update_device(dev);
2274 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2275 int nr = sattr->index;
2278 u8 vbat, diode, vbit, dbit;
2280 err = kstrtoul(buf, 10, &val);
2284 if (val != 1 && val != 3 && val != 4)
2287 mutex_lock(&data->update_lock);
2289 data->temp_type[nr] = val;
2291 dbit = data->DIODE_MASK << nr;
2292 vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2293 diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
2295 case 1: /* CPU diode (diode, current mode) */
2299 case 3: /* diode, voltage mode */
2302 case 4: /* thermistor */
2305 nct6775_write_value(data, data->REG_VBAT, vbat);
2306 nct6775_write_value(data, data->REG_DIODE, diode);
2308 mutex_unlock(&data->update_lock);
2312 static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2313 struct attribute *attr, int index)
2315 struct device *dev = container_of(kobj, struct device, kobj);
2316 struct nct6775_data *data = dev_get_drvdata(dev);
2317 int temp = index / 10; /* temp index */
2318 int nr = index % 10; /* attribute index */
2320 if (!(data->have_temp & BIT(temp)))
2323 if (nr == 1 && !data->temp_label)
2326 if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2327 return 0; /* alarm */
2329 if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2330 return 0; /* beep */
2332 if (nr == 4 && !data->reg_temp[1][temp]) /* max */
2335 if (nr == 5 && !data->reg_temp[2][temp]) /* max_hyst */
2338 if (nr == 6 && !data->reg_temp[3][temp]) /* crit */
2341 if (nr == 7 && !data->reg_temp[4][temp]) /* lcrit */
2344 /* offset and type only apply to fixed sensors */
2345 if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
2351 SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2352 SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2353 SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2355 SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2356 show_temp, store_temp, 0, 2);
2357 SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2359 SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2361 SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2362 show_temp_offset, store_temp_offset, 0);
2363 SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2364 store_temp_type, 0);
2365 SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
2366 SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2367 store_temp_beep, 0);
2370 * nct6775_temp_is_visible uses the index into the following array
2371 * to determine if attributes should be created or not.
2372 * Any change in order or content must be matched.
2374 static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2375 &sensor_dev_template_temp_input,
2376 &sensor_dev_template_temp_label,
2377 &sensor_dev_template_temp_alarm, /* 2 */
2378 &sensor_dev_template_temp_beep, /* 3 */
2379 &sensor_dev_template_temp_max, /* 4 */
2380 &sensor_dev_template_temp_max_hyst, /* 5 */
2381 &sensor_dev_template_temp_crit, /* 6 */
2382 &sensor_dev_template_temp_lcrit, /* 7 */
2383 &sensor_dev_template_temp_offset, /* 8 */
2384 &sensor_dev_template_temp_type, /* 9 */
2388 static const struct sensor_template_group nct6775_temp_template_group = {
2389 .templates = nct6775_attributes_temp_template,
2390 .is_visible = nct6775_temp_is_visible,
2395 show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2397 struct nct6775_data *data = nct6775_update_device(dev);
2398 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2400 return sprintf(buf, "%d\n", data->pwm_mode[sattr->index]);
2404 store_pwm_mode(struct device *dev, struct device_attribute *attr,
2405 const char *buf, size_t count)
2407 struct nct6775_data *data = dev_get_drvdata(dev);
2408 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2409 int nr = sattr->index;
2414 err = kstrtoul(buf, 10, &val);
2421 /* Setting DC mode (0) is not supported for all chips/channels */
2422 if (data->REG_PWM_MODE[nr] == 0) {
2428 mutex_lock(&data->update_lock);
2429 data->pwm_mode[nr] = val;
2430 reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2431 reg &= ~data->PWM_MODE_MASK[nr];
2433 reg |= data->PWM_MODE_MASK[nr];
2434 nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2435 mutex_unlock(&data->update_lock);
2440 show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2442 struct nct6775_data *data = nct6775_update_device(dev);
2443 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2445 int index = sattr->index;
2449 * For automatic fan control modes, show current pwm readings.
2450 * Otherwise, show the configured value.
2452 if (index == 0 && data->pwm_enable[nr] > manual)
2453 pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2455 pwm = data->pwm[index][nr];
2457 return sprintf(buf, "%d\n", pwm);
2461 store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2464 struct nct6775_data *data = dev_get_drvdata(dev);
2465 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2467 int index = sattr->index;
2469 int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2471 = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
2475 err = kstrtoul(buf, 10, &val);
2478 val = clamp_val(val, minval[index], maxval[index]);
2480 mutex_lock(&data->update_lock);
2481 data->pwm[index][nr] = val;
2482 nct6775_write_value(data, data->REG_PWM[index][nr], val);
2483 if (index == 2) { /* floor: disable if val == 0 */
2484 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2488 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2490 mutex_unlock(&data->update_lock);
2494 /* Returns 0 if OK, -EINVAL otherwise */
2495 static int check_trip_points(struct nct6775_data *data, int nr)
2499 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2500 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2503 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2504 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2507 /* validate critical temperature and pwm if enabled (pwm > 0) */
2508 if (data->auto_pwm[nr][data->auto_pwm_num]) {
2509 if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2510 data->auto_temp[nr][data->auto_pwm_num] ||
2511 data->auto_pwm[nr][data->auto_pwm_num - 1] >
2512 data->auto_pwm[nr][data->auto_pwm_num])
2518 static void pwm_update_registers(struct nct6775_data *data, int nr)
2522 switch (data->pwm_enable[nr]) {
2527 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2528 reg = (reg & ~data->tolerance_mask) |
2529 (data->target_speed_tolerance[nr] & data->tolerance_mask);
2530 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2531 nct6775_write_value(data, data->REG_TARGET[nr],
2532 data->target_speed[nr] & 0xff);
2533 if (data->REG_TOLERANCE_H) {
2534 reg = (data->target_speed[nr] >> 8) & 0x0f;
2535 reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2536 nct6775_write_value(data,
2537 data->REG_TOLERANCE_H[nr],
2541 case thermal_cruise:
2542 nct6775_write_value(data, data->REG_TARGET[nr],
2543 data->target_temp[nr]);
2546 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2547 reg = (reg & ~data->tolerance_mask) |
2548 data->temp_tolerance[0][nr];
2549 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2555 show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2557 struct nct6775_data *data = nct6775_update_device(dev);
2558 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2560 return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2564 store_pwm_enable(struct device *dev, struct device_attribute *attr,
2565 const char *buf, size_t count)
2567 struct nct6775_data *data = dev_get_drvdata(dev);
2568 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2569 int nr = sattr->index;
2574 err = kstrtoul(buf, 10, &val);
2581 if (val == sf3 && data->kind != nct6775)
2584 if (val == sf4 && check_trip_points(data, nr)) {
2585 dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2586 dev_err(dev, "Adjust trip points and try again\n");
2590 mutex_lock(&data->update_lock);
2591 data->pwm_enable[nr] = val;
2594 * turn off pwm control: select manual mode, set pwm to maximum
2596 data->pwm[0][nr] = 255;
2597 nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2599 pwm_update_registers(data, nr);
2600 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2602 reg |= pwm_enable_to_reg(val) << 4;
2603 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2604 mutex_unlock(&data->update_lock);
2609 show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
2613 for (i = 0; i < NUM_TEMP; i++) {
2614 if (!(data->have_temp & BIT(i)))
2616 if (src == data->temp_src[i]) {
2622 return sprintf(buf, "%d\n", sel);
2626 show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2628 struct nct6775_data *data = nct6775_update_device(dev);
2629 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2630 int index = sattr->index;
2632 return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2636 store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2637 const char *buf, size_t count)
2639 struct nct6775_data *data = nct6775_update_device(dev);
2640 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2641 int nr = sattr->index;
2645 err = kstrtoul(buf, 10, &val);
2648 if (val == 0 || val > NUM_TEMP)
2650 if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
2653 mutex_lock(&data->update_lock);
2654 src = data->temp_src[val - 1];
2655 data->pwm_temp_sel[nr] = src;
2656 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2659 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2660 mutex_unlock(&data->update_lock);
2666 show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2669 struct nct6775_data *data = nct6775_update_device(dev);
2670 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2671 int index = sattr->index;
2673 return show_pwm_temp_sel_common(data, buf,
2674 data->pwm_weight_temp_sel[index]);
2678 store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2679 const char *buf, size_t count)
2681 struct nct6775_data *data = nct6775_update_device(dev);
2682 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2683 int nr = sattr->index;
2687 err = kstrtoul(buf, 10, &val);
2692 if (val && (!(data->have_temp & BIT(val - 1)) ||
2693 !data->temp_src[val - 1]))
2696 mutex_lock(&data->update_lock);
2698 src = data->temp_src[val - 1];
2699 data->pwm_weight_temp_sel[nr] = src;
2700 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2702 reg |= (src | 0x80);
2703 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2705 data->pwm_weight_temp_sel[nr] = 0;
2706 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2708 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2710 mutex_unlock(&data->update_lock);
2716 show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2718 struct nct6775_data *data = nct6775_update_device(dev);
2719 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2721 return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2725 store_target_temp(struct device *dev, struct device_attribute *attr,
2726 const char *buf, size_t count)
2728 struct nct6775_data *data = dev_get_drvdata(dev);
2729 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2730 int nr = sattr->index;
2734 err = kstrtoul(buf, 10, &val);
2738 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2739 data->target_temp_mask);
2741 mutex_lock(&data->update_lock);
2742 data->target_temp[nr] = val;
2743 pwm_update_registers(data, nr);
2744 mutex_unlock(&data->update_lock);
2749 show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2751 struct nct6775_data *data = nct6775_update_device(dev);
2752 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2753 int nr = sattr->index;
2755 return sprintf(buf, "%d\n",
2756 fan_from_reg16(data->target_speed[nr],
2757 data->fan_div[nr]));
2761 store_target_speed(struct device *dev, struct device_attribute *attr,
2762 const char *buf, size_t count)
2764 struct nct6775_data *data = dev_get_drvdata(dev);
2765 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2766 int nr = sattr->index;
2771 err = kstrtoul(buf, 10, &val);
2775 val = clamp_val(val, 0, 1350000U);
2776 speed = fan_to_reg(val, data->fan_div[nr]);
2778 mutex_lock(&data->update_lock);
2779 data->target_speed[nr] = speed;
2780 pwm_update_registers(data, nr);
2781 mutex_unlock(&data->update_lock);
2786 show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2789 struct nct6775_data *data = nct6775_update_device(dev);
2790 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2792 int index = sattr->index;
2794 return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2798 store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2799 const char *buf, size_t count)
2801 struct nct6775_data *data = dev_get_drvdata(dev);
2802 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2804 int index = sattr->index;
2808 err = kstrtoul(buf, 10, &val);
2812 /* Limit tolerance as needed */
2813 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2815 mutex_lock(&data->update_lock);
2816 data->temp_tolerance[index][nr] = val;
2818 pwm_update_registers(data, nr);
2820 nct6775_write_value(data,
2821 data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2823 mutex_unlock(&data->update_lock);
2828 * Fan speed tolerance is a tricky beast, since the associated register is
2829 * a tick counter, but the value is reported and configured as rpm.
2830 * Compute resulting low and high rpm values and report the difference.
2833 show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2836 struct nct6775_data *data = nct6775_update_device(dev);
2837 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2838 int nr = sattr->index;
2839 int low = data->target_speed[nr] - data->target_speed_tolerance[nr];
2840 int high = data->target_speed[nr] + data->target_speed_tolerance[nr];
2850 tolerance = (fan_from_reg16(low, data->fan_div[nr])
2851 - fan_from_reg16(high, data->fan_div[nr])) / 2;
2853 return sprintf(buf, "%d\n", tolerance);
2857 store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2858 const char *buf, size_t count)
2860 struct nct6775_data *data = dev_get_drvdata(dev);
2861 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2862 int nr = sattr->index;
2867 err = kstrtoul(buf, 10, &val);
2871 high = fan_from_reg16(data->target_speed[nr],
2872 data->fan_div[nr]) + val;
2873 low = fan_from_reg16(data->target_speed[nr],
2874 data->fan_div[nr]) - val;
2880 val = (fan_to_reg(low, data->fan_div[nr]) -
2881 fan_to_reg(high, data->fan_div[nr])) / 2;
2883 /* Limit tolerance as needed */
2884 val = clamp_val(val, 0, data->speed_tolerance_limit);
2886 mutex_lock(&data->update_lock);
2887 data->target_speed_tolerance[nr] = val;
2888 pwm_update_registers(data, nr);
2889 mutex_unlock(&data->update_lock);
2893 SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2894 SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2896 SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2897 store_pwm_enable, 0);
2898 SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2899 show_pwm_temp_sel, store_pwm_temp_sel, 0);
2900 SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2901 show_target_temp, store_target_temp, 0);
2902 SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2903 show_target_speed, store_target_speed, 0);
2904 SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2905 show_speed_tolerance, store_speed_tolerance, 0);
2907 /* Smart Fan registers */
2910 show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
2912 struct nct6775_data *data = nct6775_update_device(dev);
2913 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2915 int index = sattr->index;
2917 return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
2921 store_weight_temp(struct device *dev, struct device_attribute *attr,
2922 const char *buf, size_t count)
2924 struct nct6775_data *data = dev_get_drvdata(dev);
2925 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2927 int index = sattr->index;
2931 err = kstrtoul(buf, 10, &val);
2935 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255);
2937 mutex_lock(&data->update_lock);
2938 data->weight_temp[index][nr] = val;
2939 nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val);
2940 mutex_unlock(&data->update_lock);
2944 SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO,
2945 show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0);
2946 SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step",
2947 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0);
2948 SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol",
2949 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1);
2950 SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base",
2951 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2);
2952 SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step",
2953 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5);
2954 SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base",
2955 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6);
2958 show_fan_time(struct device *dev, struct device_attribute *attr, char *buf)
2960 struct nct6775_data *data = nct6775_update_device(dev);
2961 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2963 int index = sattr->index;
2965 return sprintf(buf, "%d\n",
2966 step_time_from_reg(data->fan_time[index][nr],
2967 data->pwm_mode[nr]));
2971 store_fan_time(struct device *dev, struct device_attribute *attr,
2972 const char *buf, size_t count)
2974 struct nct6775_data *data = dev_get_drvdata(dev);
2975 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2977 int index = sattr->index;
2981 err = kstrtoul(buf, 10, &val);
2985 val = step_time_to_reg(val, data->pwm_mode[nr]);
2986 mutex_lock(&data->update_lock);
2987 data->fan_time[index][nr] = val;
2988 nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val);
2989 mutex_unlock(&data->update_lock);
2994 show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2996 struct nct6775_data *data = nct6775_update_device(dev);
2997 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2999 return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]);
3003 store_auto_pwm(struct device *dev, struct device_attribute *attr,
3004 const char *buf, size_t count)
3006 struct nct6775_data *data = dev_get_drvdata(dev);
3007 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3009 int point = sattr->index;
3014 err = kstrtoul(buf, 10, &val);
3020 if (point == data->auto_pwm_num) {
3021 if (data->kind != nct6775 && !val)
3023 if (data->kind != nct6779 && val)
3027 mutex_lock(&data->update_lock);
3028 data->auto_pwm[nr][point] = val;
3029 if (point < data->auto_pwm_num) {
3030 nct6775_write_value(data,
3031 NCT6775_AUTO_PWM(data, nr, point),
3032 data->auto_pwm[nr][point]);
3034 switch (data->kind) {
3036 /* disable if needed (pwm == 0) */
3037 reg = nct6775_read_value(data,
3038 NCT6775_REG_CRITICAL_ENAB[nr]);
3043 nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr],
3047 break; /* always enabled, nothing to do */
3055 nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
3057 reg = nct6775_read_value(data,
3058 data->REG_CRITICAL_PWM_ENABLE[nr]);
3060 reg &= ~data->CRITICAL_PWM_ENABLE_MASK;
3062 reg |= data->CRITICAL_PWM_ENABLE_MASK;
3063 nct6775_write_value(data,
3064 data->REG_CRITICAL_PWM_ENABLE[nr],
3069 mutex_unlock(&data->update_lock);
3074 show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf)
3076 struct nct6775_data *data = nct6775_update_device(dev);
3077 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3079 int point = sattr->index;
3082 * We don't know for sure if the temperature is signed or unsigned.
3083 * Assume it is unsigned.
3085 return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000);
3089 store_auto_temp(struct device *dev, struct device_attribute *attr,
3090 const char *buf, size_t count)
3092 struct nct6775_data *data = dev_get_drvdata(dev);
3093 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3095 int point = sattr->index;
3099 err = kstrtoul(buf, 10, &val);
3105 mutex_lock(&data->update_lock);
3106 data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000);
3107 if (point < data->auto_pwm_num) {
3108 nct6775_write_value(data,
3109 NCT6775_AUTO_TEMP(data, nr, point),
3110 data->auto_temp[nr][point]);
3112 nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr],
3113 data->auto_temp[nr][point]);
3115 mutex_unlock(&data->update_lock);
3119 static umode_t nct6775_pwm_is_visible(struct kobject *kobj,
3120 struct attribute *attr, int index)
3122 struct device *dev = container_of(kobj, struct device, kobj);
3123 struct nct6775_data *data = dev_get_drvdata(dev);
3124 int pwm = index / 36; /* pwm index */
3125 int nr = index % 36; /* attribute index */
3127 if (!(data->has_pwm & BIT(pwm)))
3130 if ((nr >= 14 && nr <= 18) || nr == 21) /* weight */
3131 if (!data->REG_WEIGHT_TEMP_SEL[pwm])
3133 if (nr == 19 && data->REG_PWM[3] == NULL) /* pwm_max */
3135 if (nr == 20 && data->REG_PWM[4] == NULL) /* pwm_step */
3137 if (nr == 21 && data->REG_PWM[6] == NULL) /* weight_duty_base */
3140 if (nr >= 22 && nr <= 35) { /* auto point */
3141 int api = (nr - 22) / 2; /* auto point index */
3143 if (api > data->auto_pwm_num)
3149 SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO,
3150 show_fan_time, store_fan_time, 0, 0);
3151 SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO,
3152 show_fan_time, store_fan_time, 0, 1);
3153 SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO,
3154 show_fan_time, store_fan_time, 0, 2);
3155 SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm,
3157 SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm,
3159 SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO,
3160 show_temp_tolerance, store_temp_tolerance, 0, 0);
3161 SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance",
3162 S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance,
3165 SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm,
3168 SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm,
3171 SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm",
3172 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0);
3173 SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp",
3174 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0);
3176 SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm",
3177 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1);
3178 SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp",
3179 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1);
3181 SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm",
3182 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2);
3183 SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp",
3184 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2);
3186 SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm",
3187 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3);
3188 SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp",
3189 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3);
3191 SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm",
3192 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4);
3193 SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp",
3194 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4);
3196 SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm",
3197 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5);
3198 SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp",
3199 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5);
3201 SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm",
3202 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6);
3203 SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp",
3204 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6);
3207 * nct6775_pwm_is_visible uses the index into the following array
3208 * to determine if attributes should be created or not.
3209 * Any change in order or content must be matched.
3211 static struct sensor_device_template *nct6775_attributes_pwm_template[] = {
3212 &sensor_dev_template_pwm,
3213 &sensor_dev_template_pwm_mode,
3214 &sensor_dev_template_pwm_enable,
3215 &sensor_dev_template_pwm_temp_sel,
3216 &sensor_dev_template_pwm_temp_tolerance,
3217 &sensor_dev_template_pwm_crit_temp_tolerance,
3218 &sensor_dev_template_pwm_target_temp,
3219 &sensor_dev_template_fan_target,
3220 &sensor_dev_template_fan_tolerance,
3221 &sensor_dev_template_pwm_stop_time,
3222 &sensor_dev_template_pwm_step_up_time,
3223 &sensor_dev_template_pwm_step_down_time,
3224 &sensor_dev_template_pwm_start,
3225 &sensor_dev_template_pwm_floor,
3226 &sensor_dev_template_pwm_weight_temp_sel, /* 14 */
3227 &sensor_dev_template_pwm_weight_temp_step,
3228 &sensor_dev_template_pwm_weight_temp_step_tol,
3229 &sensor_dev_template_pwm_weight_temp_step_base,
3230 &sensor_dev_template_pwm_weight_duty_step, /* 18 */
3231 &sensor_dev_template_pwm_max, /* 19 */
3232 &sensor_dev_template_pwm_step, /* 20 */
3233 &sensor_dev_template_pwm_weight_duty_base, /* 21 */
3234 &sensor_dev_template_pwm_auto_point1_pwm, /* 22 */
3235 &sensor_dev_template_pwm_auto_point1_temp,
3236 &sensor_dev_template_pwm_auto_point2_pwm,
3237 &sensor_dev_template_pwm_auto_point2_temp,
3238 &sensor_dev_template_pwm_auto_point3_pwm,
3239 &sensor_dev_template_pwm_auto_point3_temp,
3240 &sensor_dev_template_pwm_auto_point4_pwm,
3241 &sensor_dev_template_pwm_auto_point4_temp,
3242 &sensor_dev_template_pwm_auto_point5_pwm,
3243 &sensor_dev_template_pwm_auto_point5_temp,
3244 &sensor_dev_template_pwm_auto_point6_pwm,
3245 &sensor_dev_template_pwm_auto_point6_temp,
3246 &sensor_dev_template_pwm_auto_point7_pwm,
3247 &sensor_dev_template_pwm_auto_point7_temp, /* 35 */
3252 static const struct sensor_template_group nct6775_pwm_template_group = {
3253 .templates = nct6775_attributes_pwm_template,
3254 .is_visible = nct6775_pwm_is_visible,
3259 cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
3261 struct nct6775_data *data = dev_get_drvdata(dev);
3263 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
3266 static DEVICE_ATTR_RO(cpu0_vid);
3268 /* Case open detection */
3271 clear_caseopen(struct device *dev, struct device_attribute *attr,
3272 const char *buf, size_t count)
3274 struct nct6775_data *data = dev_get_drvdata(dev);
3275 int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE;
3280 if (kstrtoul(buf, 10, &val) || val != 0)
3283 mutex_lock(&data->update_lock);
3286 * Use CR registers to clear caseopen status.
3287 * The CR registers are the same for all chips, and not all chips
3288 * support clearing the caseopen status through "regular" registers.
3290 ret = superio_enter(data->sioreg);
3296 superio_select(data->sioreg, NCT6775_LD_ACPI);
3297 reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]);
3298 reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3299 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3300 reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3301 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3302 superio_exit(data->sioreg);
3304 data->valid = false; /* Force cache refresh */
3306 mutex_unlock(&data->update_lock);
3310 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm,
3311 clear_caseopen, INTRUSION_ALARM_BASE);
3312 static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm,
3313 clear_caseopen, INTRUSION_ALARM_BASE + 1);
3314 static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep,
3315 store_beep, INTRUSION_ALARM_BASE);
3316 static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep,
3317 store_beep, INTRUSION_ALARM_BASE + 1);
3318 static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep,
3319 store_beep, BEEP_ENABLE_BASE);
3321 static umode_t nct6775_other_is_visible(struct kobject *kobj,
3322 struct attribute *attr, int index)
3324 struct device *dev = container_of(kobj, struct device, kobj);
3325 struct nct6775_data *data = dev_get_drvdata(dev);
3327 if (index == 0 && !data->have_vid)
3330 if (index == 1 || index == 2) {
3331 if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0)
3335 if (index == 3 || index == 4) {
3336 if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0)
3344 * nct6775_other_is_visible uses the index into the following array
3345 * to determine if attributes should be created or not.
3346 * Any change in order or content must be matched.
3348 static struct attribute *nct6775_attributes_other[] = {
3349 &dev_attr_cpu0_vid.attr, /* 0 */
3350 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, /* 1 */
3351 &sensor_dev_attr_intrusion1_alarm.dev_attr.attr, /* 2 */
3352 &sensor_dev_attr_intrusion0_beep.dev_attr.attr, /* 3 */
3353 &sensor_dev_attr_intrusion1_beep.dev_attr.attr, /* 4 */
3354 &sensor_dev_attr_beep_enable.dev_attr.attr, /* 5 */
3359 static const struct attribute_group nct6775_group_other = {
3360 .attrs = nct6775_attributes_other,
3361 .is_visible = nct6775_other_is_visible,
3364 static inline void nct6775_init_device(struct nct6775_data *data)
3369 /* Start monitoring if needed */
3370 if (data->REG_CONFIG) {
3371 tmp = nct6775_read_value(data, data->REG_CONFIG);
3373 nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01);
3376 /* Enable temperature sensors if needed */
3377 for (i = 0; i < NUM_TEMP; i++) {
3378 if (!(data->have_temp & BIT(i)))
3380 if (!data->reg_temp_config[i])
3382 tmp = nct6775_read_value(data, data->reg_temp_config[i]);
3384 nct6775_write_value(data, data->reg_temp_config[i],
3388 /* Enable VBAT monitoring if needed */
3389 tmp = nct6775_read_value(data, data->REG_VBAT);
3391 nct6775_write_value(data, data->REG_VBAT, tmp | 0x01);
3393 diode = nct6775_read_value(data, data->REG_DIODE);
3395 for (i = 0; i < data->temp_fixed_num; i++) {
3396 if (!(data->have_temp_fixed & BIT(i)))
3398 if ((tmp & (data->DIODE_MASK << i))) /* diode */
3400 = 3 - ((diode >> i) & data->DIODE_MASK);
3401 else /* thermistor */
3402 data->temp_type[i] = 4;
3407 nct6775_check_fan_inputs(struct nct6775_data *data)
3409 bool fan3pin = false, fan4pin = false, fan4min = false;
3410 bool fan5pin = false, fan6pin = false, fan7pin = false;
3411 bool pwm3pin = false, pwm4pin = false, pwm5pin = false;
3412 bool pwm6pin = false, pwm7pin = false;
3413 int sioreg = data->sioreg;
3416 /* Store SIO_REG_ENABLE for use during resume */
3417 superio_select(sioreg, NCT6775_LD_HWM);
3418 data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE);
3420 /* fan4 and fan5 share some pins with the GPIO and serial flash */
3421 if (data->kind == nct6775) {
3422 regval = superio_inb(sioreg, 0x2c);
3424 fan3pin = regval & BIT(6);
3425 pwm3pin = regval & BIT(7);
3427 /* On NCT6775, fan4 shares pins with the fdc interface */
3428 fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
3429 } else if (data->kind == nct6776) {
3430 bool gpok = superio_inb(sioreg, 0x27) & 0x80;
3431 const char *board_vendor, *board_name;
3433 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3434 board_name = dmi_get_system_info(DMI_BOARD_NAME);
3436 if (board_name && board_vendor &&
3437 !strcmp(board_vendor, "ASRock")) {
3439 * Auxiliary fan monitoring is not enabled on ASRock
3440 * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode.
3441 * Observed with BIOS version 2.00.
3443 if (!strcmp(board_name, "Z77 Pro4-M")) {
3444 if ((data->sio_reg_enable & 0xe0) != 0xe0) {
3445 data->sio_reg_enable |= 0xe0;
3446 superio_outb(sioreg, SIO_REG_ENABLE,
3447 data->sio_reg_enable);
3452 if (data->sio_reg_enable & 0x80)
3455 fan3pin = !(superio_inb(sioreg, 0x24) & 0x40);
3457 if (data->sio_reg_enable & 0x40)
3460 fan4pin = superio_inb(sioreg, 0x1C) & 0x01;
3462 if (data->sio_reg_enable & 0x20)
3465 fan5pin = superio_inb(sioreg, 0x1C) & 0x02;
3469 } else if (data->kind == nct6106) {
3470 regval = superio_inb(sioreg, 0x24);
3471 fan3pin = !(regval & 0x80);
3472 pwm3pin = regval & 0x08;
3474 /* NCT6779D, NCT6791D, NCT6792D, NCT6793D, NCT6795D, NCT6796D */
3475 int regval_1b, regval_2a, regval_2f;
3478 regval = superio_inb(sioreg, 0x1c);
3480 fan3pin = !(regval & BIT(5));
3481 fan4pin = !(regval & BIT(6));
3482 fan5pin = !(regval & BIT(7));
3484 pwm3pin = !(regval & BIT(0));
3485 pwm4pin = !(regval & BIT(1));
3486 pwm5pin = !(regval & BIT(2));
3488 regval = superio_inb(sioreg, 0x2d);
3489 switch (data->kind) {
3492 fan6pin = regval & BIT(1);
3493 pwm6pin = regval & BIT(0);
3498 regval_1b = superio_inb(sioreg, 0x1b);
3499 regval_2a = superio_inb(sioreg, 0x2a);
3500 regval_2f = superio_inb(sioreg, 0x2f);
3501 dsw_en = regval_2f & BIT(3);
3504 pwm5pin = regval & BIT(7);
3507 fan5pin = regval_1b & BIT(5);
3509 superio_select(sioreg, NCT6775_LD_12);
3510 if (data->kind != nct6796) {
3511 int regval_eb = superio_inb(sioreg, 0xeb);
3514 fan6pin = regval & BIT(1);
3515 pwm6pin = regval & BIT(0);
3519 fan5pin = regval_eb & BIT(5);
3521 pwm5pin = (regval_eb & BIT(4)) &&
3522 !(regval_2a & BIT(0));
3524 fan6pin = regval_eb & BIT(3);
3526 pwm6pin = regval_eb & BIT(2);
3529 if (data->kind == nct6795 || data->kind == nct6796) {
3530 int regval_ed = superio_inb(sioreg, 0xed);
3533 fan6pin = (regval_2a & BIT(4)) &&
3535 (dsw_en && (regval_ed & BIT(4))));
3537 pwm6pin = (regval_2a & BIT(3)) &&
3538 (regval_ed & BIT(2));
3541 if (data->kind == nct6796) {
3542 int regval_1d = superio_inb(sioreg, 0x1d);
3543 int regval_2b = superio_inb(sioreg, 0x2b);
3545 fan7pin = !(regval_2b & BIT(2));
3546 pwm7pin = !(regval_1d & (BIT(2) | BIT(3)));
3550 default: /* NCT6779D */
3557 /* fan 1 and 2 (0x03) are always present */
3558 data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) |
3559 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3560 data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) |
3561 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3562 data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) |
3563 (pwm5pin << 4) | (pwm6pin << 5) | (pwm7pin << 6);
3566 static void add_temp_sensors(struct nct6775_data *data, const u16 *regp,
3567 int *available, int *mask)
3572 for (i = 0; i < data->pwm_num && *available; i++) {
3577 src = nct6775_read_value(data, regp[i]);
3579 if (!src || (*mask & BIT(src)))
3581 if (!(data->temp_mask & BIT(src)))
3584 index = __ffs(*available);
3585 nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src);
3586 *available &= ~BIT(index);
3591 static int nct6775_probe(struct platform_device *pdev)
3593 struct device *dev = &pdev->dev;
3594 struct nct6775_sio_data *sio_data = dev_get_platdata(dev);
3595 struct nct6775_data *data;
3596 struct resource *res;
3598 int src, mask, available;
3599 const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config;
3600 const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit;
3601 const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL;
3602 int num_reg_temp, num_reg_temp_mon;
3604 struct attribute_group *group;
3605 struct device *hwmon_dev;
3606 int num_attr_groups = 0;
3608 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3609 if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH,
3613 data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data),
3618 data->kind = sio_data->kind;
3619 data->sioreg = sio_data->sioreg;
3620 data->addr = res->start;
3621 mutex_init(&data->update_lock);
3622 data->name = nct6775_device_names[data->kind];
3623 data->bank = 0xff; /* Force initial bank selection */
3624 platform_set_drvdata(pdev, data);
3626 switch (data->kind) {
3630 data->auto_pwm_num = 4;
3631 data->temp_fixed_num = 3;
3632 data->num_temp_alarms = 6;
3633 data->num_temp_beeps = 6;
3635 data->fan_from_reg = fan_from_reg13;
3636 data->fan_from_reg_min = fan_from_reg13;
3638 data->temp_label = nct6776_temp_label;
3639 data->temp_mask = NCT6776_TEMP_MASK;
3641 data->REG_VBAT = NCT6106_REG_VBAT;
3642 data->REG_DIODE = NCT6106_REG_DIODE;
3643 data->DIODE_MASK = NCT6106_DIODE_MASK;
3644 data->REG_VIN = NCT6106_REG_IN;
3645 data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN;
3646 data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX;
3647 data->REG_TARGET = NCT6106_REG_TARGET;
3648 data->REG_FAN = NCT6106_REG_FAN;
3649 data->REG_FAN_MODE = NCT6106_REG_FAN_MODE;
3650 data->REG_FAN_MIN = NCT6106_REG_FAN_MIN;
3651 data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES;
3652 data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT;
3653 data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME;
3654 data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME;
3655 data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME;
3656 data->REG_PWM[0] = NCT6106_REG_PWM;
3657 data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT;
3658 data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT;
3659 data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
3660 data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
3661 data->REG_PWM_READ = NCT6106_REG_PWM_READ;
3662 data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
3663 data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
3664 data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP;
3665 data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM;
3666 data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP;
3667 data->REG_CRITICAL_TEMP_TOLERANCE
3668 = NCT6106_REG_CRITICAL_TEMP_TOLERANCE;
3669 data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE;
3670 data->CRITICAL_PWM_ENABLE_MASK
3671 = NCT6106_CRITICAL_PWM_ENABLE_MASK;
3672 data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM;
3673 data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
3674 data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
3675 data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL;
3676 data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL;
3677 data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
3678 data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
3679 data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
3680 data->REG_ALARM = NCT6106_REG_ALARM;
3681 data->ALARM_BITS = NCT6106_ALARM_BITS;
3682 data->REG_BEEP = NCT6106_REG_BEEP;
3683 data->BEEP_BITS = NCT6106_BEEP_BITS;
3685 reg_temp = NCT6106_REG_TEMP;
3686 reg_temp_mon = NCT6106_REG_TEMP_MON;
3687 num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP);
3688 num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON);
3689 reg_temp_over = NCT6106_REG_TEMP_OVER;
3690 reg_temp_hyst = NCT6106_REG_TEMP_HYST;
3691 reg_temp_config = NCT6106_REG_TEMP_CONFIG;
3692 reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
3693 reg_temp_crit = NCT6106_REG_TEMP_CRIT;
3694 reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
3695 reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
3701 data->auto_pwm_num = 6;
3702 data->has_fan_div = true;
3703 data->temp_fixed_num = 3;
3704 data->num_temp_alarms = 3;
3705 data->num_temp_beeps = 3;
3707 data->ALARM_BITS = NCT6775_ALARM_BITS;
3708 data->BEEP_BITS = NCT6775_BEEP_BITS;
3710 data->fan_from_reg = fan_from_reg16;
3711 data->fan_from_reg_min = fan_from_reg8;
3712 data->target_temp_mask = 0x7f;
3713 data->tolerance_mask = 0x0f;
3714 data->speed_tolerance_limit = 15;
3716 data->temp_label = nct6775_temp_label;
3717 data->temp_mask = NCT6775_TEMP_MASK;
3719 data->REG_CONFIG = NCT6775_REG_CONFIG;
3720 data->REG_VBAT = NCT6775_REG_VBAT;
3721 data->REG_DIODE = NCT6775_REG_DIODE;
3722 data->DIODE_MASK = NCT6775_DIODE_MASK;
3723 data->REG_VIN = NCT6775_REG_IN;
3724 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3725 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3726 data->REG_TARGET = NCT6775_REG_TARGET;
3727 data->REG_FAN = NCT6775_REG_FAN;
3728 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3729 data->REG_FAN_MIN = NCT6775_REG_FAN_MIN;
3730 data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES;
3731 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3732 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3733 data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME;
3734 data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME;
3735 data->REG_PWM[0] = NCT6775_REG_PWM;
3736 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3737 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3738 data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT;
3739 data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT;
3740 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3741 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3742 data->REG_PWM_MODE = NCT6775_REG_PWM_MODE;
3743 data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK;
3744 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3745 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3746 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3747 data->REG_CRITICAL_TEMP_TOLERANCE
3748 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3749 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3750 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3751 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3752 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3753 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3754 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3755 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3756 data->REG_ALARM = NCT6775_REG_ALARM;
3757 data->REG_BEEP = NCT6775_REG_BEEP;
3759 reg_temp = NCT6775_REG_TEMP;
3760 reg_temp_mon = NCT6775_REG_TEMP_MON;
3761 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3762 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3763 reg_temp_over = NCT6775_REG_TEMP_OVER;
3764 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3765 reg_temp_config = NCT6775_REG_TEMP_CONFIG;
3766 reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE;
3767 reg_temp_crit = NCT6775_REG_TEMP_CRIT;
3773 data->auto_pwm_num = 4;
3774 data->has_fan_div = false;
3775 data->temp_fixed_num = 3;
3776 data->num_temp_alarms = 3;
3777 data->num_temp_beeps = 6;
3779 data->ALARM_BITS = NCT6776_ALARM_BITS;
3780 data->BEEP_BITS = NCT6776_BEEP_BITS;
3782 data->fan_from_reg = fan_from_reg13;
3783 data->fan_from_reg_min = fan_from_reg13;
3784 data->target_temp_mask = 0xff;
3785 data->tolerance_mask = 0x07;
3786 data->speed_tolerance_limit = 63;
3788 data->temp_label = nct6776_temp_label;
3789 data->temp_mask = NCT6776_TEMP_MASK;
3791 data->REG_CONFIG = NCT6775_REG_CONFIG;
3792 data->REG_VBAT = NCT6775_REG_VBAT;
3793 data->REG_DIODE = NCT6775_REG_DIODE;
3794 data->DIODE_MASK = NCT6775_DIODE_MASK;
3795 data->REG_VIN = NCT6775_REG_IN;
3796 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3797 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3798 data->REG_TARGET = NCT6775_REG_TARGET;
3799 data->REG_FAN = NCT6775_REG_FAN;
3800 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3801 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3802 data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES;
3803 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3804 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3805 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3806 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3807 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3808 data->REG_PWM[0] = NCT6775_REG_PWM;
3809 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3810 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3811 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3812 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3813 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3814 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3815 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3816 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3817 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3818 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3819 data->REG_CRITICAL_TEMP_TOLERANCE
3820 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3821 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3822 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3823 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3824 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3825 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3826 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3827 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3828 data->REG_ALARM = NCT6775_REG_ALARM;
3829 data->REG_BEEP = NCT6776_REG_BEEP;
3831 reg_temp = NCT6775_REG_TEMP;
3832 reg_temp_mon = NCT6775_REG_TEMP_MON;
3833 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3834 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3835 reg_temp_over = NCT6775_REG_TEMP_OVER;
3836 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3837 reg_temp_config = NCT6776_REG_TEMP_CONFIG;
3838 reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE;
3839 reg_temp_crit = NCT6776_REG_TEMP_CRIT;
3845 data->auto_pwm_num = 4;
3846 data->has_fan_div = false;
3847 data->temp_fixed_num = 6;
3848 data->num_temp_alarms = 2;
3849 data->num_temp_beeps = 2;
3851 data->ALARM_BITS = NCT6779_ALARM_BITS;
3852 data->BEEP_BITS = NCT6779_BEEP_BITS;
3854 data->fan_from_reg = fan_from_reg13;
3855 data->fan_from_reg_min = fan_from_reg13;
3856 data->target_temp_mask = 0xff;
3857 data->tolerance_mask = 0x07;
3858 data->speed_tolerance_limit = 63;
3860 data->temp_label = nct6779_temp_label;
3861 data->temp_mask = NCT6779_TEMP_MASK;
3863 data->REG_CONFIG = NCT6775_REG_CONFIG;
3864 data->REG_VBAT = NCT6775_REG_VBAT;
3865 data->REG_DIODE = NCT6775_REG_DIODE;
3866 data->DIODE_MASK = NCT6775_DIODE_MASK;
3867 data->REG_VIN = NCT6779_REG_IN;
3868 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3869 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3870 data->REG_TARGET = NCT6775_REG_TARGET;
3871 data->REG_FAN = NCT6779_REG_FAN;
3872 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3873 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3874 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3875 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3876 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3877 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3878 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3879 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3880 data->REG_PWM[0] = NCT6775_REG_PWM;
3881 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3882 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3883 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3884 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3885 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3886 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3887 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3888 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3889 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3890 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3891 data->REG_CRITICAL_TEMP_TOLERANCE
3892 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3893 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3894 data->CRITICAL_PWM_ENABLE_MASK
3895 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3896 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
3897 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
3898 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3899 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3900 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3901 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3902 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3903 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3904 data->REG_ALARM = NCT6779_REG_ALARM;
3905 data->REG_BEEP = NCT6776_REG_BEEP;
3907 reg_temp = NCT6779_REG_TEMP;
3908 reg_temp_mon = NCT6779_REG_TEMP_MON;
3909 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
3910 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
3911 reg_temp_over = NCT6779_REG_TEMP_OVER;
3912 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
3913 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
3914 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
3915 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
3924 data->pwm_num = (data->kind == nct6796) ? 7 : 6;
3925 data->auto_pwm_num = 4;
3926 data->has_fan_div = false;
3927 data->temp_fixed_num = 6;
3928 data->num_temp_alarms = 2;
3929 data->num_temp_beeps = 2;
3931 data->ALARM_BITS = NCT6791_ALARM_BITS;
3932 data->BEEP_BITS = NCT6779_BEEP_BITS;
3934 data->fan_from_reg = fan_from_reg13;
3935 data->fan_from_reg_min = fan_from_reg13;
3936 data->target_temp_mask = 0xff;
3937 data->tolerance_mask = 0x07;
3938 data->speed_tolerance_limit = 63;
3940 switch (data->kind) {
3943 data->temp_label = nct6779_temp_label;
3944 data->temp_mask = NCT6791_TEMP_MASK;
3947 data->temp_label = nct6792_temp_label;
3948 data->temp_mask = NCT6792_TEMP_MASK;
3951 data->temp_label = nct6793_temp_label;
3952 data->temp_mask = NCT6793_TEMP_MASK;
3955 data->temp_label = nct6795_temp_label;
3956 data->temp_mask = NCT6795_TEMP_MASK;
3959 data->temp_label = nct6796_temp_label;
3960 data->temp_mask = NCT6796_TEMP_MASK;
3964 data->REG_CONFIG = NCT6775_REG_CONFIG;
3965 data->REG_VBAT = NCT6775_REG_VBAT;
3966 data->REG_DIODE = NCT6775_REG_DIODE;
3967 data->DIODE_MASK = NCT6775_DIODE_MASK;
3968 data->REG_VIN = NCT6779_REG_IN;
3969 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3970 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3971 data->REG_TARGET = NCT6775_REG_TARGET;
3972 data->REG_FAN = NCT6779_REG_FAN;
3973 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3974 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3975 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3976 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3977 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3978 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3979 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3980 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3981 data->REG_PWM[0] = NCT6775_REG_PWM;
3982 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3983 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3984 data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP;
3985 data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE;
3986 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3987 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3988 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3989 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3990 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3991 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3992 data->REG_CRITICAL_TEMP_TOLERANCE
3993 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3994 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3995 data->CRITICAL_PWM_ENABLE_MASK
3996 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3997 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
3998 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
3999 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4000 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4001 data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL;
4002 data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP;
4003 data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL;
4004 data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE;
4005 data->REG_ALARM = NCT6791_REG_ALARM;
4006 if (data->kind == nct6791)
4007 data->REG_BEEP = NCT6776_REG_BEEP;
4009 data->REG_BEEP = NCT6792_REG_BEEP;
4011 reg_temp = NCT6779_REG_TEMP;
4012 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4013 if (data->kind == nct6791) {
4014 reg_temp_mon = NCT6779_REG_TEMP_MON;
4015 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4017 reg_temp_mon = NCT6792_REG_TEMP_MON;
4018 num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON);
4020 reg_temp_over = NCT6779_REG_TEMP_OVER;
4021 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4022 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4023 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4024 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4030 data->have_in = BIT(data->in_num) - 1;
4031 data->have_temp = 0;
4034 * On some boards, not all available temperature sources are monitored,
4035 * even though some of the monitoring registers are unused.
4036 * Get list of unused monitoring registers, then detect if any fan
4037 * controls are configured to use unmonitored temperature sources.
4038 * If so, assign the unmonitored temperature sources to available
4039 * monitoring registers.
4043 for (i = 0; i < num_reg_temp; i++) {
4044 if (reg_temp[i] == 0)
4047 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4048 if (!src || (mask & BIT(src)))
4049 available |= BIT(i);
4055 * Now find unmonitored temperature registers and enable monitoring
4056 * if additional monitoring registers are available.
4058 add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask);
4059 add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask);
4062 s = NUM_TEMP_FIXED; /* First dynamic temperature attribute */
4063 for (i = 0; i < num_reg_temp; i++) {
4064 if (reg_temp[i] == 0)
4067 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4068 if (!src || (mask & BIT(src)))
4071 if (!(data->temp_mask & BIT(src))) {
4073 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4074 src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]);
4080 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4081 if (src <= data->temp_fixed_num) {
4082 data->have_temp |= BIT(src - 1);
4083 data->have_temp_fixed |= BIT(src - 1);
4084 data->reg_temp[0][src - 1] = reg_temp[i];
4085 data->reg_temp[1][src - 1] = reg_temp_over[i];
4086 data->reg_temp[2][src - 1] = reg_temp_hyst[i];
4087 if (reg_temp_crit_h && reg_temp_crit_h[i])
4088 data->reg_temp[3][src - 1] = reg_temp_crit_h[i];
4089 else if (reg_temp_crit[src - 1])
4090 data->reg_temp[3][src - 1]
4091 = reg_temp_crit[src - 1];
4092 if (reg_temp_crit_l && reg_temp_crit_l[i])
4093 data->reg_temp[4][src - 1] = reg_temp_crit_l[i];
4094 data->reg_temp_config[src - 1] = reg_temp_config[i];
4095 data->temp_src[src - 1] = src;
4102 /* Use dynamic index for other sources */
4103 data->have_temp |= BIT(s);
4104 data->reg_temp[0][s] = reg_temp[i];
4105 data->reg_temp[1][s] = reg_temp_over[i];
4106 data->reg_temp[2][s] = reg_temp_hyst[i];
4107 data->reg_temp_config[s] = reg_temp_config[i];
4108 if (reg_temp_crit_h && reg_temp_crit_h[i])
4109 data->reg_temp[3][s] = reg_temp_crit_h[i];
4110 else if (reg_temp_crit[src - 1])
4111 data->reg_temp[3][s] = reg_temp_crit[src - 1];
4112 if (reg_temp_crit_l && reg_temp_crit_l[i])
4113 data->reg_temp[4][s] = reg_temp_crit_l[i];
4115 data->temp_src[s] = src;
4120 * Repeat with temperatures used for fan control.
4121 * This set of registers does not support limits.
4123 for (i = 0; i < num_reg_temp_mon; i++) {
4124 if (reg_temp_mon[i] == 0)
4127 src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f;
4131 if (!(data->temp_mask & BIT(src))) {
4133 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4134 src, i, data->REG_TEMP_SEL[i],
4140 * For virtual temperature sources, the 'virtual' temperature
4141 * for each fan reflects a different temperature, and there
4142 * are no duplicates.
4144 if (src != TEMP_SOURCE_VIRTUAL) {
4145 if (mask & BIT(src))
4150 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4151 if (src <= data->temp_fixed_num) {
4152 if (data->have_temp & BIT(src - 1))
4154 data->have_temp |= BIT(src - 1);
4155 data->have_temp_fixed |= BIT(src - 1);
4156 data->reg_temp[0][src - 1] = reg_temp_mon[i];
4157 data->temp_src[src - 1] = src;
4164 /* Use dynamic index for other sources */
4165 data->have_temp |= BIT(s);
4166 data->reg_temp[0][s] = reg_temp_mon[i];
4167 data->temp_src[s] = src;
4171 #ifdef USE_ALTERNATE
4173 * Go through the list of alternate temp registers and enable
4175 * The temperature is already monitored if the respective bit in <mask>
4178 for (i = 0; i < 32; i++) {
4179 if (!(data->temp_mask & BIT(i + 1)))
4181 if (!reg_temp_alternate[i])
4183 if (mask & BIT(i + 1))
4185 if (i < data->temp_fixed_num) {
4186 if (data->have_temp & BIT(i))
4188 data->have_temp |= BIT(i);
4189 data->have_temp_fixed |= BIT(i);
4190 data->reg_temp[0][i] = reg_temp_alternate[i];
4191 if (i < num_reg_temp) {
4192 data->reg_temp[1][i] = reg_temp_over[i];
4193 data->reg_temp[2][i] = reg_temp_hyst[i];
4195 data->temp_src[i] = i + 1;
4199 if (s >= NUM_TEMP) /* Abort if no more space */
4202 data->have_temp |= BIT(s);
4203 data->reg_temp[0][s] = reg_temp_alternate[i];
4204 data->temp_src[s] = i + 1;
4207 #endif /* USE_ALTERNATE */
4209 /* Initialize the chip */
4210 nct6775_init_device(data);
4212 err = superio_enter(sio_data->sioreg);
4216 cr2a = superio_inb(sio_data->sioreg, 0x2a);
4217 switch (data->kind) {
4219 data->have_vid = (cr2a & 0x40);
4222 data->have_vid = (cr2a & 0x60) == 0x40;
4236 * We can get the VID input values directly at logical device D 0xe3.
4238 if (data->have_vid) {
4239 superio_select(sio_data->sioreg, NCT6775_LD_VID);
4240 data->vid = superio_inb(sio_data->sioreg, 0xe3);
4241 data->vrm = vid_which_vrm();
4247 superio_select(sio_data->sioreg, NCT6775_LD_HWM);
4248 tmp = superio_inb(sio_data->sioreg,
4249 NCT6775_REG_CR_FAN_DEBOUNCE);
4250 switch (data->kind) {
4269 superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE,
4271 dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n",
4275 nct6775_check_fan_inputs(data);
4277 superio_exit(sio_data->sioreg);
4279 /* Read fan clock dividers immediately */
4280 nct6775_init_fan_common(dev, data);
4282 /* Register sysfs hooks */
4283 group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group,
4286 return PTR_ERR(group);
4288 data->groups[num_attr_groups++] = group;
4290 group = nct6775_create_attr_group(dev, &nct6775_in_template_group,
4291 fls(data->have_in));
4293 return PTR_ERR(group);
4295 data->groups[num_attr_groups++] = group;
4297 group = nct6775_create_attr_group(dev, &nct6775_fan_template_group,
4298 fls(data->has_fan));
4300 return PTR_ERR(group);
4302 data->groups[num_attr_groups++] = group;
4304 group = nct6775_create_attr_group(dev, &nct6775_temp_template_group,
4305 fls(data->have_temp));
4307 return PTR_ERR(group);
4309 data->groups[num_attr_groups++] = group;
4310 data->groups[num_attr_groups++] = &nct6775_group_other;
4312 hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name,
4313 data, data->groups);
4314 return PTR_ERR_OR_ZERO(hwmon_dev);
4317 static void nct6791_enable_io_mapping(int sioaddr)
4321 val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE);
4323 pr_info("Enabling hardware monitor logical device mappings.\n");
4324 superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE,
4329 static int __maybe_unused nct6775_suspend(struct device *dev)
4331 struct nct6775_data *data = nct6775_update_device(dev);
4333 mutex_lock(&data->update_lock);
4334 data->vbat = nct6775_read_value(data, data->REG_VBAT);
4335 if (data->kind == nct6775) {
4336 data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1);
4337 data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2);
4339 mutex_unlock(&data->update_lock);
4344 static int __maybe_unused nct6775_resume(struct device *dev)
4346 struct nct6775_data *data = dev_get_drvdata(dev);
4347 int sioreg = data->sioreg;
4351 mutex_lock(&data->update_lock);
4352 data->bank = 0xff; /* Force initial bank selection */
4354 err = superio_enter(sioreg);
4358 superio_select(sioreg, NCT6775_LD_HWM);
4359 reg = superio_inb(sioreg, SIO_REG_ENABLE);
4360 if (reg != data->sio_reg_enable)
4361 superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable);
4363 if (data->kind == nct6791 || data->kind == nct6792 ||
4364 data->kind == nct6793 || data->kind == nct6795 ||
4365 data->kind == nct6796)
4366 nct6791_enable_io_mapping(sioreg);
4368 superio_exit(sioreg);
4370 /* Restore limits */
4371 for (i = 0; i < data->in_num; i++) {
4372 if (!(data->have_in & BIT(i)))
4375 nct6775_write_value(data, data->REG_IN_MINMAX[0][i],
4377 nct6775_write_value(data, data->REG_IN_MINMAX[1][i],
4381 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
4382 if (!(data->has_fan_min & BIT(i)))
4385 nct6775_write_value(data, data->REG_FAN_MIN[i],
4389 for (i = 0; i < NUM_TEMP; i++) {
4390 if (!(data->have_temp & BIT(i)))
4393 for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++)
4394 if (data->reg_temp[j][i])
4395 nct6775_write_temp(data, data->reg_temp[j][i],
4399 /* Restore other settings */
4400 nct6775_write_value(data, data->REG_VBAT, data->vbat);
4401 if (data->kind == nct6775) {
4402 nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
4403 nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
4407 /* Force re-reading all values */
4408 data->valid = false;
4409 mutex_unlock(&data->update_lock);
4414 static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume);
4416 static struct platform_driver nct6775_driver = {
4419 .pm = &nct6775_dev_pm_ops,
4421 .probe = nct6775_probe,
4424 /* nct6775_find() looks for a '627 in the Super-I/O config space */
4425 static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
4431 err = superio_enter(sioaddr);
4435 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) |
4436 superio_inb(sioaddr, SIO_REG_DEVID + 1);
4437 if (force_id && val != 0xffff)
4440 switch (val & SIO_ID_MASK) {
4441 case SIO_NCT6106_ID:
4442 sio_data->kind = nct6106;
4444 case SIO_NCT6775_ID:
4445 sio_data->kind = nct6775;
4447 case SIO_NCT6776_ID:
4448 sio_data->kind = nct6776;
4450 case SIO_NCT6779_ID:
4451 sio_data->kind = nct6779;
4453 case SIO_NCT6791_ID:
4454 sio_data->kind = nct6791;
4456 case SIO_NCT6792_ID:
4457 sio_data->kind = nct6792;
4459 case SIO_NCT6793_ID:
4460 sio_data->kind = nct6793;
4462 case SIO_NCT6795_ID:
4463 sio_data->kind = nct6795;
4465 case SIO_NCT6796_ID:
4466 sio_data->kind = nct6796;
4470 pr_debug("unsupported chip ID: 0x%04x\n", val);
4471 superio_exit(sioaddr);
4475 /* We have a known chip, find the HWM I/O address */
4476 superio_select(sioaddr, NCT6775_LD_HWM);
4477 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
4478 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
4479 addr = val & IOREGION_ALIGNMENT;
4481 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
4482 superio_exit(sioaddr);
4486 /* Activate logical device if needed */
4487 val = superio_inb(sioaddr, SIO_REG_ENABLE);
4488 if (!(val & 0x01)) {
4489 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
4490 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
4493 if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
4494 sio_data->kind == nct6793 || sio_data->kind == nct6795 ||
4495 sio_data->kind == nct6796)
4496 nct6791_enable_io_mapping(sioaddr);
4498 superio_exit(sioaddr);
4499 pr_info("Found %s or compatible chip at %#x:%#x\n",
4500 nct6775_sio_names[sio_data->kind], sioaddr, addr);
4501 sio_data->sioreg = sioaddr;
4507 * when Super-I/O functions move to a separate file, the Super-I/O
4508 * bus will manage the lifetime of the device and this module will only keep
4509 * track of the nct6775 driver. But since we use platform_device_alloc(), we
4510 * must keep track of the device
4512 static struct platform_device *pdev[2];
4514 static int __init sensors_nct6775_init(void)
4519 struct resource res;
4520 struct nct6775_sio_data sio_data;
4521 int sioaddr[2] = { 0x2e, 0x4e };
4523 err = platform_driver_register(&nct6775_driver);
4528 * initialize sio_data->kind and sio_data->sioreg.
4530 * when Super-I/O functions move to a separate file, the Super-I/O
4531 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
4532 * nct6775 hardware monitor, and call probe()
4534 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4535 address = nct6775_find(sioaddr[i], &sio_data);
4541 pdev[i] = platform_device_alloc(DRVNAME, address);
4544 goto exit_device_unregister;
4547 err = platform_device_add_data(pdev[i], &sio_data,
4548 sizeof(struct nct6775_sio_data));
4550 goto exit_device_put;
4552 memset(&res, 0, sizeof(res));
4554 res.start = address + IOREGION_OFFSET;
4555 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
4556 res.flags = IORESOURCE_IO;
4558 err = acpi_check_resource_conflict(&res);
4560 platform_device_put(pdev[i]);
4565 err = platform_device_add_resources(pdev[i], &res, 1);
4567 goto exit_device_put;
4569 /* platform_device_add calls probe() */
4570 err = platform_device_add(pdev[i]);
4572 goto exit_device_put;
4576 goto exit_unregister;
4582 platform_device_put(pdev[i]);
4583 exit_device_unregister:
4586 platform_device_unregister(pdev[i]);
4589 platform_driver_unregister(&nct6775_driver);
4593 static void __exit sensors_nct6775_exit(void)
4597 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4599 platform_device_unregister(pdev[i]);
4601 platform_driver_unregister(&nct6775_driver);
4604 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4605 MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips");
4606 MODULE_LICENSE("GPL");
4608 module_init(sensors_nct6775_init);
4609 module_exit(sensors_nct6775_exit);