2 * nct6775 - Driver for the hardware monitoring functionality of
3 * Nuvoton NCT677x Super-I/O chips
5 * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net>
7 * Derived from w83627ehf driver
8 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
9 * Copyright (C) 2006 Yuan Mu (Winbond),
10 * Rudolf Marek <r.marek@assembler.cz>
11 * David Hubbard <david.c.hubbard@gmail.com>
12 * Daniel J Blueman <daniel.blueman@gmail.com>
13 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
15 * Shamelessly ripped from the w83627hf driver
16 * Copyright (C) 2003 Mark Studebaker
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 * Supports the following chips:
35 * Chip #vin #fan #pwm #temp chip IDs man ID
36 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
37 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
38 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
39 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
40 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
41 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
42 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
43 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
44 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
46 * #temp lists the number of monitored temperature sources (first value) plus
47 * the number of directly connectable temperature sensors (second value).
50 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
52 #include <linux/module.h>
53 #include <linux/init.h>
54 #include <linux/slab.h>
55 #include <linux/jiffies.h>
56 #include <linux/platform_device.h>
57 #include <linux/hwmon.h>
58 #include <linux/hwmon-sysfs.h>
59 #include <linux/hwmon-vid.h>
60 #include <linux/err.h>
61 #include <linux/mutex.h>
62 #include <linux/acpi.h>
63 #include <linux/bitops.h>
64 #include <linux/dmi.h>
66 #include <linux/nospec.h>
71 enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
74 /* used to set data->name = nct6775_device_names[data->sio_kind] */
75 static const char * const nct6775_device_names[] = {
87 static const char * const nct6775_sio_names[] __initconst = {
99 static unsigned short force_id;
100 module_param(force_id, ushort, 0);
101 MODULE_PARM_DESC(force_id, "Override the detected device ID");
103 static unsigned short fan_debounce;
104 module_param(fan_debounce, ushort, 0);
105 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
107 #define DRVNAME "nct6775"
110 * Super-I/O constants and functions
113 #define NCT6775_LD_ACPI 0x0a
114 #define NCT6775_LD_HWM 0x0b
115 #define NCT6775_LD_VID 0x0d
116 #define NCT6775_LD_12 0x12
118 #define SIO_REG_LDSEL 0x07 /* Logical device select */
119 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
120 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
121 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
123 #define SIO_NCT6106_ID 0xc450
124 #define SIO_NCT6775_ID 0xb470
125 #define SIO_NCT6776_ID 0xc330
126 #define SIO_NCT6779_ID 0xc560
127 #define SIO_NCT6791_ID 0xc800
128 #define SIO_NCT6792_ID 0xc910
129 #define SIO_NCT6793_ID 0xd120
130 #define SIO_NCT6795_ID 0xd350
131 #define SIO_NCT6796_ID 0xd420
132 #define SIO_ID_MASK 0xFFF0
134 enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
137 superio_outb(int ioreg, int reg, int val)
140 outb(val, ioreg + 1);
144 superio_inb(int ioreg, int reg)
147 return inb(ioreg + 1);
151 superio_select(int ioreg, int ld)
153 outb(SIO_REG_LDSEL, ioreg);
158 superio_enter(int ioreg)
161 * Try to reserve <ioreg> and <ioreg + 1> for exclusive access.
163 if (!request_muxed_region(ioreg, 2, DRVNAME))
173 superio_exit(int ioreg)
177 outb(0x02, ioreg + 1);
178 release_region(ioreg, 2);
185 #define IOREGION_ALIGNMENT (~7)
186 #define IOREGION_OFFSET 5
187 #define IOREGION_LENGTH 2
188 #define ADDR_REG_OFFSET 0
189 #define DATA_REG_OFFSET 1
191 #define NCT6775_REG_BANK 0x4E
192 #define NCT6775_REG_CONFIG 0x40
195 * Not currently used:
196 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
197 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
198 * REG_MAN_ID is at port 0x4f
199 * REG_CHIP_ID is at port 0x58
202 #define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/
203 #define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */
205 #define NUM_REG_ALARM 7 /* Max number of alarm registers */
206 #define NUM_REG_BEEP 5 /* Max number of beep registers */
210 #define TEMP_SOURCE_VIRTUAL 0x1f
212 /* Common and NCT6775 specific data */
214 /* Voltage min/max registers for nr=7..14 are in bank 5 */
216 static const u16 NCT6775_REG_IN_MAX[] = {
217 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
218 0x55c, 0x55e, 0x560, 0x562 };
219 static const u16 NCT6775_REG_IN_MIN[] = {
220 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
221 0x55d, 0x55f, 0x561, 0x563 };
222 static const u16 NCT6775_REG_IN[] = {
223 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
226 #define NCT6775_REG_VBAT 0x5D
227 #define NCT6775_REG_DIODE 0x5E
228 #define NCT6775_DIODE_MASK 0x02
230 #define NCT6775_REG_FANDIV1 0x506
231 #define NCT6775_REG_FANDIV2 0x507
233 #define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0
235 static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
237 /* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */
239 static const s8 NCT6775_ALARM_BITS[] = {
240 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
241 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
243 6, 7, 11, -1, -1, /* fan1..fan5 */
244 -1, -1, -1, /* unused */
245 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
246 12, -1 }; /* intrusion0, intrusion1 */
248 #define FAN_ALARM_BASE 16
249 #define TEMP_ALARM_BASE 24
250 #define INTRUSION_ALARM_BASE 30
252 static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
255 * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures,
258 static const s8 NCT6775_BEEP_BITS[] = {
259 0, 1, 2, 3, 8, 9, 10, 16, /* in0.. in7 */
260 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
261 21, /* global beep enable */
262 6, 7, 11, 28, -1, /* fan1..fan5 */
263 -1, -1, -1, /* unused */
264 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
265 12, -1 }; /* intrusion0, intrusion1 */
267 #define BEEP_ENABLE_BASE 15
269 static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
270 static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
272 /* DC or PWM output fan configuration */
273 static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
274 static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
276 /* Advanced Fan control, some values are common for all fans */
278 static const u16 NCT6775_REG_TARGET[] = {
279 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01, 0xb01 };
280 static const u16 NCT6775_REG_FAN_MODE[] = {
281 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02, 0xb02 };
282 static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
283 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03, 0xb03 };
284 static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
285 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04, 0xb04 };
286 static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
287 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05, 0xb05 };
288 static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
289 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06, 0xb06 };
290 static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
291 static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
293 static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
294 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07, 0xb07 };
295 static const u16 NCT6775_REG_PWM[] = {
296 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09, 0xb09 };
297 static const u16 NCT6775_REG_PWM_READ[] = {
298 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09, 0xb09 };
300 static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
301 static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
302 static const u16 NCT6775_REG_FAN_PULSES[] = { 0x641, 0x642, 0x643, 0x644, 0 };
303 static const u16 NCT6775_FAN_PULSE_SHIFT[] = { 0, 0, 0, 0, 0, 0 };
305 static const u16 NCT6775_REG_TEMP[] = {
306 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
308 static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
310 static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
311 0, 0x152, 0x252, 0x628, 0x629, 0x62A };
312 static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
313 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
314 static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
315 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
317 static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
318 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
320 static const u16 NCT6775_REG_TEMP_SEL[] = {
321 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00, 0xb00 };
323 static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
324 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
325 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
326 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
327 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
328 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
329 static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
330 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
331 static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
332 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
334 static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
336 static const u16 NCT6775_REG_AUTO_TEMP[] = {
337 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21, 0xb21 };
338 static const u16 NCT6775_REG_AUTO_PWM[] = {
339 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27, 0xb27 };
341 #define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p))
342 #define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p))
344 static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
346 static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
347 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35, 0xb35 };
348 static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
349 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38, 0xb38 };
351 static const char *const nct6775_temp_label[] = {
365 "PCH_CHIP_CPU_MAX_TEMP",
375 #define NCT6775_TEMP_MASK 0x001ffffe
377 static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
383 static const u16 NCT6775_REG_TEMP_CRIT[32] = {
394 /* NCT6776 specific data */
396 /* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */
397 #define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
398 #define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
400 static const s8 NCT6776_ALARM_BITS[] = {
401 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
402 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
404 6, 7, 11, 10, 23, /* fan1..fan5 */
405 -1, -1, -1, /* unused */
406 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
407 12, 9 }; /* intrusion0, intrusion1 */
409 static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
411 static const s8 NCT6776_BEEP_BITS[] = {
412 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
413 8, -1, -1, -1, -1, -1, -1, /* in8..in14 */
414 24, /* global beep enable */
415 25, 26, 27, 28, 29, /* fan1..fan5 */
416 -1, -1, -1, /* unused */
417 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
418 30, 31 }; /* intrusion0, intrusion1 */
420 static const u16 NCT6776_REG_TOLERANCE_H[] = {
421 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c, 0xb0c };
423 static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
424 static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
426 static const u16 NCT6776_REG_FAN_MIN[] = {
427 0x63a, 0x63c, 0x63e, 0x640, 0x642, 0x64a, 0x64c };
428 static const u16 NCT6776_REG_FAN_PULSES[] = {
429 0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0 };
431 static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
432 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
434 static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
435 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
437 static const char *const nct6776_temp_label[] = {
452 "PCH_CHIP_CPU_MAX_TEMP",
463 #define NCT6776_TEMP_MASK 0x007ffffe
465 static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
471 static const u16 NCT6776_REG_TEMP_CRIT[32] = {
476 /* NCT6779 specific data */
478 static const u16 NCT6779_REG_IN[] = {
479 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
480 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
482 static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
483 0x459, 0x45A, 0x45B, 0x568 };
485 static const s8 NCT6779_ALARM_BITS[] = {
486 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
487 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
489 6, 7, 11, 10, 23, /* fan1..fan5 */
490 -1, -1, -1, /* unused */
491 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
492 12, 9 }; /* intrusion0, intrusion1 */
494 static const s8 NCT6779_BEEP_BITS[] = {
495 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
496 8, 9, 10, 11, 12, 13, 14, /* in8..in14 */
497 24, /* global beep enable */
498 25, 26, 27, 28, 29, /* fan1..fan5 */
499 -1, -1, -1, /* unused */
500 16, 17, -1, -1, -1, -1, /* temp1..temp6 */
501 30, 31 }; /* intrusion0, intrusion1 */
503 static const u16 NCT6779_REG_FAN[] = {
504 0x4b0, 0x4b2, 0x4b4, 0x4b6, 0x4b8, 0x4ba, 0x660 };
505 static const u16 NCT6779_REG_FAN_PULSES[] = {
506 0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0 };
508 static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
509 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36, 0xb36 };
510 #define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01
511 static const u16 NCT6779_REG_CRITICAL_PWM[] = {
512 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37, 0xb37 };
514 static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
515 static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
516 static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
518 static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
520 static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
523 static const u16 NCT6779_REG_TEMP_OFFSET[] = {
524 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
526 static const char *const nct6779_temp_label[] = {
545 "PCH_CHIP_CPU_MAX_TEMP",
561 #define NCT6779_TEMP_MASK 0x07ffff7e
562 #define NCT6791_TEMP_MASK 0x87ffff7e
564 static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
565 = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
566 0, 0, 0, 0, 0, 0, 0, 0,
567 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
570 static const u16 NCT6779_REG_TEMP_CRIT[32] = {
575 /* NCT6791 specific data */
577 #define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
579 static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[NUM_FAN] = { 0, 0x239 };
580 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[NUM_FAN] = { 0, 0x23a };
581 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[NUM_FAN] = { 0, 0x23b };
582 static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[NUM_FAN] = { 0, 0x23c };
583 static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[NUM_FAN] = { 0, 0x23d };
584 static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[NUM_FAN] = { 0, 0x23e };
586 static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
587 0x459, 0x45A, 0x45B, 0x568, 0x45D };
589 static const s8 NCT6791_ALARM_BITS[] = {
590 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
591 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
593 6, 7, 11, 10, 23, 33, /* fan1..fan6 */
595 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
596 12, 9 }; /* intrusion0, intrusion1 */
598 /* NCT6792/NCT6793 specific data */
600 static const u16 NCT6792_REG_TEMP_MON[] = {
601 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
602 static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
603 0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
605 static const char *const nct6792_temp_label[] = {
624 "PCH_CHIP_CPU_MAX_TEMP",
633 "PECI Agent 0 Calibration",
634 "PECI Agent 1 Calibration",
640 #define NCT6792_TEMP_MASK 0x9fffff7e
642 static const char *const nct6793_temp_label[] = {
661 "PCH_CHIP_CPU_MAX_TEMP",
671 "PECI Agent 0 Calibration",
672 "PECI Agent 1 Calibration",
677 #define NCT6793_TEMP_MASK 0xbfff037e
679 static const char *const nct6795_temp_label[] = {
698 "PCH_CHIP_CPU_MAX_TEMP",
708 "PECI Agent 0 Calibration",
709 "PECI Agent 1 Calibration",
714 #define NCT6795_TEMP_MASK 0xbfffff7e
716 static const char *const nct6796_temp_label[] = {
735 "PCH_CHIP_CPU_MAX_TEMP",
745 "PECI Agent 0 Calibration",
746 "PECI Agent 1 Calibration",
751 #define NCT6796_TEMP_MASK 0xbfff03fe
753 /* NCT6102D/NCT6106D specific data */
755 #define NCT6106_REG_VBAT 0x318
756 #define NCT6106_REG_DIODE 0x319
757 #define NCT6106_DIODE_MASK 0x01
759 static const u16 NCT6106_REG_IN_MAX[] = {
760 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
761 static const u16 NCT6106_REG_IN_MIN[] = {
762 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
763 static const u16 NCT6106_REG_IN[] = {
764 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
766 static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
767 static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
768 static const u16 NCT6106_REG_TEMP_HYST[] = {
769 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
770 static const u16 NCT6106_REG_TEMP_OVER[] = {
771 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
772 static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
773 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
774 static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
775 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
776 static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
777 static const u16 NCT6106_REG_TEMP_CONFIG[] = {
778 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
780 static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
781 static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
782 static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6, 0, 0 };
783 static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4, 0, 0 };
785 static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
786 static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
787 static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
788 static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
789 static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
790 static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
791 static const u16 NCT6106_REG_TEMP_SOURCE[] = {
792 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
794 static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
795 static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
796 0x11b, 0x12b, 0x13b };
798 static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
799 #define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10
800 static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
802 static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
803 static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
804 static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
805 static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
806 static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
807 static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
809 static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
811 static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
812 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
813 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
814 static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x17c };
815 static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
816 static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
818 static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
819 static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
821 static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
822 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
824 static const s8 NCT6106_ALARM_BITS[] = {
825 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
826 9, -1, -1, -1, -1, -1, -1, /* in8..in14 */
828 32, 33, 34, -1, -1, /* fan1..fan5 */
829 -1, -1, -1, /* unused */
830 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
831 48, -1 /* intrusion0, intrusion1 */
834 static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
835 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
837 static const s8 NCT6106_BEEP_BITS[] = {
838 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
839 9, 10, 11, 12, -1, -1, -1, /* in8..in14 */
840 32, /* global beep enable */
841 24, 25, 26, 27, 28, /* fan1..fan5 */
842 -1, -1, -1, /* unused */
843 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
844 34, -1 /* intrusion0, intrusion1 */
847 static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
853 static const u16 NCT6106_REG_TEMP_CRIT[32] = {
858 static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
860 if (mode == 0 && pwm == 255)
865 static int pwm_enable_to_reg(enum pwm_enable mode)
876 /* 1 is DC mode, output in ms */
877 static unsigned int step_time_from_reg(u8 reg, u8 mode)
879 return mode ? 400 * reg : 100 * reg;
882 static u8 step_time_to_reg(unsigned int msec, u8 mode)
884 return clamp_val((mode ? (msec + 200) / 400 :
885 (msec + 50) / 100), 1, 255);
888 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
890 if (reg == 0 || reg == 255)
892 return 1350000U / (reg << divreg);
895 static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
897 if ((reg & 0xff1f) == 0xff1f)
900 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
905 return 1350000U / reg;
908 static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
910 if (reg == 0 || reg == 0xffff)
914 * Even though the registers are 16 bit wide, the fan divisor
917 return 1350000U / (reg << divreg);
920 static u16 fan_to_reg(u32 fan, unsigned int divreg)
925 return (1350000U / fan) >> divreg;
928 static inline unsigned int
935 * Some of the voltage inputs have internal scaling, the tables below
936 * contain 8 (the ADC LSB in mV) * scaling factor * 100
938 static const u16 scale_in[15] = {
939 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
943 static inline long in_from_reg(u8 reg, u8 nr)
945 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
948 static inline u8 in_to_reg(u32 val, u8 nr)
950 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
954 * Data structures and manipulation thereof
957 struct nct6775_data {
958 int addr; /* IO base of hw monitor block */
959 int sioreg; /* SIO register address */
963 const struct attribute_group *groups[6];
965 u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
966 * 3=temp_crit, 4=temp_lcrit
968 u8 temp_src[NUM_TEMP];
969 u16 reg_temp_config[NUM_TEMP];
970 const char * const *temp_label;
978 const s8 *ALARM_BITS;
982 const u16 *REG_IN_MINMAX[2];
984 const u16 *REG_TARGET;
986 const u16 *REG_FAN_MODE;
987 const u16 *REG_FAN_MIN;
988 const u16 *REG_FAN_PULSES;
989 const u16 *FAN_PULSE_SHIFT;
990 const u16 *REG_FAN_TIME[3];
992 const u16 *REG_TOLERANCE_H;
994 const u8 *REG_PWM_MODE;
995 const u8 *PWM_MODE_MASK;
997 const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
998 * [3]=pwm_max, [4]=pwm_step,
999 * [5]=weight_duty_step, [6]=weight_duty_base
1001 const u16 *REG_PWM_READ;
1003 const u16 *REG_CRITICAL_PWM_ENABLE;
1004 u8 CRITICAL_PWM_ENABLE_MASK;
1005 const u16 *REG_CRITICAL_PWM;
1007 const u16 *REG_AUTO_TEMP;
1008 const u16 *REG_AUTO_PWM;
1010 const u16 *REG_CRITICAL_TEMP;
1011 const u16 *REG_CRITICAL_TEMP_TOLERANCE;
1013 const u16 *REG_TEMP_SOURCE; /* temp register sources */
1014 const u16 *REG_TEMP_SEL;
1015 const u16 *REG_WEIGHT_TEMP_SEL;
1016 const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */
1018 const u16 *REG_TEMP_OFFSET;
1020 const u16 *REG_ALARM;
1021 const u16 *REG_BEEP;
1023 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
1024 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
1026 struct mutex update_lock;
1027 bool valid; /* true if following fields are valid */
1028 unsigned long last_updated; /* In jiffies */
1030 /* Register values */
1031 u8 bank; /* current register bank */
1032 u8 in_num; /* number of in inputs we have */
1033 u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */
1034 unsigned int rpm[NUM_FAN];
1035 u16 fan_min[NUM_FAN];
1036 u8 fan_pulses[NUM_FAN];
1037 u8 fan_div[NUM_FAN];
1039 u8 has_fan; /* some fan inputs can be disabled */
1040 u8 has_fan_min; /* some fans don't have min register */
1043 u8 num_temp_alarms; /* 2, 3, or 6 */
1044 u8 num_temp_beeps; /* 2, 3, or 6 */
1045 u8 temp_fixed_num; /* 3 or 6 */
1046 u8 temp_type[NUM_TEMP_FIXED];
1047 s8 temp_offset[NUM_TEMP_FIXED];
1048 s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1049 * 3=temp_crit, 4=temp_lcrit */
1053 u8 pwm_num; /* number of pwm */
1054 u8 pwm_mode[NUM_FAN]; /* 0->DC variable voltage,
1055 * 1->PWM variable duty cycle
1057 enum pwm_enable pwm_enable[NUM_FAN];
1060 * 2->thermal cruise mode (also called SmartFan I)
1061 * 3->fan speed cruise mode
1063 * 5->enhanced variable thermal cruise (SmartFan IV)
1065 u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1066 * [3]=pwm_max, [4]=pwm_step,
1067 * [5]=weight_duty_step, [6]=weight_duty_base
1070 u8 target_temp[NUM_FAN];
1071 u8 target_temp_mask;
1072 u32 target_speed[NUM_FAN];
1073 u32 target_speed_tolerance[NUM_FAN];
1074 u8 speed_tolerance_limit;
1076 u8 temp_tolerance[2][NUM_FAN];
1079 u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
1081 /* Automatic fan speed control registers */
1083 u8 auto_pwm[NUM_FAN][7];
1084 u8 auto_temp[NUM_FAN][7];
1085 u8 pwm_temp_sel[NUM_FAN];
1086 u8 pwm_weight_temp_sel[NUM_FAN];
1087 u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol,
1097 u16 have_temp_fixed;
1100 /* Remember extra register values over suspend/resume */
1107 struct nct6775_sio_data {
1112 struct sensor_device_template {
1113 struct device_attribute dev_attr;
1121 bool s2; /* true if both index and nr are used */
1124 struct sensor_device_attr_u {
1126 struct sensor_device_attribute a1;
1127 struct sensor_device_attribute_2 a2;
1132 #define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \
1133 .attr = {.name = _template, .mode = _mode }, \
1138 #define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1139 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1140 .u.index = _index, \
1143 #define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1145 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1146 .u.s.index = _index, \
1150 #define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1151 static struct sensor_device_template sensor_dev_template_##_name \
1152 = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \
1155 #define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \
1157 static struct sensor_device_template sensor_dev_template_##_name \
1158 = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1161 struct sensor_template_group {
1162 struct sensor_device_template **templates;
1163 umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1167 static struct attribute_group *
1168 nct6775_create_attr_group(struct device *dev,
1169 const struct sensor_template_group *tg,
1172 struct attribute_group *group;
1173 struct sensor_device_attr_u *su;
1174 struct sensor_device_attribute *a;
1175 struct sensor_device_attribute_2 *a2;
1176 struct attribute **attrs;
1177 struct sensor_device_template **t;
1181 return ERR_PTR(-EINVAL);
1184 for (count = 0; *t; t++, count++)
1188 return ERR_PTR(-EINVAL);
1190 group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1192 return ERR_PTR(-ENOMEM);
1194 attrs = devm_kcalloc(dev, repeat * count + 1, sizeof(*attrs),
1197 return ERR_PTR(-ENOMEM);
1199 su = devm_kzalloc(dev, array3_size(repeat, count, sizeof(*su)),
1202 return ERR_PTR(-ENOMEM);
1204 group->attrs = attrs;
1205 group->is_visible = tg->is_visible;
1207 for (i = 0; i < repeat; i++) {
1209 while (*t != NULL) {
1210 snprintf(su->name, sizeof(su->name),
1211 (*t)->dev_attr.attr.name, tg->base + i);
1214 sysfs_attr_init(&a2->dev_attr.attr);
1215 a2->dev_attr.attr.name = su->name;
1216 a2->nr = (*t)->u.s.nr + i;
1217 a2->index = (*t)->u.s.index;
1218 a2->dev_attr.attr.mode =
1219 (*t)->dev_attr.attr.mode;
1220 a2->dev_attr.show = (*t)->dev_attr.show;
1221 a2->dev_attr.store = (*t)->dev_attr.store;
1222 *attrs = &a2->dev_attr.attr;
1225 sysfs_attr_init(&a->dev_attr.attr);
1226 a->dev_attr.attr.name = su->name;
1227 a->index = (*t)->u.index + i;
1228 a->dev_attr.attr.mode =
1229 (*t)->dev_attr.attr.mode;
1230 a->dev_attr.show = (*t)->dev_attr.show;
1231 a->dev_attr.store = (*t)->dev_attr.store;
1232 *attrs = &a->dev_attr.attr;
1243 static bool is_word_sized(struct nct6775_data *data, u16 reg)
1245 switch (data->kind) {
1247 return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1248 reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1249 reg == 0x111 || reg == 0x121 || reg == 0x131;
1251 return (((reg & 0xff00) == 0x100 ||
1252 (reg & 0xff00) == 0x200) &&
1253 ((reg & 0x00ff) == 0x50 ||
1254 (reg & 0x00ff) == 0x53 ||
1255 (reg & 0x00ff) == 0x55)) ||
1256 (reg & 0xfff0) == 0x630 ||
1257 reg == 0x640 || reg == 0x642 ||
1259 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1260 reg == 0x73 || reg == 0x75 || reg == 0x77;
1262 return (((reg & 0xff00) == 0x100 ||
1263 (reg & 0xff00) == 0x200) &&
1264 ((reg & 0x00ff) == 0x50 ||
1265 (reg & 0x00ff) == 0x53 ||
1266 (reg & 0x00ff) == 0x55)) ||
1267 (reg & 0xfff0) == 0x630 ||
1269 reg == 0x640 || reg == 0x642 ||
1270 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1271 reg == 0x73 || reg == 0x75 || reg == 0x77;
1278 return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
1279 ((reg & 0xfff0) == 0x4b0 && (reg & 0x000f) < 0x0b) ||
1281 reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1282 reg == 0x640 || reg == 0x642 || reg == 0x64a ||
1283 reg == 0x64c || reg == 0x660 ||
1284 reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
1285 reg == 0x7b || reg == 0x7d;
1291 * On older chips, only registers 0x50-0x5f are banked.
1292 * On more recent chips, all registers are banked.
1293 * Assume that is the case and set the bank number for each access.
1294 * Cache the bank number so it only needs to be set if it changes.
1296 static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1300 if (data->bank != bank) {
1301 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1302 outb_p(bank, data->addr + DATA_REG_OFFSET);
1307 static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1309 int res, word_sized = is_word_sized(data, reg);
1311 nct6775_set_bank(data, reg);
1312 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1313 res = inb_p(data->addr + DATA_REG_OFFSET);
1315 outb_p((reg & 0xff) + 1,
1316 data->addr + ADDR_REG_OFFSET);
1317 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1322 static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1324 int word_sized = is_word_sized(data, reg);
1326 nct6775_set_bank(data, reg);
1327 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1329 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1330 outb_p((reg & 0xff) + 1,
1331 data->addr + ADDR_REG_OFFSET);
1333 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
1337 /* We left-align 8-bit temperature values to make the code simpler */
1338 static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1342 res = nct6775_read_value(data, reg);
1343 if (!is_word_sized(data, reg))
1349 static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1351 if (!is_word_sized(data, reg))
1353 return nct6775_write_value(data, reg, value);
1356 /* This function assumes that the caller holds data->update_lock */
1357 static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1363 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1364 | (data->fan_div[0] & 0x7);
1365 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1368 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1369 | ((data->fan_div[1] << 4) & 0x70);
1370 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1373 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1374 | (data->fan_div[2] & 0x7);
1375 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1378 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1379 | ((data->fan_div[3] << 4) & 0x70);
1380 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1385 static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1387 if (data->kind == nct6775)
1388 nct6775_write_fan_div(data, nr);
1391 static void nct6775_update_fan_div(struct nct6775_data *data)
1395 i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1396 data->fan_div[0] = i & 0x7;
1397 data->fan_div[1] = (i & 0x70) >> 4;
1398 i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1399 data->fan_div[2] = i & 0x7;
1400 if (data->has_fan & BIT(3))
1401 data->fan_div[3] = (i & 0x70) >> 4;
1404 static void nct6775_update_fan_div_common(struct nct6775_data *data)
1406 if (data->kind == nct6775)
1407 nct6775_update_fan_div(data);
1410 static void nct6775_init_fan_div(struct nct6775_data *data)
1414 nct6775_update_fan_div_common(data);
1416 * For all fans, start with highest divider value if the divider
1417 * register is not initialized. This ensures that we get a
1418 * reading from the fan count register, even if it is not optimal.
1419 * We'll compute a better divider later on.
1421 for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
1422 if (!(data->has_fan & BIT(i)))
1424 if (data->fan_div[i] == 0) {
1425 data->fan_div[i] = 7;
1426 nct6775_write_fan_div_common(data, i);
1431 static void nct6775_init_fan_common(struct device *dev,
1432 struct nct6775_data *data)
1437 if (data->has_fan_div)
1438 nct6775_init_fan_div(data);
1441 * If fan_min is not set (0), set it to 0xff to disable it. This
1442 * prevents the unnecessary warning when fanX_min is reported as 0.
1444 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
1445 if (data->has_fan_min & BIT(i)) {
1446 reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1448 nct6775_write_value(data, data->REG_FAN_MIN[i],
1449 data->has_fan_div ? 0xff
1455 static void nct6775_select_fan_div(struct device *dev,
1456 struct nct6775_data *data, int nr, u16 reg)
1458 u8 fan_div = data->fan_div[nr];
1461 if (!data->has_fan_div)
1465 * If we failed to measure the fan speed, or the reported value is not
1466 * in the optimal range, and the clock divider can be modified,
1467 * let's try that for next time.
1469 if (reg == 0x00 && fan_div < 0x07)
1471 else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1474 if (fan_div != data->fan_div[nr]) {
1475 dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1476 nr + 1, div_from_reg(data->fan_div[nr]),
1477 div_from_reg(fan_div));
1479 /* Preserve min limit if possible */
1480 if (data->has_fan_min & BIT(nr)) {
1481 fan_min = data->fan_min[nr];
1482 if (fan_div > data->fan_div[nr]) {
1483 if (fan_min != 255 && fan_min > 1)
1486 if (fan_min != 255) {
1492 if (fan_min != data->fan_min[nr]) {
1493 data->fan_min[nr] = fan_min;
1494 nct6775_write_value(data, data->REG_FAN_MIN[nr],
1498 data->fan_div[nr] = fan_div;
1499 nct6775_write_fan_div_common(data, nr);
1503 static void nct6775_update_pwm(struct device *dev)
1505 struct nct6775_data *data = dev_get_drvdata(dev);
1507 int fanmodecfg, reg;
1510 for (i = 0; i < data->pwm_num; i++) {
1511 if (!(data->has_pwm & BIT(i)))
1514 duty_is_dc = data->REG_PWM_MODE[i] &&
1515 (nct6775_read_value(data, data->REG_PWM_MODE[i])
1516 & data->PWM_MODE_MASK[i]);
1517 data->pwm_mode[i] = !duty_is_dc;
1519 fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1520 for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1521 if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1523 = nct6775_read_value(data,
1524 data->REG_PWM[j][i]);
1528 data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1529 (fanmodecfg >> 4) & 7);
1531 if (!data->temp_tolerance[0][i] ||
1532 data->pwm_enable[i] != speed_cruise)
1533 data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1534 if (!data->target_speed_tolerance[i] ||
1535 data->pwm_enable[i] == speed_cruise) {
1536 u8 t = fanmodecfg & 0x0f;
1538 if (data->REG_TOLERANCE_H) {
1539 t |= (nct6775_read_value(data,
1540 data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1542 data->target_speed_tolerance[i] = t;
1545 data->temp_tolerance[1][i] =
1546 nct6775_read_value(data,
1547 data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1549 reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1550 data->pwm_temp_sel[i] = reg & 0x1f;
1551 /* If fan can stop, report floor as 0 */
1553 data->pwm[2][i] = 0;
1555 if (!data->REG_WEIGHT_TEMP_SEL[i])
1558 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1559 data->pwm_weight_temp_sel[i] = reg & 0x1f;
1560 /* If weight is disabled, report weight source as 0 */
1561 if (j == 1 && !(reg & 0x80))
1562 data->pwm_weight_temp_sel[i] = 0;
1564 /* Weight temp data */
1565 for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
1566 data->weight_temp[j][i]
1567 = nct6775_read_value(data,
1568 data->REG_WEIGHT_TEMP[j][i]);
1573 static void nct6775_update_pwm_limits(struct device *dev)
1575 struct nct6775_data *data = dev_get_drvdata(dev);
1580 for (i = 0; i < data->pwm_num; i++) {
1581 if (!(data->has_pwm & BIT(i)))
1584 for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
1585 data->fan_time[j][i] =
1586 nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1589 reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1590 /* Update only in matching mode or if never updated */
1591 if (!data->target_temp[i] ||
1592 data->pwm_enable[i] == thermal_cruise)
1593 data->target_temp[i] = reg_t & data->target_temp_mask;
1594 if (!data->target_speed[i] ||
1595 data->pwm_enable[i] == speed_cruise) {
1596 if (data->REG_TOLERANCE_H) {
1597 reg_t |= (nct6775_read_value(data,
1598 data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1600 data->target_speed[i] = reg_t;
1603 for (j = 0; j < data->auto_pwm_num; j++) {
1604 data->auto_pwm[i][j] =
1605 nct6775_read_value(data,
1606 NCT6775_AUTO_PWM(data, i, j));
1607 data->auto_temp[i][j] =
1608 nct6775_read_value(data,
1609 NCT6775_AUTO_TEMP(data, i, j));
1612 /* critical auto_pwm temperature data */
1613 data->auto_temp[i][data->auto_pwm_num] =
1614 nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1616 switch (data->kind) {
1618 reg = nct6775_read_value(data,
1619 NCT6775_REG_CRITICAL_ENAB[i]);
1620 data->auto_pwm[i][data->auto_pwm_num] =
1621 (reg & 0x02) ? 0xff : 0x00;
1624 data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1633 reg = nct6775_read_value(data,
1634 data->REG_CRITICAL_PWM_ENABLE[i]);
1635 if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1636 reg = nct6775_read_value(data,
1637 data->REG_CRITICAL_PWM[i]);
1640 data->auto_pwm[i][data->auto_pwm_num] = reg;
1646 static struct nct6775_data *nct6775_update_device(struct device *dev)
1648 struct nct6775_data *data = dev_get_drvdata(dev);
1651 mutex_lock(&data->update_lock);
1653 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1655 /* Fan clock dividers */
1656 nct6775_update_fan_div_common(data);
1658 /* Measured voltages and limits */
1659 for (i = 0; i < data->in_num; i++) {
1660 if (!(data->have_in & BIT(i)))
1663 data->in[i][0] = nct6775_read_value(data,
1665 data->in[i][1] = nct6775_read_value(data,
1666 data->REG_IN_MINMAX[0][i]);
1667 data->in[i][2] = nct6775_read_value(data,
1668 data->REG_IN_MINMAX[1][i]);
1671 /* Measured fan speeds and limits */
1672 for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1675 if (!(data->has_fan & BIT(i)))
1678 reg = nct6775_read_value(data, data->REG_FAN[i]);
1679 data->rpm[i] = data->fan_from_reg(reg,
1682 if (data->has_fan_min & BIT(i))
1683 data->fan_min[i] = nct6775_read_value(data,
1684 data->REG_FAN_MIN[i]);
1685 data->fan_pulses[i] =
1686 (nct6775_read_value(data, data->REG_FAN_PULSES[i])
1687 >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1689 nct6775_select_fan_div(dev, data, i, reg);
1692 nct6775_update_pwm(dev);
1693 nct6775_update_pwm_limits(dev);
1695 /* Measured temperatures and limits */
1696 for (i = 0; i < NUM_TEMP; i++) {
1697 if (!(data->have_temp & BIT(i)))
1699 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1700 if (data->reg_temp[j][i])
1702 = nct6775_read_temp(data,
1703 data->reg_temp[j][i]);
1705 if (i >= NUM_TEMP_FIXED ||
1706 !(data->have_temp_fixed & BIT(i)))
1708 data->temp_offset[i]
1709 = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1713 for (i = 0; i < NUM_REG_ALARM; i++) {
1716 if (!data->REG_ALARM[i])
1718 alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1719 data->alarms |= ((u64)alarm) << (i << 3);
1723 for (i = 0; i < NUM_REG_BEEP; i++) {
1726 if (!data->REG_BEEP[i])
1728 beep = nct6775_read_value(data, data->REG_BEEP[i]);
1729 data->beeps |= ((u64)beep) << (i << 3);
1732 data->last_updated = jiffies;
1736 mutex_unlock(&data->update_lock);
1741 * Sysfs callback functions
1744 show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1746 struct nct6775_data *data = nct6775_update_device(dev);
1747 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1748 int index = sattr->index;
1751 return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1755 store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1758 struct nct6775_data *data = dev_get_drvdata(dev);
1759 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1760 int index = sattr->index;
1765 err = kstrtoul(buf, 10, &val);
1768 mutex_lock(&data->update_lock);
1769 data->in[nr][index] = in_to_reg(val, nr);
1770 nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
1771 data->in[nr][index]);
1772 mutex_unlock(&data->update_lock);
1777 show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1779 struct nct6775_data *data = nct6775_update_device(dev);
1780 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1781 int nr = data->ALARM_BITS[sattr->index];
1783 return sprintf(buf, "%u\n",
1784 (unsigned int)((data->alarms >> nr) & 0x01));
1787 static int find_temp_source(struct nct6775_data *data, int index, int count)
1789 int source = data->temp_src[index];
1792 for (nr = 0; nr < count; nr++) {
1795 src = nct6775_read_value(data,
1796 data->REG_TEMP_SOURCE[nr]) & 0x1f;
1804 show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1806 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1807 struct nct6775_data *data = nct6775_update_device(dev);
1808 unsigned int alarm = 0;
1812 * For temperatures, there is no fixed mapping from registers to alarm
1813 * bits. Alarm bits are determined by the temperature source mapping.
1815 nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1817 int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
1819 alarm = (data->alarms >> bit) & 0x01;
1821 return sprintf(buf, "%u\n", alarm);
1825 show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1827 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1828 struct nct6775_data *data = nct6775_update_device(dev);
1829 int nr = data->BEEP_BITS[sattr->index];
1831 return sprintf(buf, "%u\n",
1832 (unsigned int)((data->beeps >> nr) & 0x01));
1836 store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1839 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1840 struct nct6775_data *data = dev_get_drvdata(dev);
1841 int nr = data->BEEP_BITS[sattr->index];
1842 int regindex = nr >> 3;
1846 err = kstrtoul(buf, 10, &val);
1852 mutex_lock(&data->update_lock);
1854 data->beeps |= (1ULL << nr);
1856 data->beeps &= ~(1ULL << nr);
1857 nct6775_write_value(data, data->REG_BEEP[regindex],
1858 (data->beeps >> (regindex << 3)) & 0xff);
1859 mutex_unlock(&data->update_lock);
1864 show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1866 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1867 struct nct6775_data *data = nct6775_update_device(dev);
1868 unsigned int beep = 0;
1872 * For temperatures, there is no fixed mapping from registers to beep
1873 * enable bits. Beep enable bits are determined by the temperature
1876 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1878 int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1880 beep = (data->beeps >> bit) & 0x01;
1882 return sprintf(buf, "%u\n", beep);
1886 store_temp_beep(struct device *dev, struct device_attribute *attr,
1887 const char *buf, size_t count)
1889 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1890 struct nct6775_data *data = dev_get_drvdata(dev);
1891 int nr, bit, regindex;
1895 err = kstrtoul(buf, 10, &val);
1901 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1905 bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1906 regindex = bit >> 3;
1908 mutex_lock(&data->update_lock);
1910 data->beeps |= (1ULL << bit);
1912 data->beeps &= ~(1ULL << bit);
1913 nct6775_write_value(data, data->REG_BEEP[regindex],
1914 (data->beeps >> (regindex << 3)) & 0xff);
1915 mutex_unlock(&data->update_lock);
1920 static umode_t nct6775_in_is_visible(struct kobject *kobj,
1921 struct attribute *attr, int index)
1923 struct device *dev = container_of(kobj, struct device, kobj);
1924 struct nct6775_data *data = dev_get_drvdata(dev);
1925 int in = index / 5; /* voltage index */
1927 if (!(data->have_in & BIT(in)))
1933 SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
1934 SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
1935 SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
1937 SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
1938 store_in_reg, 0, 1);
1939 SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
1940 store_in_reg, 0, 2);
1943 * nct6775_in_is_visible uses the index into the following array
1944 * to determine if attributes should be created or not.
1945 * Any change in order or content must be matched.
1947 static struct sensor_device_template *nct6775_attributes_in_template[] = {
1948 &sensor_dev_template_in_input,
1949 &sensor_dev_template_in_alarm,
1950 &sensor_dev_template_in_beep,
1951 &sensor_dev_template_in_min,
1952 &sensor_dev_template_in_max,
1956 static const struct sensor_template_group nct6775_in_template_group = {
1957 .templates = nct6775_attributes_in_template,
1958 .is_visible = nct6775_in_is_visible,
1962 show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1964 struct nct6775_data *data = nct6775_update_device(dev);
1965 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1966 int nr = sattr->index;
1968 return sprintf(buf, "%d\n", data->rpm[nr]);
1972 show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1974 struct nct6775_data *data = nct6775_update_device(dev);
1975 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1976 int nr = sattr->index;
1978 return sprintf(buf, "%d\n",
1979 data->fan_from_reg_min(data->fan_min[nr],
1980 data->fan_div[nr]));
1984 show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
1986 struct nct6775_data *data = nct6775_update_device(dev);
1987 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1988 int nr = sattr->index;
1990 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
1994 store_fan_min(struct device *dev, struct device_attribute *attr,
1995 const char *buf, size_t count)
1997 struct nct6775_data *data = dev_get_drvdata(dev);
1998 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1999 int nr = sattr->index;
2005 err = kstrtoul(buf, 10, &val);
2009 mutex_lock(&data->update_lock);
2010 if (!data->has_fan_div) {
2011 /* NCT6776F or NCT6779D; we know this is a 13 bit register */
2017 val = 1350000U / val;
2018 val = (val & 0x1f) | ((val << 3) & 0xff00);
2020 data->fan_min[nr] = val;
2021 goto write_min; /* Leave fan divider alone */
2024 /* No min limit, alarm disabled */
2025 data->fan_min[nr] = 255;
2026 new_div = data->fan_div[nr]; /* No change */
2027 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
2030 reg = 1350000U / val;
2031 if (reg >= 128 * 255) {
2033 * Speed below this value cannot possibly be represented,
2034 * even with the highest divider (128)
2036 data->fan_min[nr] = 254;
2037 new_div = 7; /* 128 == BIT(7) */
2039 "fan%u low limit %lu below minimum %u, set to minimum\n",
2040 nr + 1, val, data->fan_from_reg_min(254, 7));
2043 * Speed above this value cannot possibly be represented,
2044 * even with the lowest divider (1)
2046 data->fan_min[nr] = 1;
2047 new_div = 0; /* 1 == BIT(0) */
2049 "fan%u low limit %lu above maximum %u, set to maximum\n",
2050 nr + 1, val, data->fan_from_reg_min(1, 0));
2053 * Automatically pick the best divider, i.e. the one such
2054 * that the min limit will correspond to a register value
2055 * in the 96..192 range
2058 while (reg > 192 && new_div < 7) {
2062 data->fan_min[nr] = reg;
2067 * Write both the fan clock divider (if it changed) and the new
2068 * fan min (unconditionally)
2070 if (new_div != data->fan_div[nr]) {
2071 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2072 nr + 1, div_from_reg(data->fan_div[nr]),
2073 div_from_reg(new_div));
2074 data->fan_div[nr] = new_div;
2075 nct6775_write_fan_div_common(data, nr);
2076 /* Give the chip time to sample a new speed value */
2077 data->last_updated = jiffies;
2081 nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2082 mutex_unlock(&data->update_lock);
2088 show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2090 struct nct6775_data *data = nct6775_update_device(dev);
2091 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2092 int p = data->fan_pulses[sattr->index];
2094 return sprintf(buf, "%d\n", p ? : 4);
2098 store_fan_pulses(struct device *dev, struct device_attribute *attr,
2099 const char *buf, size_t count)
2101 struct nct6775_data *data = dev_get_drvdata(dev);
2102 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2103 int nr = sattr->index;
2108 err = kstrtoul(buf, 10, &val);
2115 mutex_lock(&data->update_lock);
2116 data->fan_pulses[nr] = val & 3;
2117 reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2118 reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2119 reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2120 nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
2121 mutex_unlock(&data->update_lock);
2126 static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2127 struct attribute *attr, int index)
2129 struct device *dev = container_of(kobj, struct device, kobj);
2130 struct nct6775_data *data = dev_get_drvdata(dev);
2131 int fan = index / 6; /* fan index */
2132 int nr = index % 6; /* attribute index */
2134 if (!(data->has_fan & BIT(fan)))
2137 if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2139 if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
2141 if (nr == 3 && !data->REG_FAN_PULSES[fan])
2143 if (nr == 4 && !(data->has_fan_min & BIT(fan)))
2145 if (nr == 5 && data->kind != nct6775)
2151 SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2152 SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2154 SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2155 store_beep, FAN_ALARM_BASE);
2156 SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2157 store_fan_pulses, 0);
2158 SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2160 SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2163 * nct6775_fan_is_visible uses the index into the following array
2164 * to determine if attributes should be created or not.
2165 * Any change in order or content must be matched.
2167 static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2168 &sensor_dev_template_fan_input,
2169 &sensor_dev_template_fan_alarm, /* 1 */
2170 &sensor_dev_template_fan_beep, /* 2 */
2171 &sensor_dev_template_fan_pulses,
2172 &sensor_dev_template_fan_min, /* 4 */
2173 &sensor_dev_template_fan_div, /* 5 */
2177 static const struct sensor_template_group nct6775_fan_template_group = {
2178 .templates = nct6775_attributes_fan_template,
2179 .is_visible = nct6775_fan_is_visible,
2184 show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2186 struct nct6775_data *data = nct6775_update_device(dev);
2187 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2188 int nr = sattr->index;
2190 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2194 show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2196 struct nct6775_data *data = nct6775_update_device(dev);
2197 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2199 int index = sattr->index;
2201 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2205 store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2208 struct nct6775_data *data = dev_get_drvdata(dev);
2209 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2211 int index = sattr->index;
2215 err = kstrtol(buf, 10, &val);
2219 mutex_lock(&data->update_lock);
2220 data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2221 nct6775_write_temp(data, data->reg_temp[index][nr],
2222 data->temp[index][nr]);
2223 mutex_unlock(&data->update_lock);
2228 show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2230 struct nct6775_data *data = nct6775_update_device(dev);
2231 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2233 return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2237 store_temp_offset(struct device *dev, struct device_attribute *attr,
2238 const char *buf, size_t count)
2240 struct nct6775_data *data = dev_get_drvdata(dev);
2241 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2242 int nr = sattr->index;
2246 err = kstrtol(buf, 10, &val);
2250 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2252 mutex_lock(&data->update_lock);
2253 data->temp_offset[nr] = val;
2254 nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2255 mutex_unlock(&data->update_lock);
2261 show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2263 struct nct6775_data *data = nct6775_update_device(dev);
2264 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2265 int nr = sattr->index;
2267 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2271 store_temp_type(struct device *dev, struct device_attribute *attr,
2272 const char *buf, size_t count)
2274 struct nct6775_data *data = nct6775_update_device(dev);
2275 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2276 int nr = sattr->index;
2279 u8 vbat, diode, vbit, dbit;
2281 err = kstrtoul(buf, 10, &val);
2285 if (val != 1 && val != 3 && val != 4)
2288 mutex_lock(&data->update_lock);
2290 data->temp_type[nr] = val;
2292 dbit = data->DIODE_MASK << nr;
2293 vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2294 diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
2296 case 1: /* CPU diode (diode, current mode) */
2300 case 3: /* diode, voltage mode */
2303 case 4: /* thermistor */
2306 nct6775_write_value(data, data->REG_VBAT, vbat);
2307 nct6775_write_value(data, data->REG_DIODE, diode);
2309 mutex_unlock(&data->update_lock);
2313 static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2314 struct attribute *attr, int index)
2316 struct device *dev = container_of(kobj, struct device, kobj);
2317 struct nct6775_data *data = dev_get_drvdata(dev);
2318 int temp = index / 10; /* temp index */
2319 int nr = index % 10; /* attribute index */
2321 if (!(data->have_temp & BIT(temp)))
2324 if (nr == 1 && !data->temp_label)
2327 if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2328 return 0; /* alarm */
2330 if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2331 return 0; /* beep */
2333 if (nr == 4 && !data->reg_temp[1][temp]) /* max */
2336 if (nr == 5 && !data->reg_temp[2][temp]) /* max_hyst */
2339 if (nr == 6 && !data->reg_temp[3][temp]) /* crit */
2342 if (nr == 7 && !data->reg_temp[4][temp]) /* lcrit */
2345 /* offset and type only apply to fixed sensors */
2346 if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
2352 SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2353 SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2354 SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2356 SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2357 show_temp, store_temp, 0, 2);
2358 SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2360 SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2362 SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2363 show_temp_offset, store_temp_offset, 0);
2364 SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2365 store_temp_type, 0);
2366 SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
2367 SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2368 store_temp_beep, 0);
2371 * nct6775_temp_is_visible uses the index into the following array
2372 * to determine if attributes should be created or not.
2373 * Any change in order or content must be matched.
2375 static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2376 &sensor_dev_template_temp_input,
2377 &sensor_dev_template_temp_label,
2378 &sensor_dev_template_temp_alarm, /* 2 */
2379 &sensor_dev_template_temp_beep, /* 3 */
2380 &sensor_dev_template_temp_max, /* 4 */
2381 &sensor_dev_template_temp_max_hyst, /* 5 */
2382 &sensor_dev_template_temp_crit, /* 6 */
2383 &sensor_dev_template_temp_lcrit, /* 7 */
2384 &sensor_dev_template_temp_offset, /* 8 */
2385 &sensor_dev_template_temp_type, /* 9 */
2389 static const struct sensor_template_group nct6775_temp_template_group = {
2390 .templates = nct6775_attributes_temp_template,
2391 .is_visible = nct6775_temp_is_visible,
2396 show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2398 struct nct6775_data *data = nct6775_update_device(dev);
2399 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2401 return sprintf(buf, "%d\n", data->pwm_mode[sattr->index]);
2405 store_pwm_mode(struct device *dev, struct device_attribute *attr,
2406 const char *buf, size_t count)
2408 struct nct6775_data *data = dev_get_drvdata(dev);
2409 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2410 int nr = sattr->index;
2415 err = kstrtoul(buf, 10, &val);
2422 /* Setting DC mode (0) is not supported for all chips/channels */
2423 if (data->REG_PWM_MODE[nr] == 0) {
2429 mutex_lock(&data->update_lock);
2430 data->pwm_mode[nr] = val;
2431 reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2432 reg &= ~data->PWM_MODE_MASK[nr];
2434 reg |= data->PWM_MODE_MASK[nr];
2435 nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2436 mutex_unlock(&data->update_lock);
2441 show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2443 struct nct6775_data *data = nct6775_update_device(dev);
2444 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2446 int index = sattr->index;
2450 * For automatic fan control modes, show current pwm readings.
2451 * Otherwise, show the configured value.
2453 if (index == 0 && data->pwm_enable[nr] > manual)
2454 pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2456 pwm = data->pwm[index][nr];
2458 return sprintf(buf, "%d\n", pwm);
2462 store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2465 struct nct6775_data *data = dev_get_drvdata(dev);
2466 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2468 int index = sattr->index;
2470 int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2472 = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
2476 err = kstrtoul(buf, 10, &val);
2479 val = clamp_val(val, minval[index], maxval[index]);
2481 mutex_lock(&data->update_lock);
2482 data->pwm[index][nr] = val;
2483 nct6775_write_value(data, data->REG_PWM[index][nr], val);
2484 if (index == 2) { /* floor: disable if val == 0 */
2485 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2489 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2491 mutex_unlock(&data->update_lock);
2495 /* Returns 0 if OK, -EINVAL otherwise */
2496 static int check_trip_points(struct nct6775_data *data, int nr)
2500 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2501 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2504 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2505 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2508 /* validate critical temperature and pwm if enabled (pwm > 0) */
2509 if (data->auto_pwm[nr][data->auto_pwm_num]) {
2510 if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2511 data->auto_temp[nr][data->auto_pwm_num] ||
2512 data->auto_pwm[nr][data->auto_pwm_num - 1] >
2513 data->auto_pwm[nr][data->auto_pwm_num])
2519 static void pwm_update_registers(struct nct6775_data *data, int nr)
2523 switch (data->pwm_enable[nr]) {
2528 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2529 reg = (reg & ~data->tolerance_mask) |
2530 (data->target_speed_tolerance[nr] & data->tolerance_mask);
2531 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2532 nct6775_write_value(data, data->REG_TARGET[nr],
2533 data->target_speed[nr] & 0xff);
2534 if (data->REG_TOLERANCE_H) {
2535 reg = (data->target_speed[nr] >> 8) & 0x0f;
2536 reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2537 nct6775_write_value(data,
2538 data->REG_TOLERANCE_H[nr],
2542 case thermal_cruise:
2543 nct6775_write_value(data, data->REG_TARGET[nr],
2544 data->target_temp[nr]);
2547 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2548 reg = (reg & ~data->tolerance_mask) |
2549 data->temp_tolerance[0][nr];
2550 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2556 show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2558 struct nct6775_data *data = nct6775_update_device(dev);
2559 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2561 return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2565 store_pwm_enable(struct device *dev, struct device_attribute *attr,
2566 const char *buf, size_t count)
2568 struct nct6775_data *data = dev_get_drvdata(dev);
2569 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2570 int nr = sattr->index;
2575 err = kstrtoul(buf, 10, &val);
2582 if (val == sf3 && data->kind != nct6775)
2585 if (val == sf4 && check_trip_points(data, nr)) {
2586 dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2587 dev_err(dev, "Adjust trip points and try again\n");
2591 mutex_lock(&data->update_lock);
2592 data->pwm_enable[nr] = val;
2595 * turn off pwm control: select manual mode, set pwm to maximum
2597 data->pwm[0][nr] = 255;
2598 nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2600 pwm_update_registers(data, nr);
2601 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2603 reg |= pwm_enable_to_reg(val) << 4;
2604 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2605 mutex_unlock(&data->update_lock);
2610 show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
2614 for (i = 0; i < NUM_TEMP; i++) {
2615 if (!(data->have_temp & BIT(i)))
2617 if (src == data->temp_src[i]) {
2623 return sprintf(buf, "%d\n", sel);
2627 show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2629 struct nct6775_data *data = nct6775_update_device(dev);
2630 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2631 int index = sattr->index;
2633 return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2637 store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2638 const char *buf, size_t count)
2640 struct nct6775_data *data = nct6775_update_device(dev);
2641 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2642 int nr = sattr->index;
2646 err = kstrtoul(buf, 10, &val);
2649 if (val == 0 || val > NUM_TEMP)
2651 if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
2654 mutex_lock(&data->update_lock);
2655 src = data->temp_src[val - 1];
2656 data->pwm_temp_sel[nr] = src;
2657 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2660 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2661 mutex_unlock(&data->update_lock);
2667 show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2670 struct nct6775_data *data = nct6775_update_device(dev);
2671 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2672 int index = sattr->index;
2674 return show_pwm_temp_sel_common(data, buf,
2675 data->pwm_weight_temp_sel[index]);
2679 store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2680 const char *buf, size_t count)
2682 struct nct6775_data *data = nct6775_update_device(dev);
2683 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2684 int nr = sattr->index;
2688 err = kstrtoul(buf, 10, &val);
2693 val = array_index_nospec(val, NUM_TEMP + 1);
2694 if (val && (!(data->have_temp & BIT(val - 1)) ||
2695 !data->temp_src[val - 1]))
2698 mutex_lock(&data->update_lock);
2700 src = data->temp_src[val - 1];
2701 data->pwm_weight_temp_sel[nr] = src;
2702 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2704 reg |= (src | 0x80);
2705 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2707 data->pwm_weight_temp_sel[nr] = 0;
2708 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2710 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2712 mutex_unlock(&data->update_lock);
2718 show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2720 struct nct6775_data *data = nct6775_update_device(dev);
2721 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2723 return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2727 store_target_temp(struct device *dev, struct device_attribute *attr,
2728 const char *buf, size_t count)
2730 struct nct6775_data *data = dev_get_drvdata(dev);
2731 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2732 int nr = sattr->index;
2736 err = kstrtoul(buf, 10, &val);
2740 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2741 data->target_temp_mask);
2743 mutex_lock(&data->update_lock);
2744 data->target_temp[nr] = val;
2745 pwm_update_registers(data, nr);
2746 mutex_unlock(&data->update_lock);
2751 show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2753 struct nct6775_data *data = nct6775_update_device(dev);
2754 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2755 int nr = sattr->index;
2757 return sprintf(buf, "%d\n",
2758 fan_from_reg16(data->target_speed[nr],
2759 data->fan_div[nr]));
2763 store_target_speed(struct device *dev, struct device_attribute *attr,
2764 const char *buf, size_t count)
2766 struct nct6775_data *data = dev_get_drvdata(dev);
2767 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2768 int nr = sattr->index;
2773 err = kstrtoul(buf, 10, &val);
2777 val = clamp_val(val, 0, 1350000U);
2778 speed = fan_to_reg(val, data->fan_div[nr]);
2780 mutex_lock(&data->update_lock);
2781 data->target_speed[nr] = speed;
2782 pwm_update_registers(data, nr);
2783 mutex_unlock(&data->update_lock);
2788 show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2791 struct nct6775_data *data = nct6775_update_device(dev);
2792 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2794 int index = sattr->index;
2796 return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2800 store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2801 const char *buf, size_t count)
2803 struct nct6775_data *data = dev_get_drvdata(dev);
2804 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2806 int index = sattr->index;
2810 err = kstrtoul(buf, 10, &val);
2814 /* Limit tolerance as needed */
2815 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2817 mutex_lock(&data->update_lock);
2818 data->temp_tolerance[index][nr] = val;
2820 pwm_update_registers(data, nr);
2822 nct6775_write_value(data,
2823 data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2825 mutex_unlock(&data->update_lock);
2830 * Fan speed tolerance is a tricky beast, since the associated register is
2831 * a tick counter, but the value is reported and configured as rpm.
2832 * Compute resulting low and high rpm values and report the difference.
2835 show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2838 struct nct6775_data *data = nct6775_update_device(dev);
2839 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2840 int nr = sattr->index;
2841 int low = data->target_speed[nr] - data->target_speed_tolerance[nr];
2842 int high = data->target_speed[nr] + data->target_speed_tolerance[nr];
2852 tolerance = (fan_from_reg16(low, data->fan_div[nr])
2853 - fan_from_reg16(high, data->fan_div[nr])) / 2;
2855 return sprintf(buf, "%d\n", tolerance);
2859 store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2860 const char *buf, size_t count)
2862 struct nct6775_data *data = dev_get_drvdata(dev);
2863 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2864 int nr = sattr->index;
2869 err = kstrtoul(buf, 10, &val);
2873 high = fan_from_reg16(data->target_speed[nr],
2874 data->fan_div[nr]) + val;
2875 low = fan_from_reg16(data->target_speed[nr],
2876 data->fan_div[nr]) - val;
2882 val = (fan_to_reg(low, data->fan_div[nr]) -
2883 fan_to_reg(high, data->fan_div[nr])) / 2;
2885 /* Limit tolerance as needed */
2886 val = clamp_val(val, 0, data->speed_tolerance_limit);
2888 mutex_lock(&data->update_lock);
2889 data->target_speed_tolerance[nr] = val;
2890 pwm_update_registers(data, nr);
2891 mutex_unlock(&data->update_lock);
2895 SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2896 SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2898 SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2899 store_pwm_enable, 0);
2900 SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2901 show_pwm_temp_sel, store_pwm_temp_sel, 0);
2902 SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2903 show_target_temp, store_target_temp, 0);
2904 SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2905 show_target_speed, store_target_speed, 0);
2906 SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2907 show_speed_tolerance, store_speed_tolerance, 0);
2909 /* Smart Fan registers */
2912 show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
2914 struct nct6775_data *data = nct6775_update_device(dev);
2915 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2917 int index = sattr->index;
2919 return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
2923 store_weight_temp(struct device *dev, struct device_attribute *attr,
2924 const char *buf, size_t count)
2926 struct nct6775_data *data = dev_get_drvdata(dev);
2927 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2929 int index = sattr->index;
2933 err = kstrtoul(buf, 10, &val);
2937 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255);
2939 mutex_lock(&data->update_lock);
2940 data->weight_temp[index][nr] = val;
2941 nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val);
2942 mutex_unlock(&data->update_lock);
2946 SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO,
2947 show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0);
2948 SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step",
2949 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0);
2950 SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol",
2951 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1);
2952 SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base",
2953 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2);
2954 SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step",
2955 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5);
2956 SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base",
2957 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6);
2960 show_fan_time(struct device *dev, struct device_attribute *attr, char *buf)
2962 struct nct6775_data *data = nct6775_update_device(dev);
2963 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2965 int index = sattr->index;
2967 return sprintf(buf, "%d\n",
2968 step_time_from_reg(data->fan_time[index][nr],
2969 data->pwm_mode[nr]));
2973 store_fan_time(struct device *dev, struct device_attribute *attr,
2974 const char *buf, size_t count)
2976 struct nct6775_data *data = dev_get_drvdata(dev);
2977 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2979 int index = sattr->index;
2983 err = kstrtoul(buf, 10, &val);
2987 val = step_time_to_reg(val, data->pwm_mode[nr]);
2988 mutex_lock(&data->update_lock);
2989 data->fan_time[index][nr] = val;
2990 nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val);
2991 mutex_unlock(&data->update_lock);
2996 show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2998 struct nct6775_data *data = nct6775_update_device(dev);
2999 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3001 return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]);
3005 store_auto_pwm(struct device *dev, struct device_attribute *attr,
3006 const char *buf, size_t count)
3008 struct nct6775_data *data = dev_get_drvdata(dev);
3009 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3011 int point = sattr->index;
3016 err = kstrtoul(buf, 10, &val);
3022 if (point == data->auto_pwm_num) {
3023 if (data->kind != nct6775 && !val)
3025 if (data->kind != nct6779 && val)
3029 mutex_lock(&data->update_lock);
3030 data->auto_pwm[nr][point] = val;
3031 if (point < data->auto_pwm_num) {
3032 nct6775_write_value(data,
3033 NCT6775_AUTO_PWM(data, nr, point),
3034 data->auto_pwm[nr][point]);
3036 switch (data->kind) {
3038 /* disable if needed (pwm == 0) */
3039 reg = nct6775_read_value(data,
3040 NCT6775_REG_CRITICAL_ENAB[nr]);
3045 nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr],
3049 break; /* always enabled, nothing to do */
3057 nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
3059 reg = nct6775_read_value(data,
3060 data->REG_CRITICAL_PWM_ENABLE[nr]);
3062 reg &= ~data->CRITICAL_PWM_ENABLE_MASK;
3064 reg |= data->CRITICAL_PWM_ENABLE_MASK;
3065 nct6775_write_value(data,
3066 data->REG_CRITICAL_PWM_ENABLE[nr],
3071 mutex_unlock(&data->update_lock);
3076 show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf)
3078 struct nct6775_data *data = nct6775_update_device(dev);
3079 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3081 int point = sattr->index;
3084 * We don't know for sure if the temperature is signed or unsigned.
3085 * Assume it is unsigned.
3087 return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000);
3091 store_auto_temp(struct device *dev, struct device_attribute *attr,
3092 const char *buf, size_t count)
3094 struct nct6775_data *data = dev_get_drvdata(dev);
3095 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3097 int point = sattr->index;
3101 err = kstrtoul(buf, 10, &val);
3107 mutex_lock(&data->update_lock);
3108 data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000);
3109 if (point < data->auto_pwm_num) {
3110 nct6775_write_value(data,
3111 NCT6775_AUTO_TEMP(data, nr, point),
3112 data->auto_temp[nr][point]);
3114 nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr],
3115 data->auto_temp[nr][point]);
3117 mutex_unlock(&data->update_lock);
3121 static umode_t nct6775_pwm_is_visible(struct kobject *kobj,
3122 struct attribute *attr, int index)
3124 struct device *dev = container_of(kobj, struct device, kobj);
3125 struct nct6775_data *data = dev_get_drvdata(dev);
3126 int pwm = index / 36; /* pwm index */
3127 int nr = index % 36; /* attribute index */
3129 if (!(data->has_pwm & BIT(pwm)))
3132 if ((nr >= 14 && nr <= 18) || nr == 21) /* weight */
3133 if (!data->REG_WEIGHT_TEMP_SEL[pwm])
3135 if (nr == 19 && data->REG_PWM[3] == NULL) /* pwm_max */
3137 if (nr == 20 && data->REG_PWM[4] == NULL) /* pwm_step */
3139 if (nr == 21 && data->REG_PWM[6] == NULL) /* weight_duty_base */
3142 if (nr >= 22 && nr <= 35) { /* auto point */
3143 int api = (nr - 22) / 2; /* auto point index */
3145 if (api > data->auto_pwm_num)
3151 SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO,
3152 show_fan_time, store_fan_time, 0, 0);
3153 SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO,
3154 show_fan_time, store_fan_time, 0, 1);
3155 SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO,
3156 show_fan_time, store_fan_time, 0, 2);
3157 SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm,
3159 SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm,
3161 SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO,
3162 show_temp_tolerance, store_temp_tolerance, 0, 0);
3163 SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance",
3164 S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance,
3167 SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm,
3170 SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm,
3173 SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm",
3174 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0);
3175 SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp",
3176 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0);
3178 SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm",
3179 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1);
3180 SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp",
3181 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1);
3183 SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm",
3184 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2);
3185 SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp",
3186 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2);
3188 SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm",
3189 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3);
3190 SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp",
3191 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3);
3193 SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm",
3194 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4);
3195 SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp",
3196 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4);
3198 SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm",
3199 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5);
3200 SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp",
3201 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5);
3203 SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm",
3204 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6);
3205 SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp",
3206 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6);
3209 * nct6775_pwm_is_visible uses the index into the following array
3210 * to determine if attributes should be created or not.
3211 * Any change in order or content must be matched.
3213 static struct sensor_device_template *nct6775_attributes_pwm_template[] = {
3214 &sensor_dev_template_pwm,
3215 &sensor_dev_template_pwm_mode,
3216 &sensor_dev_template_pwm_enable,
3217 &sensor_dev_template_pwm_temp_sel,
3218 &sensor_dev_template_pwm_temp_tolerance,
3219 &sensor_dev_template_pwm_crit_temp_tolerance,
3220 &sensor_dev_template_pwm_target_temp,
3221 &sensor_dev_template_fan_target,
3222 &sensor_dev_template_fan_tolerance,
3223 &sensor_dev_template_pwm_stop_time,
3224 &sensor_dev_template_pwm_step_up_time,
3225 &sensor_dev_template_pwm_step_down_time,
3226 &sensor_dev_template_pwm_start,
3227 &sensor_dev_template_pwm_floor,
3228 &sensor_dev_template_pwm_weight_temp_sel, /* 14 */
3229 &sensor_dev_template_pwm_weight_temp_step,
3230 &sensor_dev_template_pwm_weight_temp_step_tol,
3231 &sensor_dev_template_pwm_weight_temp_step_base,
3232 &sensor_dev_template_pwm_weight_duty_step, /* 18 */
3233 &sensor_dev_template_pwm_max, /* 19 */
3234 &sensor_dev_template_pwm_step, /* 20 */
3235 &sensor_dev_template_pwm_weight_duty_base, /* 21 */
3236 &sensor_dev_template_pwm_auto_point1_pwm, /* 22 */
3237 &sensor_dev_template_pwm_auto_point1_temp,
3238 &sensor_dev_template_pwm_auto_point2_pwm,
3239 &sensor_dev_template_pwm_auto_point2_temp,
3240 &sensor_dev_template_pwm_auto_point3_pwm,
3241 &sensor_dev_template_pwm_auto_point3_temp,
3242 &sensor_dev_template_pwm_auto_point4_pwm,
3243 &sensor_dev_template_pwm_auto_point4_temp,
3244 &sensor_dev_template_pwm_auto_point5_pwm,
3245 &sensor_dev_template_pwm_auto_point5_temp,
3246 &sensor_dev_template_pwm_auto_point6_pwm,
3247 &sensor_dev_template_pwm_auto_point6_temp,
3248 &sensor_dev_template_pwm_auto_point7_pwm,
3249 &sensor_dev_template_pwm_auto_point7_temp, /* 35 */
3254 static const struct sensor_template_group nct6775_pwm_template_group = {
3255 .templates = nct6775_attributes_pwm_template,
3256 .is_visible = nct6775_pwm_is_visible,
3261 cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
3263 struct nct6775_data *data = dev_get_drvdata(dev);
3265 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
3268 static DEVICE_ATTR_RO(cpu0_vid);
3270 /* Case open detection */
3273 clear_caseopen(struct device *dev, struct device_attribute *attr,
3274 const char *buf, size_t count)
3276 struct nct6775_data *data = dev_get_drvdata(dev);
3277 int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE;
3282 if (kstrtoul(buf, 10, &val) || val != 0)
3285 mutex_lock(&data->update_lock);
3288 * Use CR registers to clear caseopen status.
3289 * The CR registers are the same for all chips, and not all chips
3290 * support clearing the caseopen status through "regular" registers.
3292 ret = superio_enter(data->sioreg);
3298 superio_select(data->sioreg, NCT6775_LD_ACPI);
3299 reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]);
3300 reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3301 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3302 reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3303 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3304 superio_exit(data->sioreg);
3306 data->valid = false; /* Force cache refresh */
3308 mutex_unlock(&data->update_lock);
3312 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm,
3313 clear_caseopen, INTRUSION_ALARM_BASE);
3314 static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm,
3315 clear_caseopen, INTRUSION_ALARM_BASE + 1);
3316 static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep,
3317 store_beep, INTRUSION_ALARM_BASE);
3318 static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep,
3319 store_beep, INTRUSION_ALARM_BASE + 1);
3320 static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep,
3321 store_beep, BEEP_ENABLE_BASE);
3323 static umode_t nct6775_other_is_visible(struct kobject *kobj,
3324 struct attribute *attr, int index)
3326 struct device *dev = container_of(kobj, struct device, kobj);
3327 struct nct6775_data *data = dev_get_drvdata(dev);
3329 if (index == 0 && !data->have_vid)
3332 if (index == 1 || index == 2) {
3333 if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0)
3337 if (index == 3 || index == 4) {
3338 if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0)
3346 * nct6775_other_is_visible uses the index into the following array
3347 * to determine if attributes should be created or not.
3348 * Any change in order or content must be matched.
3350 static struct attribute *nct6775_attributes_other[] = {
3351 &dev_attr_cpu0_vid.attr, /* 0 */
3352 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, /* 1 */
3353 &sensor_dev_attr_intrusion1_alarm.dev_attr.attr, /* 2 */
3354 &sensor_dev_attr_intrusion0_beep.dev_attr.attr, /* 3 */
3355 &sensor_dev_attr_intrusion1_beep.dev_attr.attr, /* 4 */
3356 &sensor_dev_attr_beep_enable.dev_attr.attr, /* 5 */
3361 static const struct attribute_group nct6775_group_other = {
3362 .attrs = nct6775_attributes_other,
3363 .is_visible = nct6775_other_is_visible,
3366 static inline void nct6775_init_device(struct nct6775_data *data)
3371 /* Start monitoring if needed */
3372 if (data->REG_CONFIG) {
3373 tmp = nct6775_read_value(data, data->REG_CONFIG);
3375 nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01);
3378 /* Enable temperature sensors if needed */
3379 for (i = 0; i < NUM_TEMP; i++) {
3380 if (!(data->have_temp & BIT(i)))
3382 if (!data->reg_temp_config[i])
3384 tmp = nct6775_read_value(data, data->reg_temp_config[i]);
3386 nct6775_write_value(data, data->reg_temp_config[i],
3390 /* Enable VBAT monitoring if needed */
3391 tmp = nct6775_read_value(data, data->REG_VBAT);
3393 nct6775_write_value(data, data->REG_VBAT, tmp | 0x01);
3395 diode = nct6775_read_value(data, data->REG_DIODE);
3397 for (i = 0; i < data->temp_fixed_num; i++) {
3398 if (!(data->have_temp_fixed & BIT(i)))
3400 if ((tmp & (data->DIODE_MASK << i))) /* diode */
3402 = 3 - ((diode >> i) & data->DIODE_MASK);
3403 else /* thermistor */
3404 data->temp_type[i] = 4;
3409 nct6775_check_fan_inputs(struct nct6775_data *data)
3411 bool fan3pin = false, fan4pin = false, fan4min = false;
3412 bool fan5pin = false, fan6pin = false, fan7pin = false;
3413 bool pwm3pin = false, pwm4pin = false, pwm5pin = false;
3414 bool pwm6pin = false, pwm7pin = false;
3415 int sioreg = data->sioreg;
3418 /* Store SIO_REG_ENABLE for use during resume */
3419 superio_select(sioreg, NCT6775_LD_HWM);
3420 data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE);
3422 /* fan4 and fan5 share some pins with the GPIO and serial flash */
3423 if (data->kind == nct6775) {
3424 regval = superio_inb(sioreg, 0x2c);
3426 fan3pin = regval & BIT(6);
3427 pwm3pin = regval & BIT(7);
3429 /* On NCT6775, fan4 shares pins with the fdc interface */
3430 fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
3431 } else if (data->kind == nct6776) {
3432 bool gpok = superio_inb(sioreg, 0x27) & 0x80;
3433 const char *board_vendor, *board_name;
3435 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3436 board_name = dmi_get_system_info(DMI_BOARD_NAME);
3438 if (board_name && board_vendor &&
3439 !strcmp(board_vendor, "ASRock")) {
3441 * Auxiliary fan monitoring is not enabled on ASRock
3442 * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode.
3443 * Observed with BIOS version 2.00.
3445 if (!strcmp(board_name, "Z77 Pro4-M")) {
3446 if ((data->sio_reg_enable & 0xe0) != 0xe0) {
3447 data->sio_reg_enable |= 0xe0;
3448 superio_outb(sioreg, SIO_REG_ENABLE,
3449 data->sio_reg_enable);
3454 if (data->sio_reg_enable & 0x80)
3457 fan3pin = !(superio_inb(sioreg, 0x24) & 0x40);
3459 if (data->sio_reg_enable & 0x40)
3462 fan4pin = superio_inb(sioreg, 0x1C) & 0x01;
3464 if (data->sio_reg_enable & 0x20)
3467 fan5pin = superio_inb(sioreg, 0x1C) & 0x02;
3471 } else if (data->kind == nct6106) {
3472 regval = superio_inb(sioreg, 0x24);
3473 fan3pin = !(regval & 0x80);
3474 pwm3pin = regval & 0x08;
3476 /* NCT6779D, NCT6791D, NCT6792D, NCT6793D, NCT6795D, NCT6796D */
3477 int regval_1b, regval_2a, regval_2f;
3480 regval = superio_inb(sioreg, 0x1c);
3482 fan3pin = !(regval & BIT(5));
3483 fan4pin = !(regval & BIT(6));
3484 fan5pin = !(regval & BIT(7));
3486 pwm3pin = !(regval & BIT(0));
3487 pwm4pin = !(regval & BIT(1));
3488 pwm5pin = !(regval & BIT(2));
3490 regval = superio_inb(sioreg, 0x2d);
3491 switch (data->kind) {
3494 fan6pin = regval & BIT(1);
3495 pwm6pin = regval & BIT(0);
3500 regval_1b = superio_inb(sioreg, 0x1b);
3501 regval_2a = superio_inb(sioreg, 0x2a);
3502 regval_2f = superio_inb(sioreg, 0x2f);
3503 dsw_en = regval_2f & BIT(3);
3506 pwm5pin = regval & BIT(7);
3509 fan5pin = regval_1b & BIT(5);
3511 superio_select(sioreg, NCT6775_LD_12);
3512 if (data->kind != nct6796) {
3513 int regval_eb = superio_inb(sioreg, 0xeb);
3516 fan6pin = regval & BIT(1);
3517 pwm6pin = regval & BIT(0);
3521 fan5pin = regval_eb & BIT(5);
3523 pwm5pin = (regval_eb & BIT(4)) &&
3524 !(regval_2a & BIT(0));
3526 fan6pin = regval_eb & BIT(3);
3528 pwm6pin = regval_eb & BIT(2);
3531 if (data->kind == nct6795 || data->kind == nct6796) {
3532 int regval_ed = superio_inb(sioreg, 0xed);
3535 fan6pin = (regval_2a & BIT(4)) &&
3537 (dsw_en && (regval_ed & BIT(4))));
3539 pwm6pin = (regval_2a & BIT(3)) &&
3540 (regval_ed & BIT(2));
3543 if (data->kind == nct6796) {
3544 int regval_1d = superio_inb(sioreg, 0x1d);
3545 int regval_2b = superio_inb(sioreg, 0x2b);
3547 fan7pin = !(regval_2b & BIT(2));
3548 pwm7pin = !(regval_1d & (BIT(2) | BIT(3)));
3552 default: /* NCT6779D */
3559 /* fan 1 and 2 (0x03) are always present */
3560 data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) |
3561 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3562 data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) |
3563 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3564 data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) |
3565 (pwm5pin << 4) | (pwm6pin << 5) | (pwm7pin << 6);
3568 static void add_temp_sensors(struct nct6775_data *data, const u16 *regp,
3569 int *available, int *mask)
3574 for (i = 0; i < data->pwm_num && *available; i++) {
3579 src = nct6775_read_value(data, regp[i]);
3581 if (!src || (*mask & BIT(src)))
3583 if (!(data->temp_mask & BIT(src)))
3586 index = __ffs(*available);
3587 nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src);
3588 *available &= ~BIT(index);
3593 static int nct6775_probe(struct platform_device *pdev)
3595 struct device *dev = &pdev->dev;
3596 struct nct6775_sio_data *sio_data = dev_get_platdata(dev);
3597 struct nct6775_data *data;
3598 struct resource *res;
3600 int src, mask, available;
3601 const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config;
3602 const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit;
3603 const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL;
3604 int num_reg_temp, num_reg_temp_mon;
3606 struct attribute_group *group;
3607 struct device *hwmon_dev;
3608 int num_attr_groups = 0;
3610 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3611 if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH,
3615 data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data),
3620 data->kind = sio_data->kind;
3621 data->sioreg = sio_data->sioreg;
3622 data->addr = res->start;
3623 mutex_init(&data->update_lock);
3624 data->name = nct6775_device_names[data->kind];
3625 data->bank = 0xff; /* Force initial bank selection */
3626 platform_set_drvdata(pdev, data);
3628 switch (data->kind) {
3632 data->auto_pwm_num = 4;
3633 data->temp_fixed_num = 3;
3634 data->num_temp_alarms = 6;
3635 data->num_temp_beeps = 6;
3637 data->fan_from_reg = fan_from_reg13;
3638 data->fan_from_reg_min = fan_from_reg13;
3640 data->temp_label = nct6776_temp_label;
3641 data->temp_mask = NCT6776_TEMP_MASK;
3643 data->REG_VBAT = NCT6106_REG_VBAT;
3644 data->REG_DIODE = NCT6106_REG_DIODE;
3645 data->DIODE_MASK = NCT6106_DIODE_MASK;
3646 data->REG_VIN = NCT6106_REG_IN;
3647 data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN;
3648 data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX;
3649 data->REG_TARGET = NCT6106_REG_TARGET;
3650 data->REG_FAN = NCT6106_REG_FAN;
3651 data->REG_FAN_MODE = NCT6106_REG_FAN_MODE;
3652 data->REG_FAN_MIN = NCT6106_REG_FAN_MIN;
3653 data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES;
3654 data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT;
3655 data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME;
3656 data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME;
3657 data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME;
3658 data->REG_PWM[0] = NCT6106_REG_PWM;
3659 data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT;
3660 data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT;
3661 data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
3662 data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
3663 data->REG_PWM_READ = NCT6106_REG_PWM_READ;
3664 data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
3665 data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
3666 data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP;
3667 data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM;
3668 data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP;
3669 data->REG_CRITICAL_TEMP_TOLERANCE
3670 = NCT6106_REG_CRITICAL_TEMP_TOLERANCE;
3671 data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE;
3672 data->CRITICAL_PWM_ENABLE_MASK
3673 = NCT6106_CRITICAL_PWM_ENABLE_MASK;
3674 data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM;
3675 data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
3676 data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
3677 data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL;
3678 data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL;
3679 data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
3680 data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
3681 data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
3682 data->REG_ALARM = NCT6106_REG_ALARM;
3683 data->ALARM_BITS = NCT6106_ALARM_BITS;
3684 data->REG_BEEP = NCT6106_REG_BEEP;
3685 data->BEEP_BITS = NCT6106_BEEP_BITS;
3687 reg_temp = NCT6106_REG_TEMP;
3688 reg_temp_mon = NCT6106_REG_TEMP_MON;
3689 num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP);
3690 num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON);
3691 reg_temp_over = NCT6106_REG_TEMP_OVER;
3692 reg_temp_hyst = NCT6106_REG_TEMP_HYST;
3693 reg_temp_config = NCT6106_REG_TEMP_CONFIG;
3694 reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
3695 reg_temp_crit = NCT6106_REG_TEMP_CRIT;
3696 reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
3697 reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
3703 data->auto_pwm_num = 6;
3704 data->has_fan_div = true;
3705 data->temp_fixed_num = 3;
3706 data->num_temp_alarms = 3;
3707 data->num_temp_beeps = 3;
3709 data->ALARM_BITS = NCT6775_ALARM_BITS;
3710 data->BEEP_BITS = NCT6775_BEEP_BITS;
3712 data->fan_from_reg = fan_from_reg16;
3713 data->fan_from_reg_min = fan_from_reg8;
3714 data->target_temp_mask = 0x7f;
3715 data->tolerance_mask = 0x0f;
3716 data->speed_tolerance_limit = 15;
3718 data->temp_label = nct6775_temp_label;
3719 data->temp_mask = NCT6775_TEMP_MASK;
3721 data->REG_CONFIG = NCT6775_REG_CONFIG;
3722 data->REG_VBAT = NCT6775_REG_VBAT;
3723 data->REG_DIODE = NCT6775_REG_DIODE;
3724 data->DIODE_MASK = NCT6775_DIODE_MASK;
3725 data->REG_VIN = NCT6775_REG_IN;
3726 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3727 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3728 data->REG_TARGET = NCT6775_REG_TARGET;
3729 data->REG_FAN = NCT6775_REG_FAN;
3730 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3731 data->REG_FAN_MIN = NCT6775_REG_FAN_MIN;
3732 data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES;
3733 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3734 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3735 data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME;
3736 data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME;
3737 data->REG_PWM[0] = NCT6775_REG_PWM;
3738 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3739 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3740 data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT;
3741 data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT;
3742 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3743 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3744 data->REG_PWM_MODE = NCT6775_REG_PWM_MODE;
3745 data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK;
3746 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3747 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3748 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3749 data->REG_CRITICAL_TEMP_TOLERANCE
3750 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3751 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3752 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3753 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3754 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3755 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3756 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3757 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3758 data->REG_ALARM = NCT6775_REG_ALARM;
3759 data->REG_BEEP = NCT6775_REG_BEEP;
3761 reg_temp = NCT6775_REG_TEMP;
3762 reg_temp_mon = NCT6775_REG_TEMP_MON;
3763 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3764 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3765 reg_temp_over = NCT6775_REG_TEMP_OVER;
3766 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3767 reg_temp_config = NCT6775_REG_TEMP_CONFIG;
3768 reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE;
3769 reg_temp_crit = NCT6775_REG_TEMP_CRIT;
3775 data->auto_pwm_num = 4;
3776 data->has_fan_div = false;
3777 data->temp_fixed_num = 3;
3778 data->num_temp_alarms = 3;
3779 data->num_temp_beeps = 6;
3781 data->ALARM_BITS = NCT6776_ALARM_BITS;
3782 data->BEEP_BITS = NCT6776_BEEP_BITS;
3784 data->fan_from_reg = fan_from_reg13;
3785 data->fan_from_reg_min = fan_from_reg13;
3786 data->target_temp_mask = 0xff;
3787 data->tolerance_mask = 0x07;
3788 data->speed_tolerance_limit = 63;
3790 data->temp_label = nct6776_temp_label;
3791 data->temp_mask = NCT6776_TEMP_MASK;
3793 data->REG_CONFIG = NCT6775_REG_CONFIG;
3794 data->REG_VBAT = NCT6775_REG_VBAT;
3795 data->REG_DIODE = NCT6775_REG_DIODE;
3796 data->DIODE_MASK = NCT6775_DIODE_MASK;
3797 data->REG_VIN = NCT6775_REG_IN;
3798 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3799 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3800 data->REG_TARGET = NCT6775_REG_TARGET;
3801 data->REG_FAN = NCT6775_REG_FAN;
3802 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3803 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3804 data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES;
3805 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3806 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3807 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3808 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3809 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3810 data->REG_PWM[0] = NCT6775_REG_PWM;
3811 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3812 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3813 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3814 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3815 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3816 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3817 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3818 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3819 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3820 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3821 data->REG_CRITICAL_TEMP_TOLERANCE
3822 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3823 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3824 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3825 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3826 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3827 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3828 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3829 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3830 data->REG_ALARM = NCT6775_REG_ALARM;
3831 data->REG_BEEP = NCT6776_REG_BEEP;
3833 reg_temp = NCT6775_REG_TEMP;
3834 reg_temp_mon = NCT6775_REG_TEMP_MON;
3835 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3836 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3837 reg_temp_over = NCT6775_REG_TEMP_OVER;
3838 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3839 reg_temp_config = NCT6776_REG_TEMP_CONFIG;
3840 reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE;
3841 reg_temp_crit = NCT6776_REG_TEMP_CRIT;
3847 data->auto_pwm_num = 4;
3848 data->has_fan_div = false;
3849 data->temp_fixed_num = 6;
3850 data->num_temp_alarms = 2;
3851 data->num_temp_beeps = 2;
3853 data->ALARM_BITS = NCT6779_ALARM_BITS;
3854 data->BEEP_BITS = NCT6779_BEEP_BITS;
3856 data->fan_from_reg = fan_from_reg13;
3857 data->fan_from_reg_min = fan_from_reg13;
3858 data->target_temp_mask = 0xff;
3859 data->tolerance_mask = 0x07;
3860 data->speed_tolerance_limit = 63;
3862 data->temp_label = nct6779_temp_label;
3863 data->temp_mask = NCT6779_TEMP_MASK;
3865 data->REG_CONFIG = NCT6775_REG_CONFIG;
3866 data->REG_VBAT = NCT6775_REG_VBAT;
3867 data->REG_DIODE = NCT6775_REG_DIODE;
3868 data->DIODE_MASK = NCT6775_DIODE_MASK;
3869 data->REG_VIN = NCT6779_REG_IN;
3870 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3871 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3872 data->REG_TARGET = NCT6775_REG_TARGET;
3873 data->REG_FAN = NCT6779_REG_FAN;
3874 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3875 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3876 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3877 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3878 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3879 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3880 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3881 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3882 data->REG_PWM[0] = NCT6775_REG_PWM;
3883 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3884 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3885 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3886 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3887 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3888 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3889 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3890 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3891 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3892 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3893 data->REG_CRITICAL_TEMP_TOLERANCE
3894 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3895 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3896 data->CRITICAL_PWM_ENABLE_MASK
3897 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3898 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
3899 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
3900 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3901 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3902 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3903 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3904 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3905 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3906 data->REG_ALARM = NCT6779_REG_ALARM;
3907 data->REG_BEEP = NCT6776_REG_BEEP;
3909 reg_temp = NCT6779_REG_TEMP;
3910 reg_temp_mon = NCT6779_REG_TEMP_MON;
3911 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
3912 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
3913 reg_temp_over = NCT6779_REG_TEMP_OVER;
3914 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
3915 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
3916 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
3917 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
3926 data->pwm_num = (data->kind == nct6796) ? 7 : 6;
3927 data->auto_pwm_num = 4;
3928 data->has_fan_div = false;
3929 data->temp_fixed_num = 6;
3930 data->num_temp_alarms = 2;
3931 data->num_temp_beeps = 2;
3933 data->ALARM_BITS = NCT6791_ALARM_BITS;
3934 data->BEEP_BITS = NCT6779_BEEP_BITS;
3936 data->fan_from_reg = fan_from_reg13;
3937 data->fan_from_reg_min = fan_from_reg13;
3938 data->target_temp_mask = 0xff;
3939 data->tolerance_mask = 0x07;
3940 data->speed_tolerance_limit = 63;
3942 switch (data->kind) {
3945 data->temp_label = nct6779_temp_label;
3946 data->temp_mask = NCT6791_TEMP_MASK;
3949 data->temp_label = nct6792_temp_label;
3950 data->temp_mask = NCT6792_TEMP_MASK;
3953 data->temp_label = nct6793_temp_label;
3954 data->temp_mask = NCT6793_TEMP_MASK;
3957 data->temp_label = nct6795_temp_label;
3958 data->temp_mask = NCT6795_TEMP_MASK;
3961 data->temp_label = nct6796_temp_label;
3962 data->temp_mask = NCT6796_TEMP_MASK;
3966 data->REG_CONFIG = NCT6775_REG_CONFIG;
3967 data->REG_VBAT = NCT6775_REG_VBAT;
3968 data->REG_DIODE = NCT6775_REG_DIODE;
3969 data->DIODE_MASK = NCT6775_DIODE_MASK;
3970 data->REG_VIN = NCT6779_REG_IN;
3971 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3972 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3973 data->REG_TARGET = NCT6775_REG_TARGET;
3974 data->REG_FAN = NCT6779_REG_FAN;
3975 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3976 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3977 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3978 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3979 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3980 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3981 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3982 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3983 data->REG_PWM[0] = NCT6775_REG_PWM;
3984 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3985 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3986 data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP;
3987 data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE;
3988 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3989 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3990 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3991 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3992 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3993 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3994 data->REG_CRITICAL_TEMP_TOLERANCE
3995 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3996 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3997 data->CRITICAL_PWM_ENABLE_MASK
3998 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3999 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
4000 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4001 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4002 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4003 data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL;
4004 data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP;
4005 data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL;
4006 data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE;
4007 data->REG_ALARM = NCT6791_REG_ALARM;
4008 if (data->kind == nct6791)
4009 data->REG_BEEP = NCT6776_REG_BEEP;
4011 data->REG_BEEP = NCT6792_REG_BEEP;
4013 reg_temp = NCT6779_REG_TEMP;
4014 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4015 if (data->kind == nct6791) {
4016 reg_temp_mon = NCT6779_REG_TEMP_MON;
4017 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4019 reg_temp_mon = NCT6792_REG_TEMP_MON;
4020 num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON);
4022 reg_temp_over = NCT6779_REG_TEMP_OVER;
4023 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4024 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4025 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4026 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4032 data->have_in = BIT(data->in_num) - 1;
4033 data->have_temp = 0;
4036 * On some boards, not all available temperature sources are monitored,
4037 * even though some of the monitoring registers are unused.
4038 * Get list of unused monitoring registers, then detect if any fan
4039 * controls are configured to use unmonitored temperature sources.
4040 * If so, assign the unmonitored temperature sources to available
4041 * monitoring registers.
4045 for (i = 0; i < num_reg_temp; i++) {
4046 if (reg_temp[i] == 0)
4049 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4050 if (!src || (mask & BIT(src)))
4051 available |= BIT(i);
4057 * Now find unmonitored temperature registers and enable monitoring
4058 * if additional monitoring registers are available.
4060 add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask);
4061 add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask);
4064 s = NUM_TEMP_FIXED; /* First dynamic temperature attribute */
4065 for (i = 0; i < num_reg_temp; i++) {
4066 if (reg_temp[i] == 0)
4069 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4070 if (!src || (mask & BIT(src)))
4073 if (!(data->temp_mask & BIT(src))) {
4075 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4076 src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]);
4082 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4083 if (src <= data->temp_fixed_num) {
4084 data->have_temp |= BIT(src - 1);
4085 data->have_temp_fixed |= BIT(src - 1);
4086 data->reg_temp[0][src - 1] = reg_temp[i];
4087 data->reg_temp[1][src - 1] = reg_temp_over[i];
4088 data->reg_temp[2][src - 1] = reg_temp_hyst[i];
4089 if (reg_temp_crit_h && reg_temp_crit_h[i])
4090 data->reg_temp[3][src - 1] = reg_temp_crit_h[i];
4091 else if (reg_temp_crit[src - 1])
4092 data->reg_temp[3][src - 1]
4093 = reg_temp_crit[src - 1];
4094 if (reg_temp_crit_l && reg_temp_crit_l[i])
4095 data->reg_temp[4][src - 1] = reg_temp_crit_l[i];
4096 data->reg_temp_config[src - 1] = reg_temp_config[i];
4097 data->temp_src[src - 1] = src;
4104 /* Use dynamic index for other sources */
4105 data->have_temp |= BIT(s);
4106 data->reg_temp[0][s] = reg_temp[i];
4107 data->reg_temp[1][s] = reg_temp_over[i];
4108 data->reg_temp[2][s] = reg_temp_hyst[i];
4109 data->reg_temp_config[s] = reg_temp_config[i];
4110 if (reg_temp_crit_h && reg_temp_crit_h[i])
4111 data->reg_temp[3][s] = reg_temp_crit_h[i];
4112 else if (reg_temp_crit[src - 1])
4113 data->reg_temp[3][s] = reg_temp_crit[src - 1];
4114 if (reg_temp_crit_l && reg_temp_crit_l[i])
4115 data->reg_temp[4][s] = reg_temp_crit_l[i];
4117 data->temp_src[s] = src;
4122 * Repeat with temperatures used for fan control.
4123 * This set of registers does not support limits.
4125 for (i = 0; i < num_reg_temp_mon; i++) {
4126 if (reg_temp_mon[i] == 0)
4129 src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f;
4133 if (!(data->temp_mask & BIT(src))) {
4135 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4136 src, i, data->REG_TEMP_SEL[i],
4142 * For virtual temperature sources, the 'virtual' temperature
4143 * for each fan reflects a different temperature, and there
4144 * are no duplicates.
4146 if (src != TEMP_SOURCE_VIRTUAL) {
4147 if (mask & BIT(src))
4152 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4153 if (src <= data->temp_fixed_num) {
4154 if (data->have_temp & BIT(src - 1))
4156 data->have_temp |= BIT(src - 1);
4157 data->have_temp_fixed |= BIT(src - 1);
4158 data->reg_temp[0][src - 1] = reg_temp_mon[i];
4159 data->temp_src[src - 1] = src;
4166 /* Use dynamic index for other sources */
4167 data->have_temp |= BIT(s);
4168 data->reg_temp[0][s] = reg_temp_mon[i];
4169 data->temp_src[s] = src;
4173 #ifdef USE_ALTERNATE
4175 * Go through the list of alternate temp registers and enable
4177 * The temperature is already monitored if the respective bit in <mask>
4180 for (i = 0; i < 31; i++) {
4181 if (!(data->temp_mask & BIT(i + 1)))
4183 if (!reg_temp_alternate[i])
4185 if (mask & BIT(i + 1))
4187 if (i < data->temp_fixed_num) {
4188 if (data->have_temp & BIT(i))
4190 data->have_temp |= BIT(i);
4191 data->have_temp_fixed |= BIT(i);
4192 data->reg_temp[0][i] = reg_temp_alternate[i];
4193 if (i < num_reg_temp) {
4194 data->reg_temp[1][i] = reg_temp_over[i];
4195 data->reg_temp[2][i] = reg_temp_hyst[i];
4197 data->temp_src[i] = i + 1;
4201 if (s >= NUM_TEMP) /* Abort if no more space */
4204 data->have_temp |= BIT(s);
4205 data->reg_temp[0][s] = reg_temp_alternate[i];
4206 data->temp_src[s] = i + 1;
4209 #endif /* USE_ALTERNATE */
4211 /* Initialize the chip */
4212 nct6775_init_device(data);
4214 err = superio_enter(sio_data->sioreg);
4218 cr2a = superio_inb(sio_data->sioreg, 0x2a);
4219 switch (data->kind) {
4221 data->have_vid = (cr2a & 0x40);
4224 data->have_vid = (cr2a & 0x60) == 0x40;
4238 * We can get the VID input values directly at logical device D 0xe3.
4240 if (data->have_vid) {
4241 superio_select(sio_data->sioreg, NCT6775_LD_VID);
4242 data->vid = superio_inb(sio_data->sioreg, 0xe3);
4243 data->vrm = vid_which_vrm();
4249 superio_select(sio_data->sioreg, NCT6775_LD_HWM);
4250 tmp = superio_inb(sio_data->sioreg,
4251 NCT6775_REG_CR_FAN_DEBOUNCE);
4252 switch (data->kind) {
4271 superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE,
4273 dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n",
4277 nct6775_check_fan_inputs(data);
4279 superio_exit(sio_data->sioreg);
4281 /* Read fan clock dividers immediately */
4282 nct6775_init_fan_common(dev, data);
4284 /* Register sysfs hooks */
4285 group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group,
4288 return PTR_ERR(group);
4290 data->groups[num_attr_groups++] = group;
4292 group = nct6775_create_attr_group(dev, &nct6775_in_template_group,
4293 fls(data->have_in));
4295 return PTR_ERR(group);
4297 data->groups[num_attr_groups++] = group;
4299 group = nct6775_create_attr_group(dev, &nct6775_fan_template_group,
4300 fls(data->has_fan));
4302 return PTR_ERR(group);
4304 data->groups[num_attr_groups++] = group;
4306 group = nct6775_create_attr_group(dev, &nct6775_temp_template_group,
4307 fls(data->have_temp));
4309 return PTR_ERR(group);
4311 data->groups[num_attr_groups++] = group;
4312 data->groups[num_attr_groups++] = &nct6775_group_other;
4314 hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name,
4315 data, data->groups);
4316 return PTR_ERR_OR_ZERO(hwmon_dev);
4319 static void nct6791_enable_io_mapping(int sioaddr)
4323 val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE);
4325 pr_info("Enabling hardware monitor logical device mappings.\n");
4326 superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE,
4331 static int __maybe_unused nct6775_suspend(struct device *dev)
4333 struct nct6775_data *data = nct6775_update_device(dev);
4335 mutex_lock(&data->update_lock);
4336 data->vbat = nct6775_read_value(data, data->REG_VBAT);
4337 if (data->kind == nct6775) {
4338 data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1);
4339 data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2);
4341 mutex_unlock(&data->update_lock);
4346 static int __maybe_unused nct6775_resume(struct device *dev)
4348 struct nct6775_data *data = dev_get_drvdata(dev);
4349 int sioreg = data->sioreg;
4353 mutex_lock(&data->update_lock);
4354 data->bank = 0xff; /* Force initial bank selection */
4356 err = superio_enter(sioreg);
4360 superio_select(sioreg, NCT6775_LD_HWM);
4361 reg = superio_inb(sioreg, SIO_REG_ENABLE);
4362 if (reg != data->sio_reg_enable)
4363 superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable);
4365 if (data->kind == nct6791 || data->kind == nct6792 ||
4366 data->kind == nct6793 || data->kind == nct6795 ||
4367 data->kind == nct6796)
4368 nct6791_enable_io_mapping(sioreg);
4370 superio_exit(sioreg);
4372 /* Restore limits */
4373 for (i = 0; i < data->in_num; i++) {
4374 if (!(data->have_in & BIT(i)))
4377 nct6775_write_value(data, data->REG_IN_MINMAX[0][i],
4379 nct6775_write_value(data, data->REG_IN_MINMAX[1][i],
4383 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
4384 if (!(data->has_fan_min & BIT(i)))
4387 nct6775_write_value(data, data->REG_FAN_MIN[i],
4391 for (i = 0; i < NUM_TEMP; i++) {
4392 if (!(data->have_temp & BIT(i)))
4395 for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++)
4396 if (data->reg_temp[j][i])
4397 nct6775_write_temp(data, data->reg_temp[j][i],
4401 /* Restore other settings */
4402 nct6775_write_value(data, data->REG_VBAT, data->vbat);
4403 if (data->kind == nct6775) {
4404 nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
4405 nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
4409 /* Force re-reading all values */
4410 data->valid = false;
4411 mutex_unlock(&data->update_lock);
4416 static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume);
4418 static struct platform_driver nct6775_driver = {
4421 .pm = &nct6775_dev_pm_ops,
4423 .probe = nct6775_probe,
4426 /* nct6775_find() looks for a '627 in the Super-I/O config space */
4427 static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
4433 err = superio_enter(sioaddr);
4437 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) |
4438 superio_inb(sioaddr, SIO_REG_DEVID + 1);
4439 if (force_id && val != 0xffff)
4442 switch (val & SIO_ID_MASK) {
4443 case SIO_NCT6106_ID:
4444 sio_data->kind = nct6106;
4446 case SIO_NCT6775_ID:
4447 sio_data->kind = nct6775;
4449 case SIO_NCT6776_ID:
4450 sio_data->kind = nct6776;
4452 case SIO_NCT6779_ID:
4453 sio_data->kind = nct6779;
4455 case SIO_NCT6791_ID:
4456 sio_data->kind = nct6791;
4458 case SIO_NCT6792_ID:
4459 sio_data->kind = nct6792;
4461 case SIO_NCT6793_ID:
4462 sio_data->kind = nct6793;
4464 case SIO_NCT6795_ID:
4465 sio_data->kind = nct6795;
4467 case SIO_NCT6796_ID:
4468 sio_data->kind = nct6796;
4472 pr_debug("unsupported chip ID: 0x%04x\n", val);
4473 superio_exit(sioaddr);
4477 /* We have a known chip, find the HWM I/O address */
4478 superio_select(sioaddr, NCT6775_LD_HWM);
4479 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
4480 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
4481 addr = val & IOREGION_ALIGNMENT;
4483 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
4484 superio_exit(sioaddr);
4488 /* Activate logical device if needed */
4489 val = superio_inb(sioaddr, SIO_REG_ENABLE);
4490 if (!(val & 0x01)) {
4491 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
4492 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
4495 if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
4496 sio_data->kind == nct6793 || sio_data->kind == nct6795 ||
4497 sio_data->kind == nct6796)
4498 nct6791_enable_io_mapping(sioaddr);
4500 superio_exit(sioaddr);
4501 pr_info("Found %s or compatible chip at %#x:%#x\n",
4502 nct6775_sio_names[sio_data->kind], sioaddr, addr);
4503 sio_data->sioreg = sioaddr;
4509 * when Super-I/O functions move to a separate file, the Super-I/O
4510 * bus will manage the lifetime of the device and this module will only keep
4511 * track of the nct6775 driver. But since we use platform_device_alloc(), we
4512 * must keep track of the device
4514 static struct platform_device *pdev[2];
4516 static int __init sensors_nct6775_init(void)
4521 struct resource res;
4522 struct nct6775_sio_data sio_data;
4523 int sioaddr[2] = { 0x2e, 0x4e };
4525 err = platform_driver_register(&nct6775_driver);
4530 * initialize sio_data->kind and sio_data->sioreg.
4532 * when Super-I/O functions move to a separate file, the Super-I/O
4533 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
4534 * nct6775 hardware monitor, and call probe()
4536 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4537 address = nct6775_find(sioaddr[i], &sio_data);
4543 pdev[i] = platform_device_alloc(DRVNAME, address);
4546 goto exit_device_unregister;
4549 err = platform_device_add_data(pdev[i], &sio_data,
4550 sizeof(struct nct6775_sio_data));
4552 goto exit_device_put;
4554 memset(&res, 0, sizeof(res));
4556 res.start = address + IOREGION_OFFSET;
4557 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
4558 res.flags = IORESOURCE_IO;
4560 err = acpi_check_resource_conflict(&res);
4562 platform_device_put(pdev[i]);
4567 err = platform_device_add_resources(pdev[i], &res, 1);
4569 goto exit_device_put;
4571 /* platform_device_add calls probe() */
4572 err = platform_device_add(pdev[i]);
4574 goto exit_device_put;
4578 goto exit_unregister;
4584 platform_device_put(pdev[i]);
4585 exit_device_unregister:
4588 platform_device_unregister(pdev[i]);
4591 platform_driver_unregister(&nct6775_driver);
4595 static void __exit sensors_nct6775_exit(void)
4599 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4601 platform_device_unregister(pdev[i]);
4603 platform_driver_unregister(&nct6775_driver);
4606 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4607 MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips");
4608 MODULE_LICENSE("GPL");
4610 module_init(sensors_nct6775_init);
4611 module_exit(sensors_nct6775_exit);