1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * LTC2992 - Dual Wide Range Power Monitor
5 * Copyright 2020 Analog Devices Inc.
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/err.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/hwmon.h>
13 #include <linux/i2c.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/property.h>
17 #include <linux/regmap.h>
19 #define LTC2992_CTRLB 0x01
20 #define LTC2992_FAULT1 0x03
21 #define LTC2992_POWER1 0x05
22 #define LTC2992_POWER1_MAX 0x08
23 #define LTC2992_POWER1_MIN 0x0B
24 #define LTC2992_POWER1_MAX_THRESH 0x0E
25 #define LTC2992_POWER1_MIN_THRESH 0x11
26 #define LTC2992_DSENSE1 0x14
27 #define LTC2992_DSENSE1_MAX 0x16
28 #define LTC2992_DSENSE1_MIN 0x18
29 #define LTC2992_DSENSE1_MAX_THRESH 0x1A
30 #define LTC2992_DSENSE1_MIN_THRESH 0x1C
31 #define LTC2992_SENSE1 0x1E
32 #define LTC2992_SENSE1_MAX 0x20
33 #define LTC2992_SENSE1_MIN 0x22
34 #define LTC2992_SENSE1_MAX_THRESH 0x24
35 #define LTC2992_SENSE1_MIN_THRESH 0x26
36 #define LTC2992_G1 0x28
37 #define LTC2992_G1_MAX 0x2A
38 #define LTC2992_G1_MIN 0x2C
39 #define LTC2992_G1_MAX_THRESH 0x2E
40 #define LTC2992_G1_MIN_THRESH 0x30
41 #define LTC2992_FAULT2 0x35
42 #define LTC2992_G2 0x5A
43 #define LTC2992_G2_MAX 0x5C
44 #define LTC2992_G2_MIN 0x5E
45 #define LTC2992_G2_MAX_THRESH 0x60
46 #define LTC2992_G2_MIN_THRESH 0x62
47 #define LTC2992_G3 0x64
48 #define LTC2992_G3_MAX 0x66
49 #define LTC2992_G3_MIN 0x68
50 #define LTC2992_G3_MAX_THRESH 0x6A
51 #define LTC2992_G3_MIN_THRESH 0x6C
52 #define LTC2992_G4 0x6E
53 #define LTC2992_G4_MAX 0x70
54 #define LTC2992_G4_MIN 0x72
55 #define LTC2992_G4_MAX_THRESH 0x74
56 #define LTC2992_G4_MIN_THRESH 0x76
57 #define LTC2992_FAULT3 0x92
58 #define LTC2992_GPIO_STATUS 0x95
59 #define LTC2992_GPIO_IO_CTRL 0x96
60 #define LTC2992_GPIO_CTRL 0x97
62 #define LTC2992_POWER(x) (LTC2992_POWER1 + ((x) * 0x32))
63 #define LTC2992_POWER_MAX(x) (LTC2992_POWER1_MAX + ((x) * 0x32))
64 #define LTC2992_POWER_MIN(x) (LTC2992_POWER1_MIN + ((x) * 0x32))
65 #define LTC2992_POWER_MAX_THRESH(x) (LTC2992_POWER1_MAX_THRESH + ((x) * 0x32))
66 #define LTC2992_POWER_MIN_THRESH(x) (LTC2992_POWER1_MIN_THRESH + ((x) * 0x32))
67 #define LTC2992_DSENSE(x) (LTC2992_DSENSE1 + ((x) * 0x32))
68 #define LTC2992_DSENSE_MAX(x) (LTC2992_DSENSE1_MAX + ((x) * 0x32))
69 #define LTC2992_DSENSE_MIN(x) (LTC2992_DSENSE1_MIN + ((x) * 0x32))
70 #define LTC2992_DSENSE_MAX_THRESH(x) (LTC2992_DSENSE1_MAX_THRESH + ((x) * 0x32))
71 #define LTC2992_DSENSE_MIN_THRESH(x) (LTC2992_DSENSE1_MIN_THRESH + ((x) * 0x32))
72 #define LTC2992_SENSE(x) (LTC2992_SENSE1 + ((x) * 0x32))
73 #define LTC2992_SENSE_MAX(x) (LTC2992_SENSE1_MAX + ((x) * 0x32))
74 #define LTC2992_SENSE_MIN(x) (LTC2992_SENSE1_MIN + ((x) * 0x32))
75 #define LTC2992_SENSE_MAX_THRESH(x) (LTC2992_SENSE1_MAX_THRESH + ((x) * 0x32))
76 #define LTC2992_SENSE_MIN_THRESH(x) (LTC2992_SENSE1_MIN_THRESH + ((x) * 0x32))
77 #define LTC2992_POWER_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
78 #define LTC2992_SENSE_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
79 #define LTC2992_DSENSE_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
81 /* CTRLB register bitfields */
82 #define LTC2992_RESET_HISTORY BIT(3)
84 /* FAULT1 FAULT2 registers common bitfields */
85 #define LTC2992_POWER_FAULT_MSK(x) (BIT(6) << (x))
86 #define LTC2992_DSENSE_FAULT_MSK(x) (BIT(4) << (x))
87 #define LTC2992_SENSE_FAULT_MSK(x) (BIT(2) << (x))
89 /* FAULT1 bitfields */
90 #define LTC2992_GPIO1_FAULT_MSK(x) (BIT(0) << (x))
92 /* FAULT2 bitfields */
93 #define LTC2992_GPIO2_FAULT_MSK(x) (BIT(0) << (x))
95 /* FAULT3 bitfields */
96 #define LTC2992_GPIO3_FAULT_MSK(x) (BIT(6) << (x))
97 #define LTC2992_GPIO4_FAULT_MSK(x) (BIT(4) << (x))
99 #define LTC2992_IADC_NANOV_LSB 12500
100 #define LTC2992_VADC_UV_LSB 25000
101 #define LTC2992_VADC_GPIO_UV_LSB 500
103 #define LTC2992_GPIO_NR 4
104 #define LTC2992_GPIO1_BIT 7
105 #define LTC2992_GPIO2_BIT 6
106 #define LTC2992_GPIO3_BIT 0
107 #define LTC2992_GPIO4_BIT 6
108 #define LTC2992_GPIO_BIT(x) (LTC2992_GPIO_NR - (x) - 1)
110 struct ltc2992_state {
111 struct i2c_client *client;
113 struct mutex gpio_mutex; /* lock for gpio access */
114 const char *gpio_names[LTC2992_GPIO_NR];
115 struct regmap *regmap;
119 struct ltc2992_gpio_regs {
132 static const struct ltc2992_gpio_regs ltc2992_gpio_addr_map[] = {
135 .max = LTC2992_G1_MAX,
136 .min = LTC2992_G1_MIN,
137 .max_thresh = LTC2992_G1_MAX_THRESH,
138 .min_thresh = LTC2992_G1_MIN_THRESH,
139 .alarm = LTC2992_FAULT1,
140 .min_alarm_msk = LTC2992_GPIO1_FAULT_MSK(0),
141 .max_alarm_msk = LTC2992_GPIO1_FAULT_MSK(1),
142 .ctrl = LTC2992_GPIO_IO_CTRL,
143 .ctrl_bit = LTC2992_GPIO1_BIT,
147 .max = LTC2992_G2_MAX,
148 .min = LTC2992_G2_MIN,
149 .max_thresh = LTC2992_G2_MAX_THRESH,
150 .min_thresh = LTC2992_G2_MIN_THRESH,
151 .alarm = LTC2992_FAULT2,
152 .min_alarm_msk = LTC2992_GPIO2_FAULT_MSK(0),
153 .max_alarm_msk = LTC2992_GPIO2_FAULT_MSK(1),
154 .ctrl = LTC2992_GPIO_IO_CTRL,
155 .ctrl_bit = LTC2992_GPIO2_BIT,
159 .max = LTC2992_G3_MAX,
160 .min = LTC2992_G3_MIN,
161 .max_thresh = LTC2992_G3_MAX_THRESH,
162 .min_thresh = LTC2992_G3_MIN_THRESH,
163 .alarm = LTC2992_FAULT3,
164 .min_alarm_msk = LTC2992_GPIO3_FAULT_MSK(0),
165 .max_alarm_msk = LTC2992_GPIO3_FAULT_MSK(1),
166 .ctrl = LTC2992_GPIO_IO_CTRL,
167 .ctrl_bit = LTC2992_GPIO3_BIT,
171 .max = LTC2992_G4_MAX,
172 .min = LTC2992_G4_MIN,
173 .max_thresh = LTC2992_G4_MAX_THRESH,
174 .min_thresh = LTC2992_G4_MIN_THRESH,
175 .alarm = LTC2992_FAULT3,
176 .min_alarm_msk = LTC2992_GPIO4_FAULT_MSK(0),
177 .max_alarm_msk = LTC2992_GPIO4_FAULT_MSK(1),
178 .ctrl = LTC2992_GPIO_CTRL,
179 .ctrl_bit = LTC2992_GPIO4_BIT,
183 static const char *ltc2992_gpio_names[LTC2992_GPIO_NR] = {
184 "GPIO1", "GPIO2", "GPIO3", "GPIO4",
187 static int ltc2992_read_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len)
194 ret = regmap_bulk_read(st->regmap, addr, regvals, reg_len);
199 for (i = 0; i < reg_len; i++)
200 val |= regvals[reg_len - i - 1] << (i * 8);
205 static int ltc2992_write_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len, u32 val)
210 for (i = 0; i < reg_len; i++)
211 regvals[reg_len - i - 1] = (val >> (i * 8)) & 0xFF;
213 return regmap_bulk_write(st->regmap, addr, regvals, reg_len);
216 static int ltc2992_gpio_get(struct gpio_chip *chip, unsigned int offset)
218 struct ltc2992_state *st = gpiochip_get_data(chip);
219 unsigned long gpio_status;
222 mutex_lock(&st->gpio_mutex);
223 reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
224 mutex_unlock(&st->gpio_mutex);
231 return !test_bit(LTC2992_GPIO_BIT(offset), &gpio_status);
234 static int ltc2992_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
237 struct ltc2992_state *st = gpiochip_get_data(chip);
238 unsigned long gpio_status;
239 unsigned int gpio_nr;
242 mutex_lock(&st->gpio_mutex);
243 reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
244 mutex_unlock(&st->gpio_mutex);
252 for_each_set_bit_from(gpio_nr, mask, LTC2992_GPIO_NR) {
253 if (test_bit(LTC2992_GPIO_BIT(gpio_nr), &gpio_status))
254 set_bit(gpio_nr, bits);
260 static void ltc2992_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
262 struct ltc2992_state *st = gpiochip_get_data(chip);
263 unsigned long gpio_ctrl;
266 mutex_lock(&st->gpio_mutex);
267 reg = ltc2992_read_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1);
269 mutex_unlock(&st->gpio_mutex);
274 assign_bit(ltc2992_gpio_addr_map[offset].ctrl_bit, &gpio_ctrl, value);
276 ltc2992_write_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1, gpio_ctrl);
277 mutex_unlock(&st->gpio_mutex);
280 static void ltc2992_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
283 struct ltc2992_state *st = gpiochip_get_data(chip);
284 unsigned long gpio_ctrl_io = 0;
285 unsigned long gpio_ctrl = 0;
286 unsigned int gpio_nr;
288 for_each_set_bit(gpio_nr, mask, LTC2992_GPIO_NR) {
290 assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl_io, true);
293 assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl, true);
296 mutex_lock(&st->gpio_mutex);
297 ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, gpio_ctrl_io);
298 ltc2992_write_reg(st, LTC2992_GPIO_CTRL, 1, gpio_ctrl);
299 mutex_unlock(&st->gpio_mutex);
302 static int ltc2992_config_gpio(struct ltc2992_state *st)
304 const char *name = dev_name(&st->client->dev);
309 ret = ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, 0);
313 mutex_init(&st->gpio_mutex);
315 for (i = 0; i < ARRAY_SIZE(st->gpio_names); i++) {
316 gpio_name = devm_kasprintf(&st->client->dev, GFP_KERNEL, "ltc2992-%x-%s",
317 st->client->addr, ltc2992_gpio_names[i]);
321 st->gpio_names[i] = gpio_name;
325 st->gc.parent = &st->client->dev;
326 st->gc.owner = THIS_MODULE;
328 st->gc.names = st->gpio_names;
329 st->gc.ngpio = ARRAY_SIZE(st->gpio_names);
330 st->gc.get = ltc2992_gpio_get;
331 st->gc.get_multiple = ltc2992_gpio_get_multiple;
332 st->gc.set = ltc2992_gpio_set;
333 st->gc.set_multiple = ltc2992_gpio_set_multiple;
335 ret = devm_gpiochip_add_data(&st->client->dev, &st->gc, st);
337 dev_err(&st->client->dev, "GPIO registering failed (%d)\n", ret);
342 static umode_t ltc2992_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr,
345 const struct ltc2992_state *st = data;
350 case hwmon_chip_in_reset_history:
357 case hwmon_in_lowest:
358 case hwmon_in_highest:
359 case hwmon_in_min_alarm:
360 case hwmon_in_max_alarm:
369 case hwmon_curr_input:
370 case hwmon_curr_lowest:
371 case hwmon_curr_highest:
372 case hwmon_curr_min_alarm:
373 case hwmon_curr_max_alarm:
374 if (st->r_sense_uohm[channel])
379 if (st->r_sense_uohm[channel])
386 case hwmon_power_input:
387 case hwmon_power_input_lowest:
388 case hwmon_power_input_highest:
389 case hwmon_power_min_alarm:
390 case hwmon_power_max_alarm:
391 if (st->r_sense_uohm[channel])
394 case hwmon_power_min:
395 case hwmon_power_max:
396 if (st->r_sense_uohm[channel])
408 static int ltc2992_get_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long *val)
412 reg_val = ltc2992_read_reg(st, reg, 2);
416 reg_val = reg_val >> 4;
417 *val = DIV_ROUND_CLOSEST(reg_val * scale, 1000);
422 static int ltc2992_set_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long val)
424 val = DIV_ROUND_CLOSEST(val * 1000, scale);
427 return ltc2992_write_reg(st, reg, 2, val);
430 static int ltc2992_read_gpio_alarm(struct ltc2992_state *st, int nr_gpio, u32 attr, long *val)
435 if (attr == hwmon_in_max_alarm)
436 mask = ltc2992_gpio_addr_map[nr_gpio].max_alarm_msk;
438 mask = ltc2992_gpio_addr_map[nr_gpio].min_alarm_msk;
440 reg_val = ltc2992_read_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1);
444 *val = !!(reg_val & mask);
447 return ltc2992_write_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1, reg_val);
450 static int ltc2992_read_gpios_in(struct device *dev, u32 attr, int nr_gpio, long *val)
452 struct ltc2992_state *st = dev_get_drvdata(dev);
457 reg = ltc2992_gpio_addr_map[nr_gpio].data;
459 case hwmon_in_lowest:
460 reg = ltc2992_gpio_addr_map[nr_gpio].min;
462 case hwmon_in_highest:
463 reg = ltc2992_gpio_addr_map[nr_gpio].max;
466 reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
469 reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
471 case hwmon_in_min_alarm:
472 case hwmon_in_max_alarm:
473 return ltc2992_read_gpio_alarm(st, nr_gpio, attr, val);
478 return ltc2992_get_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
481 static int ltc2992_read_in_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
486 if (attr == hwmon_in_max_alarm)
487 mask = LTC2992_SENSE_FAULT_MSK(1);
489 mask = LTC2992_SENSE_FAULT_MSK(0);
491 reg_val = ltc2992_read_reg(st, LTC2992_SENSE_FAULT(channel), 1);
495 *val = !!(reg_val & mask);
498 return ltc2992_write_reg(st, LTC2992_SENSE_FAULT(channel), 1, reg_val);
501 static int ltc2992_read_in(struct device *dev, u32 attr, int channel, long *val)
503 struct ltc2992_state *st = dev_get_drvdata(dev);
507 return ltc2992_read_gpios_in(dev, attr, channel - 2, val);
511 reg = LTC2992_SENSE(channel);
513 case hwmon_in_lowest:
514 reg = LTC2992_SENSE_MIN(channel);
516 case hwmon_in_highest:
517 reg = LTC2992_SENSE_MAX(channel);
520 reg = LTC2992_SENSE_MIN_THRESH(channel);
523 reg = LTC2992_SENSE_MAX_THRESH(channel);
525 case hwmon_in_min_alarm:
526 case hwmon_in_max_alarm:
527 return ltc2992_read_in_alarm(st, channel, val, attr);
532 return ltc2992_get_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
535 static int ltc2992_get_current(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
539 reg_val = ltc2992_read_reg(st, reg, 2);
543 reg_val = reg_val >> 4;
544 *val = DIV_ROUND_CLOSEST(reg_val * LTC2992_IADC_NANOV_LSB, st->r_sense_uohm[channel]);
549 static int ltc2992_set_current(struct ltc2992_state *st, u32 reg, u32 channel, long val)
553 reg_val = DIV_ROUND_CLOSEST(val * st->r_sense_uohm[channel], LTC2992_IADC_NANOV_LSB);
554 reg_val = reg_val << 4;
556 return ltc2992_write_reg(st, reg, 2, reg_val);
559 static int ltc2992_read_curr_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
564 if (attr == hwmon_curr_max_alarm)
565 mask = LTC2992_DSENSE_FAULT_MSK(1);
567 mask = LTC2992_DSENSE_FAULT_MSK(0);
569 reg_val = ltc2992_read_reg(st, LTC2992_DSENSE_FAULT(channel), 1);
573 *val = !!(reg_val & mask);
576 return ltc2992_write_reg(st, LTC2992_DSENSE_FAULT(channel), 1, reg_val);
579 static int ltc2992_read_curr(struct device *dev, u32 attr, int channel, long *val)
581 struct ltc2992_state *st = dev_get_drvdata(dev);
585 case hwmon_curr_input:
586 reg = LTC2992_DSENSE(channel);
588 case hwmon_curr_lowest:
589 reg = LTC2992_DSENSE_MIN(channel);
591 case hwmon_curr_highest:
592 reg = LTC2992_DSENSE_MAX(channel);
595 reg = LTC2992_DSENSE_MIN_THRESH(channel);
598 reg = LTC2992_DSENSE_MAX_THRESH(channel);
600 case hwmon_curr_min_alarm:
601 case hwmon_curr_max_alarm:
602 return ltc2992_read_curr_alarm(st, channel, val, attr);
607 return ltc2992_get_current(st, reg, channel, val);
610 static int ltc2992_get_power(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
614 reg_val = ltc2992_read_reg(st, reg, 3);
618 *val = mul_u64_u32_div(reg_val, LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB,
619 st->r_sense_uohm[channel] * 1000);
624 static int ltc2992_set_power(struct ltc2992_state *st, u32 reg, u32 channel, long val)
628 reg_val = mul_u64_u32_div(val, st->r_sense_uohm[channel] * 1000,
629 LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB);
631 return ltc2992_write_reg(st, reg, 3, reg_val);
634 static int ltc2992_read_power_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
639 if (attr == hwmon_power_max_alarm)
640 mask = LTC2992_POWER_FAULT_MSK(1);
642 mask = LTC2992_POWER_FAULT_MSK(0);
644 reg_val = ltc2992_read_reg(st, LTC2992_POWER_FAULT(channel), 1);
648 *val = !!(reg_val & mask);
651 return ltc2992_write_reg(st, LTC2992_POWER_FAULT(channel), 1, reg_val);
654 static int ltc2992_read_power(struct device *dev, u32 attr, int channel, long *val)
656 struct ltc2992_state *st = dev_get_drvdata(dev);
660 case hwmon_power_input:
661 reg = LTC2992_POWER(channel);
663 case hwmon_power_input_lowest:
664 reg = LTC2992_POWER_MIN(channel);
666 case hwmon_power_input_highest:
667 reg = LTC2992_POWER_MAX(channel);
669 case hwmon_power_min:
670 reg = LTC2992_POWER_MIN_THRESH(channel);
672 case hwmon_power_max:
673 reg = LTC2992_POWER_MAX_THRESH(channel);
675 case hwmon_power_min_alarm:
676 case hwmon_power_max_alarm:
677 return ltc2992_read_power_alarm(st, channel, val, attr);
682 return ltc2992_get_power(st, reg, channel, val);
685 static int ltc2992_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
690 return ltc2992_read_in(dev, attr, channel, val);
692 return ltc2992_read_curr(dev, attr, channel, val);
694 return ltc2992_read_power(dev, attr, channel, val);
700 static int ltc2992_write_curr(struct device *dev, u32 attr, int channel, long val)
702 struct ltc2992_state *st = dev_get_drvdata(dev);
707 reg = LTC2992_DSENSE_MIN_THRESH(channel);
710 reg = LTC2992_DSENSE_MAX_THRESH(channel);
716 return ltc2992_set_current(st, reg, channel, val);
719 static int ltc2992_write_gpios_in(struct device *dev, u32 attr, int nr_gpio, long val)
721 struct ltc2992_state *st = dev_get_drvdata(dev);
726 reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
729 reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
735 return ltc2992_set_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
738 static int ltc2992_write_in(struct device *dev, u32 attr, int channel, long val)
740 struct ltc2992_state *st = dev_get_drvdata(dev);
744 return ltc2992_write_gpios_in(dev, attr, channel - 2, val);
748 reg = LTC2992_SENSE_MIN_THRESH(channel);
751 reg = LTC2992_SENSE_MAX_THRESH(channel);
757 return ltc2992_set_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
760 static int ltc2992_write_power(struct device *dev, u32 attr, int channel, long val)
762 struct ltc2992_state *st = dev_get_drvdata(dev);
766 case hwmon_power_min:
767 reg = LTC2992_POWER_MIN_THRESH(channel);
769 case hwmon_power_max:
770 reg = LTC2992_POWER_MAX_THRESH(channel);
776 return ltc2992_set_power(st, reg, channel, val);
779 static int ltc2992_write_chip(struct device *dev, u32 attr, int channel, long val)
781 struct ltc2992_state *st = dev_get_drvdata(dev);
784 case hwmon_chip_in_reset_history:
785 return regmap_update_bits(st->regmap, LTC2992_CTRLB, LTC2992_RESET_HISTORY,
786 LTC2992_RESET_HISTORY);
792 static int ltc2992_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
797 return ltc2992_write_chip(dev, attr, channel, val);
799 return ltc2992_write_in(dev, attr, channel, val);
801 return ltc2992_write_curr(dev, attr, channel, val);
803 return ltc2992_write_power(dev, attr, channel, val);
809 static const struct hwmon_ops ltc2992_hwmon_ops = {
810 .is_visible = ltc2992_is_visible,
811 .read = ltc2992_read,
812 .write = ltc2992_write,
815 static const u32 ltc2992_chip_config[] = {
816 HWMON_C_IN_RESET_HISTORY,
820 static const struct hwmon_channel_info ltc2992_chip = {
822 .config = ltc2992_chip_config,
825 static const u32 ltc2992_in_config[] = {
826 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
827 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
828 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
829 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
830 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
831 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
832 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
833 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
834 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
835 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
836 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN | HWMON_I_MAX |
837 HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
841 static const struct hwmon_channel_info ltc2992_in = {
843 .config = ltc2992_in_config,
846 static const u32 ltc2992_curr_config[] = {
847 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN | HWMON_C_MAX |
848 HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM,
849 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN | HWMON_C_MAX |
850 HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM,
854 static const struct hwmon_channel_info ltc2992_curr = {
856 .config = ltc2992_curr_config,
859 static const u32 ltc2992_power_config[] = {
860 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST | HWMON_P_MIN | HWMON_P_MAX |
861 HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM,
862 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST | HWMON_P_MIN | HWMON_P_MAX |
863 HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM,
867 static const struct hwmon_channel_info ltc2992_power = {
869 .config = ltc2992_power_config,
872 static const struct hwmon_channel_info *ltc2992_info[] = {
880 static const struct hwmon_chip_info ltc2992_chip_info = {
881 .ops = <c2992_hwmon_ops,
882 .info = ltc2992_info,
885 static const struct regmap_config ltc2992_regmap_config = {
888 .max_register = 0xE8,
891 static int ltc2992_parse_dt(struct ltc2992_state *st)
893 struct fwnode_handle *fwnode;
894 struct fwnode_handle *child;
899 fwnode = dev_fwnode(&st->client->dev);
901 fwnode_for_each_available_child_node(fwnode, child) {
902 ret = fwnode_property_read_u32(child, "reg", &addr);
904 fwnode_handle_put(child);
909 fwnode_handle_put(child);
913 ret = fwnode_property_read_u32(child, "shunt-resistor-micro-ohms", &val);
915 st->r_sense_uohm[addr] = val;
921 static int ltc2992_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
923 struct device *hwmon_dev;
924 struct ltc2992_state *st;
927 st = devm_kzalloc(&client->dev, sizeof(*st), GFP_KERNEL);
932 st->regmap = devm_regmap_init_i2c(client, <c2992_regmap_config);
933 if (IS_ERR(st->regmap))
934 return PTR_ERR(st->regmap);
936 ret = ltc2992_parse_dt(st);
940 ret = ltc2992_config_gpio(st);
944 hwmon_dev = devm_hwmon_device_register_with_info(&client->dev, client->name, st,
945 <c2992_chip_info, NULL);
947 return PTR_ERR_OR_ZERO(hwmon_dev);
950 static const struct of_device_id ltc2992_of_match[] = {
951 { .compatible = "adi,ltc2992" },
954 MODULE_DEVICE_TABLE(of, ltc2992_of_match);
956 static const struct i2c_device_id ltc2992_i2c_id[] = {
960 MODULE_DEVICE_TABLE(i2c, ltc2992_i2c_id);
962 static struct i2c_driver ltc2992_i2c_driver = {
965 .of_match_table = ltc2992_of_match,
967 .probe = ltc2992_i2c_probe,
968 .id_table = ltc2992_i2c_id,
971 module_i2c_driver(ltc2992_i2c_driver);
973 MODULE_AUTHOR("Alexandru Tachici <alexandru.tachici@analog.com>");
974 MODULE_DESCRIPTION("Hwmon driver for Linear Technology 2992");
975 MODULE_LICENSE("Dual BSD/GPL");