drivers/hwmon/k10temp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
   4  *              processor hardware monitoring
   5  *
   6  * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
   7  * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
   8  *
   9  * Implementation notes:
  10  * - CCD register address information as well as the calculation to
  11  *   convert raw register values is from https://github.com/ocerman/zenpower.
  12  *   The information is not confirmed from chip datasheets, but experiments
  13  *   suggest that it provides reasonable temperature values.
  14  * - Register addresses to read chip voltage and current are also from
  15  *   https://github.com/ocerman/zenpower, and not confirmed from chip
  16  *   datasheets. Current calibration is board specific and not typically
  17  *   shared by board vendors. For this reason, current values are
  18  *   normalized to report 1A/LSB for core current and and 0.25A/LSB for SoC
  19  *   current. Reported values can be adjusted using the sensors configuration
  20  *   file.
  21  */
  22
  23 #include <linux/bitops.h>
  24 #include <linux/err.h>
  25 #include <linux/hwmon.h>
  26 #include <linux/init.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include <linux/pci_ids.h>
  30 #include <asm/amd_nb.h>
  31 #include <asm/processor.h>
  32
  33 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
  34 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  35 MODULE_LICENSE("GPL");
  36
  37 static bool force;
  38 module_param(force, bool, 0444);
  39 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
  40
  41 /* Provide lock for writing to NB_SMU_IND_ADDR */
  42 static DEFINE_MUTEX(nb_smu_ind_mutex);
  43
  44 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
  45 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3        0x15b3
  46 #endif
  47
  48 /* CPUID function 0x80000001, ebx */
  49 #define CPUID_PKGTYPE_MASK      GENMASK(31, 28)
  50 #define CPUID_PKGTYPE_F         0x00000000
  51 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
  52
  53 /* DRAM controller (PCI function 2) */
  54 #define REG_DCT0_CONFIG_HIGH            0x094
  55 #define  DDR3_MODE                      BIT(8)
  56
  57 /* miscellaneous (PCI function 3) */
  58 #define REG_HARDWARE_THERMAL_CONTROL    0x64
  59 #define  HTC_ENABLE                     BIT(0)
  60
  61 #define REG_REPORTED_TEMPERATURE        0xa4
  62
  63 #define REG_NORTHBRIDGE_CAPABILITIES    0xe8
  64 #define  NB_CAP_HTC                     BIT(10)
  65
  66 /*
  67  * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
  68  * and REG_REPORTED_TEMPERATURE have been moved to
  69  * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
  70  * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
  71  */
  72 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET     0xd8200c64
  73 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET     0xd8200ca4
  74
  75 /* Common for Zen CPU families (Family 17h and 18h) */
  76 #define ZEN_REPORTED_TEMP_CTRL_OFFSET           0x00059800
  77
  78 #define ZEN_CCD_TEMP(x)                         (0x00059954 + ((x) * 4))
  79 #define ZEN_CCD_TEMP_VALID                      BIT(11)
  80 #define ZEN_CCD_TEMP_MASK                       GENMASK(10, 0)
  81
  82 #define ZEN_CUR_TEMP_SHIFT                      21
  83 #define ZEN_CUR_TEMP_RANGE_SEL_MASK             BIT(19)
  84
  85 #define ZEN_SVI_BASE                            0x0005A000
  86
  87 /* F17h thermal registers through SMN */
  88 #define F17H_M01H_SVI_TEL_PLANE0                (ZEN_SVI_BASE + 0xc)
  89 #define F17H_M01H_SVI_TEL_PLANE1                (ZEN_SVI_BASE + 0x10)
  90 #define F17H_M31H_SVI_TEL_PLANE0                (ZEN_SVI_BASE + 0x14)
  91 #define F17H_M31H_SVI_TEL_PLANE1                (ZEN_SVI_BASE + 0x10)
  92
  93 #define F17H_M01H_CFACTOR_ICORE                 1000000 /* 1A / LSB     */
  94 #define F17H_M01H_CFACTOR_ISOC                  250000  /* 0.25A / LSB  */
  95 #define F17H_M31H_CFACTOR_ICORE                 1000000 /* 1A / LSB     */
  96 #define F17H_M31H_CFACTOR_ISOC                  310000  /* 0.31A / LSB  */
  97
  98 /* F19h thermal registers through SMN */
  99 #define F19H_M01_SVI_TEL_PLANE0                 (ZEN_SVI_BASE + 0x14)
 100 #define F19H_M01_SVI_TEL_PLANE1                 (ZEN_SVI_BASE + 0x10)
 101
 102 #define F19H_M01H_CFACTOR_ICORE                 1000000 /* 1A / LSB     */
 103 #define F19H_M01H_CFACTOR_ISOC                  310000  /* 0.31A / LSB  */
 104
 105 struct k10temp_data {
 106         struct pci_dev *pdev;
 107         void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
 108         void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
 109         int temp_offset;
 110         u32 temp_adjust_mask;
 111         u32 show_temp;
 112         u32 svi_addr[2];
 113         bool is_zen;
 114         bool show_current;
 115         int cfactor[2];
 116 };
 117
 118 #define TCTL_BIT        0
 119 #define TDIE_BIT        1
 120 #define TCCD_BIT(x)     ((x) + 2)
 121
 122 #define HAVE_TEMP(d, channel)   ((d)->show_temp & BIT(channel))
 123 #define HAVE_TDIE(d)            HAVE_TEMP(d, TDIE_BIT)
 124
 125 struct tctl_offset {
 126         u8 model;
 127         char const *id;
 128         int offset;
 129 };
 130
 131 static const struct tctl_offset tctl_offset_table[] = {
 132         { 0x17, "AMD Ryzen 5 1600X", 20000 },
 133         { 0x17, "AMD Ryzen 7 1700X", 20000 },
 134         { 0x17, "AMD Ryzen 7 1800X", 20000 },
 135         { 0x17, "AMD Ryzen 7 2700X", 10000 },
 136         { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
 137         { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
 138 };
 139
 140 static bool is_threadripper(void)
 141 {
 142         return strstr(boot_cpu_data.x86_model_id, "Threadripper");
 143 }
 144
 145 static bool is_epyc(void)
 146 {
 147         return strstr(boot_cpu_data.x86_model_id, "EPYC");
 148 }
 149
 150 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
 151 {
 152         pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
 153 }
 154
 155 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
 156 {
 157         pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
 158 }
 159
 160 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
 161                               unsigned int base, int offset, u32 *val)
 162 {
 163         mutex_lock(&nb_smu_ind_mutex);
 164         pci_bus_write_config_dword(pdev->bus, devfn,
 165                                    base, offset);
 166         pci_bus_read_config_dword(pdev->bus, devfn,
 167                                   base + 4, val);
 168         mutex_unlock(&nb_smu_ind_mutex);
 169 }
 170
 171 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
 172 {
 173         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
 174                           F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
 175 }
 176
 177 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
 178 {
 179         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
 180                           F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
 181 }
 182
 183 static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
 184 {
 185         amd_smn_read(amd_pci_dev_to_node_id(pdev),
 186                      ZEN_REPORTED_TEMP_CTRL_OFFSET, regval);
 187 }
 188
 189 static long get_raw_temp(struct k10temp_data *data)
 190 {
 191         u32 regval;
 192         long temp;
 193
 194         data->read_tempreg(data->pdev, &regval);
 195         temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
 196         if (regval & data->temp_adjust_mask)
 197                 temp -= 49000;
 198         return temp;
 199 }
 200
 201 static const char *k10temp_temp_label[] = {
 202         "Tctl",
 203         "Tdie",
 204         "Tccd1",
 205         "Tccd2",
 206         "Tccd3",
 207         "Tccd4",
 208         "Tccd5",
 209         "Tccd6",
 210         "Tccd7",
 211         "Tccd8",
 212 };
 213
 214 static const char *k10temp_in_label[] = {
 215         "Vcore",
 216         "Vsoc",
 217 };
 218
 219 static const char *k10temp_curr_label[] = {
 220         "Icore",
 221         "Isoc",
 222 };
 223
 224 static int k10temp_read_labels(struct device *dev,
 225                                enum hwmon_sensor_types type,
 226                                u32 attr, int channel, const char **str)
 227 {
 228         switch (type) {
 229         case hwmon_temp:
 230                 *str = k10temp_temp_label[channel];
 231                 break;
 232         case hwmon_in:
 233                 *str = k10temp_in_label[channel];
 234                 break;
 235         case hwmon_curr:
 236                 *str = k10temp_curr_label[channel];
 237                 break;
 238         default:
 239                 return -EOPNOTSUPP;
 240         }
 241         return 0;
 242 }
 243
 244 static int k10temp_read_curr(struct device *dev, u32 attr, int channel,
 245                              long *val)
 246 {
 247         struct k10temp_data *data = dev_get_drvdata(dev);
 248         u32 regval;
 249
 250         switch (attr) {
 251         case hwmon_curr_input:
 252                 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 253                              data->svi_addr[channel], &regval);
 254                 *val = DIV_ROUND_CLOSEST(data->cfactor[channel] *
 255                                          (regval & 0xff),
 256                                          1000);
 257                 break;
 258         default:
 259                 return -EOPNOTSUPP;
 260         }
 261         return 0;
 262 }
 263
 264 static int k10temp_read_in(struct device *dev, u32 attr, int channel, long *val)
 265 {
 266         struct k10temp_data *data = dev_get_drvdata(dev);
 267         u32 regval;
 268
 269         switch (attr) {
 270         case hwmon_in_input:
 271                 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 272                              data->svi_addr[channel], &regval);
 273                 regval = (regval >> 16) & 0xff;
 274                 *val = DIV_ROUND_CLOSEST(155000 - regval * 625, 100);
 275                 break;
 276         default:
 277                 return -EOPNOTSUPP;
 278         }
 279         return 0;
 280 }
 281
 282 static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
 283                              long *val)
 284 {
 285         struct k10temp_data *data = dev_get_drvdata(dev);
 286         u32 regval;
 287
 288         switch (attr) {
 289         case hwmon_temp_input:
 290                 switch (channel) {
 291                 case 0:         /* Tctl */
 292                         *val = get_raw_temp(data);
 293                         if (*val < 0)
 294                                 *val = 0;
 295                         break;
 296                 case 1:         /* Tdie */
 297                         *val = get_raw_temp(data) - data->temp_offset;
 298                         if (*val < 0)
 299                                 *val = 0;
 300                         break;
 301                 case 2 ... 9:           /* Tccd{1-8} */
 302                         amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 303                                      ZEN_CCD_TEMP(channel - 2), &regval);
 304                         *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
 305                         break;
 306                 default:
 307                         return -EOPNOTSUPP;
 308                 }
 309                 break;
 310         case hwmon_temp_max:
 311                 *val = 70 * 1000;
 312                 break;
 313         case hwmon_temp_crit:
 314                 data->read_htcreg(data->pdev, &regval);
 315                 *val = ((regval >> 16) & 0x7f) * 500 + 52000;
 316                 break;
 317         case hwmon_temp_crit_hyst:
 318                 data->read_htcreg(data->pdev, &regval);
 319                 *val = (((regval >> 16) & 0x7f)
 320                         - ((regval >> 24) & 0xf)) * 500 + 52000;
 321                 break;
 322         default:
 323                 return -EOPNOTSUPP;
 324         }
 325         return 0;
 326 }
 327
 328 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
 329                         u32 attr, int channel, long *val)
 330 {
 331         switch (type) {
 332         case hwmon_temp:
 333                 return k10temp_read_temp(dev, attr, channel, val);
 334         case hwmon_in:
 335                 return k10temp_read_in(dev, attr, channel, val);
 336         case hwmon_curr:
 337                 return k10temp_read_curr(dev, attr, channel, val);
 338         default:
 339                 return -EOPNOTSUPP;
 340         }
 341 }
 342
 343 static umode_t k10temp_is_visible(const void *_data,
 344                                   enum hwmon_sensor_types type,
 345                                   u32 attr, int channel)
 346 {
 347         const struct k10temp_data *data = _data;
 348         struct pci_dev *pdev = data->pdev;
 349         u32 reg;
 350
 351         switch (type) {
 352         case hwmon_temp:
 353                 switch (attr) {
 354                 case hwmon_temp_input:
 355                         if (!HAVE_TEMP(data, channel))
 356                                 return 0;
 357                         break;
 358                 case hwmon_temp_max:
 359                         if (channel || data->is_zen)
 360                                 return 0;
 361                         break;
 362                 case hwmon_temp_crit:
 363                 case hwmon_temp_crit_hyst:
 364                         if (channel || !data->read_htcreg)
 365                                 return 0;
 366
 367                         pci_read_config_dword(pdev,
 368                                               REG_NORTHBRIDGE_CAPABILITIES,
 369                                               &reg);
 370                         if (!(reg & NB_CAP_HTC))
 371                                 return 0;
 372
 373                         data->read_htcreg(data->pdev, &reg);
 374                         if (!(reg & HTC_ENABLE))
 375                                 return 0;
 376                         break;
 377                 case hwmon_temp_label:
 378                         /* Show temperature labels only on Zen CPUs */
 379                         if (!data->is_zen || !HAVE_TEMP(data, channel))
 380                                 return 0;
 381                         break;
 382                 default:
 383                         return 0;
 384                 }
 385                 break;
 386         case hwmon_in:
 387         case hwmon_curr:
 388                 if (!data->show_current)
 389                         return 0;
 390                 break;
 391         default:
 392                 return 0;
 393         }
 394         return 0444;
 395 }
 396
 397 static bool has_erratum_319(struct pci_dev *pdev)
 398 {
 399         u32 pkg_type, reg_dram_cfg;
 400
 401         if (boot_cpu_data.x86 != 0x10)
 402                 return false;
 403
 404         /*
 405          * Erratum 319: The thermal sensor of Socket F/AM2+ processors
 406          *              may be unreliable.
 407          */
 408         pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
 409         if (pkg_type == CPUID_PKGTYPE_F)
 410                 return true;
 411         if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
 412                 return false;
 413
 414         /* DDR3 memory implies socket AM3, which is good */
 415         pci_bus_read_config_dword(pdev->bus,
 416                                   PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
 417                                   REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
 418         if (reg_dram_cfg & DDR3_MODE)
 419                 return false;
 420
 421         /*
 422          * Unfortunately it is possible to run a socket AM3 CPU with DDR2
 423          * memory. We blacklist all the cores which do exist in socket AM2+
 424          * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
 425          * and AM3 formats, but that's the best we can do.
 426          */
 427         return boot_cpu_data.x86_model < 4 ||
 428                (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
 429 }
 430
 431 static const struct hwmon_channel_info *k10temp_info[] = {
 432         HWMON_CHANNEL_INFO(temp,
 433                            HWMON_T_INPUT | HWMON_T_MAX |
 434                            HWMON_T_CRIT | HWMON_T_CRIT_HYST |
 435                            HWMON_T_LABEL,
 436                            HWMON_T_INPUT | HWMON_T_LABEL,
 437                            HWMON_T_INPUT | HWMON_T_LABEL,
 438                            HWMON_T_INPUT | HWMON_T_LABEL,
 439                            HWMON_T_INPUT | HWMON_T_LABEL,
 440                            HWMON_T_INPUT | HWMON_T_LABEL,
 441                            HWMON_T_INPUT | HWMON_T_LABEL,
 442                            HWMON_T_INPUT | HWMON_T_LABEL,
 443                            HWMON_T_INPUT | HWMON_T_LABEL,
 444                            HWMON_T_INPUT | HWMON_T_LABEL),
 445         HWMON_CHANNEL_INFO(in,
 446                            HWMON_I_INPUT | HWMON_I_LABEL,
 447                            HWMON_I_INPUT | HWMON_I_LABEL),
 448         HWMON_CHANNEL_INFO(curr,
 449                            HWMON_C_INPUT | HWMON_C_LABEL,
 450                            HWMON_C_INPUT | HWMON_C_LABEL),
 451         NULL
 452 };
 453
 454 static const struct hwmon_ops k10temp_hwmon_ops = {
 455         .is_visible = k10temp_is_visible,
 456         .read = k10temp_read,
 457         .read_string = k10temp_read_labels,
 458 };
 459
 460 static const struct hwmon_chip_info k10temp_chip_info = {
 461         .ops = &k10temp_hwmon_ops,
 462         .info = k10temp_info,
 463 };
 464
 465 static void k10temp_get_ccd_support(struct pci_dev *pdev,
 466                                     struct k10temp_data *data, int limit)
 467 {
 468         u32 regval;
 469         int i;
 470
 471         for (i = 0; i < limit; i++) {
 472                 amd_smn_read(amd_pci_dev_to_node_id(pdev),
 473                              ZEN_CCD_TEMP(i), &regval);
 474                 if (regval & ZEN_CCD_TEMP_VALID)
 475                         data->show_temp |= BIT(TCCD_BIT(i));
 476         }
 477 }
 478
 479 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 480 {
 481         int unreliable = has_erratum_319(pdev);
 482         struct device *dev = &pdev->dev;
 483         struct k10temp_data *data;
 484         struct device *hwmon_dev;
 485         int i;
 486
 487         if (unreliable) {
 488                 if (!force) {
 489                         dev_err(dev,
 490                                 "unreliable CPU thermal sensor; monitoring disabled\n");
 491                         return -ENODEV;
 492                 }
 493                 dev_warn(dev,
 494                          "unreliable CPU thermal sensor; check erratum 319\n");
 495         }
 496
 497         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 498         if (!data)
 499                 return -ENOMEM;
 500
 501         data->pdev = pdev;
 502         data->show_temp |= BIT(TCTL_BIT);       /* Always show Tctl */
 503
 504         if (boot_cpu_data.x86 == 0x15 &&
 505             ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
 506              (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
 507                 data->read_htcreg = read_htcreg_nb_f15;
 508                 data->read_tempreg = read_tempreg_nb_f15;
 509         } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
 510                 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
 511                 data->read_tempreg = read_tempreg_nb_zen;
 512                 data->show_temp |= BIT(TDIE_BIT);       /* show Tdie */
 513                 data->is_zen = true;
 514
 515                 switch (boot_cpu_data.x86_model) {
 516                 case 0x1:       /* Zen */
 517                 case 0x8:       /* Zen+ */
 518                 case 0x11:      /* Zen APU */
 519                 case 0x18:      /* Zen+ APU */
 520                         data->show_current = !is_threadripper() && !is_epyc();
 521                         data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE0;
 522                         data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1;
 523                         data->cfactor[0] = F17H_M01H_CFACTOR_ICORE;
 524                         data->cfactor[1] = F17H_M01H_CFACTOR_ISOC;
 525                         k10temp_get_ccd_support(pdev, data, 4);
 526                         break;
 527                 case 0x31:      /* Zen2 Threadripper */
 528                 case 0x71:      /* Zen2 */
 529                         data->show_current = !is_threadripper() && !is_epyc();
 530                         data->cfactor[0] = F17H_M31H_CFACTOR_ICORE;
 531                         data->cfactor[1] = F17H_M31H_CFACTOR_ISOC;
 532                         data->svi_addr[0] = F17H_M31H_SVI_TEL_PLANE0;
 533                         data->svi_addr[1] = F17H_M31H_SVI_TEL_PLANE1;
 534                         k10temp_get_ccd_support(pdev, data, 8);
 535                         break;
 536                 }
 537         } else if (boot_cpu_data.x86 == 0x19) {
 538                 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
 539                 data->read_tempreg = read_tempreg_nb_zen;
 540                 data->show_temp |= BIT(TDIE_BIT);
 541                 data->is_zen = true;
 542
 543                 switch (boot_cpu_data.x86_model) {
 544                 case 0x0 ... 0x1:       /* Zen3 */
 545                         data->show_current = true;
 546                         data->svi_addr[0] = F19H_M01_SVI_TEL_PLANE0;
 547                         data->svi_addr[1] = F19H_M01_SVI_TEL_PLANE1;
 548                         data->cfactor[0] = F19H_M01H_CFACTOR_ICORE;
 549                         data->cfactor[1] = F19H_M01H_CFACTOR_ISOC;
 550                         k10temp_get_ccd_support(pdev, data, 8);
 551                         break;
 552                 }
 553         } else {
 554                 data->read_htcreg = read_htcreg_pci;
 555                 data->read_tempreg = read_tempreg_pci;
 556         }
 557
 558         for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
 559                 const struct tctl_offset *entry = &tctl_offset_table[i];
 560
 561                 if (boot_cpu_data.x86 == entry->model &&
 562                     strstr(boot_cpu_data.x86_model_id, entry->id)) {
 563                         data->temp_offset = entry->offset;
 564                         break;
 565                 }
 566         }
 567
 568         hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
 569                                                          &k10temp_chip_info,
 570                                                          NULL);
 571         return PTR_ERR_OR_ZERO(hwmon_dev);
 572 }
 573
 574 static const struct pci_device_id k10temp_id_table[] = {
 575         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
 576         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
 577         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
 578         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
 579         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
 580         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
 581         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
 582         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
 583         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
 584         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
 585         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 586         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
 587         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
 588         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
 589         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
 590         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
 591         { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 592         {}
 593 };
 594 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
 595
 596 static struct pci_driver k10temp_driver = {
 597         .name = "k10temp",
 598         .id_table = k10temp_id_table,
 599         .probe = k10temp_probe,
 600 };
 601
 602 module_pci_driver(k10temp_driver);