drivers/hwmon/k10temp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
   4  *              processor hardware monitoring
   5  *
   6  * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
   7  * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
   8  *
   9  * Implementation notes:
  10  * - CCD1 and CCD2 register address information as well as the calculation to
  11  *   convert raw register values is from https://github.com/ocerman/zenpower.
  12  *   The information is not confirmed from chip datasheets, but experiments
  13  *   suggest that it provides reasonable temperature values.
  14  * - Register addresses to read chip voltage and current are also from
  15  *   https://github.com/ocerman/zenpower, and not confirmed from chip
  16  *   datasheets. Current calibration is board specific and not typically
  17  *   shared by board vendors. For this reason, current values are
  18  *   normalized to report 1A/LSB for core current and and 0.25A/LSB for SoC
  19  *   current. Reported values can be adjusted using the sensors configuration
  20  *   file.
  21  * - It is unknown if the mechanism to read CCD1/CCD2 temperature as well as
  22  *   current and voltage information works on higher-end Ryzen CPUs.
  23  *   Information reported by Windows tools suggests that additional sensors
  24  *   (both temperature and voltage/current) are supported, but their register
  25  *   location is currently unknown.
  26  */
  27
  28 #include <linux/bitops.h>
  29 #include <linux/err.h>
  30 #include <linux/hwmon.h>
  31 #include <linux/init.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/pci_ids.h>
  35 #include <asm/amd_nb.h>
  36 #include <asm/processor.h>
  37
  38 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
  39 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  40 MODULE_LICENSE("GPL");
  41
  42 static bool force;
  43 module_param(force, bool, 0444);
  44 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
  45
  46 /* Provide lock for writing to NB_SMU_IND_ADDR */
  47 static DEFINE_MUTEX(nb_smu_ind_mutex);
  48
  49 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
  50 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3        0x15b3
  51 #endif
  52
  53 /* CPUID function 0x80000001, ebx */
  54 #define CPUID_PKGTYPE_MASK      GENMASK(31, 28)
  55 #define CPUID_PKGTYPE_F         0x00000000
  56 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
  57
  58 /* DRAM controller (PCI function 2) */
  59 #define REG_DCT0_CONFIG_HIGH            0x094
  60 #define  DDR3_MODE                      BIT(8)
  61
  62 /* miscellaneous (PCI function 3) */
  63 #define REG_HARDWARE_THERMAL_CONTROL    0x64
  64 #define  HTC_ENABLE                     BIT(0)
  65
  66 #define REG_REPORTED_TEMPERATURE        0xa4
  67
  68 #define REG_NORTHBRIDGE_CAPABILITIES    0xe8
  69 #define  NB_CAP_HTC                     BIT(10)
  70
  71 /*
  72  * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
  73  * and REG_REPORTED_TEMPERATURE have been moved to
  74  * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
  75  * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
  76  */
  77 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET     0xd8200c64
  78 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET     0xd8200ca4
  79
  80 /* F17h M01h Access througn SMN */
  81 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET     0x00059800
  82 #define F17H_M70H_CCD1_TEMP                     0x00059954
  83 #define F17H_M70H_CCD2_TEMP                     0x00059958
  84
  85 #define F17H_M01H_SVI                           0x0005A000
  86 #define F17H_M01H_SVI_TEL_PLANE0                (F17H_M01H_SVI + 0xc)
  87 #define F17H_M01H_SVI_TEL_PLANE1                (F17H_M01H_SVI + 0x10)
  88
  89 #define CUR_TEMP_SHIFT                          21
  90 #define CUR_TEMP_RANGE_SEL_MASK                 BIT(19)
  91
  92 #define CFACTOR_ICORE                           1000000 /* 1A / LSB     */
  93 #define CFACTOR_ISOC                            250000  /* 0.25A / LSB  */
  94
  95 struct k10temp_data {
  96         struct pci_dev *pdev;
  97         void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
  98         void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
  99         int temp_offset;
 100         u32 temp_adjust_mask;
 101         bool show_tdie;
 102         bool show_tccd1;
 103         bool show_tccd2;
 104         u32 svi_addr[2];
 105         bool show_current;
 106         int cfactor[2];
 107 };
 108
 109 struct tctl_offset {
 110         u8 model;
 111         char const *id;
 112         int offset;
 113 };
 114
 115 static const struct tctl_offset tctl_offset_table[] = {
 116         { 0x17, "AMD Ryzen 5 1600X", 20000 },
 117         { 0x17, "AMD Ryzen 7 1700X", 20000 },
 118         { 0x17, "AMD Ryzen 7 1800X", 20000 },
 119         { 0x17, "AMD Ryzen 7 2700X", 10000 },
 120         { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
 121         { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
 122 };
 123
 124 static bool is_threadripper(void)
 125 {
 126         return strstr(boot_cpu_data.x86_model_id, "Threadripper");
 127 }
 128
 129 static bool is_epyc(void)
 130 {
 131         return strstr(boot_cpu_data.x86_model_id, "EPYC");
 132 }
 133
 134 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
 135 {
 136         pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
 137 }
 138
 139 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
 140 {
 141         pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
 142 }
 143
 144 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
 145                               unsigned int base, int offset, u32 *val)
 146 {
 147         mutex_lock(&nb_smu_ind_mutex);
 148         pci_bus_write_config_dword(pdev->bus, devfn,
 149                                    base, offset);
 150         pci_bus_read_config_dword(pdev->bus, devfn,
 151                                   base + 4, val);
 152         mutex_unlock(&nb_smu_ind_mutex);
 153 }
 154
 155 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
 156 {
 157         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
 158                           F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
 159 }
 160
 161 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
 162 {
 163         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
 164                           F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
 165 }
 166
 167 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
 168 {
 169         amd_smn_read(amd_pci_dev_to_node_id(pdev),
 170                      F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
 171 }
 172
 173 static long get_raw_temp(struct k10temp_data *data)
 174 {
 175         u32 regval;
 176         long temp;
 177
 178         data->read_tempreg(data->pdev, &regval);
 179         temp = (regval >> CUR_TEMP_SHIFT) * 125;
 180         if (regval & data->temp_adjust_mask)
 181                 temp -= 49000;
 182         return temp;
 183 }
 184
 185 const char *k10temp_temp_label[] = {
 186         "Tdie",
 187         "Tctl",
 188         "Tccd1",
 189         "Tccd2",
 190 };
 191
 192 const char *k10temp_in_label[] = {
 193         "Vcore",
 194         "Vsoc",
 195 };
 196
 197 const char *k10temp_curr_label[] = {
 198         "Icore",
 199         "Isoc",
 200 };
 201
 202 static int k10temp_read_labels(struct device *dev,
 203                                enum hwmon_sensor_types type,
 204                                u32 attr, int channel, const char **str)
 205 {
 206         switch (type) {
 207         case hwmon_temp:
 208                 *str = k10temp_temp_label[channel];
 209                 break;
 210         case hwmon_in:
 211                 *str = k10temp_in_label[channel];
 212                 break;
 213         case hwmon_curr:
 214                 *str = k10temp_curr_label[channel];
 215                 break;
 216         default:
 217                 return -EOPNOTSUPP;
 218         }
 219         return 0;
 220 }
 221
 222 static int k10temp_read_curr(struct device *dev, u32 attr, int channel,
 223                              long *val)
 224 {
 225         struct k10temp_data *data = dev_get_drvdata(dev);
 226         u32 regval;
 227
 228         switch (attr) {
 229         case hwmon_curr_input:
 230                 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 231                              data->svi_addr[channel], &regval);
 232                 *val = DIV_ROUND_CLOSEST(data->cfactor[channel] *
 233                                          (regval & 0xff),
 234                                          1000);
 235                 break;
 236         default:
 237                 return -EOPNOTSUPP;
 238         }
 239         return 0;
 240 }
 241
 242 static int k10temp_read_in(struct device *dev, u32 attr, int channel, long *val)
 243 {
 244         struct k10temp_data *data = dev_get_drvdata(dev);
 245         u32 regval;
 246
 247         switch (attr) {
 248         case hwmon_in_input:
 249                 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 250                              data->svi_addr[channel], &regval);
 251                 regval = (regval >> 16) & 0xff;
 252                 *val = DIV_ROUND_CLOSEST(155000 - regval * 625, 100);
 253                 break;
 254         default:
 255                 return -EOPNOTSUPP;
 256         }
 257         return 0;
 258 }
 259
 260 static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
 261                              long *val)
 262 {
 263         struct k10temp_data *data = dev_get_drvdata(dev);
 264         u32 regval;
 265
 266         switch (attr) {
 267         case hwmon_temp_input:
 268                 switch (channel) {
 269                 case 0:         /* Tdie */
 270                         *val = get_raw_temp(data) - data->temp_offset;
 271                         if (*val < 0)
 272                                 *val = 0;
 273                         break;
 274                 case 1:         /* Tctl */
 275                         *val = get_raw_temp(data);
 276                         if (*val < 0)
 277                                 *val = 0;
 278                         break;
 279                 case 2:         /* Tccd1 */
 280                         amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 281                                      F17H_M70H_CCD1_TEMP, &regval);
 282                         *val = (regval & 0xfff) * 125 - 305000;
 283                         break;
 284                 case 3:         /* Tccd2 */
 285                         amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 286                                      F17H_M70H_CCD2_TEMP, &regval);
 287                         *val = (regval & 0xfff) * 125 - 305000;
 288                         break;
 289                 default:
 290                         return -EOPNOTSUPP;
 291                 }
 292                 break;
 293         case hwmon_temp_max:
 294                 *val = 70 * 1000;
 295                 break;
 296         case hwmon_temp_crit:
 297                 data->read_htcreg(data->pdev, &regval);
 298                 *val = ((regval >> 16) & 0x7f) * 500 + 52000;
 299                 break;
 300         case hwmon_temp_crit_hyst:
 301                 data->read_htcreg(data->pdev, &regval);
 302                 *val = (((regval >> 16) & 0x7f)
 303                         - ((regval >> 24) & 0xf)) * 500 + 52000;
 304                 break;
 305         default:
 306                 return -EOPNOTSUPP;
 307         }
 308         return 0;
 309 }
 310
 311 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
 312                         u32 attr, int channel, long *val)
 313 {
 314         switch (type) {
 315         case hwmon_temp:
 316                 return k10temp_read_temp(dev, attr, channel, val);
 317         case hwmon_in:
 318                 return k10temp_read_in(dev, attr, channel, val);
 319         case hwmon_curr:
 320                 return k10temp_read_curr(dev, attr, channel, val);
 321         default:
 322                 return -EOPNOTSUPP;
 323         }
 324 }
 325
 326 static umode_t k10temp_is_visible(const void *_data,
 327                                   enum hwmon_sensor_types type,
 328                                   u32 attr, int channel)
 329 {
 330         const struct k10temp_data *data = _data;
 331         struct pci_dev *pdev = data->pdev;
 332         u32 reg;
 333
 334         switch (type) {
 335         case hwmon_temp:
 336                 switch (attr) {
 337                 case hwmon_temp_input:
 338                         switch (channel) {
 339                         case 0:         /* Tdie, or Tctl if we don't show it */
 340                                 break;
 341                         case 1:         /* Tctl */
 342                                 if (!data->show_tdie)
 343                                         return 0;
 344                                 break;
 345                         case 2:         /* Tccd1 */
 346                                 if (!data->show_tccd1)
 347                                         return 0;
 348                                 break;
 349                         case 3:         /* Tccd2 */
 350                                 if (!data->show_tccd2)
 351                                         return 0;
 352                                 break;
 353                         default:
 354                                 return 0;
 355                         }
 356                         break;
 357                 case hwmon_temp_max:
 358                         if (channel)
 359                                 return 0;
 360                         break;
 361                 case hwmon_temp_crit:
 362                 case hwmon_temp_crit_hyst:
 363                         if (channel || !data->read_htcreg)
 364                                 return 0;
 365
 366                         pci_read_config_dword(pdev,
 367                                               REG_NORTHBRIDGE_CAPABILITIES,
 368                                               &reg);
 369                         if (!(reg & NB_CAP_HTC))
 370                                 return 0;
 371
 372                         data->read_htcreg(data->pdev, &reg);
 373                         if (!(reg & HTC_ENABLE))
 374                                 return 0;
 375                         break;
 376                 case hwmon_temp_label:
 377                         /* No labels if we don't show the die temperature */
 378                         if (!data->show_tdie)
 379                                 return 0;
 380                         switch (channel) {
 381                         case 0:         /* Tdie */
 382                         case 1:         /* Tctl */
 383                                 break;
 384                         case 2:         /* Tccd1 */
 385                                 if (!data->show_tccd1)
 386                                         return 0;
 387                                 break;
 388                         case 3:         /* Tccd2 */
 389                                 if (!data->show_tccd2)
 390                                         return 0;
 391                                 break;
 392                         default:
 393                                 return 0;
 394                         }
 395                         break;
 396                 default:
 397                         return 0;
 398                 }
 399                 break;
 400         case hwmon_in:
 401         case hwmon_curr:
 402                 if (!data->show_current)
 403                         return 0;
 404                 break;
 405         default:
 406                 return 0;
 407         }
 408         return 0444;
 409 }
 410
 411 static bool has_erratum_319(struct pci_dev *pdev)
 412 {
 413         u32 pkg_type, reg_dram_cfg;
 414
 415         if (boot_cpu_data.x86 != 0x10)
 416                 return false;
 417
 418         /*
 419          * Erratum 319: The thermal sensor of Socket F/AM2+ processors
 420          *              may be unreliable.
 421          */
 422         pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
 423         if (pkg_type == CPUID_PKGTYPE_F)
 424                 return true;
 425         if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
 426                 return false;
 427
 428         /* DDR3 memory implies socket AM3, which is good */
 429         pci_bus_read_config_dword(pdev->bus,
 430                                   PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
 431                                   REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
 432         if (reg_dram_cfg & DDR3_MODE)
 433                 return false;
 434
 435         /*
 436          * Unfortunately it is possible to run a socket AM3 CPU with DDR2
 437          * memory. We blacklist all the cores which do exist in socket AM2+
 438          * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
 439          * and AM3 formats, but that's the best we can do.
 440          */
 441         return boot_cpu_data.x86_model < 4 ||
 442                (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
 443 }
 444
 445 static const struct hwmon_channel_info *k10temp_info[] = {
 446         HWMON_CHANNEL_INFO(temp,
 447                            HWMON_T_INPUT | HWMON_T_MAX |
 448                            HWMON_T_CRIT | HWMON_T_CRIT_HYST |
 449                            HWMON_T_LABEL,
 450                            HWMON_T_INPUT | HWMON_T_LABEL,
 451                            HWMON_T_INPUT | HWMON_T_LABEL,
 452                            HWMON_T_INPUT | HWMON_T_LABEL),
 453         HWMON_CHANNEL_INFO(in,
 454                            HWMON_I_INPUT | HWMON_I_LABEL,
 455                            HWMON_I_INPUT | HWMON_I_LABEL),
 456         HWMON_CHANNEL_INFO(curr,
 457                            HWMON_C_INPUT | HWMON_C_LABEL,
 458                            HWMON_C_INPUT | HWMON_C_LABEL),
 459         NULL
 460 };
 461
 462 static const struct hwmon_ops k10temp_hwmon_ops = {
 463         .is_visible = k10temp_is_visible,
 464         .read = k10temp_read,
 465         .read_string = k10temp_read_labels,
 466 };
 467
 468 static const struct hwmon_chip_info k10temp_chip_info = {
 469         .ops = &k10temp_hwmon_ops,
 470         .info = k10temp_info,
 471 };
 472
 473 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 474 {
 475         int unreliable = has_erratum_319(pdev);
 476         struct device *dev = &pdev->dev;
 477         struct k10temp_data *data;
 478         struct device *hwmon_dev;
 479         int i;
 480
 481         if (unreliable) {
 482                 if (!force) {
 483                         dev_err(dev,
 484                                 "unreliable CPU thermal sensor; monitoring disabled\n");
 485                         return -ENODEV;
 486                 }
 487                 dev_warn(dev,
 488                          "unreliable CPU thermal sensor; check erratum 319\n");
 489         }
 490
 491         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 492         if (!data)
 493                 return -ENOMEM;
 494
 495         data->pdev = pdev;
 496
 497         if (boot_cpu_data.x86 == 0x15 &&
 498             ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
 499              (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
 500                 data->read_htcreg = read_htcreg_nb_f15;
 501                 data->read_tempreg = read_tempreg_nb_f15;
 502         } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
 503                 u32 regval;
 504
 505                 data->temp_adjust_mask = CUR_TEMP_RANGE_SEL_MASK;
 506                 data->read_tempreg = read_tempreg_nb_f17;
 507                 data->show_tdie = true;
 508
 509                 switch (boot_cpu_data.x86_model) {
 510                 case 0x1:       /* Zen */
 511                 case 0x8:       /* Zen+ */
 512                 case 0x11:      /* Zen APU */
 513                 case 0x18:      /* Zen+ APU */
 514                         data->show_current = !is_threadripper() && !is_epyc();
 515                         data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE0;
 516                         data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1;
 517                         data->cfactor[0] = CFACTOR_ICORE;
 518                         data->cfactor[1] = CFACTOR_ISOC;
 519                         break;
 520                 case 0x31:      /* Zen2 Threadripper */
 521                 case 0x71:      /* Zen2 */
 522                         data->show_current = !is_threadripper() && !is_epyc();
 523                         data->cfactor[0] = CFACTOR_ICORE;
 524                         data->cfactor[1] = CFACTOR_ISOC;
 525                         data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE1;
 526                         data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE0;
 527                         amd_smn_read(amd_pci_dev_to_node_id(pdev),
 528                                      F17H_M70H_CCD1_TEMP, &regval);
 529                         if (regval & 0xfff)
 530                                 data->show_tccd1 = true;
 531
 532                         amd_smn_read(amd_pci_dev_to_node_id(pdev),
 533                                      F17H_M70H_CCD2_TEMP, &regval);
 534                         if (regval & 0xfff)
 535                                 data->show_tccd2 = true;
 536                         break;
 537                 }
 538         } else {
 539                 data->read_htcreg = read_htcreg_pci;
 540                 data->read_tempreg = read_tempreg_pci;
 541         }
 542
 543         for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
 544                 const struct tctl_offset *entry = &tctl_offset_table[i];
 545
 546                 if (boot_cpu_data.x86 == entry->model &&
 547                     strstr(boot_cpu_data.x86_model_id, entry->id)) {
 548                         data->temp_offset = entry->offset;
 549                         break;
 550                 }
 551         }
 552
 553         hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
 554                                                          &k10temp_chip_info,
 555                                                          NULL);
 556         return PTR_ERR_OR_ZERO(hwmon_dev);
 557 }
 558
 559 static const struct pci_device_id k10temp_id_table[] = {
 560         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
 561         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
 562         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
 563         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
 564         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
 565         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
 566         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
 567         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
 568         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
 569         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
 570         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 571         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
 572         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
 573         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
 574         { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 575         {}
 576 };
 577 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
 578
 579 static struct pci_driver k10temp_driver = {
 580         .name = "k10temp",
 581         .id_table = k10temp_id_table,
 582         .probe = k10temp_probe,
 583 };
 584
 585 module_pci_driver(k10temp_driver);