1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
5 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
8 #include <linux/bitops.h>
10 #include <linux/hwmon.h>
11 #include <linux/hwmon-sysfs.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <asm/amd_nb.h>
17 #include <asm/processor.h>
19 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
20 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
21 MODULE_LICENSE("GPL");
24 module_param(force, bool, 0444);
25 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
27 /* Provide lock for writing to NB_SMU_IND_ADDR */
28 static DEFINE_MUTEX(nb_smu_ind_mutex);
30 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
31 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
34 /* CPUID function 0x80000001, ebx */
35 #define CPUID_PKGTYPE_MASK GENMASK(31, 28)
36 #define CPUID_PKGTYPE_F 0x00000000
37 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
39 /* DRAM controller (PCI function 2) */
40 #define REG_DCT0_CONFIG_HIGH 0x094
41 #define DDR3_MODE BIT(8)
43 /* miscellaneous (PCI function 3) */
44 #define REG_HARDWARE_THERMAL_CONTROL 0x64
45 #define HTC_ENABLE BIT(0)
47 #define REG_REPORTED_TEMPERATURE 0xa4
49 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
50 #define NB_CAP_HTC BIT(10)
53 * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
54 * and REG_REPORTED_TEMPERATURE have been moved to
55 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
56 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
58 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
59 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
61 /* F17h M01h Access througn SMN */
62 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
64 #define CUR_TEMP_SHIFT 21
65 #define CUR_TEMP_RANGE_SEL_MASK BIT(19)
69 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
70 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
82 static const struct tctl_offset tctl_offset_table[] = {
83 { 0x17, "AMD Ryzen 5 1600X", 20000 },
84 { 0x17, "AMD Ryzen 7 1700X", 20000 },
85 { 0x17, "AMD Ryzen 7 1800X", 20000 },
86 { 0x17, "AMD Ryzen 7 2700X", 10000 },
87 { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
88 { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
91 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
93 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
96 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
98 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
101 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
102 unsigned int base, int offset, u32 *val)
104 mutex_lock(&nb_smu_ind_mutex);
105 pci_bus_write_config_dword(pdev->bus, devfn,
107 pci_bus_read_config_dword(pdev->bus, devfn,
109 mutex_unlock(&nb_smu_ind_mutex);
112 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
114 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
115 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
118 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
120 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
121 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
124 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
126 amd_smn_read(amd_pci_dev_to_node_id(pdev),
127 F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
130 static unsigned int get_raw_temp(struct k10temp_data *data)
135 data->read_tempreg(data->pdev, ®val);
136 temp = (regval >> CUR_TEMP_SHIFT) * 125;
137 if (regval & data->temp_adjust_mask)
142 static ssize_t temp1_input_show(struct device *dev,
143 struct device_attribute *attr, char *buf)
145 struct k10temp_data *data = dev_get_drvdata(dev);
146 unsigned int temp = get_raw_temp(data);
148 if (temp > data->temp_offset)
149 temp -= data->temp_offset;
153 return sprintf(buf, "%u\n", temp);
156 static ssize_t temp2_input_show(struct device *dev,
157 struct device_attribute *devattr, char *buf)
159 struct k10temp_data *data = dev_get_drvdata(dev);
160 unsigned int temp = get_raw_temp(data);
162 return sprintf(buf, "%u\n", temp);
165 static ssize_t temp_label_show(struct device *dev,
166 struct device_attribute *devattr, char *buf)
168 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
170 return sprintf(buf, "%s\n", attr->index ? "Tctl" : "Tdie");
173 static ssize_t temp1_max_show(struct device *dev,
174 struct device_attribute *attr, char *buf)
176 return sprintf(buf, "%d\n", 70 * 1000);
179 static ssize_t temp_crit_show(struct device *dev,
180 struct device_attribute *devattr, char *buf)
182 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
183 struct k10temp_data *data = dev_get_drvdata(dev);
184 int show_hyst = attr->index;
188 data->read_htcreg(data->pdev, ®val);
189 value = ((regval >> 16) & 0x7f) * 500 + 52000;
191 value -= ((regval >> 24) & 0xf) * 500;
192 return sprintf(buf, "%d\n", value);
195 static DEVICE_ATTR_RO(temp1_input);
196 static DEVICE_ATTR_RO(temp1_max);
197 static SENSOR_DEVICE_ATTR_RO(temp1_crit, temp_crit, 0);
198 static SENSOR_DEVICE_ATTR_RO(temp1_crit_hyst, temp_crit, 1);
200 static SENSOR_DEVICE_ATTR_RO(temp1_label, temp_label, 0);
201 static DEVICE_ATTR_RO(temp2_input);
202 static SENSOR_DEVICE_ATTR_RO(temp2_label, temp_label, 1);
204 static umode_t k10temp_is_visible(struct kobject *kobj,
205 struct attribute *attr, int index)
207 struct device *dev = container_of(kobj, struct device, kobj);
208 struct k10temp_data *data = dev_get_drvdata(dev);
209 struct pci_dev *pdev = data->pdev;
213 case 0 ... 1: /* temp1_input, temp1_max */
216 case 2 ... 3: /* temp1_crit, temp1_crit_hyst */
217 if (!data->read_htcreg)
220 pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
222 if (!(reg & NB_CAP_HTC))
225 data->read_htcreg(data->pdev, ®);
226 if (!(reg & HTC_ENABLE))
229 case 4 ... 6: /* temp1_label, temp2_input, temp2_label */
230 if (!data->show_tdie)
237 static struct attribute *k10temp_attrs[] = {
238 &dev_attr_temp1_input.attr,
239 &dev_attr_temp1_max.attr,
240 &sensor_dev_attr_temp1_crit.dev_attr.attr,
241 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
242 &sensor_dev_attr_temp1_label.dev_attr.attr,
243 &dev_attr_temp2_input.attr,
244 &sensor_dev_attr_temp2_label.dev_attr.attr,
248 static const struct attribute_group k10temp_group = {
249 .attrs = k10temp_attrs,
250 .is_visible = k10temp_is_visible,
252 __ATTRIBUTE_GROUPS(k10temp);
254 static bool has_erratum_319(struct pci_dev *pdev)
256 u32 pkg_type, reg_dram_cfg;
258 if (boot_cpu_data.x86 != 0x10)
262 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
265 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
266 if (pkg_type == CPUID_PKGTYPE_F)
268 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
271 /* DDR3 memory implies socket AM3, which is good */
272 pci_bus_read_config_dword(pdev->bus,
273 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
274 REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
275 if (reg_dram_cfg & DDR3_MODE)
279 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
280 * memory. We blacklist all the cores which do exist in socket AM2+
281 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
282 * and AM3 formats, but that's the best we can do.
284 return boot_cpu_data.x86_model < 4 ||
285 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
288 static int k10temp_probe(struct pci_dev *pdev,
289 const struct pci_device_id *id)
291 int unreliable = has_erratum_319(pdev);
292 struct device *dev = &pdev->dev;
293 struct k10temp_data *data;
294 struct device *hwmon_dev;
300 "unreliable CPU thermal sensor; monitoring disabled\n");
304 "unreliable CPU thermal sensor; check erratum 319\n");
307 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
313 if (boot_cpu_data.x86 == 0x15 &&
314 ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
315 (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
316 data->read_htcreg = read_htcreg_nb_f15;
317 data->read_tempreg = read_tempreg_nb_f15;
318 } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
319 data->temp_adjust_mask = CUR_TEMP_RANGE_SEL_MASK;
320 data->read_tempreg = read_tempreg_nb_f17;
321 data->show_tdie = true;
323 data->read_htcreg = read_htcreg_pci;
324 data->read_tempreg = read_tempreg_pci;
327 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
328 const struct tctl_offset *entry = &tctl_offset_table[i];
330 if (boot_cpu_data.x86 == entry->model &&
331 strstr(boot_cpu_data.x86_model_id, entry->id)) {
332 data->temp_offset = entry->offset;
337 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
339 return PTR_ERR_OR_ZERO(hwmon_dev);
342 static const struct pci_device_id k10temp_id_table[] = {
343 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
344 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
345 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
346 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
347 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
348 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
349 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
350 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
351 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
352 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
353 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
354 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
355 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
356 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
357 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
360 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
362 static struct pci_driver k10temp_driver = {
364 .id_table = k10temp_id_table,
365 .probe = k10temp_probe,
368 module_pci_driver(k10temp_driver);