drivers/hwmon/k10temp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
   4  *              processor hardware monitoring
   5  *
   6  * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
   7  * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
   8  *
   9  * Implementation notes:
  10  * - CCD1 and CCD2 register address information as well as the calculation to
  11  *   convert raw register values is from https://github.com/ocerman/zenpower.
  12  *   The information is not confirmed from chip datasheets, but experiments
  13  *   suggest that it provides reasonable temperature values.
  14  * - Register addresses to read chip voltage and current are also from
  15  *   https://github.com/ocerman/zenpower, and not confirmed from chip
  16  *   datasheets. Current calibration is board specific and not typically
  17  *   shared by board vendors. For this reason, current values are
  18  *   normalized to report 1A/LSB for core current and and 0.25A/LSB for SoC
  19  *   current. Reported values can be adjusted using the sensors configuration
  20  *   file.
  21  * - It is unknown if the mechanism to read CCD1/CCD2 temperature as well as
  22  *   current and voltage information works on higher-end Ryzen CPUs.
  23  *   Information reported by Windows tools suggests that additional sensors
  24  *   (both temperature and voltage/current) are supported, but their register
  25  *   location is currently unknown.
  26  */
  27
  28 #include <linux/bitops.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/err.h>
  31 #include <linux/hwmon.h>
  32 #include <linux/init.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pci_ids.h>
  36 #include <asm/amd_nb.h>
  37 #include <asm/processor.h>
  38
  39 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
  40 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  41 MODULE_LICENSE("GPL");
  42
  43 static bool force;
  44 module_param(force, bool, 0444);
  45 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
  46
  47 /* Provide lock for writing to NB_SMU_IND_ADDR */
  48 static DEFINE_MUTEX(nb_smu_ind_mutex);
  49
  50 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
  51 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3        0x15b3
  52 #endif
  53
  54 /* CPUID function 0x80000001, ebx */
  55 #define CPUID_PKGTYPE_MASK      GENMASK(31, 28)
  56 #define CPUID_PKGTYPE_F         0x00000000
  57 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
  58
  59 /* DRAM controller (PCI function 2) */
  60 #define REG_DCT0_CONFIG_HIGH            0x094
  61 #define  DDR3_MODE                      BIT(8)
  62
  63 /* miscellaneous (PCI function 3) */
  64 #define REG_HARDWARE_THERMAL_CONTROL    0x64
  65 #define  HTC_ENABLE                     BIT(0)
  66
  67 #define REG_REPORTED_TEMPERATURE        0xa4
  68
  69 #define REG_NORTHBRIDGE_CAPABILITIES    0xe8
  70 #define  NB_CAP_HTC                     BIT(10)
  71
  72 /*
  73  * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
  74  * and REG_REPORTED_TEMPERATURE have been moved to
  75  * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
  76  * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
  77  */
  78 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET     0xd8200c64
  79 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET     0xd8200ca4
  80
  81 /* F17h M01h Access througn SMN */
  82 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET     0x00059800
  83 #define F17H_M70H_CCD1_TEMP                     0x00059954
  84 #define F17H_M70H_CCD2_TEMP                     0x00059958
  85
  86 #define F17H_M01H_SVI                           0x0005A000
  87 #define F17H_M01H_SVI_TEL_PLANE0                (F17H_M01H_SVI + 0xc)
  88 #define F17H_M01H_SVI_TEL_PLANE1                (F17H_M01H_SVI + 0x10)
  89
  90 #define CUR_TEMP_SHIFT                          21
  91 #define CUR_TEMP_RANGE_SEL_MASK                 BIT(19)
  92
  93 #define CFACTOR_ICORE                           1000000 /* 1A / LSB     */
  94 #define CFACTOR_ISOC                            250000  /* 0.25A / LSB  */
  95
  96 struct k10temp_data {
  97         struct pci_dev *pdev;
  98         void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
  99         void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
 100         int temp_offset;
 101         u32 temp_adjust_mask;
 102         bool show_tdie;
 103         bool show_tccd1;
 104         bool show_tccd2;
 105         u32 svi_addr[2];
 106         bool show_current;
 107         int cfactor[2];
 108 };
 109
 110 struct tctl_offset {
 111         u8 model;
 112         char const *id;
 113         int offset;
 114 };
 115
 116 static const struct tctl_offset tctl_offset_table[] = {
 117         { 0x17, "AMD Ryzen 5 1600X", 20000 },
 118         { 0x17, "AMD Ryzen 7 1700X", 20000 },
 119         { 0x17, "AMD Ryzen 7 1800X", 20000 },
 120         { 0x17, "AMD Ryzen 7 2700X", 10000 },
 121         { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
 122         { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
 123 };
 124
 125 static bool is_threadripper(void)
 126 {
 127         return strstr(boot_cpu_data.x86_model_id, "Threadripper");
 128 }
 129
 130 static bool is_epyc(void)
 131 {
 132         return strstr(boot_cpu_data.x86_model_id, "EPYC");
 133 }
 134
 135 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
 136 {
 137         pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
 138 }
 139
 140 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
 141 {
 142         pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
 143 }
 144
 145 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
 146                               unsigned int base, int offset, u32 *val)
 147 {
 148         mutex_lock(&nb_smu_ind_mutex);
 149         pci_bus_write_config_dword(pdev->bus, devfn,
 150                                    base, offset);
 151         pci_bus_read_config_dword(pdev->bus, devfn,
 152                                   base + 4, val);
 153         mutex_unlock(&nb_smu_ind_mutex);
 154 }
 155
 156 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
 157 {
 158         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
 159                           F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
 160 }
 161
 162 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
 163 {
 164         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
 165                           F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
 166 }
 167
 168 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
 169 {
 170         amd_smn_read(amd_pci_dev_to_node_id(pdev),
 171                      F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
 172 }
 173
 174 static long get_raw_temp(struct k10temp_data *data)
 175 {
 176         u32 regval;
 177         long temp;
 178
 179         data->read_tempreg(data->pdev, &regval);
 180         temp = (regval >> CUR_TEMP_SHIFT) * 125;
 181         if (regval & data->temp_adjust_mask)
 182                 temp -= 49000;
 183         return temp;
 184 }
 185
 186 const char *k10temp_temp_label[] = {
 187         "Tdie",
 188         "Tctl",
 189         "Tccd1",
 190         "Tccd2",
 191 };
 192
 193 const char *k10temp_in_label[] = {
 194         "Vcore",
 195         "Vsoc",
 196 };
 197
 198 const char *k10temp_curr_label[] = {
 199         "Icore",
 200         "Isoc",
 201 };
 202
 203 static int k10temp_read_labels(struct device *dev,
 204                                enum hwmon_sensor_types type,
 205                                u32 attr, int channel, const char **str)
 206 {
 207         switch (type) {
 208         case hwmon_temp:
 209                 *str = k10temp_temp_label[channel];
 210                 break;
 211         case hwmon_in:
 212                 *str = k10temp_in_label[channel];
 213                 break;
 214         case hwmon_curr:
 215                 *str = k10temp_curr_label[channel];
 216                 break;
 217         default:
 218                 return -EOPNOTSUPP;
 219         }
 220         return 0;
 221 }
 222
 223 static int k10temp_read_curr(struct device *dev, u32 attr, int channel,
 224                              long *val)
 225 {
 226         struct k10temp_data *data = dev_get_drvdata(dev);
 227         u32 regval;
 228
 229         switch (attr) {
 230         case hwmon_curr_input:
 231                 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 232                              data->svi_addr[channel], &regval);
 233                 *val = DIV_ROUND_CLOSEST(data->cfactor[channel] *
 234                                          (regval & 0xff),
 235                                          1000);
 236                 break;
 237         default:
 238                 return -EOPNOTSUPP;
 239         }
 240         return 0;
 241 }
 242
 243 static int k10temp_read_in(struct device *dev, u32 attr, int channel, long *val)
 244 {
 245         struct k10temp_data *data = dev_get_drvdata(dev);
 246         u32 regval;
 247
 248         switch (attr) {
 249         case hwmon_in_input:
 250                 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 251                              data->svi_addr[channel], &regval);
 252                 regval = (regval >> 16) & 0xff;
 253                 *val = DIV_ROUND_CLOSEST(155000 - regval * 625, 100);
 254                 break;
 255         default:
 256                 return -EOPNOTSUPP;
 257         }
 258         return 0;
 259 }
 260
 261 static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
 262                              long *val)
 263 {
 264         struct k10temp_data *data = dev_get_drvdata(dev);
 265         u32 regval;
 266
 267         switch (attr) {
 268         case hwmon_temp_input:
 269                 switch (channel) {
 270                 case 0:         /* Tdie */
 271                         *val = get_raw_temp(data) - data->temp_offset;
 272                         if (*val < 0)
 273                                 *val = 0;
 274                         break;
 275                 case 1:         /* Tctl */
 276                         *val = get_raw_temp(data);
 277                         if (*val < 0)
 278                                 *val = 0;
 279                         break;
 280                 case 2:         /* Tccd1 */
 281                         amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 282                                      F17H_M70H_CCD1_TEMP, &regval);
 283                         *val = (regval & 0xfff) * 125 - 305000;
 284                         break;
 285                 case 3:         /* Tccd2 */
 286                         amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 287                                      F17H_M70H_CCD2_TEMP, &regval);
 288                         *val = (regval & 0xfff) * 125 - 305000;
 289                         break;
 290                 default:
 291                         return -EOPNOTSUPP;
 292                 }
 293                 break;
 294         case hwmon_temp_max:
 295                 *val = 70 * 1000;
 296                 break;
 297         case hwmon_temp_crit:
 298                 data->read_htcreg(data->pdev, &regval);
 299                 *val = ((regval >> 16) & 0x7f) * 500 + 52000;
 300                 break;
 301         case hwmon_temp_crit_hyst:
 302                 data->read_htcreg(data->pdev, &regval);
 303                 *val = (((regval >> 16) & 0x7f)
 304                         - ((regval >> 24) & 0xf)) * 500 + 52000;
 305                 break;
 306         default:
 307                 return -EOPNOTSUPP;
 308         }
 309         return 0;
 310 }
 311
 312 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
 313                         u32 attr, int channel, long *val)
 314 {
 315         switch (type) {
 316         case hwmon_temp:
 317                 return k10temp_read_temp(dev, attr, channel, val);
 318         case hwmon_in:
 319                 return k10temp_read_in(dev, attr, channel, val);
 320         case hwmon_curr:
 321                 return k10temp_read_curr(dev, attr, channel, val);
 322         default:
 323                 return -EOPNOTSUPP;
 324         }
 325 }
 326
 327 static umode_t k10temp_is_visible(const void *_data,
 328                                   enum hwmon_sensor_types type,
 329                                   u32 attr, int channel)
 330 {
 331         const struct k10temp_data *data = _data;
 332         struct pci_dev *pdev = data->pdev;
 333         u32 reg;
 334
 335         switch (type) {
 336         case hwmon_temp:
 337                 switch (attr) {
 338                 case hwmon_temp_input:
 339                         switch (channel) {
 340                         case 0:         /* Tdie, or Tctl if we don't show it */
 341                                 break;
 342                         case 1:         /* Tctl */
 343                                 if (!data->show_tdie)
 344                                         return 0;
 345                                 break;
 346                         case 2:         /* Tccd1 */
 347                                 if (!data->show_tccd1)
 348                                         return 0;
 349                                 break;
 350                         case 3:         /* Tccd2 */
 351                                 if (!data->show_tccd2)
 352                                         return 0;
 353                                 break;
 354                         default:
 355                                 return 0;
 356                         }
 357                         break;
 358                 case hwmon_temp_max:
 359                         if (channel || data->show_tdie)
 360                                 return 0;
 361                         break;
 362                 case hwmon_temp_crit:
 363                 case hwmon_temp_crit_hyst:
 364                         if (channel || !data->read_htcreg)
 365                                 return 0;
 366
 367                         pci_read_config_dword(pdev,
 368                                               REG_NORTHBRIDGE_CAPABILITIES,
 369                                               &reg);
 370                         if (!(reg & NB_CAP_HTC))
 371                                 return 0;
 372
 373                         data->read_htcreg(data->pdev, &reg);
 374                         if (!(reg & HTC_ENABLE))
 375                                 return 0;
 376                         break;
 377                 case hwmon_temp_label:
 378                         /* No labels if we don't show the die temperature */
 379                         if (!data->show_tdie)
 380                                 return 0;
 381                         switch (channel) {
 382                         case 0:         /* Tdie */
 383                         case 1:         /* Tctl */
 384                                 break;
 385                         case 2:         /* Tccd1 */
 386                                 if (!data->show_tccd1)
 387                                         return 0;
 388                                 break;
 389                         case 3:         /* Tccd2 */
 390                                 if (!data->show_tccd2)
 391                                         return 0;
 392                                 break;
 393                         default:
 394                                 return 0;
 395                         }
 396                         break;
 397                 default:
 398                         return 0;
 399                 }
 400                 break;
 401         case hwmon_in:
 402         case hwmon_curr:
 403                 if (!data->show_current)
 404                         return 0;
 405                 break;
 406         default:
 407                 return 0;
 408         }
 409         return 0444;
 410 }
 411
 412 static bool has_erratum_319(struct pci_dev *pdev)
 413 {
 414         u32 pkg_type, reg_dram_cfg;
 415
 416         if (boot_cpu_data.x86 != 0x10)
 417                 return false;
 418
 419         /*
 420          * Erratum 319: The thermal sensor of Socket F/AM2+ processors
 421          *              may be unreliable.
 422          */
 423         pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
 424         if (pkg_type == CPUID_PKGTYPE_F)
 425                 return true;
 426         if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
 427                 return false;
 428
 429         /* DDR3 memory implies socket AM3, which is good */
 430         pci_bus_read_config_dword(pdev->bus,
 431                                   PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
 432                                   REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
 433         if (reg_dram_cfg & DDR3_MODE)
 434                 return false;
 435
 436         /*
 437          * Unfortunately it is possible to run a socket AM3 CPU with DDR2
 438          * memory. We blacklist all the cores which do exist in socket AM2+
 439          * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
 440          * and AM3 formats, but that's the best we can do.
 441          */
 442         return boot_cpu_data.x86_model < 4 ||
 443                (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
 444 }
 445
 446 #ifdef CONFIG_DEBUG_FS
 447
 448 static void k10temp_smn_regs_show(struct seq_file *s, struct pci_dev *pdev,
 449                                   u32 addr, int count)
 450 {
 451         u32 reg;
 452         int i;
 453
 454         for (i = 0; i < count; i++) {
 455                 if (!(i & 3))
 456                         seq_printf(s, "0x%06x: ", addr + i * 4);
 457                 amd_smn_read(amd_pci_dev_to_node_id(pdev), addr + i * 4, &reg);
 458                 seq_printf(s, "%08x ", reg);
 459                 if ((i & 3) == 3)
 460                         seq_puts(s, "\n");
 461         }
 462 }
 463
 464 static int svi_show(struct seq_file *s, void *unused)
 465 {
 466         struct k10temp_data *data = s->private;
 467
 468         k10temp_smn_regs_show(s, data->pdev, F17H_M01H_SVI, 32);
 469         return 0;
 470 }
 471 DEFINE_SHOW_ATTRIBUTE(svi);
 472
 473 static int thm_show(struct seq_file *s, void *unused)
 474 {
 475         struct k10temp_data *data = s->private;
 476
 477         k10temp_smn_regs_show(s, data->pdev,
 478                               F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, 256);
 479         return 0;
 480 }
 481 DEFINE_SHOW_ATTRIBUTE(thm);
 482
 483 static void k10temp_debugfs_cleanup(void *ddir)
 484 {
 485         debugfs_remove_recursive(ddir);
 486 }
 487
 488 static void k10temp_init_debugfs(struct k10temp_data *data)
 489 {
 490         struct dentry *debugfs;
 491         char name[32];
 492
 493         /* Only show debugfs data for Family 17h/18h CPUs */
 494         if (!data->show_tdie)
 495                 return;
 496
 497         scnprintf(name, sizeof(name), "k10temp-%s", pci_name(data->pdev));
 498
 499         debugfs = debugfs_create_dir(name, NULL);
 500         if (debugfs) {
 501                 debugfs_create_file("svi", 0444, debugfs, data, &svi_fops);
 502                 debugfs_create_file("thm", 0444, debugfs, data, &thm_fops);
 503                 devm_add_action_or_reset(&data->pdev->dev,
 504                                          k10temp_debugfs_cleanup, debugfs);
 505         }
 506 }
 507
 508 #else
 509
 510 static void k10temp_init_debugfs(struct k10temp_data *data)
 511 {
 512 }
 513
 514 #endif
 515
 516 static const struct hwmon_channel_info *k10temp_info[] = {
 517         HWMON_CHANNEL_INFO(temp,
 518                            HWMON_T_INPUT | HWMON_T_MAX |
 519                            HWMON_T_CRIT | HWMON_T_CRIT_HYST |
 520                            HWMON_T_LABEL,
 521                            HWMON_T_INPUT | HWMON_T_LABEL,
 522                            HWMON_T_INPUT | HWMON_T_LABEL,
 523                            HWMON_T_INPUT | HWMON_T_LABEL),
 524         HWMON_CHANNEL_INFO(in,
 525                            HWMON_I_INPUT | HWMON_I_LABEL,
 526                            HWMON_I_INPUT | HWMON_I_LABEL),
 527         HWMON_CHANNEL_INFO(curr,
 528                            HWMON_C_INPUT | HWMON_C_LABEL,
 529                            HWMON_C_INPUT | HWMON_C_LABEL),
 530         NULL
 531 };
 532
 533 static const struct hwmon_ops k10temp_hwmon_ops = {
 534         .is_visible = k10temp_is_visible,
 535         .read = k10temp_read,
 536         .read_string = k10temp_read_labels,
 537 };
 538
 539 static const struct hwmon_chip_info k10temp_chip_info = {
 540         .ops = &k10temp_hwmon_ops,
 541         .info = k10temp_info,
 542 };
 543
 544 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 545 {
 546         int unreliable = has_erratum_319(pdev);
 547         struct device *dev = &pdev->dev;
 548         struct k10temp_data *data;
 549         struct device *hwmon_dev;
 550         int i;
 551
 552         if (unreliable) {
 553                 if (!force) {
 554                         dev_err(dev,
 555                                 "unreliable CPU thermal sensor; monitoring disabled\n");
 556                         return -ENODEV;
 557                 }
 558                 dev_warn(dev,
 559                          "unreliable CPU thermal sensor; check erratum 319\n");
 560         }
 561
 562         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 563         if (!data)
 564                 return -ENOMEM;
 565
 566         data->pdev = pdev;
 567
 568         if (boot_cpu_data.x86 == 0x15 &&
 569             ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
 570              (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
 571                 data->read_htcreg = read_htcreg_nb_f15;
 572                 data->read_tempreg = read_tempreg_nb_f15;
 573         } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
 574                 u32 regval;
 575
 576                 data->temp_adjust_mask = CUR_TEMP_RANGE_SEL_MASK;
 577                 data->read_tempreg = read_tempreg_nb_f17;
 578                 data->show_tdie = true;
 579
 580                 switch (boot_cpu_data.x86_model) {
 581                 case 0x1:       /* Zen */
 582                 case 0x8:       /* Zen+ */
 583                 case 0x11:      /* Zen APU */
 584                 case 0x18:      /* Zen+ APU */
 585                         data->show_current = !is_threadripper() && !is_epyc();
 586                         data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE0;
 587                         data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1;
 588                         data->cfactor[0] = CFACTOR_ICORE;
 589                         data->cfactor[1] = CFACTOR_ISOC;
 590                         break;
 591                 case 0x31:      /* Zen2 Threadripper */
 592                 case 0x71:      /* Zen2 */
 593                         data->show_current = !is_threadripper() && !is_epyc();
 594                         data->cfactor[0] = CFACTOR_ICORE;
 595                         data->cfactor[1] = CFACTOR_ISOC;
 596                         data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE1;
 597                         data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE0;
 598                         amd_smn_read(amd_pci_dev_to_node_id(pdev),
 599                                      F17H_M70H_CCD1_TEMP, &regval);
 600                         if (regval & 0xfff)
 601                                 data->show_tccd1 = true;
 602
 603                         amd_smn_read(amd_pci_dev_to_node_id(pdev),
 604                                      F17H_M70H_CCD2_TEMP, &regval);
 605                         if (regval & 0xfff)
 606                                 data->show_tccd2 = true;
 607                         break;
 608                 }
 609         } else {
 610                 data->read_htcreg = read_htcreg_pci;
 611                 data->read_tempreg = read_tempreg_pci;
 612         }
 613
 614         for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
 615                 const struct tctl_offset *entry = &tctl_offset_table[i];
 616
 617                 if (boot_cpu_data.x86 == entry->model &&
 618                     strstr(boot_cpu_data.x86_model_id, entry->id)) {
 619                         data->temp_offset = entry->offset;
 620                         break;
 621                 }
 622         }
 623
 624         hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
 625                                                          &k10temp_chip_info,
 626                                                          NULL);
 627         if (IS_ERR(hwmon_dev))
 628                 return PTR_ERR(hwmon_dev);
 629
 630         k10temp_init_debugfs(data);
 631
 632         return 0;
 633 }
 634
 635 static const struct pci_device_id k10temp_id_table[] = {
 636         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
 637         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
 638         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
 639         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
 640         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
 641         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
 642         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
 643         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
 644         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
 645         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
 646         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 647         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
 648         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
 649         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
 650         { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 651         {}
 652 };
 653 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
 654
 655 static struct pci_driver k10temp_driver = {
 656         .name = "k10temp",
 657         .id_table = k10temp_id_table,
 658         .probe = k10temp_probe,
 659 };
 660
 661 module_pci_driver(k10temp_driver);