1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
5 * Copyright (c) 2010 Ericsson AB.
7 * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
9 * JC42.4 compliant temperature sensors are typically used on memory modules.
12 #include <linux/bitops.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/slab.h>
16 #include <linux/jiffies.h>
17 #include <linux/i2c.h>
18 #include <linux/hwmon.h>
19 #include <linux/err.h>
20 #include <linux/mutex.h>
23 /* Addresses to scan */
24 static const unsigned short normal_i2c[] = {
25 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
27 /* JC42 registers. All registers are 16 bit. */
28 #define JC42_REG_CAP 0x00
29 #define JC42_REG_CONFIG 0x01
30 #define JC42_REG_TEMP_UPPER 0x02
31 #define JC42_REG_TEMP_LOWER 0x03
32 #define JC42_REG_TEMP_CRITICAL 0x04
33 #define JC42_REG_TEMP 0x05
34 #define JC42_REG_MANID 0x06
35 #define JC42_REG_DEVICEID 0x07
36 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
38 /* Status bits in temperature register */
39 #define JC42_ALARM_CRIT_BIT 15
40 #define JC42_ALARM_MAX_BIT 14
41 #define JC42_ALARM_MIN_BIT 13
43 /* Configuration register defines */
44 #define JC42_CFG_CRIT_ONLY (1 << 2)
45 #define JC42_CFG_TCRIT_LOCK (1 << 6)
46 #define JC42_CFG_EVENT_LOCK (1 << 7)
47 #define JC42_CFG_SHUTDOWN (1 << 8)
48 #define JC42_CFG_HYST_SHIFT 9
49 #define JC42_CFG_HYST_MASK (0x03 << 9)
52 #define JC42_CAP_RANGE (1 << 2)
54 /* Manufacturer IDs */
55 #define ADT_MANID 0x11d4 /* Analog Devices */
56 #define ATMEL_MANID 0x001f /* Atmel */
57 #define ATMEL_MANID2 0x1114 /* Atmel */
58 #define MAX_MANID 0x004d /* Maxim */
59 #define IDT_MANID 0x00b3 /* IDT */
60 #define MCP_MANID 0x0054 /* Microchip */
61 #define NXP_MANID 0x1131 /* NXP Semiconductors */
62 #define ONS_MANID 0x1b09 /* ON Semiconductor */
63 #define STM_MANID 0x104a /* ST Microelectronics */
64 #define GT_MANID 0x1c68 /* Giantec */
65 #define GT_MANID2 0x132d /* Giantec, 2nd mfg ID */
68 #define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */
73 #define ADT7408_DEVID 0x0801
74 #define ADT7408_DEVID_MASK 0xffff
77 #define AT30TS00_DEVID 0x8201
78 #define AT30TS00_DEVID_MASK 0xffff
80 #define AT30TSE004_DEVID 0x2200
81 #define AT30TSE004_DEVID_MASK 0xffff
84 #define GT30TS00_DEVID 0x2200
85 #define GT30TS00_DEVID_MASK 0xff00
87 #define GT34TS02_DEVID 0x3300
88 #define GT34TS02_DEVID_MASK 0xff00
91 #define TSE2004_DEVID 0x2200
92 #define TSE2004_DEVID_MASK 0xff00
94 #define TS3000_DEVID 0x2900 /* Also matches TSE2002 */
95 #define TS3000_DEVID_MASK 0xff00
97 #define TS3001_DEVID 0x3000
98 #define TS3001_DEVID_MASK 0xff00
101 #define MAX6604_DEVID 0x3e00
102 #define MAX6604_DEVID_MASK 0xffff
105 #define MCP9804_DEVID 0x0200
106 #define MCP9804_DEVID_MASK 0xfffc
108 #define MCP9808_DEVID 0x0400
109 #define MCP9808_DEVID_MASK 0xfffc
111 #define MCP98242_DEVID 0x2000
112 #define MCP98242_DEVID_MASK 0xfffc
114 #define MCP98243_DEVID 0x2100
115 #define MCP98243_DEVID_MASK 0xfffc
117 #define MCP98244_DEVID 0x2200
118 #define MCP98244_DEVID_MASK 0xfffc
120 #define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */
121 #define MCP9843_DEVID_MASK 0xfffe
124 #define SE97_DEVID 0xa200
125 #define SE97_DEVID_MASK 0xfffc
127 #define SE98_DEVID 0xa100
128 #define SE98_DEVID_MASK 0xfffc
130 /* ON Semiconductor */
131 #define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */
132 #define CAT6095_DEVID_MASK 0xffe0
134 #define CAT34TS02C_DEVID 0x0a00
135 #define CAT34TS02C_DEVID_MASK 0xfff0
137 #define CAT34TS04_DEVID 0x2200
138 #define CAT34TS04_DEVID_MASK 0xfff0
140 #define N34TS04_DEVID 0x2230
141 #define N34TS04_DEVID_MASK 0xfff0
143 /* ST Microelectronics */
144 #define STTS424_DEVID 0x0101
145 #define STTS424_DEVID_MASK 0xffff
147 #define STTS424E_DEVID 0x0000
148 #define STTS424E_DEVID_MASK 0xfffe
150 #define STTS2002_DEVID 0x0300
151 #define STTS2002_DEVID_MASK 0xffff
153 #define STTS2004_DEVID 0x2201
154 #define STTS2004_DEVID_MASK 0xffff
156 #define STTS3000_DEVID 0x0200
157 #define STTS3000_DEVID_MASK 0xffff
159 static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
167 static struct jc42_chips jc42_chips[] = {
168 { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
169 { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
170 { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
171 { GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK },
172 { GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
173 { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
174 { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
175 { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
176 { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
177 { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
178 { MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
179 { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
180 { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
181 { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
182 { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
183 { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
184 { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
185 { ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
186 { ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
187 { ONS_MANID, N34TS04_DEVID, N34TS04_DEVID_MASK },
188 { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
189 { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
190 { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
191 { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
192 { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
193 { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
204 static const u8 temp_regs[t_num_temp] = {
205 [t_input] = JC42_REG_TEMP,
206 [t_crit] = JC42_REG_TEMP_CRITICAL,
207 [t_min] = JC42_REG_TEMP_LOWER,
208 [t_max] = JC42_REG_TEMP_UPPER,
211 /* Each client has this additional data */
213 struct i2c_client *client;
214 struct mutex update_lock; /* protect register access */
215 bool extended; /* true if extended range supported */
217 unsigned long last_updated; /* In jiffies */
218 u16 orig_config; /* original configuration */
219 u16 config; /* current configuration */
220 u16 temp[t_num_temp];/* Temperatures */
223 #define JC42_TEMP_MIN_EXTENDED (-40000)
224 #define JC42_TEMP_MIN 0
225 #define JC42_TEMP_MAX 125000
227 static u16 jc42_temp_to_reg(long temp, bool extended)
229 int ntemp = clamp_val(temp,
230 extended ? JC42_TEMP_MIN_EXTENDED :
231 JC42_TEMP_MIN, JC42_TEMP_MAX);
233 /* convert from 0.001 to 0.0625 resolution */
234 return (ntemp * 2 / 125) & 0x1fff;
237 static int jc42_temp_from_reg(s16 reg)
239 reg = sign_extend32(reg, 12);
241 /* convert from 0.0625 to 0.001 resolution */
242 return reg * 125 / 2;
245 static struct jc42_data *jc42_update_device(struct device *dev)
247 struct jc42_data *data = dev_get_drvdata(dev);
248 struct i2c_client *client = data->client;
249 struct jc42_data *ret = data;
252 mutex_lock(&data->update_lock);
254 if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
255 for (i = 0; i < t_num_temp; i++) {
256 val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
263 data->last_updated = jiffies;
267 mutex_unlock(&data->update_lock);
271 static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
272 u32 attr, int channel, long *val)
274 struct jc42_data *data = jc42_update_device(dev);
278 return PTR_ERR(data);
281 case hwmon_temp_input:
282 *val = jc42_temp_from_reg(data->temp[t_input]);
285 *val = jc42_temp_from_reg(data->temp[t_min]);
288 *val = jc42_temp_from_reg(data->temp[t_max]);
290 case hwmon_temp_crit:
291 *val = jc42_temp_from_reg(data->temp[t_crit]);
293 case hwmon_temp_max_hyst:
294 temp = jc42_temp_from_reg(data->temp[t_max]);
295 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
296 >> JC42_CFG_HYST_SHIFT];
299 case hwmon_temp_crit_hyst:
300 temp = jc42_temp_from_reg(data->temp[t_crit]);
301 hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
302 >> JC42_CFG_HYST_SHIFT];
305 case hwmon_temp_min_alarm:
306 *val = (data->temp[t_input] >> JC42_ALARM_MIN_BIT) & 1;
308 case hwmon_temp_max_alarm:
309 *val = (data->temp[t_input] >> JC42_ALARM_MAX_BIT) & 1;
311 case hwmon_temp_crit_alarm:
312 *val = (data->temp[t_input] >> JC42_ALARM_CRIT_BIT) & 1;
319 static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
320 u32 attr, int channel, long val)
322 struct jc42_data *data = dev_get_drvdata(dev);
323 struct i2c_client *client = data->client;
327 mutex_lock(&data->update_lock);
331 data->temp[t_min] = jc42_temp_to_reg(val, data->extended);
332 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_min],
336 data->temp[t_max] = jc42_temp_to_reg(val, data->extended);
337 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_max],
340 case hwmon_temp_crit:
341 data->temp[t_crit] = jc42_temp_to_reg(val, data->extended);
342 ret = i2c_smbus_write_word_swapped(client, temp_regs[t_crit],
345 case hwmon_temp_crit_hyst:
347 * JC42.4 compliant chips only support four hysteresis values.
348 * Pick best choice and go from there.
350 val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
351 : JC42_TEMP_MIN) - 6000,
353 diff = jc42_temp_from_reg(data->temp[t_crit]) - val;
357 hyst = 1; /* 1.5 degrees C */
358 else if (diff < 4500)
359 hyst = 2; /* 3.0 degrees C */
361 hyst = 3; /* 6.0 degrees C */
363 data->config = (data->config & ~JC42_CFG_HYST_MASK) |
364 (hyst << JC42_CFG_HYST_SHIFT);
365 ret = i2c_smbus_write_word_swapped(data->client,
374 mutex_unlock(&data->update_lock);
379 static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
380 u32 attr, int channel)
382 const struct jc42_data *data = _data;
383 unsigned int config = data->config;
389 if (!(config & JC42_CFG_EVENT_LOCK))
392 case hwmon_temp_crit:
393 if (!(config & JC42_CFG_TCRIT_LOCK))
396 case hwmon_temp_crit_hyst:
397 if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK)))
400 case hwmon_temp_input:
401 case hwmon_temp_max_hyst:
402 case hwmon_temp_min_alarm:
403 case hwmon_temp_max_alarm:
404 case hwmon_temp_crit_alarm:
413 /* Return 0 if detection is successful, -ENODEV otherwise */
414 static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
416 struct i2c_adapter *adapter = client->adapter;
417 int i, config, cap, manid, devid;
419 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
420 I2C_FUNC_SMBUS_WORD_DATA))
423 cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
424 config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
425 manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
426 devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
428 if (cap < 0 || config < 0 || manid < 0 || devid < 0)
431 if ((cap & 0xff00) || (config & 0xf800))
434 for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
435 struct jc42_chips *chip = &jc42_chips[i];
436 if (manid == chip->manid &&
437 (devid & chip->devid_mask) == chip->devid) {
438 strlcpy(info->type, "jc42", I2C_NAME_SIZE);
445 static const struct hwmon_channel_info *jc42_info[] = {
446 HWMON_CHANNEL_INFO(temp,
447 HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
448 HWMON_T_CRIT | HWMON_T_MAX_HYST |
449 HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
450 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM),
454 static const struct hwmon_ops jc42_hwmon_ops = {
455 .is_visible = jc42_is_visible,
460 static const struct hwmon_chip_info jc42_chip_info = {
461 .ops = &jc42_hwmon_ops,
465 static int jc42_probe(struct i2c_client *client)
467 struct device *dev = &client->dev;
468 struct device *hwmon_dev;
469 struct jc42_data *data;
472 data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
476 data->client = client;
477 i2c_set_clientdata(client, data);
478 mutex_init(&data->update_lock);
480 cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
484 data->extended = !!(cap & JC42_CAP_RANGE);
486 if (device_property_read_bool(dev, "smbus-timeout-disable")) {
490 * Not all chips support this register, but from a
491 * quick read of various datasheets no chip appears
492 * incompatible with the below attempt to disable
493 * the timeout. And the whole thing is opt-in...
495 smbus = i2c_smbus_read_word_swapped(client, JC42_REG_SMBUS);
498 i2c_smbus_write_word_swapped(client, JC42_REG_SMBUS,
499 smbus | SMBUS_STMOUT);
502 config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
506 data->orig_config = config;
507 if (config & JC42_CFG_SHUTDOWN) {
508 config &= ~JC42_CFG_SHUTDOWN;
509 i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
511 data->config = config;
513 hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42",
514 data, &jc42_chip_info,
516 return PTR_ERR_OR_ZERO(hwmon_dev);
519 static int jc42_remove(struct i2c_client *client)
521 struct jc42_data *data = i2c_get_clientdata(client);
523 /* Restore original configuration except hysteresis */
524 if ((data->config & ~JC42_CFG_HYST_MASK) !=
525 (data->orig_config & ~JC42_CFG_HYST_MASK)) {
528 config = (data->orig_config & ~JC42_CFG_HYST_MASK)
529 | (data->config & JC42_CFG_HYST_MASK);
530 i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
537 static int jc42_suspend(struct device *dev)
539 struct jc42_data *data = dev_get_drvdata(dev);
541 data->config |= JC42_CFG_SHUTDOWN;
542 i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
547 static int jc42_resume(struct device *dev)
549 struct jc42_data *data = dev_get_drvdata(dev);
551 data->config &= ~JC42_CFG_SHUTDOWN;
552 i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
557 static const struct dev_pm_ops jc42_dev_pm_ops = {
558 .suspend = jc42_suspend,
559 .resume = jc42_resume,
562 #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
564 #define JC42_DEV_PM_OPS NULL
565 #endif /* CONFIG_PM */
567 static const struct i2c_device_id jc42_id[] = {
571 MODULE_DEVICE_TABLE(i2c, jc42_id);
574 static const struct of_device_id jc42_of_ids[] = {
575 { .compatible = "jedec,jc-42.4-temp", },
578 MODULE_DEVICE_TABLE(of, jc42_of_ids);
581 static struct i2c_driver jc42_driver = {
582 .class = I2C_CLASS_SPD | I2C_CLASS_HWMON,
585 .pm = JC42_DEV_PM_OPS,
586 .of_match_table = of_match_ptr(jc42_of_ids),
588 .probe_new = jc42_probe,
589 .remove = jc42_remove,
591 .detect = jc42_detect,
592 .address_list = normal_i2c,
595 module_i2c_driver(jc42_driver);
597 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
598 MODULE_DESCRIPTION("JC42 driver");
599 MODULE_LICENSE("GPL");