2 * Copyright (c) 2017 Lucas Stach, Pengutronix
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 #include <drm/drm_fourcc.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/genalloc.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <video/imx-ipu-v3.h>
25 #define IPU_PRE_MAX_WIDTH 2048
26 #define IPU_PRE_NUM_SCANLINES 8
28 #define IPU_PRE_CTRL 0x000
29 #define IPU_PRE_CTRL_SET 0x004
30 #define IPU_PRE_CTRL_ENABLE (1 << 0)
31 #define IPU_PRE_CTRL_BLOCK_EN (1 << 1)
32 #define IPU_PRE_CTRL_BLOCK_16 (1 << 2)
33 #define IPU_PRE_CTRL_SDW_UPDATE (1 << 4)
34 #define IPU_PRE_CTRL_VFLIP (1 << 5)
35 #define IPU_PRE_CTRL_SO (1 << 6)
36 #define IPU_PRE_CTRL_INTERLACED_FIELD (1 << 7)
37 #define IPU_PRE_CTRL_HANDSHAKE_EN (1 << 8)
38 #define IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v) ((v & 0x3) << 9)
39 #define IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN (1 << 11)
40 #define IPU_PRE_CTRL_EN_REPEAT (1 << 28)
41 #define IPU_PRE_CTRL_TPR_REST_SEL (1 << 29)
42 #define IPU_PRE_CTRL_CLKGATE (1 << 30)
43 #define IPU_PRE_CTRL_SFTRST (1 << 31)
45 #define IPU_PRE_CUR_BUF 0x030
47 #define IPU_PRE_NEXT_BUF 0x040
49 #define IPU_PRE_TPR_CTRL 0x070
50 #define IPU_PRE_TPR_CTRL_TILE_FORMAT(v) ((v & 0xff) << 0)
51 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK 0xff
52 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT (1 << 0)
53 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SPLIT_BUF (1 << 4)
54 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF (1 << 5)
55 #define IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED (1 << 6)
57 #define IPU_PRE_PREFETCH_ENG_CTRL 0x080
58 #define IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN (1 << 0)
59 #define IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v) ((v & 0x7) << 1)
60 #define IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
61 #define IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v) ((v & 0x7) << 8)
62 #define IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS (1 << 11)
63 #define IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE (1 << 12)
64 #define IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP (1 << 14)
65 #define IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN (1 << 15)
67 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE 0x0a0
68 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v) ((v & 0xffff) << 0)
69 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v) ((v & 0xffff) << 16)
71 #define IPU_PRE_PREFETCH_ENG_PITCH 0x0d0
72 #define IPU_PRE_PREFETCH_ENG_PITCH_Y(v) ((v & 0xffff) << 0)
73 #define IPU_PRE_PREFETCH_ENG_PITCH_UV(v) ((v & 0xffff) << 16)
75 #define IPU_PRE_STORE_ENG_CTRL 0x110
76 #define IPU_PRE_STORE_ENG_CTRL_STORE_EN (1 << 0)
77 #define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1)
78 #define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
80 #define IPU_PRE_STORE_ENG_STATUS 0x120
81 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK 0xffff
82 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT 0
83 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK 0x3fff
84 #define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT 16
85 #define IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL (1 << 30)
86 #define IPU_PRE_STORE_ENG_STATUS_STORE_FIELD (1 << 31)
88 #define IPU_PRE_STORE_ENG_SIZE 0x130
89 #define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0)
90 #define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16)
92 #define IPU_PRE_STORE_ENG_PITCH 0x140
93 #define IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v) ((v & 0xffff) << 0)
95 #define IPU_PRE_STORE_ENG_ADDR 0x150
98 struct list_head list;
103 struct gen_pool *iram;
105 dma_addr_t buffer_paddr;
108 unsigned int safe_window_end;
109 unsigned int last_bufaddr;
112 static DEFINE_MUTEX(ipu_pre_list_mutex);
113 static LIST_HEAD(ipu_pre_list);
114 static int available_pres;
116 int ipu_pre_get_available_count(void)
118 return available_pres;
122 ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index)
124 struct device_node *pre_node = of_parse_phandle(dev->of_node,
128 mutex_lock(&ipu_pre_list_mutex);
129 list_for_each_entry(pre, &ipu_pre_list, list) {
130 if (pre_node == pre->dev->of_node) {
131 mutex_unlock(&ipu_pre_list_mutex);
132 device_link_add(dev, pre->dev,
133 DL_FLAG_AUTOREMOVE_CONSUMER);
134 of_node_put(pre_node);
138 mutex_unlock(&ipu_pre_list_mutex);
140 of_node_put(pre_node);
145 int ipu_pre_get(struct ipu_pre *pre)
152 /* first get the engine out of reset and remove clock gating */
153 writel(0, pre->regs + IPU_PRE_CTRL);
155 /* init defaults that should be applied to all streams */
156 val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN |
157 IPU_PRE_CTRL_HANDSHAKE_EN |
158 IPU_PRE_CTRL_TPR_REST_SEL |
159 IPU_PRE_CTRL_SDW_UPDATE;
160 writel(val, pre->regs + IPU_PRE_CTRL);
166 void ipu_pre_put(struct ipu_pre *pre)
168 writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);
173 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
174 unsigned int height, unsigned int stride, u32 format,
175 uint64_t modifier, unsigned int bufaddr)
177 const struct drm_format_info *info = drm_format_info(format);
178 u32 active_bpp = info->cpp[0] >> 1;
181 /* calculate safe window for ctrl register updates */
182 if (modifier == DRM_FORMAT_MOD_LINEAR)
183 pre->safe_window_end = height - 2;
185 pre->safe_window_end = DIV_ROUND_UP(height, 4) - 1;
187 writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
188 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
189 pre->last_bufaddr = bufaddr;
191 val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) |
192 IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) |
193 IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) |
194 IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS |
195 IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN;
196 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);
198 val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) |
199 IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height);
200 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);
202 val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride);
203 writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);
205 val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) |
206 IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) |
207 IPU_PRE_STORE_ENG_CTRL_STORE_EN;
208 writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);
210 val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) |
211 IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height);
212 writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);
214 val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride);
215 writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);
217 writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);
219 val = readl(pre->regs + IPU_PRE_TPR_CTRL);
220 val &= ~IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK;
221 if (modifier != DRM_FORMAT_MOD_LINEAR) {
222 /* only support single buffer formats for now */
223 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF;
224 if (modifier == DRM_FORMAT_MOD_VIVANTE_SUPER_TILED)
225 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED;
226 if (info->cpp[0] == 2)
227 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT;
229 writel(val, pre->regs + IPU_PRE_TPR_CTRL);
231 val = readl(pre->regs + IPU_PRE_CTRL);
232 val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE |
233 IPU_PRE_CTRL_SDW_UPDATE;
234 if (modifier == DRM_FORMAT_MOD_LINEAR)
235 val &= ~IPU_PRE_CTRL_BLOCK_EN;
237 val |= IPU_PRE_CTRL_BLOCK_EN;
238 writel(val, pre->regs + IPU_PRE_CTRL);
241 void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
243 unsigned long timeout = jiffies + msecs_to_jiffies(5);
244 unsigned short current_yblock;
247 if (bufaddr == pre->last_bufaddr)
250 writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
251 pre->last_bufaddr = bufaddr;
254 if (time_after(jiffies, timeout)) {
255 dev_warn(pre->dev, "timeout waiting for PRE safe window\n");
259 val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS);
261 (val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) &
262 IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK;
263 } while (current_yblock == 0 || current_yblock >= pre->safe_window_end);
265 writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
268 bool ipu_pre_update_pending(struct ipu_pre *pre)
270 return !!(readl_relaxed(pre->regs + IPU_PRE_CTRL) &
271 IPU_PRE_CTRL_SDW_UPDATE);
274 u32 ipu_pre_get_baddr(struct ipu_pre *pre)
276 return (u32)pre->buffer_paddr;
279 static int ipu_pre_probe(struct platform_device *pdev)
281 struct device *dev = &pdev->dev;
282 struct resource *res;
285 pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL);
289 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
290 pre->regs = devm_ioremap_resource(&pdev->dev, res);
291 if (IS_ERR(pre->regs))
292 return PTR_ERR(pre->regs);
294 pre->clk_axi = devm_clk_get(dev, "axi");
295 if (IS_ERR(pre->clk_axi))
296 return PTR_ERR(pre->clk_axi);
298 pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0);
300 return -EPROBE_DEFER;
303 * Allocate IRAM buffer with maximum size. This could be made dynamic,
304 * but as there is no other user of this IRAM region and we can fit all
305 * max sized buffers into it, there is no need yet.
307 pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH *
308 IPU_PRE_NUM_SCANLINES * 4,
310 if (!pre->buffer_virt)
313 clk_prepare_enable(pre->clk_axi);
316 platform_set_drvdata(pdev, pre);
317 mutex_lock(&ipu_pre_list_mutex);
318 list_add(&pre->list, &ipu_pre_list);
320 mutex_unlock(&ipu_pre_list_mutex);
325 static int ipu_pre_remove(struct platform_device *pdev)
327 struct ipu_pre *pre = platform_get_drvdata(pdev);
329 mutex_lock(&ipu_pre_list_mutex);
330 list_del(&pre->list);
332 mutex_unlock(&ipu_pre_list_mutex);
334 clk_disable_unprepare(pre->clk_axi);
336 if (pre->buffer_virt)
337 gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
338 IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4);
342 static const struct of_device_id ipu_pre_dt_ids[] = {
343 { .compatible = "fsl,imx6qp-pre", },
347 struct platform_driver ipu_pre_drv = {
348 .probe = ipu_pre_probe,
349 .remove = ipu_pre_remove,
351 .name = "imx-ipu-pre",
352 .of_match_table = ipu_pre_dt_ids,