drivers/gpu/drm/xlnx/zynqmp_disp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ZynqMP Display Controller Driver
   4  *
   5  * Copyright (C) 2017 - 2020 Xilinx, Inc.
   6  *
   7  * Authors:
   8  * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
   9  * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10  */
  11
  12 #include <drm/drm_atomic.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_atomic_uapi.h>
  15 #include <drm/drm_crtc.h>
  16 #include <drm/drm_device.h>
  17 #include <drm/drm_fb_cma_helper.h>
  18 #include <drm/drm_fourcc.h>
  19 #include <drm/drm_framebuffer.h>
  20 #include <drm/drm_managed.h>
  21 #include <drm/drm_plane.h>
  22 #include <drm/drm_plane_helper.h>
  23 #include <drm/drm_vblank.h>
  24
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/module.h>
  30 #include <linux/of.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/spinlock.h>
  34
  35 #include "zynqmp_disp.h"
  36 #include "zynqmp_disp_regs.h"
  37 #include "zynqmp_dp.h"
  38 #include "zynqmp_dpsub.h"
  39
  40 /*
  41  * Overview
  42  * --------
  43  *
  44  * The display controller part of ZynqMP DP subsystem, made of the Audio/Video
  45  * Buffer Manager, the Video Rendering Pipeline (blender) and the Audio Mixer.
  46  *
  47  *              +------------------------------------------------------------+
  48  * +--------+   | +----------------+     +-----------+                       |
  49  * | DPDMA  | --->|                | --> |   Video   | Video +-------------+ |
  50  * | 4x vid |   | |                |     | Rendering | -+--> |             | |   +------+
  51  * | 2x aud |   | |  Audio/Video   | --> | Pipeline  |  |    | DisplayPort |---> | PHY0 |
  52  * +--------+   | | Buffer Manager |     +-----------+  |    |   Source    | |   +------+
  53  *              | |    and STC     |     +-----------+  |    | Controller  | |   +------+
  54  * Live Video --->|                | --> |   Audio   | Audio |             |---> | PHY1 |
  55  *              | |                |     |   Mixer   | --+-> |             | |   +------+
  56  * Live Audio --->|                | --> |           |  ||   +-------------+ |
  57  *              | +----------------+     +-----------+  ||                   |
  58  *              +---------------------------------------||-------------------+
  59  *                                                      vv
  60  *                                                Blended Video and
  61  *                                                Mixed Audio to PL
  62  *
  63  * Only non-live input from the DPDMA and output to the DisplayPort Source
  64  * Controller are currently supported. Interface with the programmable logic
  65  * for live streams is not implemented.
  66  *
  67  * The display controller code creates planes for the DPDMA video and graphics
  68  * layers, and a CRTC for the Video Rendering Pipeline.
  69  */
  70
  71 #define ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS          4
  72 #define ZYNQMP_DISP_AV_BUF_NUM_BUFFERS                  6
  73
  74 #define ZYNQMP_DISP_NUM_LAYERS                          2
  75 #define ZYNQMP_DISP_MAX_NUM_SUB_PLANES                  3
  76
  77 /**
  78  * struct zynqmp_disp_format - Display subsystem format information
  79  * @drm_fmt: DRM format (4CC)
  80  * @buf_fmt: AV buffer format
  81  * @bus_fmt: Media bus formats (live formats)
  82  * @swap: Flag to swap R & B for RGB formats, and U & V for YUV formats
  83  * @sf: Scaling factors for color components
  84  */
  85 struct zynqmp_disp_format {
  86         u32 drm_fmt;
  87         u32 buf_fmt;
  88         u32 bus_fmt;
  89         bool swap;
  90         const u32 *sf;
  91 };
  92
  93 /**
  94  * enum zynqmp_disp_id - Layer identifier
  95  * @ZYNQMP_DISP_LAYER_VID: Video layer
  96  * @ZYNQMP_DISP_LAYER_GFX: Graphics layer
  97  */
  98 enum zynqmp_disp_layer_id {
  99         ZYNQMP_DISP_LAYER_VID,
 100         ZYNQMP_DISP_LAYER_GFX
 101 };
 102
 103 /**
 104  * enum zynqmp_disp_layer_mode - Layer mode
 105  * @ZYNQMP_DISP_LAYER_NONLIVE: non-live (memory) mode
 106  * @ZYNQMP_DISP_LAYER_LIVE: live (stream) mode
 107  */
 108 enum zynqmp_disp_layer_mode {
 109         ZYNQMP_DISP_LAYER_NONLIVE,
 110         ZYNQMP_DISP_LAYER_LIVE
 111 };
 112
 113 /**
 114  * struct zynqmp_disp_layer_dma - DMA channel for one data plane of a layer
 115  * @chan: DMA channel
 116  * @xt: Interleaved DMA descriptor template
 117  * @sgl: Data chunk for dma_interleaved_template
 118  */
 119 struct zynqmp_disp_layer_dma {
 120         struct dma_chan *chan;
 121         struct dma_interleaved_template xt;
 122         struct data_chunk sgl;
 123 };
 124
 125 /**
 126  * struct zynqmp_disp_layer_info - Static layer information
 127  * @formats: Array of supported formats
 128  * @num_formats: Number of formats in @formats array
 129  * @num_channels: Number of DMA channels
 130  */
 131 struct zynqmp_disp_layer_info {
 132         const struct zynqmp_disp_format *formats;
 133         unsigned int num_formats;
 134         unsigned int num_channels;
 135 };
 136
 137 /**
 138  * struct zynqmp_disp_layer - Display layer (DRM plane)
 139  * @plane: DRM plane
 140  * @id: Layer ID
 141  * @disp: Back pointer to struct zynqmp_disp
 142  * @info: Static layer information
 143  * @dmas: DMA channels
 144  * @disp_fmt: Current format information
 145  * @drm_fmt: Current DRM format information
 146  * @mode: Current operation mode
 147  */
 148 struct zynqmp_disp_layer {
 149         struct drm_plane plane;
 150         enum zynqmp_disp_layer_id id;
 151         struct zynqmp_disp *disp;
 152         const struct zynqmp_disp_layer_info *info;
 153
 154         struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES];
 155
 156         const struct zynqmp_disp_format *disp_fmt;
 157         const struct drm_format_info *drm_fmt;
 158         enum zynqmp_disp_layer_mode mode;
 159 };
 160
 161 /**
 162  * struct zynqmp_disp_blend - Blender
 163  * @base: Registers I/O base address
 164  */
 165 struct zynqmp_disp_blend {
 166         void __iomem *base;
 167 };
 168
 169 /**
 170  * struct zynqmp_disp_avbuf - Audio/video buffer manager
 171  * @base: Registers I/O base address
 172  */
 173 struct zynqmp_disp_avbuf {
 174         void __iomem *base;
 175 };
 176
 177 /**
 178  * struct zynqmp_disp_audio - Audio mixer
 179  * @base: Registers I/O base address
 180  * @clk: Audio clock
 181  * @clk_from_ps: True of the audio clock comes from PS, false from PL
 182  */
 183 struct zynqmp_disp_audio {
 184         void __iomem *base;
 185         struct clk *clk;
 186         bool clk_from_ps;
 187 };
 188
 189 /**
 190  * struct zynqmp_disp - Display controller
 191  * @dev: Device structure
 192  * @drm: DRM core
 193  * @dpsub: Display subsystem
 194  * @crtc: DRM CRTC
 195  * @blend: Blender (video rendering pipeline)
 196  * @avbuf: Audio/video buffer manager
 197  * @audio: Audio mixer
 198  * @layers: Layers (planes)
 199  * @event: Pending vblank event request
 200  * @pclk: Pixel clock
 201  * @pclk_from_ps: True of the video clock comes from PS, false from PL
 202  */
 203 struct zynqmp_disp {
 204         struct device *dev;
 205         struct drm_device *drm;
 206         struct zynqmp_dpsub *dpsub;
 207
 208         struct drm_crtc crtc;
 209
 210         struct zynqmp_disp_blend blend;
 211         struct zynqmp_disp_avbuf avbuf;
 212         struct zynqmp_disp_audio audio;
 213
 214         struct zynqmp_disp_layer layers[ZYNQMP_DISP_NUM_LAYERS];
 215
 216         struct drm_pending_vblank_event *event;
 217
 218         struct clk *pclk;
 219         bool pclk_from_ps;
 220 };
 221
 222 /* -----------------------------------------------------------------------------
 223  * Audio/Video Buffer Manager
 224  */
 225
 226 static const u32 scaling_factors_444[] = {
 227         ZYNQMP_DISP_AV_BUF_4BIT_SF,
 228         ZYNQMP_DISP_AV_BUF_4BIT_SF,
 229         ZYNQMP_DISP_AV_BUF_4BIT_SF,
 230 };
 231
 232 static const u32 scaling_factors_555[] = {
 233         ZYNQMP_DISP_AV_BUF_5BIT_SF,
 234         ZYNQMP_DISP_AV_BUF_5BIT_SF,
 235         ZYNQMP_DISP_AV_BUF_5BIT_SF,
 236 };
 237
 238 static const u32 scaling_factors_565[] = {
 239         ZYNQMP_DISP_AV_BUF_5BIT_SF,
 240         ZYNQMP_DISP_AV_BUF_6BIT_SF,
 241         ZYNQMP_DISP_AV_BUF_5BIT_SF,
 242 };
 243
 244 static const u32 scaling_factors_888[] = {
 245         ZYNQMP_DISP_AV_BUF_8BIT_SF,
 246         ZYNQMP_DISP_AV_BUF_8BIT_SF,
 247         ZYNQMP_DISP_AV_BUF_8BIT_SF,
 248 };
 249
 250 static const u32 scaling_factors_101010[] = {
 251         ZYNQMP_DISP_AV_BUF_10BIT_SF,
 252         ZYNQMP_DISP_AV_BUF_10BIT_SF,
 253         ZYNQMP_DISP_AV_BUF_10BIT_SF,
 254 };
 255
 256 /* List of video layer formats */
 257 static const struct zynqmp_disp_format avbuf_vid_fmts[] = {
 258         {
 259                 .drm_fmt        = DRM_FORMAT_VYUY,
 260                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY,
 261                 .swap           = true,
 262                 .sf             = scaling_factors_888,
 263         }, {
 264                 .drm_fmt        = DRM_FORMAT_UYVY,
 265                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY,
 266                 .swap           = false,
 267                 .sf             = scaling_factors_888,
 268         }, {
 269                 .drm_fmt        = DRM_FORMAT_YUYV,
 270                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV,
 271                 .swap           = false,
 272                 .sf             = scaling_factors_888,
 273         }, {
 274                 .drm_fmt        = DRM_FORMAT_YVYU,
 275                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV,
 276                 .swap           = true,
 277                 .sf             = scaling_factors_888,
 278         }, {
 279                 .drm_fmt        = DRM_FORMAT_YUV422,
 280                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16,
 281                 .swap           = false,
 282                 .sf             = scaling_factors_888,
 283         }, {
 284                 .drm_fmt        = DRM_FORMAT_YVU422,
 285                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16,
 286                 .swap           = true,
 287                 .sf             = scaling_factors_888,
 288         }, {
 289                 .drm_fmt        = DRM_FORMAT_YUV444,
 290                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24,
 291                 .swap           = false,
 292                 .sf             = scaling_factors_888,
 293         }, {
 294                 .drm_fmt        = DRM_FORMAT_YVU444,
 295                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24,
 296                 .swap           = true,
 297                 .sf             = scaling_factors_888,
 298         }, {
 299                 .drm_fmt        = DRM_FORMAT_NV16,
 300                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI,
 301                 .swap           = false,
 302                 .sf             = scaling_factors_888,
 303         }, {
 304                 .drm_fmt        = DRM_FORMAT_NV61,
 305                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI,
 306                 .swap           = true,
 307                 .sf             = scaling_factors_888,
 308         }, {
 309                 .drm_fmt        = DRM_FORMAT_BGR888,
 310                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888,
 311                 .swap           = false,
 312                 .sf             = scaling_factors_888,
 313         }, {
 314                 .drm_fmt        = DRM_FORMAT_RGB888,
 315                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888,
 316                 .swap           = true,
 317                 .sf             = scaling_factors_888,
 318         }, {
 319                 .drm_fmt        = DRM_FORMAT_XBGR8888,
 320                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880,
 321                 .swap           = false,
 322                 .sf             = scaling_factors_888,
 323         }, {
 324                 .drm_fmt        = DRM_FORMAT_XRGB8888,
 325                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880,
 326                 .swap           = true,
 327                 .sf             = scaling_factors_888,
 328         }, {
 329                 .drm_fmt        = DRM_FORMAT_XBGR2101010,
 330                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10,
 331                 .swap           = false,
 332                 .sf             = scaling_factors_101010,
 333         }, {
 334                 .drm_fmt        = DRM_FORMAT_XRGB2101010,
 335                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10,
 336                 .swap           = true,
 337                 .sf             = scaling_factors_101010,
 338         }, {
 339                 .drm_fmt        = DRM_FORMAT_YUV420,
 340                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420,
 341                 .swap           = false,
 342                 .sf             = scaling_factors_888,
 343         }, {
 344                 .drm_fmt        = DRM_FORMAT_YVU420,
 345                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420,
 346                 .swap           = true,
 347                 .sf             = scaling_factors_888,
 348         }, {
 349                 .drm_fmt        = DRM_FORMAT_NV12,
 350                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420,
 351                 .swap           = false,
 352                 .sf             = scaling_factors_888,
 353         }, {
 354                 .drm_fmt        = DRM_FORMAT_NV21,
 355                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420,
 356                 .swap           = true,
 357                 .sf             = scaling_factors_888,
 358         },
 359 };
 360
 361 /* List of graphics layer formats */
 362 static const struct zynqmp_disp_format avbuf_gfx_fmts[] = {
 363         {
 364                 .drm_fmt        = DRM_FORMAT_ABGR8888,
 365                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888,
 366                 .swap           = false,
 367                 .sf             = scaling_factors_888,
 368         }, {
 369                 .drm_fmt        = DRM_FORMAT_ARGB8888,
 370                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888,
 371                 .swap           = true,
 372                 .sf             = scaling_factors_888,
 373         }, {
 374                 .drm_fmt        = DRM_FORMAT_RGBA8888,
 375                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888,
 376                 .swap           = false,
 377                 .sf             = scaling_factors_888,
 378         }, {
 379                 .drm_fmt        = DRM_FORMAT_BGRA8888,
 380                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888,
 381                 .swap           = true,
 382                 .sf             = scaling_factors_888,
 383         }, {
 384                 .drm_fmt        = DRM_FORMAT_BGR888,
 385                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888,
 386                 .swap           = false,
 387                 .sf             = scaling_factors_888,
 388         }, {
 389                 .drm_fmt        = DRM_FORMAT_RGB888,
 390                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888,
 391                 .swap           = false,
 392                 .sf             = scaling_factors_888,
 393         }, {
 394                 .drm_fmt        = DRM_FORMAT_RGBA5551,
 395                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551,
 396                 .swap           = false,
 397                 .sf             = scaling_factors_555,
 398         }, {
 399                 .drm_fmt        = DRM_FORMAT_BGRA5551,
 400                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551,
 401                 .swap           = true,
 402                 .sf             = scaling_factors_555,
 403         }, {
 404                 .drm_fmt        = DRM_FORMAT_RGBA4444,
 405                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444,
 406                 .swap           = false,
 407                 .sf             = scaling_factors_444,
 408         }, {
 409                 .drm_fmt        = DRM_FORMAT_BGRA4444,
 410                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444,
 411                 .swap           = true,
 412                 .sf             = scaling_factors_444,
 413         }, {
 414                 .drm_fmt        = DRM_FORMAT_RGB565,
 415                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565,
 416                 .swap           = false,
 417                 .sf             = scaling_factors_565,
 418         }, {
 419                 .drm_fmt        = DRM_FORMAT_BGR565,
 420                 .buf_fmt        = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565,
 421                 .swap           = true,
 422                 .sf             = scaling_factors_565,
 423         },
 424 };
 425
 426 static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp_avbuf *avbuf, int reg)
 427 {
 428         return readl(avbuf->base + reg);
 429 }
 430
 431 static void zynqmp_disp_avbuf_write(struct zynqmp_disp_avbuf *avbuf,
 432                                     int reg, u32 val)
 433 {
 434         writel(val, avbuf->base + reg);
 435 }
 436
 437 /**
 438  * zynqmp_disp_avbuf_set_format - Set the input format for a layer
 439  * @avbuf: Audio/video buffer manager
 440  * @layer: The layer ID
 441  * @fmt: The format information
 442  *
 443  * Set the video buffer manager format for @layer to @fmt.
 444  */
 445 static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp_avbuf *avbuf,
 446                                          enum zynqmp_disp_layer_id layer,
 447                                          const struct zynqmp_disp_format *fmt)
 448 {
 449         unsigned int i;
 450         u32 val;
 451
 452         val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_FMT);
 453         val &= layer == ZYNQMP_DISP_LAYER_VID
 454             ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK
 455             : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK;
 456         val |= fmt->buf_fmt;
 457         zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_FMT, val);
 458
 459         for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++) {
 460                 unsigned int reg = layer == ZYNQMP_DISP_LAYER_VID
 461                                  ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i)
 462                                  : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i);
 463
 464                 zynqmp_disp_avbuf_write(avbuf, reg, fmt->sf[i]);
 465         }
 466 }
 467
 468 /**
 469  * zynqmp_disp_avbuf_set_clocks_sources - Set the clocks sources
 470  * @avbuf: Audio/video buffer manager
 471  * @video_from_ps: True if the video clock originates from the PS
 472  * @audio_from_ps: True if the audio clock originates from the PS
 473  * @timings_internal: True if video timings are generated internally
 474  *
 475  * Set the source for the video and audio clocks, as well as for the video
 476  * timings. Clocks can originate from the PS or PL, and timings can be
 477  * generated internally or externally.
 478  */
 479 static void
 480 zynqmp_disp_avbuf_set_clocks_sources(struct zynqmp_disp_avbuf *avbuf,
 481                                      bool video_from_ps, bool audio_from_ps,
 482                                      bool timings_internal)
 483 {
 484         u32 val = 0;
 485
 486         if (video_from_ps)
 487                 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS;
 488         if (audio_from_ps)
 489                 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS;
 490         if (timings_internal)
 491                 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING;
 492
 493         zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CLK_SRC, val);
 494 }
 495
 496 /**
 497  * zynqmp_disp_avbuf_enable_channels - Enable buffer channels
 498  * @avbuf: Audio/video buffer manager
 499  *
 500  * Enable all (video and audio) buffer channels.
 501  */
 502 static void zynqmp_disp_avbuf_enable_channels(struct zynqmp_disp_avbuf *avbuf)
 503 {
 504         unsigned int i;
 505         u32 val;
 506
 507         val = ZYNQMP_DISP_AV_BUF_CHBUF_EN |
 508               (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX <<
 509                ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT);
 510
 511         for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS; i++)
 512                 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CHBUF(i),
 513                                         val);
 514
 515         val = ZYNQMP_DISP_AV_BUF_CHBUF_EN |
 516               (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX <<
 517                ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT);
 518
 519         for (; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++)
 520                 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CHBUF(i),
 521                                         val);
 522 }
 523
 524 /**
 525  * zynqmp_disp_avbuf_disable_channels - Disable buffer channels
 526  * @avbuf: Audio/video buffer manager
 527  *
 528  * Disable all (video and audio) buffer channels.
 529  */
 530 static void zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp_avbuf *avbuf)
 531 {
 532         unsigned int i;
 533
 534         for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++)
 535                 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CHBUF(i),
 536                                         ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH);
 537 }
 538
 539 /**
 540  * zynqmp_disp_avbuf_enable_audio - Enable audio
 541  * @avbuf: Audio/video buffer manager
 542  *
 543  * Enable all audio buffers with a non-live (memory) source.
 544  */
 545 static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp_avbuf *avbuf)
 546 {
 547         u32 val;
 548
 549         val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT);
 550         val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK;
 551         val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM;
 552         val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN;
 553         zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
 554 }
 555
 556 /**
 557  * zynqmp_disp_avbuf_disable_audio - Disable audio
 558  * @avbuf: Audio/video buffer manager
 559  *
 560  * Disable all audio buffers.
 561  */
 562 static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp_avbuf *avbuf)
 563 {
 564         u32 val;
 565
 566         val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT);
 567         val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK;
 568         val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE;
 569         val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN;
 570         zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
 571 }
 572
 573 /**
 574  * zynqmp_disp_avbuf_enable_video - Enable a video layer
 575  * @avbuf: Audio/video buffer manager
 576  * @layer: The layer ID
 577  * @mode: Operating mode of layer
 578  *
 579  * Enable the video/graphics buffer for @layer.
 580  */
 581 static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp_avbuf *avbuf,
 582                                            enum zynqmp_disp_layer_id layer,
 583                                            enum zynqmp_disp_layer_mode mode)
 584 {
 585         u32 val;
 586
 587         val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT);
 588         if (layer == ZYNQMP_DISP_LAYER_VID) {
 589                 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK;
 590                 if (mode == ZYNQMP_DISP_LAYER_NONLIVE)
 591                         val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM;
 592                 else
 593                         val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE;
 594         } else {
 595                 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK;
 596                 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM;
 597                 if (mode == ZYNQMP_DISP_LAYER_NONLIVE)
 598                         val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM;
 599                 else
 600                         val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE;
 601         }
 602         zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
 603 }
 604
 605 /**
 606  * zynqmp_disp_avbuf_disable_video - Disable a video layer
 607  * @avbuf: Audio/video buffer manager
 608  * @layer: The layer ID
 609  *
 610  * Disable the video/graphics buffer for @layer.
 611  */
 612 static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp_avbuf *avbuf,
 613                                             enum zynqmp_disp_layer_id layer)
 614 {
 615         u32 val;
 616
 617         val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT);
 618         if (layer == ZYNQMP_DISP_LAYER_VID) {
 619                 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK;
 620                 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE;
 621         } else {
 622                 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK;
 623                 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE;
 624         }
 625         zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val);
 626 }
 627
 628 /**
 629  * zynqmp_disp_avbuf_enable - Enable the video pipe
 630  * @avbuf: Audio/video buffer manager
 631  *
 632  * De-assert the video pipe reset.
 633  */
 634 static void zynqmp_disp_avbuf_enable(struct zynqmp_disp_avbuf *avbuf)
 635 {
 636         zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_SRST_REG, 0);
 637 }
 638
 639 /**
 640  * zynqmp_disp_avbuf_disable - Disable the video pipe
 641  * @avbuf: Audio/video buffer manager
 642  *
 643  * Assert the video pipe reset.
 644  */
 645 static void zynqmp_disp_avbuf_disable(struct zynqmp_disp_avbuf *avbuf)
 646 {
 647         zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_SRST_REG,
 648                                 ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST);
 649 }
 650
 651 /* -----------------------------------------------------------------------------
 652  * Blender (Video Pipeline)
 653  */
 654
 655 static void zynqmp_disp_blend_write(struct zynqmp_disp_blend *blend,
 656                                     int reg, u32 val)
 657 {
 658         writel(val, blend->base + reg);
 659 }
 660
 661 /*
 662  * Colorspace conversion matrices.
 663  *
 664  * Hardcode RGB <-> YUV conversion to full-range SDTV for now.
 665  */
 666 static const u16 csc_zero_matrix[] = {
 667         0x0,    0x0,    0x0,
 668         0x0,    0x0,    0x0,
 669         0x0,    0x0,    0x0
 670 };
 671
 672 static const u16 csc_identity_matrix[] = {
 673         0x1000, 0x0,    0x0,
 674         0x0,    0x1000, 0x0,
 675         0x0,    0x0,    0x1000
 676 };
 677
 678 static const u32 csc_zero_offsets[] = {
 679         0, 0, 0
 680 };
 681
 682 static const u16 csc_rgb_to_sdtv_matrix[] = {
 683         0x4c9,  0x864,  0x1d3,
 684         0x7d4d, 0x7ab3, 0x800,
 685         0x800,  0x794d, 0x7eb3
 686 };
 687
 688 static const u32 csc_rgb_to_sdtv_offsets[] = {
 689         0x0, 0x8000000, 0x8000000
 690 };
 691
 692 static const u16 csc_sdtv_to_rgb_matrix[] = {
 693         0x1000, 0x166f, 0x0,
 694         0x1000, 0x7483, 0x7a7f,
 695         0x1000, 0x0,    0x1c5a
 696 };
 697
 698 static const u32 csc_sdtv_to_rgb_offsets[] = {
 699         0x0, 0x1800, 0x1800
 700 };
 701
 702 /**
 703  * zynqmp_disp_blend_set_output_format - Set the output format of the blender
 704  * @blend: Blender object
 705  * @format: Output format
 706  *
 707  * Set the output format of the blender to @format.
 708  */
 709 static void zynqmp_disp_blend_set_output_format(struct zynqmp_disp_blend *blend,
 710                                                 enum zynqmp_dpsub_format format)
 711 {
 712         static const unsigned int blend_output_fmts[] = {
 713                 [ZYNQMP_DPSUB_FORMAT_RGB] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB,
 714                 [ZYNQMP_DPSUB_FORMAT_YCRCB444] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444,
 715                 [ZYNQMP_DPSUB_FORMAT_YCRCB422] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422
 716                                                | ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE,
 717                 [ZYNQMP_DPSUB_FORMAT_YONLY] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY,
 718         };
 719
 720         u32 fmt = blend_output_fmts[format];
 721         const u16 *coeffs;
 722         const u32 *offsets;
 723         unsigned int i;
 724
 725         zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT, fmt);
 726         if (fmt == ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB) {
 727                 coeffs = csc_identity_matrix;
 728                 offsets = csc_zero_offsets;
 729         } else {
 730                 coeffs = csc_rgb_to_sdtv_matrix;
 731                 offsets = csc_rgb_to_sdtv_offsets;
 732         }
 733
 734         for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++)
 735                 zynqmp_disp_blend_write(blend,
 736                                         ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(i),
 737                                         coeffs[i]);
 738
 739         for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
 740                 zynqmp_disp_blend_write(blend,
 741                                         ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(i),
 742                                         offsets[i]);
 743 }
 744
 745 /**
 746  * zynqmp_disp_blend_set_bg_color - Set the background color
 747  * @blend: Blender object
 748  * @rcr: Red/Cr color component
 749  * @gy: Green/Y color component
 750  * @bcb: Blue/Cb color component
 751  *
 752  * Set the background color to (@rcr, @gy, @bcb), corresponding to the R, G and
 753  * B or Cr, Y and Cb components respectively depending on the selected output
 754  * format.
 755  */
 756 static void zynqmp_disp_blend_set_bg_color(struct zynqmp_disp_blend *blend,
 757                                            u32 rcr, u32 gy, u32 bcb)
 758 {
 759         zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_BG_CLR_0, rcr);
 760         zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_BG_CLR_1, gy);
 761         zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_BG_CLR_2, bcb);
 762 }
 763
 764 /**
 765  * zynqmp_disp_blend_set_global_alpha - Configure global alpha blending
 766  * @blend: Blender object
 767  * @enable: True to enable global alpha blending
 768  * @alpha: Global alpha value (ignored if @enabled is false)
 769  */
 770 static void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp_blend *blend,
 771                                                bool enable, u32 alpha)
 772 {
 773         zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA,
 774                                 ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(alpha) |
 775                                 (enable ? ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN : 0));
 776 }
 777
 778 /**
 779  * zynqmp_disp_blend_layer_set_csc - Configure colorspace conversion for layer
 780  * @blend: Blender object
 781  * @layer: The layer
 782  * @coeffs: Colorspace conversion matrix
 783  * @offsets: Colorspace conversion offsets
 784  *
 785  * Configure the input colorspace conversion matrix and offsets for the @layer.
 786  * Columns of the matrix are automatically swapped based on the input format to
 787  * handle RGB and YCrCb components permutations.
 788  */
 789 static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp_blend *blend,
 790                                             struct zynqmp_disp_layer *layer,
 791                                             const u16 *coeffs,
 792                                             const u32 *offsets)
 793 {
 794         unsigned int swap[3] = { 0, 1, 2 };
 795         unsigned int reg;
 796         unsigned int i;
 797
 798         if (layer->disp_fmt->swap) {
 799                 if (layer->drm_fmt->is_yuv) {
 800                         /* Swap U and V. */
 801                         swap[1] = 2;
 802                         swap[2] = 1;
 803                 } else {
 804                         /* Swap R and B. */
 805                         swap[0] = 2;
 806                         swap[2] = 0;
 807                 }
 808         }
 809
 810         if (layer->id == ZYNQMP_DISP_LAYER_VID)
 811                 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(0);
 812         else
 813                 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(0);
 814
 815         for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i += 3, reg += 12) {
 816                 zynqmp_disp_blend_write(blend, reg + 0, coeffs[i + swap[0]]);
 817                 zynqmp_disp_blend_write(blend, reg + 4, coeffs[i + swap[1]]);
 818                 zynqmp_disp_blend_write(blend, reg + 8, coeffs[i + swap[2]]);
 819         }
 820
 821         if (layer->id == ZYNQMP_DISP_LAYER_VID)
 822                 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(0);
 823         else
 824                 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(0);
 825
 826         for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++)
 827                 zynqmp_disp_blend_write(blend, reg + i * 4, offsets[i]);
 828 }
 829
 830 /**
 831  * zynqmp_disp_blend_layer_enable - Enable a layer
 832  * @blend: Blender object
 833  * @layer: The layer
 834  */
 835 static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp_blend *blend,
 836                                            struct zynqmp_disp_layer *layer)
 837 {
 838         const u16 *coeffs;
 839         const u32 *offsets;
 840         u32 val;
 841
 842         val = (layer->drm_fmt->is_yuv ?
 843                0 : ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB) |
 844               (layer->drm_fmt->hsub > 1 ?
 845                ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US : 0);
 846
 847         zynqmp_disp_blend_write(blend,
 848                                 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id),
 849                                 val);
 850
 851         if (layer->drm_fmt->is_yuv) {
 852                 coeffs = csc_sdtv_to_rgb_matrix;
 853                 offsets = csc_sdtv_to_rgb_offsets;
 854         } else {
 855                 coeffs = csc_identity_matrix;
 856                 offsets = csc_zero_offsets;
 857         }
 858
 859         zynqmp_disp_blend_layer_set_csc(blend, layer, coeffs, offsets);
 860 }
 861
 862 /**
 863  * zynqmp_disp_blend_layer_disable - Disable a layer
 864  * @blend: Blender object
 865  * @layer: The layer
 866  */
 867 static void zynqmp_disp_blend_layer_disable(struct zynqmp_disp_blend *blend,
 868                                             struct zynqmp_disp_layer *layer)
 869 {
 870         zynqmp_disp_blend_write(blend,
 871                                 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id),
 872                                 0);
 873
 874         zynqmp_disp_blend_layer_set_csc(blend, layer, csc_zero_matrix,
 875                                         csc_zero_offsets);
 876 }
 877
 878 /* -----------------------------------------------------------------------------
 879  * Audio Mixer
 880  */
 881
 882 static void zynqmp_disp_audio_write(struct zynqmp_disp_audio *audio,
 883                                   int reg, u32 val)
 884 {
 885         writel(val, audio->base + reg);
 886 }
 887
 888 /**
 889  * zynqmp_disp_audio_enable - Enable the audio mixer
 890  * @audio: Audio mixer
 891  *
 892  * Enable the audio mixer by de-asserting the soft reset. The audio state is set to
 893  * default values by the reset, set the default mixer volume explicitly.
 894  */
 895 static void zynqmp_disp_audio_enable(struct zynqmp_disp_audio *audio)
 896 {
 897         /* Clear the audio soft reset register as it's an non-reset flop. */
 898         zynqmp_disp_audio_write(audio, ZYNQMP_DISP_AUD_SOFT_RESET, 0);
 899         zynqmp_disp_audio_write(audio, ZYNQMP_DISP_AUD_MIXER_VOLUME,
 900                                 ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE);
 901 }
 902
 903 /**
 904  * zynqmp_disp_audio_disable - Disable the audio mixer
 905  * @audio: Audio mixer
 906  *
 907  * Disable the audio mixer by asserting its soft reset.
 908  */
 909 static void zynqmp_disp_audio_disable(struct zynqmp_disp_audio *audio)
 910 {
 911         zynqmp_disp_audio_write(audio, ZYNQMP_DISP_AUD_SOFT_RESET,
 912                                 ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST);
 913 }
 914
 915 static void zynqmp_disp_audio_init(struct device *dev,
 916                                    struct zynqmp_disp_audio *audio)
 917 {
 918         /* Try the live PL audio clock. */
 919         audio->clk = devm_clk_get(dev, "dp_live_audio_aclk");
 920         if (!IS_ERR(audio->clk)) {
 921                 audio->clk_from_ps = false;
 922                 return;
 923         }
 924
 925         /* If the live PL audio clock is not valid, fall back to PS clock. */
 926         audio->clk = devm_clk_get(dev, "dp_aud_clk");
 927         if (!IS_ERR(audio->clk)) {
 928                 audio->clk_from_ps = true;
 929                 return;
 930         }
 931
 932         dev_err(dev, "audio disabled due to missing clock\n");
 933 }
 934
 935 /* -----------------------------------------------------------------------------
 936  * ZynqMP Display external functions for zynqmp_dp
 937  */
 938
 939 /**
 940  * zynqmp_disp_handle_vblank - Handle the vblank event
 941  * @disp: Display controller
 942  *
 943  * This function handles the vblank interrupt, and sends an event to
 944  * CRTC object. This will be called by the DP vblank interrupt handler.
 945  */
 946 void zynqmp_disp_handle_vblank(struct zynqmp_disp *disp)
 947 {
 948         struct drm_crtc *crtc = &disp->crtc;
 949
 950         drm_crtc_handle_vblank(crtc);
 951 }
 952
 953 /**
 954  * zynqmp_disp_audio_enabled - If the audio is enabled
 955  * @disp: Display controller
 956  *
 957  * Return if the audio is enabled depending on the audio clock.
 958  *
 959  * Return: true if audio is enabled, or false.
 960  */
 961 bool zynqmp_disp_audio_enabled(struct zynqmp_disp *disp)
 962 {
 963         return !!disp->audio.clk;
 964 }
 965
 966 /**
 967  * zynqmp_disp_get_audio_clk_rate - Get the current audio clock rate
 968  * @disp: Display controller
 969  *
 970  * Return: the current audio clock rate.
 971  */
 972 unsigned int zynqmp_disp_get_audio_clk_rate(struct zynqmp_disp *disp)
 973 {
 974         if (zynqmp_disp_audio_enabled(disp))
 975                 return 0;
 976         return clk_get_rate(disp->audio.clk);
 977 }
 978
 979 /**
 980  * zynqmp_disp_get_crtc_mask - Return the CRTC bit mask
 981  * @disp: Display controller
 982  *
 983  * Return: the crtc mask of the zyqnmp_disp CRTC.
 984  */
 985 uint32_t zynqmp_disp_get_crtc_mask(struct zynqmp_disp *disp)
 986 {
 987         return drm_crtc_mask(&disp->crtc);
 988 }
 989
 990 /* -----------------------------------------------------------------------------
 991  * ZynqMP Display Layer & DRM Plane
 992  */
 993
 994 /**
 995  * zynqmp_disp_layer_find_format - Find format information for a DRM format
 996  * @layer: The layer
 997  * @drm_fmt: DRM format to search
 998  *
 999  * Search display subsystem format information corresponding to the given DRM
1000  * format @drm_fmt for the @layer, and return a pointer to the format
1001  * descriptor.
1002  *
1003  * Return: A pointer to the format descriptor if found, NULL otherwise
1004  */
1005 static const struct zynqmp_disp_format *
1006 zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer,
1007                               u32 drm_fmt)
1008 {
1009         unsigned int i;
1010
1011         for (i = 0; i < layer->info->num_formats; i++) {
1012                 if (layer->info->formats[i].drm_fmt == drm_fmt)
1013                         return &layer->info->formats[i];
1014         }
1015
1016         return NULL;
1017 }
1018
1019 /**
1020  * zynqmp_disp_layer_enable - Enable a layer
1021  * @layer: The layer
1022  *
1023  * Enable the @layer in the audio/video buffer manager and the blender. DMA
1024  * channels are started separately by zynqmp_disp_layer_update().
1025  */
1026 static void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer)
1027 {
1028         zynqmp_disp_avbuf_enable_video(&layer->disp->avbuf, layer->id,
1029                                        ZYNQMP_DISP_LAYER_NONLIVE);
1030         zynqmp_disp_blend_layer_enable(&layer->disp->blend, layer);
1031
1032         layer->mode = ZYNQMP_DISP_LAYER_NONLIVE;
1033 }
1034
1035 /**
1036  * zynqmp_disp_layer_disable - Disable the layer
1037  * @layer: The layer
1038  *
1039  * Disable the layer by stopping its DMA channels and disabling it in the
1040  * audio/video buffer manager and the blender.
1041  */
1042 static void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer)
1043 {
1044         unsigned int i;
1045
1046         for (i = 0; i < layer->drm_fmt->num_planes; i++)
1047                 dmaengine_terminate_sync(layer->dmas[i].chan);
1048
1049         zynqmp_disp_avbuf_disable_video(&layer->disp->avbuf, layer->id);
1050         zynqmp_disp_blend_layer_disable(&layer->disp->blend, layer);
1051 }
1052
1053 /**
1054  * zynqmp_disp_layer_set_format - Set the layer format
1055  * @layer: The layer
1056  * @state: The plane state
1057  *
1058  * Set the format for @layer based on @state->fb->format. The layer must be
1059  * disabled.
1060  */
1061 static void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,
1062                                          struct drm_plane_state *state)
1063 {
1064         const struct drm_format_info *info = state->fb->format;
1065         unsigned int i;
1066
1067         layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format);
1068         layer->drm_fmt = info;
1069
1070         zynqmp_disp_avbuf_set_format(&layer->disp->avbuf, layer->id,
1071                                      layer->disp_fmt);
1072
1073         /*
1074          * Set slave_id for each DMA channel to indicate they're part of a
1075          * video group.
1076          */
1077         for (i = 0; i < info->num_planes; i++) {
1078                 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1079                 struct dma_slave_config config = {
1080                         .direction = DMA_MEM_TO_DEV,
1081                         .slave_id = 1,
1082                 };
1083
1084                 dmaengine_slave_config(dma->chan, &config);
1085         }
1086 }
1087
1088 /**
1089  * zynqmp_disp_layer_update - Update the layer framebuffer
1090  * @layer: The layer
1091  * @state: The plane state
1092  *
1093  * Update the framebuffer for the layer by issuing a new DMA engine transaction
1094  * for the new framebuffer.
1095  *
1096  * Return: 0 on success, or the DMA descriptor failure error otherwise
1097  */
1098 static int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,
1099                                     struct drm_plane_state *state)
1100 {
1101         const struct drm_format_info *info = layer->drm_fmt;
1102         unsigned int i;
1103
1104         for (i = 0; i < layer->drm_fmt->num_planes; i++) {
1105                 unsigned int width = state->crtc_w / (i ? info->hsub : 1);
1106                 unsigned int height = state->crtc_h / (i ? info->vsub : 1);
1107                 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1108                 struct dma_async_tx_descriptor *desc;
1109                 dma_addr_t paddr;
1110
1111                 paddr = drm_fb_cma_get_gem_addr(state->fb, state, i);
1112
1113                 dma->xt.numf = height;
1114                 dma->sgl.size = width * info->cpp[i];
1115                 dma->sgl.icg = state->fb->pitches[i] - dma->sgl.size;
1116                 dma->xt.src_start = paddr;
1117                 dma->xt.frame_size = 1;
1118                 dma->xt.dir = DMA_MEM_TO_DEV;
1119                 dma->xt.src_sgl = true;
1120                 dma->xt.dst_sgl = false;
1121
1122                 desc = dmaengine_prep_interleaved_dma(dma->chan, &dma->xt,
1123                                                       DMA_CTRL_ACK |
1124                                                       DMA_PREP_REPEAT |
1125                                                       DMA_PREP_LOAD_EOT);
1126                 if (!desc) {
1127                         dev_err(layer->disp->dev,
1128                                 "failed to prepare DMA descriptor\n");
1129                         return -ENOMEM;
1130                 }
1131
1132                 dmaengine_submit(desc);
1133                 dma_async_issue_pending(dma->chan);
1134         }
1135
1136         return 0;
1137 }
1138
1139 static inline struct zynqmp_disp_layer *plane_to_layer(struct drm_plane *plane)
1140 {
1141         return container_of(plane, struct zynqmp_disp_layer, plane);
1142 }
1143
1144 static int
1145 zynqmp_disp_plane_atomic_check(struct drm_plane *plane,
1146                                struct drm_plane_state *state)
1147 {
1148         struct drm_crtc_state *crtc_state;
1149
1150         if (!state->crtc)
1151                 return 0;
1152
1153         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
1154         if (IS_ERR(crtc_state))
1155                 return PTR_ERR(crtc_state);
1156
1157         return drm_atomic_helper_check_plane_state(state, crtc_state,
1158                                                    DRM_PLANE_HELPER_NO_SCALING,
1159                                                    DRM_PLANE_HELPER_NO_SCALING,
1160                                                    false, false);
1161 }
1162
1163 static void
1164 zynqmp_disp_plane_atomic_disable(struct drm_plane *plane,
1165                                  struct drm_plane_state *old_state)
1166 {
1167         struct zynqmp_disp_layer *layer = plane_to_layer(plane);
1168
1169         if (!old_state->fb)
1170                 return;
1171
1172         zynqmp_disp_layer_disable(layer);
1173 }
1174
1175 static void
1176 zynqmp_disp_plane_atomic_update(struct drm_plane *plane,
1177                                 struct drm_plane_state *old_state)
1178 {
1179         struct zynqmp_disp_layer *layer = plane_to_layer(plane);
1180         bool format_changed = false;
1181
1182         if (!old_state->fb ||
1183             old_state->fb->format->format != plane->state->fb->format->format)
1184                 format_changed = true;
1185
1186         /*
1187          * If the format has changed (including going from a previously
1188          * disabled state to any format), reconfigure the format. Disable the
1189          * plane first if needed.
1190          */
1191         if (format_changed) {
1192                 if (old_state->fb)
1193                         zynqmp_disp_layer_disable(layer);
1194
1195                 zynqmp_disp_layer_set_format(layer, plane->state);
1196         }
1197
1198         zynqmp_disp_layer_update(layer, plane->state);
1199
1200         /* Enable or re-enable the plane is the format has changed. */
1201         if (format_changed)
1202                 zynqmp_disp_layer_enable(layer);
1203 }
1204
1205 static const struct drm_plane_helper_funcs zynqmp_disp_plane_helper_funcs = {
1206         .atomic_check           = zynqmp_disp_plane_atomic_check,
1207         .atomic_update          = zynqmp_disp_plane_atomic_update,
1208         .atomic_disable         = zynqmp_disp_plane_atomic_disable,
1209 };
1210
1211 static const struct drm_plane_funcs zynqmp_disp_plane_funcs = {
1212         .update_plane           = drm_atomic_helper_update_plane,
1213         .disable_plane          = drm_atomic_helper_disable_plane,
1214         .destroy                = drm_plane_cleanup,
1215         .reset                  = drm_atomic_helper_plane_reset,
1216         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1217         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
1218 };
1219
1220 static int zynqmp_disp_create_planes(struct zynqmp_disp *disp)
1221 {
1222         unsigned int i, j;
1223         int ret;
1224
1225         for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) {
1226                 struct zynqmp_disp_layer *layer = &disp->layers[i];
1227                 enum drm_plane_type type;
1228                 u32 *drm_formats;
1229
1230                 drm_formats = drmm_kcalloc(disp->drm, sizeof(*drm_formats),
1231                                            layer->info->num_formats,
1232                                            GFP_KERNEL);
1233                 if (!drm_formats)
1234                         return -ENOMEM;
1235
1236                 for (j = 0; j < layer->info->num_formats; ++j)
1237                         drm_formats[j] = layer->info->formats[j].drm_fmt;
1238
1239                 /* Graphics layer is primary, and video layer is overlay. */
1240                 type = i == ZYNQMP_DISP_LAYER_GFX
1241                      ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
1242                 ret = drm_universal_plane_init(disp->drm, &layer->plane, 0,
1243                                                &zynqmp_disp_plane_funcs,
1244                                                drm_formats,
1245                                                layer->info->num_formats,
1246                                                NULL, type, NULL);
1247                 if (ret)
1248                         return ret;
1249
1250                 drm_plane_helper_add(&layer->plane,
1251                                      &zynqmp_disp_plane_helper_funcs);
1252         }
1253
1254         return 0;
1255 }
1256
1257 /**
1258  * zynqmp_disp_layer_release_dma - Release DMA channels for a layer
1259  * @disp: Display controller
1260  * @layer: The layer
1261  *
1262  * Release the DMA channels associated with @layer.
1263  */
1264 static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp,
1265                                           struct zynqmp_disp_layer *layer)
1266 {
1267         unsigned int i;
1268
1269         if (!layer->info)
1270                 return;
1271
1272         for (i = 0; i < layer->info->num_channels; i++) {
1273                 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1274
1275                 if (!dma->chan)
1276                         continue;
1277
1278                 /* Make sure the channel is terminated before release. */
1279                 dmaengine_terminate_sync(dma->chan);
1280                 dma_release_channel(dma->chan);
1281         }
1282 }
1283
1284 /**
1285  * zynqmp_disp_destroy_layers - Destroy all layers
1286  * @disp: Display controller
1287  */
1288 static void zynqmp_disp_destroy_layers(struct zynqmp_disp *disp)
1289 {
1290         unsigned int i;
1291
1292         for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++)
1293                 zynqmp_disp_layer_release_dma(disp, &disp->layers[i]);
1294 }
1295
1296 /**
1297  * zynqmp_disp_layer_request_dma - Request DMA channels for a layer
1298  * @disp: Display controller
1299  * @layer: The layer
1300  *
1301  * Request all DMA engine channels needed by @layer.
1302  *
1303  * Return: 0 on success, or the DMA channel request error otherwise
1304  */
1305 static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp,
1306                                          struct zynqmp_disp_layer *layer)
1307 {
1308         static const char * const dma_names[] = { "vid", "gfx" };
1309         unsigned int i;
1310         int ret;
1311
1312         for (i = 0; i < layer->info->num_channels; i++) {
1313                 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
1314                 char dma_channel_name[16];
1315
1316                 snprintf(dma_channel_name, sizeof(dma_channel_name),
1317                          "%s%u", dma_names[layer->id], i);
1318                 dma->chan = dma_request_chan(disp->dev, dma_channel_name);
1319                 if (IS_ERR(dma->chan)) {
1320                         dev_err(disp->dev, "failed to request dma channel\n");
1321                         ret = PTR_ERR(dma->chan);
1322                         dma->chan = NULL;
1323                         return ret;
1324                 }
1325         }
1326
1327         return 0;
1328 }
1329
1330 /**
1331  * zynqmp_disp_create_layers - Create and initialize all layers
1332  * @disp: Display controller
1333  *
1334  * Return: 0 on success, or the DMA channel request error otherwise
1335  */
1336 static int zynqmp_disp_create_layers(struct zynqmp_disp *disp)
1337 {
1338         static const struct zynqmp_disp_layer_info layer_info[] = {
1339                 [ZYNQMP_DISP_LAYER_VID] = {
1340                         .formats = avbuf_vid_fmts,
1341                         .num_formats = ARRAY_SIZE(avbuf_vid_fmts),
1342                         .num_channels = 3,
1343                 },
1344                 [ZYNQMP_DISP_LAYER_GFX] = {
1345                         .formats = avbuf_gfx_fmts,
1346                         .num_formats = ARRAY_SIZE(avbuf_gfx_fmts),
1347                         .num_channels = 1,
1348                 },
1349         };
1350
1351         unsigned int i;
1352         int ret;
1353
1354         for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) {
1355                 struct zynqmp_disp_layer *layer = &disp->layers[i];
1356
1357                 layer->id = i;
1358                 layer->disp = disp;
1359                 layer->info = &layer_info[i];
1360
1361                 ret = zynqmp_disp_layer_request_dma(disp, layer);
1362                 if (ret)
1363                         goto err;
1364         }
1365
1366         return 0;
1367
1368 err:
1369         zynqmp_disp_destroy_layers(disp);
1370         return ret;
1371 }
1372
1373 /* -----------------------------------------------------------------------------
1374  * ZynqMP Display & DRM CRTC
1375  */
1376
1377 /**
1378  * zynqmp_disp_enable - Enable the display controller
1379  * @disp: Display controller
1380  */
1381 static void zynqmp_disp_enable(struct zynqmp_disp *disp)
1382 {
1383         zynqmp_disp_avbuf_enable(&disp->avbuf);
1384         /* Choose clock source based on the DT clock handle. */
1385         zynqmp_disp_avbuf_set_clocks_sources(&disp->avbuf, disp->pclk_from_ps,
1386                                              disp->audio.clk_from_ps, true);
1387         zynqmp_disp_avbuf_enable_channels(&disp->avbuf);
1388         zynqmp_disp_avbuf_enable_audio(&disp->avbuf);
1389
1390         zynqmp_disp_audio_enable(&disp->audio);
1391 }
1392
1393 /**
1394  * zynqmp_disp_disable - Disable the display controller
1395  * @disp: Display controller
1396  */
1397 static void zynqmp_disp_disable(struct zynqmp_disp *disp)
1398 {
1399         struct drm_crtc *crtc = &disp->crtc;
1400
1401         zynqmp_disp_audio_disable(&disp->audio);
1402
1403         zynqmp_disp_avbuf_disable_audio(&disp->avbuf);
1404         zynqmp_disp_avbuf_disable_channels(&disp->avbuf);
1405         zynqmp_disp_avbuf_disable(&disp->avbuf);
1406
1407         /* Mark the flip is done as crtc is disabled anyway */
1408         if (crtc->state->event) {
1409                 complete_all(crtc->state->event->base.completion);
1410                 crtc->state->event = NULL;
1411         }
1412 }
1413
1414 static inline struct zynqmp_disp *crtc_to_disp(struct drm_crtc *crtc)
1415 {
1416         return container_of(crtc, struct zynqmp_disp, crtc);
1417 }
1418
1419 static int zynqmp_disp_crtc_setup_clock(struct drm_crtc *crtc,
1420                                         struct drm_display_mode *adjusted_mode)
1421 {
1422         struct zynqmp_disp *disp = crtc_to_disp(crtc);
1423         unsigned long mode_clock = adjusted_mode->clock * 1000;
1424         unsigned long rate;
1425         long diff;
1426         int ret;
1427
1428         ret = clk_set_rate(disp->pclk, mode_clock);
1429         if (ret) {
1430                 dev_err(disp->dev, "failed to set a pixel clock\n");
1431                 return ret;
1432         }
1433
1434         rate = clk_get_rate(disp->pclk);
1435         diff = rate - mode_clock;
1436         if (abs(diff) > mode_clock / 20)
1437                 dev_info(disp->dev,
1438                          "requested pixel rate: %lu actual rate: %lu\n",
1439                          mode_clock, rate);
1440         else
1441                 dev_dbg(disp->dev,
1442                         "requested pixel rate: %lu actual rate: %lu\n",
1443                         mode_clock, rate);
1444
1445         return 0;
1446 }
1447
1448 static void
1449 zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc,
1450                                struct drm_atomic_state *state)
1451 {
1452         struct zynqmp_disp *disp = crtc_to_disp(crtc);
1453         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1454         int ret, vrefresh;
1455
1456         zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode);
1457
1458         pm_runtime_get_sync(disp->dev);
1459         ret = clk_prepare_enable(disp->pclk);
1460         if (ret) {
1461                 dev_err(disp->dev, "failed to enable a pixel clock\n");
1462                 pm_runtime_put_sync(disp->dev);
1463                 return;
1464         }
1465
1466         zynqmp_disp_blend_set_output_format(&disp->blend,
1467                                             ZYNQMP_DPSUB_FORMAT_RGB);
1468         zynqmp_disp_blend_set_bg_color(&disp->blend, 0, 0, 0);
1469         zynqmp_disp_blend_set_global_alpha(&disp->blend, false, 0);
1470
1471         zynqmp_disp_enable(disp);
1472
1473         /* Delay of 3 vblank intervals for timing gen to be stable */
1474         vrefresh = (adjusted_mode->clock * 1000) /
1475                    (adjusted_mode->vtotal * adjusted_mode->htotal);
1476         msleep(3 * 1000 / vrefresh);
1477 }
1478
1479 static void
1480 zynqmp_disp_crtc_atomic_disable(struct drm_crtc *crtc,
1481                                 struct drm_atomic_state *state)
1482 {
1483         struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1484                                                                               crtc);
1485         struct zynqmp_disp *disp = crtc_to_disp(crtc);
1486         struct drm_plane_state *old_plane_state;
1487
1488         /*
1489          * Disable the plane if active. The old plane state can be NULL in the
1490          * .shutdown() path if the plane is already disabled, skip
1491          * zynqmp_disp_plane_atomic_disable() in that case.
1492          */
1493         old_plane_state = drm_atomic_get_old_plane_state(old_crtc_state->state,
1494                                                          crtc->primary);
1495         if (old_plane_state)
1496                 zynqmp_disp_plane_atomic_disable(crtc->primary, old_plane_state);
1497
1498         zynqmp_disp_disable(disp);
1499
1500         drm_crtc_vblank_off(&disp->crtc);
1501
1502         clk_disable_unprepare(disp->pclk);
1503         pm_runtime_put_sync(disp->dev);
1504 }
1505
1506 static int zynqmp_disp_crtc_atomic_check(struct drm_crtc *crtc,
1507                                          struct drm_atomic_state *state)
1508 {
1509         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1510                                                                           crtc);
1511         return drm_atomic_add_affected_planes(crtc_state->state, crtc);
1512 }
1513
1514 static void
1515 zynqmp_disp_crtc_atomic_begin(struct drm_crtc *crtc,
1516                               struct drm_atomic_state *state)
1517 {
1518         drm_crtc_vblank_on(crtc);
1519 }
1520
1521 static void
1522 zynqmp_disp_crtc_atomic_flush(struct drm_crtc *crtc,
1523                               struct drm_atomic_state *state)
1524 {
1525         if (crtc->state->event) {
1526                 struct drm_pending_vblank_event *event;
1527
1528                 /* Consume the flip_done event from atomic helper. */
1529                 event = crtc->state->event;
1530                 crtc->state->event = NULL;
1531
1532                 event->pipe = drm_crtc_index(crtc);
1533
1534                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1535
1536                 spin_lock_irq(&crtc->dev->event_lock);
1537                 drm_crtc_arm_vblank_event(crtc, event);
1538                 spin_unlock_irq(&crtc->dev->event_lock);
1539         }
1540 }
1541
1542 static const struct drm_crtc_helper_funcs zynqmp_disp_crtc_helper_funcs = {
1543         .atomic_enable  = zynqmp_disp_crtc_atomic_enable,
1544         .atomic_disable = zynqmp_disp_crtc_atomic_disable,
1545         .atomic_check   = zynqmp_disp_crtc_atomic_check,
1546         .atomic_begin   = zynqmp_disp_crtc_atomic_begin,
1547         .atomic_flush   = zynqmp_disp_crtc_atomic_flush,
1548 };
1549
1550 static int zynqmp_disp_crtc_enable_vblank(struct drm_crtc *crtc)
1551 {
1552         struct zynqmp_disp *disp = crtc_to_disp(crtc);
1553
1554         zynqmp_dp_enable_vblank(disp->dpsub->dp);
1555
1556         return 0;
1557 }
1558
1559 static void zynqmp_disp_crtc_disable_vblank(struct drm_crtc *crtc)
1560 {
1561         struct zynqmp_disp *disp = crtc_to_disp(crtc);
1562
1563         zynqmp_dp_disable_vblank(disp->dpsub->dp);
1564 }
1565
1566 static const struct drm_crtc_funcs zynqmp_disp_crtc_funcs = {
1567         .destroy                = drm_crtc_cleanup,
1568         .set_config             = drm_atomic_helper_set_config,
1569         .page_flip              = drm_atomic_helper_page_flip,
1570         .reset                  = drm_atomic_helper_crtc_reset,
1571         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1572         .atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
1573         .enable_vblank          = zynqmp_disp_crtc_enable_vblank,
1574         .disable_vblank         = zynqmp_disp_crtc_disable_vblank,
1575 };
1576
1577 static int zynqmp_disp_create_crtc(struct zynqmp_disp *disp)
1578 {
1579         struct drm_plane *plane = &disp->layers[ZYNQMP_DISP_LAYER_GFX].plane;
1580         int ret;
1581
1582         ret = drm_crtc_init_with_planes(disp->drm, &disp->crtc, plane,
1583                                         NULL, &zynqmp_disp_crtc_funcs, NULL);
1584         if (ret < 0)
1585                 return ret;
1586
1587         drm_crtc_helper_add(&disp->crtc, &zynqmp_disp_crtc_helper_funcs);
1588
1589         /* Start with vertical blanking interrupt reporting disabled. */
1590         drm_crtc_vblank_off(&disp->crtc);
1591
1592         return 0;
1593 }
1594
1595 static void zynqmp_disp_map_crtc_to_plane(struct zynqmp_disp *disp)
1596 {
1597         u32 possible_crtcs = drm_crtc_mask(&disp->crtc);
1598         unsigned int i;
1599
1600         for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++)
1601                 disp->layers[i].plane.possible_crtcs = possible_crtcs;
1602 }
1603
1604 /* -----------------------------------------------------------------------------
1605  * Initialization & Cleanup
1606  */
1607
1608 int zynqmp_disp_drm_init(struct zynqmp_dpsub *dpsub)
1609 {
1610         struct zynqmp_disp *disp = dpsub->disp;
1611         int ret;
1612
1613         ret = zynqmp_disp_create_planes(disp);
1614         if (ret)
1615                 return ret;
1616
1617         ret = zynqmp_disp_create_crtc(disp);
1618         if (ret < 0)
1619                 return ret;
1620
1621         zynqmp_disp_map_crtc_to_plane(disp);
1622
1623         return 0;
1624 }
1625
1626 int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub, struct drm_device *drm)
1627 {
1628         struct platform_device *pdev = to_platform_device(dpsub->dev);
1629         struct zynqmp_disp *disp;
1630         struct zynqmp_disp_layer *layer;
1631         struct resource *res;
1632         int ret;
1633
1634         disp = drmm_kzalloc(drm, sizeof(*disp), GFP_KERNEL);
1635         if (!disp)
1636                 return -ENOMEM;
1637
1638         disp->dev = &pdev->dev;
1639         disp->dpsub = dpsub;
1640         disp->drm = drm;
1641
1642         dpsub->disp = disp;
1643
1644         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "blend");
1645         disp->blend.base = devm_ioremap_resource(disp->dev, res);
1646         if (IS_ERR(disp->blend.base))
1647                 return PTR_ERR(disp->blend.base);
1648
1649         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "av_buf");
1650         disp->avbuf.base = devm_ioremap_resource(disp->dev, res);
1651         if (IS_ERR(disp->avbuf.base))
1652                 return PTR_ERR(disp->avbuf.base);
1653
1654         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aud");
1655         disp->audio.base = devm_ioremap_resource(disp->dev, res);
1656         if (IS_ERR(disp->audio.base))
1657                 return PTR_ERR(disp->audio.base);
1658
1659         /* Try the live PL video clock */
1660         disp->pclk = devm_clk_get(disp->dev, "dp_live_video_in_clk");
1661         if (!IS_ERR(disp->pclk))
1662                 disp->pclk_from_ps = false;
1663         else if (PTR_ERR(disp->pclk) == -EPROBE_DEFER)
1664                 return PTR_ERR(disp->pclk);
1665
1666         /* If the live PL video clock is not valid, fall back to PS clock */
1667         if (IS_ERR_OR_NULL(disp->pclk)) {
1668                 disp->pclk = devm_clk_get(disp->dev, "dp_vtc_pixel_clk_in");
1669                 if (IS_ERR(disp->pclk)) {
1670                         dev_err(disp->dev, "failed to init any video clock\n");
1671                         return PTR_ERR(disp->pclk);
1672                 }
1673                 disp->pclk_from_ps = true;
1674         }
1675
1676         zynqmp_disp_audio_init(disp->dev, &disp->audio);
1677
1678         ret = zynqmp_disp_create_layers(disp);
1679         if (ret)
1680                 return ret;
1681
1682         layer = &disp->layers[ZYNQMP_DISP_LAYER_VID];
1683         dpsub->dma_align = 1 << layer->dmas[0].chan->device->copy_align;
1684
1685         return 0;
1686 }
1687
1688 void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub)
1689 {
1690         struct zynqmp_disp *disp = dpsub->disp;
1691
1692         zynqmp_disp_destroy_layers(disp);
1693 }