drivers/gpu/drm/xe/xe_hw_engine_types.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2022 Intel Corporation
   4  */
   5
   6 #ifndef _XE_HW_ENGINE_TYPES_H_
   7 #define _XE_HW_ENGINE_TYPES_H_
   8
   9 #include "xe_force_wake_types.h"
  10 #include "xe_lrc_types.h"
  11 #include "xe_reg_sr_types.h"
  12
  13 /* See "Engine ID Definition" struct in the Icelake PRM */
  14 enum xe_engine_class {
  15         XE_ENGINE_CLASS_RENDER = 0,
  16         XE_ENGINE_CLASS_VIDEO_DECODE = 1,
  17         XE_ENGINE_CLASS_VIDEO_ENHANCE = 2,
  18         XE_ENGINE_CLASS_COPY = 3,
  19         XE_ENGINE_CLASS_OTHER = 4,
  20         XE_ENGINE_CLASS_COMPUTE = 5,
  21         XE_ENGINE_CLASS_MAX = 6,
  22 };
  23
  24 enum xe_hw_engine_id {
  25         XE_HW_ENGINE_RCS0,
  26 #define XE_HW_ENGINE_RCS_MASK   GENMASK_ULL(XE_HW_ENGINE_RCS0, XE_HW_ENGINE_RCS0)
  27         XE_HW_ENGINE_BCS0,
  28         XE_HW_ENGINE_BCS1,
  29         XE_HW_ENGINE_BCS2,
  30         XE_HW_ENGINE_BCS3,
  31         XE_HW_ENGINE_BCS4,
  32         XE_HW_ENGINE_BCS5,
  33         XE_HW_ENGINE_BCS6,
  34         XE_HW_ENGINE_BCS7,
  35         XE_HW_ENGINE_BCS8,
  36 #define XE_HW_ENGINE_BCS_MASK   GENMASK_ULL(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS0)
  37         XE_HW_ENGINE_VCS0,
  38         XE_HW_ENGINE_VCS1,
  39         XE_HW_ENGINE_VCS2,
  40         XE_HW_ENGINE_VCS3,
  41         XE_HW_ENGINE_VCS4,
  42         XE_HW_ENGINE_VCS5,
  43         XE_HW_ENGINE_VCS6,
  44         XE_HW_ENGINE_VCS7,
  45 #define XE_HW_ENGINE_VCS_MASK   GENMASK_ULL(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0)
  46         XE_HW_ENGINE_VECS0,
  47         XE_HW_ENGINE_VECS1,
  48         XE_HW_ENGINE_VECS2,
  49         XE_HW_ENGINE_VECS3,
  50 #define XE_HW_ENGINE_VECS_MASK  GENMASK_ULL(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0)
  51         XE_HW_ENGINE_CCS0,
  52         XE_HW_ENGINE_CCS1,
  53         XE_HW_ENGINE_CCS2,
  54         XE_HW_ENGINE_CCS3,
  55 #define XE_HW_ENGINE_CCS_MASK   GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
  56         XE_HW_ENGINE_GSCCS0,
  57 #define XE_HW_ENGINE_GSCCS_MASK GENMASK_ULL(XE_HW_ENGINE_GSCCS0, XE_HW_ENGINE_GSCCS0)
  58         XE_NUM_HW_ENGINES,
  59 };
  60
  61 /* FIXME: s/XE_HW_ENGINE_MAX_INSTANCE/XE_HW_ENGINE_MAX_COUNT */
  62 #define XE_HW_ENGINE_MAX_INSTANCE       9
  63
  64 struct xe_bo;
  65 struct xe_execlist_port;
  66 struct xe_gt;
  67
  68 /**
  69  * struct xe_hw_engine_class_intf - per hw engine class struct interface
  70  *
  71  * Contains all the hw engine properties per engine class.
  72  *
  73  * @sched_props: scheduling properties
  74  * @defaults: default scheduling properties
  75  */
  76 struct xe_hw_engine_class_intf {
  77         /**
  78          * @sched_props: scheduling properties
  79          * @defaults: default scheduling properties
  80          */
  81         struct {
  82                 /** @sched_props.set_job_timeout: Set job timeout in ms for engine */
  83                 u32 job_timeout_ms;
  84                 /** @sched_props.job_timeout_min: Min job timeout in ms for engine */
  85                 u32 job_timeout_min;
  86                 /** @sched_props.job_timeout_max: Max job timeout in ms for engine */
  87                 u32 job_timeout_max;
  88                 /** @sched_props.timeslice_us: timeslice period in micro-seconds */
  89                 u32 timeslice_us;
  90                 /** @sched_props.timeslice_min: min timeslice period in micro-seconds */
  91                 u32 timeslice_min;
  92                 /** @sched_props.timeslice_max: max timeslice period in micro-seconds */
  93                 u32 timeslice_max;
  94                 /** @sched_props.preempt_timeout_us: preemption timeout in micro-seconds */
  95                 u32 preempt_timeout_us;
  96                 /** @sched_props.preempt_timeout_min: min preemption timeout in micro-seconds */
  97                 u32 preempt_timeout_min;
  98                 /** @sched_props.preempt_timeout_max: max preemption timeout in micro-seconds */
  99                 u32 preempt_timeout_max;
 100         } sched_props, defaults;
 101 };
 102
 103 /**
 104  * struct xe_hw_engine - Hardware engine
 105  *
 106  * Contains all the hardware engine state for physical instances.
 107  */
 108 struct xe_hw_engine {
 109         /** @gt: graphics tile this hw engine belongs to */
 110         struct xe_gt *gt;
 111         /** @name: name of this hw engine */
 112         const char *name;
 113         /** @class: class of this hw engine */
 114         enum xe_engine_class class;
 115         /** @instance: physical instance of this hw engine */
 116         u16 instance;
 117         /** @logical_instance: logical instance of this hw engine */
 118         u16 logical_instance;
 119         /** @irq_offset: IRQ offset of this hw engine */
 120         u16 irq_offset;
 121         /** @mmio_base: MMIO base address of this hw engine*/
 122         u32 mmio_base;
 123         /**
 124          * @reg_sr: table with registers to be restored on GT init/resume/reset
 125          */
 126         struct xe_reg_sr reg_sr;
 127         /**
 128          * @reg_whitelist: table with registers to be whitelisted
 129          */
 130         struct xe_reg_sr reg_whitelist;
 131         /**
 132          * @reg_lrc: LRC workaround registers
 133          */
 134         struct xe_reg_sr reg_lrc;
 135         /** @domain: force wake domain of this hw engine */
 136         enum xe_force_wake_domains domain;
 137         /** @hwsp: hardware status page buffer object */
 138         struct xe_bo *hwsp;
 139         /** @exl_port: execlists port */
 140         struct xe_execlist_port *exl_port;
 141         /** @fence_irq: fence IRQ to run when a hw engine IRQ is received */
 142         struct xe_hw_fence_irq *fence_irq;
 143         /** @irq_handler: IRQ handler to run when hw engine IRQ is received */
 144         void (*irq_handler)(struct xe_hw_engine *hwe, u16 intr_vec);
 145         /** @engine_id: id  for this hw engine */
 146         enum xe_hw_engine_id engine_id;
 147         /** @eclass: pointer to per hw engine class interface */
 148         struct xe_hw_engine_class_intf *eclass;
 149         /** @oa_unit: oa unit for this hw engine */
 150         struct xe_oa_unit *oa_unit;
 151         /** @hw_engine_group: the group of hw engines this one belongs to */
 152         struct xe_hw_engine_group *hw_engine_group;
 153 };
 154
 155 /**
 156  * struct xe_hw_engine_snapshot - Hardware engine snapshot
 157  *
 158  * Contains the snapshot of useful hardware engine info and registers.
 159  */
 160 struct xe_hw_engine_snapshot {
 161         /** @name: name of the hw engine */
 162         char *name;
 163         /** @hwe: hw engine */
 164         struct xe_hw_engine *hwe;
 165         /** @logical_instance: logical instance of this hw engine */
 166         u16 logical_instance;
 167         /** @forcewake: Force Wake information snapshot */
 168         struct {
 169                 /** @forcewake.domain: force wake domain of this hw engine */
 170                 enum xe_force_wake_domains domain;
 171                 /** @forcewake.ref: Forcewake ref for the above domain */
 172                 int ref;
 173         } forcewake;
 174         /** @mmio_base: MMIO base address of this hw engine*/
 175         u32 mmio_base;
 176         /** @reg: Useful MMIO register snapshot */
 177         struct {
 178                 /** @reg.ring_execlist_status: RING_EXECLIST_STATUS */
 179                 u64 ring_execlist_status;
 180                 /** @reg.ring_execlist_sq_contents: RING_EXECLIST_SQ_CONTENTS */
 181                 u64 ring_execlist_sq_contents;
 182                 /** @reg.ring_acthd: RING_ACTHD */
 183                 u64 ring_acthd;
 184                 /** @reg.ring_bbaddr: RING_BBADDR */
 185                 u64 ring_bbaddr;
 186                 /** @reg.ring_dma_fadd: RING_DMA_FADD */
 187                 u64 ring_dma_fadd;
 188                 /** @reg.ring_hwstam: RING_HWSTAM */
 189                 u32 ring_hwstam;
 190                 /** @reg.ring_hws_pga: RING_HWS_PGA */
 191                 u32 ring_hws_pga;
 192                 /** @reg.ring_start: RING_START */
 193                 u64 ring_start;
 194                 /** @reg.ring_head: RING_HEAD */
 195                 u32 ring_head;
 196                 /** @reg.ring_tail: RING_TAIL */
 197                 u32 ring_tail;
 198                 /** @reg.ring_ctl: RING_CTL */
 199                 u32 ring_ctl;
 200                 /** @reg.ring_mi_mode: RING_MI_MODE */
 201                 u32 ring_mi_mode;
 202                 /** @reg.ring_mode: RING_MODE */
 203                 u32 ring_mode;
 204                 /** @reg.ring_imr: RING_IMR */
 205                 u32 ring_imr;
 206                 /** @reg.ring_esr: RING_ESR */
 207                 u32 ring_esr;
 208                 /** @reg.ring_emr: RING_EMR */
 209                 u32 ring_emr;
 210                 /** @reg.ring_eir: RING_EIR */
 211                 u32 ring_eir;
 212                 /** @reg.indirect_ring_state: INDIRECT_RING_STATE */
 213                 u32 indirect_ring_state;
 214                 /** @reg.ipehr: IPEHR */
 215                 u32 ipehr;
 216                 /** @reg.rcu_mode: RCU_MODE */
 217                 u32 rcu_mode;
 218                 struct {
 219                         /** @reg.instdone.ring: RING_INSTDONE */
 220                         u32 ring;
 221                         /** @reg.instdone.slice_common: SC_INSTDONE */
 222                         u32 *slice_common;
 223                         /** @reg.instdone.slice_common_extra: SC_INSTDONE_EXTRA */
 224                         u32 *slice_common_extra;
 225                         /** @reg.instdone.slice_common_extra2: SC_INSTDONE_EXTRA2 */
 226                         u32 *slice_common_extra2;
 227                         /** @reg.instdone.sampler: SAMPLER_INSTDONE */
 228                         u32 *sampler;
 229                         /** @reg.instdone.row: ROW_INSTDONE */
 230                         u32 *row;
 231                         /** @reg.instdone.geom_svg: INSTDONE_GEOM_SVGUNIT */
 232                         u32 *geom_svg;
 233                 } instdone;
 234         } reg;
 235 };
 236
 237 #endif