1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2022 Intel Corporation
6 #ifndef _XE_HW_ENGINE_TYPES_H_
7 #define _XE_HW_ENGINE_TYPES_H_
9 #include "xe_force_wake_types.h"
10 #include "xe_lrc_types.h"
11 #include "xe_reg_sr_types.h"
13 /* See "Engine ID Definition" struct in the Icelake PRM */
14 enum xe_engine_class {
15 XE_ENGINE_CLASS_RENDER = 0,
16 XE_ENGINE_CLASS_VIDEO_DECODE = 1,
17 XE_ENGINE_CLASS_VIDEO_ENHANCE = 2,
18 XE_ENGINE_CLASS_COPY = 3,
19 XE_ENGINE_CLASS_OTHER = 4,
20 XE_ENGINE_CLASS_COMPUTE = 5,
21 XE_ENGINE_CLASS_MAX = 6,
24 enum xe_hw_engine_id {
26 #define XE_HW_ENGINE_RCS_MASK GENMASK_ULL(XE_HW_ENGINE_RCS0, XE_HW_ENGINE_RCS0)
36 #define XE_HW_ENGINE_BCS_MASK GENMASK_ULL(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS0)
45 #define XE_HW_ENGINE_VCS_MASK GENMASK_ULL(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0)
50 #define XE_HW_ENGINE_VECS_MASK GENMASK_ULL(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0)
55 #define XE_HW_ENGINE_CCS_MASK GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
57 #define XE_HW_ENGINE_GSCCS_MASK GENMASK_ULL(XE_HW_ENGINE_GSCCS0, XE_HW_ENGINE_GSCCS0)
61 /* FIXME: s/XE_HW_ENGINE_MAX_INSTANCE/XE_HW_ENGINE_MAX_COUNT */
62 #define XE_HW_ENGINE_MAX_INSTANCE 9
65 struct xe_execlist_port;
69 * struct xe_hw_engine_class_intf - per hw engine class struct interface
71 * Contains all the hw engine properties per engine class.
73 * @sched_props: scheduling properties
74 * @defaults: default scheduling properties
76 struct xe_hw_engine_class_intf {
78 * @sched_props: scheduling properties
79 * @defaults: default scheduling properties
82 /** @sched_props.set_job_timeout: Set job timeout in ms for engine */
84 /** @sched_props.job_timeout_min: Min job timeout in ms for engine */
86 /** @sched_props.job_timeout_max: Max job timeout in ms for engine */
88 /** @sched_props.timeslice_us: timeslice period in micro-seconds */
90 /** @sched_props.timeslice_min: min timeslice period in micro-seconds */
92 /** @sched_props.timeslice_max: max timeslice period in micro-seconds */
94 /** @sched_props.preempt_timeout_us: preemption timeout in micro-seconds */
95 u32 preempt_timeout_us;
96 /** @sched_props.preempt_timeout_min: min preemption timeout in micro-seconds */
97 u32 preempt_timeout_min;
98 /** @sched_props.preempt_timeout_max: max preemption timeout in micro-seconds */
99 u32 preempt_timeout_max;
100 } sched_props, defaults;
104 * struct xe_hw_engine - Hardware engine
106 * Contains all the hardware engine state for physical instances.
108 struct xe_hw_engine {
109 /** @gt: graphics tile this hw engine belongs to */
111 /** @name: name of this hw engine */
113 /** @class: class of this hw engine */
114 enum xe_engine_class class;
115 /** @instance: physical instance of this hw engine */
117 /** @logical_instance: logical instance of this hw engine */
118 u16 logical_instance;
119 /** @irq_offset: IRQ offset of this hw engine */
121 /** @mmio_base: MMIO base address of this hw engine*/
124 * @reg_sr: table with registers to be restored on GT init/resume/reset
126 struct xe_reg_sr reg_sr;
128 * @reg_whitelist: table with registers to be whitelisted
130 struct xe_reg_sr reg_whitelist;
132 * @reg_lrc: LRC workaround registers
134 struct xe_reg_sr reg_lrc;
135 /** @domain: force wake domain of this hw engine */
136 enum xe_force_wake_domains domain;
137 /** @hwsp: hardware status page buffer object */
139 /** @kernel_lrc: Kernel LRC (should be replaced /w an xe_engine) */
140 struct xe_lrc kernel_lrc;
141 /** @exl_port: execlists port */
142 struct xe_execlist_port *exl_port;
143 /** @fence_irq: fence IRQ to run when a hw engine IRQ is received */
144 struct xe_hw_fence_irq *fence_irq;
145 /** @irq_handler: IRQ handler to run when hw engine IRQ is received */
146 void (*irq_handler)(struct xe_hw_engine *hwe, u16 intr_vec);
147 /** @engine_id: id for this hw engine */
148 enum xe_hw_engine_id engine_id;
149 /** @eclass: pointer to per hw engine class interface */
150 struct xe_hw_engine_class_intf *eclass;
154 * struct xe_hw_engine_snapshot - Hardware engine snapshot
156 * Contains the snapshot of useful hardware engine info and registers.
158 struct xe_hw_engine_snapshot {
159 /** @name: name of the hw engine */
161 /** @class: class of this hw engine */
162 enum xe_engine_class class;
163 /** @logical_instance: logical instance of this hw engine */
164 u16 logical_instance;
165 /** @forcewake: Force Wake information snapshot */
167 /** @forcewake.domain: force wake domain of this hw engine */
168 enum xe_force_wake_domains domain;
169 /** @forcewake.ref: Forcewake ref for the above domain */
172 /** @mmio_base: MMIO base address of this hw engine*/
174 /** @reg: Useful MMIO register snapshot */
176 /** @reg.ring_hwstam: RING_HWSTAM */
178 /** @reg.ring_hws_pga: RING_HWS_PGA */
180 /** @reg.ring_execlist_status_lo: RING_EXECLIST_STATUS_LO */
181 u32 ring_execlist_status_lo;
182 /** @reg.ring_execlist_status_hi: RING_EXECLIST_STATUS_HI */
183 u32 ring_execlist_status_hi;
184 /** @reg.ring_execlist_sq_contents_lo: RING_EXECLIST_SQ_CONTENTS */
185 u32 ring_execlist_sq_contents_lo;
186 /** @reg.ring_execlist_sq_contents_hi: RING_EXECLIST_SQ_CONTENTS + 4 */
187 u32 ring_execlist_sq_contents_hi;
188 /** @reg.ring_start: RING_START */
190 /** @reg.ring_head: RING_HEAD */
192 /** @reg.ring_tail: RING_TAIL */
194 /** @reg.ring_ctl: RING_CTL */
196 /** @reg.ring_mi_mode: RING_MI_MODE */
198 /** @reg.ring_mode: RING_MODE */
200 /** @reg.ring_imr: RING_IMR */
202 /** @reg.ring_esr: RING_ESR */
204 /** @reg.ring_emr: RING_EMR */
206 /** @reg.ring_eir: RING_EIR */
208 /** @reg.ring_acthd_udw: RING_ACTHD_UDW */
210 /** @reg.ring_acthd: RING_ACTHD */
212 /** @reg.ring_bbaddr_udw: RING_BBADDR_UDW */
214 /** @reg.ring_bbaddr: RING_BBADDR */
216 /** @reg.ring_dma_fadd_udw: RING_DMA_FADD_UDW */
217 u32 ring_dma_fadd_udw;
218 /** @reg.ring_dma_fadd: RING_DMA_FADD */
220 /** @reg.ipehr: IPEHR */
222 /** @reg.rcu_mode: RCU_MODE */