1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2022-2023 Intel Corporation
6 #ifndef _XE_DEVICE_TYPES_H_
7 #define _XE_DEVICE_TYPES_H_
11 #include <drm/drm_device.h>
12 #include <drm/drm_file.h>
13 #include <drm/ttm/ttm_device.h>
15 #include "xe_devcoredump_types.h"
16 #include "xe_heci_gsc.h"
17 #include "xe_gt_types.h"
18 #include "xe_lmtt_types.h"
19 #include "xe_memirq_types.h"
20 #include "xe_platform_types.h"
21 #include "xe_pt_types.h"
22 #include "xe_sriov_types.h"
23 #include "xe_step_types.h"
25 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
26 #include "soc/intel_pch.h"
27 #include "intel_display_core.h"
28 #include "intel_display_device.h"
34 #define XE_BO_INVALID_OFFSET LONG_MAX
36 #define GRAPHICS_VER(xe) ((xe)->info.graphics_verx100 / 100)
37 #define MEDIA_VER(xe) ((xe)->info.media_verx100 / 100)
38 #define GRAPHICS_VERx100(xe) ((xe)->info.graphics_verx100)
39 #define MEDIA_VERx100(xe) ((xe)->info.media_verx100)
40 #define IS_DGFX(xe) ((xe)->info.is_dgfx)
41 #define HAS_HECI_GSCFI(xe) ((xe)->info.has_heci_gscfi)
43 #define XE_VRAM_FLAGS_NEED64K BIT(0)
47 #define XE_MAX_TILES_PER_DEVICE (XE_GT1 + 1)
49 #define XE_MAX_ASID (BIT(20))
51 #define IS_PLATFORM_STEP(_xe, _platform, min_step, max_step) \
52 ((_xe)->info.platform == (_platform) && \
53 (_xe)->info.step.graphics >= (min_step) && \
54 (_xe)->info.step.graphics < (max_step))
55 #define IS_SUBPLATFORM_STEP(_xe, _platform, sub, min_step, max_step) \
56 ((_xe)->info.platform == (_platform) && \
57 (_xe)->info.subplatform == (sub) && \
58 (_xe)->info.step.graphics >= (min_step) && \
59 (_xe)->info.step.graphics < (max_step))
61 #define tile_to_xe(tile__) \
63 const struct xe_tile * : (const struct xe_device *)((tile__)->xe), \
64 struct xe_tile * : (tile__)->xe)
67 * struct xe_mem_region - memory region structure
68 * This is used to describe a memory region in xe
69 * device, such as HBM memory or CXL extension memory.
71 struct xe_mem_region {
72 /** @io_start: IO start address of this VRAM instance */
73 resource_size_t io_start;
75 * @io_size: IO size of this VRAM instance
77 * This represents how much of this VRAM we can access
78 * via the CPU through the VRAM BAR. This can be smaller
79 * than @usable_size, in which case only part of VRAM is CPU
80 * accessible (typically the first 256M). This
81 * configuration is known as small-bar.
83 resource_size_t io_size;
84 /** @dpa_base: This memory regions's DPA (device physical address) base */
85 resource_size_t dpa_base;
87 * @usable_size: usable size of VRAM
89 * Usable size of VRAM excluding reserved portions
92 resource_size_t usable_size;
94 * @actual_physical_size: Actual VRAM size
96 * Actual VRAM size including reserved portions
99 resource_size_t actual_physical_size;
100 /** @mapping: pointer to VRAM mappable space */
101 void __iomem *mapping;
105 * struct xe_tile - hardware tile structure
107 * From a driver perspective, a "tile" is effectively a complete GPU, containing
108 * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM.
110 * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI
111 * device and designate one "root" tile as being responsible for external PCI
112 * communication. PCI BAR0 exposes the GGTT and MMIO register space for each
113 * tile in a stacked layout, and PCI BAR2 exposes the local memory associated
114 * with each tile similarly. Device-wide interrupts can be enabled/disabled
115 * at the root tile, and the MSTR_TILE_INTR register will report which tiles
116 * have interrupts that need servicing.
119 /** @xe: Backpointer to tile's PCI device */
120 struct xe_device *xe;
122 /** @id: ID of the tile */
126 * @primary_gt: Primary GT
128 struct xe_gt *primary_gt;
131 * @media_gt: Media GT
133 * Only present on devices with media version >= 13.
135 struct xe_gt *media_gt;
138 * @mmio: MMIO info for a tile.
140 * Each tile has its own 16MB space in BAR0, laid out as:
142 * * 4MB-8MB: reserved
143 * * 8MB-16MB: global GTT
146 /** @size: size of tile's MMIO space */
149 /** @regs: pointer to tile's MMIO space (starting with registers) */
154 * @mmio_ext: MMIO-extension info for a tile.
156 * Each tile has its own additional 256MB (28-bit) MMIO-extension space.
159 /** @size: size of tile's additional MMIO-extension space */
162 /** @regs: pointer to tile's additional MMIO-extension space */
166 /** @mem: memory management info for tile */
169 * @vram: VRAM info for tile.
171 * Although VRAM is associated with a specific tile, it can
172 * still be accessed by all tiles' GTs.
174 struct xe_mem_region vram;
176 /** @vram_mgr: VRAM TTM manager */
177 struct xe_ttm_vram_mgr *vram_mgr;
179 /** @ggtt: Global graphics translation table */
180 struct xe_ggtt *ggtt;
183 * @kernel_bb_pool: Pool from which batchbuffers are allocated.
185 * Media GT shares a pool with its primary GT.
187 struct xe_sa_manager *kernel_bb_pool;
190 /** @sriov: tile level virtualization data */
193 /** @sriov.pf.lmtt: Local Memory Translation Table. */
197 /** @sriov.vf.memirq: Memory Based Interrupts. */
198 struct xe_memirq memirq;
202 /** @migrate: Migration helper for vram blits and clearing */
203 struct xe_migrate *migrate;
205 /** @sysfs: sysfs' kobj used by xe_tile_sysfs */
206 struct kobject *sysfs;
210 * struct xe_device - Top level struct of XE device
213 /** @drm: drm device */
214 struct drm_device drm;
216 /** @devcoredump: device coredump */
217 struct xe_devcoredump devcoredump;
219 /** @info: device info */
220 struct intel_device_info {
221 /** @graphics_name: graphics IP name */
222 const char *graphics_name;
223 /** @media_name: media IP name */
224 const char *media_name;
225 /** @tile_mmio_ext_size: size of MMIO extension space, per-tile */
226 u32 tile_mmio_ext_size;
227 /** @graphics_verx100: graphics IP version */
228 u32 graphics_verx100;
229 /** @media_verx100: media IP version */
231 /** @mem_region_mask: mask of valid memory regions */
233 /** @platform: XE platform enum */
234 enum xe_platform platform;
235 /** @subplatform: XE subplatform enum */
236 enum xe_subplatform subplatform;
237 /** @devid: device ID */
239 /** @revid: device revision */
241 /** @step: stepping information for each IP */
242 struct xe_step_info step;
243 /** @dma_mask_size: DMA address bits */
245 /** @vram_flags: Vram flags */
247 /** @tile_count: Number of tiles */
249 /** @gt_count: Total number of GTs for entire device */
251 /** @vm_max_level: Max VM level */
253 /** @va_bits: Maximum bits of a virtual address */
256 /** @is_dgfx: is discrete device */
258 /** @has_asid: Has address space ID */
260 /** @force_execlist: Forced execlist submission */
262 /** @has_flat_ccs: Whether flat CCS metadata is used */
264 /** @has_llc: Device has a shared CPU+GPU last level cache */
266 /** @has_mmio_ext: Device has extra MMIO address range */
268 /** @has_range_tlb_invalidation: Has range based TLB invalidations */
269 u8 has_range_tlb_invalidation:1;
270 /** @has_sriov: Supports SR-IOV */
272 /** @has_usm: Device has unified shared memory support */
274 /** @enable_display: display enabled */
276 /** @skip_mtcfg: skip Multi-Tile configuration from MTCFG register */
278 /** @skip_pcode: skip access to PCODE uC */
280 /** @has_heci_gscfi: device has heci gscfi */
282 /** @skip_guc_pc: Skip GuC based PM feature init */
285 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
292 /** @irq: device interrupt state */
294 /** @lock: lock for processing irq's on this device */
297 /** @enabled: interrupts enabled on this device */
301 /** @ttm: ttm device */
302 struct ttm_device ttm;
304 /** @mmio: mmio info for device */
306 /** @size: size of MMIO space for device */
308 /** @regs: pointer to MMIO space for device */
312 /** @mem: memory info for device */
314 /** @vram: VRAM info for device */
315 struct xe_mem_region vram;
316 /** @sys_mgr: system TTM manager */
317 struct ttm_resource_manager sys_mgr;
320 /** @sriov: device level virtualization data */
322 /** @sriov.__mode: SR-IOV mode (Don't access directly!) */
323 enum xe_sriov_mode __mode;
324 /** @sriov.wq: workqueue used by the virtualization workers */
325 struct workqueue_struct *wq;
328 /** @clients: drm clients info */
330 /** @lock: Protects drm clients info */
333 /** @count: number of drm clients */
337 /** @usm: unified memory state */
339 /** @asid: convert a ASID to VM */
340 struct xarray asid_to_vm;
341 /** @next_asid: next ASID, used to cyclical alloc asids */
343 /** @num_vm_in_fault_mode: number of VM in fault mode */
344 u32 num_vm_in_fault_mode;
345 /** @num_vm_in_non_fault_mode: number of VM in non-fault mode */
346 u32 num_vm_in_non_fault_mode;
347 /** @lock: protects UM state */
351 /** @persistent_engines: engines that are closed but still running */
353 /** @lock: protects persistent engines */
355 /** @list: list of persistent engines */
356 struct list_head list;
357 } persistent_engines;
359 /** @pinned: pinned BO state */
361 /** @lock: protected pinned BO list state */
363 /** @evicted: pinned kernel BO that are present */
364 struct list_head kernel_bo_present;
365 /** @evicted: pinned BO that have been evicted */
366 struct list_head evicted;
367 /** @external_vram: pinned external BO in vram*/
368 struct list_head external_vram;
371 /** @ufence_wq: user fence wait queue */
372 wait_queue_head_t ufence_wq;
374 /** @ordered_wq: used to serialize compute mode resume */
375 struct workqueue_struct *ordered_wq;
377 /** @unordered_wq: used to serialize unordered work, mostly display */
378 struct workqueue_struct *unordered_wq;
380 /** @tiles: device tiles */
381 struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE];
384 * @mem_access: keep track of memory access in the device, possibly
385 * triggering additional actions when they occur.
388 /** @ref: ref count of memory accesses */
391 /** @vram_userfault: Encapsulate vram_userfault related stuff */
394 * @lock: Protects access to @vram_usefault.list
395 * Using mutex instead of spinlock as lock is applied to entire
396 * list operation which may sleep
401 * @list: Keep list of userfaulted vram bo, which require to release their
402 * mmap mappings at runtime suspend path
404 struct list_head list;
409 * @pat: Encapsulate PAT related stuff
412 /** Internal operations to abstract platforms */
413 const struct xe_pat_ops *ops;
414 /** PAT table to program in the HW */
415 const struct xe_pat_table_entry *table;
416 /** Number of PAT entries */
418 u32 idx[__XE_CACHE_LEVEL_COUNT];
421 /** @d3cold: Encapsulate d3cold related stuff */
423 /** capable: Indicates if root port is d3cold capable */
426 /** @allowed: Indicates if d3cold is a valid device state */
429 /** @power_lost: Indicates if card has really lost power. */
435 * This represents the permissible threshold(in megabytes)
436 * for vram save/restore. d3cold will be disallowed,
437 * when vram_usages is above or equals the threshold value
438 * to avoid the vram save/restore latency.
439 * Default threshold value is 300mb.
442 /** @lock: protect vram_threshold */
447 * @pm_callback_task: Track the active task that is running in either
448 * the runtime_suspend or runtime_resume callbacks.
450 struct task_struct *pm_callback_task;
452 /** @hwmon: hwmon subsystem integration */
453 struct xe_hwmon *hwmon;
455 /** @heci_gsc: graphics security controller */
456 struct xe_heci_gsc heci_gsc;
458 /** @needs_flr_on_fini: requests function-reset on fini */
459 bool needs_flr_on_fini;
463 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
465 * Any fields below this point are the ones used by display.
466 * They are temporarily added here so xe_device can be desguised as
467 * drm_i915_private during build. After cleanup these should go away,
468 * migrating to the right sub-structs
470 struct intel_display display;
471 enum intel_pch pch_type;
475 bool wm_lv_0_adjust_needed;
477 bool symmetric_memory;
478 enum intel_dram_type {
488 u8 num_psf_gv_points;
493 * Cannot be determined by PCIID. You must always read a register.
497 /* To shut up runtime pm macros.. */
498 struct xe_runtime_pm {} runtime_pm;
501 struct mutex sb_lock;
503 /* Should be in struct intel_display */
504 u32 skl_preferred_vco_freq, max_dotclk_freq, hti_state;
505 u8 snps_phy_failed_calibration;
506 struct drm_atomic_state *modeset_restore_state;
507 struct list_head global_obj_list;
510 /* only to allow build, not used functionally */
512 u32 de_irq_mask[I915_MAX_PIPES];
514 u32 pipestat_irq_mask[I915_MAX_PIPES];
516 bool display_irqs_enabled;
517 u32 enabled_irq_mask;
519 struct intel_uncore {
523 /* only to allow build, not used functionally */
525 unsigned int hpll_freq;
526 unsigned int czclk_freq;
527 unsigned int fsb_freq, mem_freq, is_ddr3;
531 const char *dmc_firmware_path;
539 * struct xe_file - file handle for XE driver
542 /** @xe: xe DEVICE **/
543 struct xe_device *xe;
545 /** @drm: base DRM file */
546 struct drm_file *drm;
548 /** @vm: VM state for file */
550 /** @xe: xarray to store VMs */
552 /** @lock: protects file VM state */
556 /** @exec_queue: Submission exec queue state for file */
558 /** @xe: xarray to store engines */
560 /** @lock: protects file engine state */
564 /** @client: drm client */
565 struct xe_drm_client *client;