1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /**************************************************************************
4 * Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include <linux/sched/signal.h>
30 #include <drm/ttm/ttm_placement.h>
32 #include "vmwgfx_drv.h"
34 struct vmw_temp_set_context {
35 SVGA3dCmdHeader header;
36 SVGA3dCmdDXTempSetContext body;
39 bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
41 u32 *fifo_mem = dev_priv->mmio_virt;
42 uint32_t fifo_min, hwversion;
43 const struct vmw_fifo_state *fifo = &dev_priv->fifo;
45 if (!(dev_priv->capabilities & SVGA_CAP_3D))
48 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
51 if (!dev_priv->has_mob)
54 spin_lock(&dev_priv->cap_lock);
55 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
56 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
57 spin_unlock(&dev_priv->cap_lock);
62 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
65 fifo_min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
66 if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
69 hwversion = vmw_mmio_read(fifo_mem +
70 ((fifo->capabilities &
71 SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
72 SVGA_FIFO_3D_HWVERSION_REVISED :
73 SVGA_FIFO_3D_HWVERSION));
78 if (hwversion < SVGA3D_HWVERSION_WS8_B1)
81 /* Legacy Display Unit does not support surfaces */
82 if (dev_priv->active_display_unit == vmw_du_legacy)
88 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
90 u32 *fifo_mem = dev_priv->mmio_virt;
93 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
96 caps = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
97 if (caps & SVGA_FIFO_CAP_PITCHLOCK)
103 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
105 u32 *fifo_mem = dev_priv->mmio_virt;
110 fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
111 fifo->static_buffer = vmalloc(fifo->static_buffer_size);
112 if (unlikely(fifo->static_buffer == NULL))
115 fifo->dynamic_buffer = NULL;
116 fifo->reserved_size = 0;
117 fifo->using_bounce_buffer = false;
119 mutex_init(&fifo->fifo_mutex);
120 init_rwsem(&fifo->rwsem);
122 DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
123 DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
124 DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
126 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
127 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
128 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
130 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
131 SVGA_REG_ENABLE_HIDE);
132 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
135 if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
136 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
142 vmw_mmio_write(min, fifo_mem + SVGA_FIFO_MIN);
143 vmw_mmio_write(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
145 vmw_mmio_write(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
146 vmw_mmio_write(min, fifo_mem + SVGA_FIFO_STOP);
147 vmw_mmio_write(0, fifo_mem + SVGA_FIFO_BUSY);
150 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
152 max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
153 min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
154 fifo->capabilities = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
156 DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
159 (unsigned int) fifo->capabilities);
161 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
162 vmw_mmio_write(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
163 vmw_marker_queue_init(&fifo->marker_queue);
168 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
170 u32 *fifo_mem = dev_priv->mmio_virt;
173 if (cmpxchg(fifo_mem + SVGA_FIFO_BUSY, 0, 1) == 0)
174 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
178 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
180 u32 *fifo_mem = dev_priv->mmio_virt;
182 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
183 while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
186 dev_priv->last_read_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
188 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
189 dev_priv->config_done_state);
190 vmw_write(dev_priv, SVGA_REG_ENABLE,
191 dev_priv->enable_state);
192 vmw_write(dev_priv, SVGA_REG_TRACES,
193 dev_priv->traces_state);
195 vmw_marker_queue_takedown(&fifo->marker_queue);
197 if (likely(fifo->static_buffer != NULL)) {
198 vfree(fifo->static_buffer);
199 fifo->static_buffer = NULL;
202 if (likely(fifo->dynamic_buffer != NULL)) {
203 vfree(fifo->dynamic_buffer);
204 fifo->dynamic_buffer = NULL;
208 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
210 u32 *fifo_mem = dev_priv->mmio_virt;
211 uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
212 uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
213 uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
214 uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
216 return ((max - next_cmd) + (stop - min) <= bytes);
219 static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
220 uint32_t bytes, bool interruptible,
221 unsigned long timeout)
224 unsigned long end_jiffies = jiffies + timeout;
227 DRM_INFO("Fifo wait noirq.\n");
230 prepare_to_wait(&dev_priv->fifo_queue, &__wait,
232 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
233 if (!vmw_fifo_is_full(dev_priv, bytes))
235 if (time_after_eq(jiffies, end_jiffies)) {
237 DRM_ERROR("SVGA device lockup.\n");
241 if (interruptible && signal_pending(current)) {
246 finish_wait(&dev_priv->fifo_queue, &__wait);
247 wake_up_all(&dev_priv->fifo_queue);
248 DRM_INFO("Fifo noirq exit.\n");
252 static int vmw_fifo_wait(struct vmw_private *dev_priv,
253 uint32_t bytes, bool interruptible,
254 unsigned long timeout)
258 if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
261 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
262 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
263 return vmw_fifo_wait_noirq(dev_priv, bytes,
264 interruptible, timeout);
266 vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,
267 &dev_priv->fifo_queue_waiters);
270 ret = wait_event_interruptible_timeout
271 (dev_priv->fifo_queue,
272 !vmw_fifo_is_full(dev_priv, bytes), timeout);
274 ret = wait_event_timeout
275 (dev_priv->fifo_queue,
276 !vmw_fifo_is_full(dev_priv, bytes), timeout);
278 if (unlikely(ret == 0))
280 else if (likely(ret > 0))
283 vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,
284 &dev_priv->fifo_queue_waiters);
290 * Reserve @bytes number of bytes in the fifo.
292 * This function will return NULL (error) on two conditions:
293 * If it timeouts waiting for fifo space, or if @bytes is larger than the
294 * available fifo space.
297 * Pointer to the fifo, or null on error (possible hardware hang).
299 static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv,
302 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
303 u32 *fifo_mem = dev_priv->mmio_virt;
307 uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
310 mutex_lock(&fifo_state->fifo_mutex);
311 max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
312 min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
313 next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
315 if (unlikely(bytes >= (max - min)))
318 BUG_ON(fifo_state->reserved_size != 0);
319 BUG_ON(fifo_state->dynamic_buffer != NULL);
321 fifo_state->reserved_size = bytes;
324 uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
325 bool need_bounce = false;
326 bool reserve_in_place = false;
328 if (next_cmd >= stop) {
329 if (likely((next_cmd + bytes < max ||
330 (next_cmd + bytes == max && stop > min))))
331 reserve_in_place = true;
333 else if (vmw_fifo_is_full(dev_priv, bytes)) {
334 ret = vmw_fifo_wait(dev_priv, bytes,
336 if (unlikely(ret != 0))
343 if (likely((next_cmd + bytes < stop)))
344 reserve_in_place = true;
346 ret = vmw_fifo_wait(dev_priv, bytes,
348 if (unlikely(ret != 0))
353 if (reserve_in_place) {
354 if (reserveable || bytes <= sizeof(uint32_t)) {
355 fifo_state->using_bounce_buffer = false;
358 vmw_mmio_write(bytes, fifo_mem +
360 return (void __force *) (fifo_mem +
368 fifo_state->using_bounce_buffer = true;
369 if (bytes < fifo_state->static_buffer_size)
370 return fifo_state->static_buffer;
372 fifo_state->dynamic_buffer = vmalloc(bytes);
373 if (!fifo_state->dynamic_buffer)
375 return fifo_state->dynamic_buffer;
380 fifo_state->reserved_size = 0;
381 mutex_unlock(&fifo_state->fifo_mutex);
386 void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes,
392 ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes,
393 ctx_id, false, NULL);
394 else if (ctx_id == SVGA3D_INVALID_ID)
395 ret = vmw_local_fifo_reserve(dev_priv, bytes);
397 WARN(1, "Command buffer has not been allocated.\n");
400 if (IS_ERR_OR_NULL(ret))
406 static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
409 uint32_t max, uint32_t min, uint32_t bytes)
411 uint32_t chunk_size = max - next_cmd;
413 uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
414 fifo_state->dynamic_buffer : fifo_state->static_buffer;
416 if (bytes < chunk_size)
419 vmw_mmio_write(bytes, fifo_mem + SVGA_FIFO_RESERVED);
421 memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
422 rest = bytes - chunk_size;
424 memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), rest);
427 static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
430 uint32_t max, uint32_t min, uint32_t bytes)
432 uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
433 fifo_state->dynamic_buffer : fifo_state->static_buffer;
436 vmw_mmio_write(*buffer++, fifo_mem + (next_cmd >> 2));
437 next_cmd += sizeof(uint32_t);
438 if (unlikely(next_cmd == max))
441 vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
443 bytes -= sizeof(uint32_t);
447 static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
449 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
450 u32 *fifo_mem = dev_priv->mmio_virt;
451 uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
452 uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
453 uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
454 bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
457 bytes += sizeof(struct vmw_temp_set_context);
459 fifo_state->dx = false;
460 BUG_ON((bytes & 3) != 0);
461 BUG_ON(bytes > fifo_state->reserved_size);
463 fifo_state->reserved_size = 0;
465 if (fifo_state->using_bounce_buffer) {
467 vmw_fifo_res_copy(fifo_state, fifo_mem,
468 next_cmd, max, min, bytes);
470 vmw_fifo_slow_copy(fifo_state, fifo_mem,
471 next_cmd, max, min, bytes);
473 if (fifo_state->dynamic_buffer) {
474 vfree(fifo_state->dynamic_buffer);
475 fifo_state->dynamic_buffer = NULL;
480 down_write(&fifo_state->rwsem);
481 if (fifo_state->using_bounce_buffer || reserveable) {
484 next_cmd -= max - min;
486 vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
490 vmw_mmio_write(0, fifo_mem + SVGA_FIFO_RESERVED);
492 up_write(&fifo_state->rwsem);
493 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
494 mutex_unlock(&fifo_state->fifo_mutex);
497 void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
500 vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false);
502 vmw_local_fifo_commit(dev_priv, bytes);
507 * vmw_fifo_commit_flush - Commit fifo space and flush any buffered commands.
509 * @dev_priv: Pointer to device private structure.
510 * @bytes: Number of bytes to commit.
512 void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)
515 vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true);
517 vmw_local_fifo_commit(dev_priv, bytes);
521 * vmw_fifo_flush - Flush any buffered commands and make sure command processing
524 * @dev_priv: Pointer to device private structure.
525 * @interruptible: Whether to wait interruptible if function needs to sleep.
527 int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible)
532 return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible);
537 int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
539 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
540 struct svga_fifo_cmd_fence *cmd_fence;
543 uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence);
545 fm = VMW_FIFO_RESERVE(dev_priv, bytes);
546 if (unlikely(fm == NULL)) {
547 *seqno = atomic_read(&dev_priv->marker_seq);
549 (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
555 *seqno = atomic_add_return(1, &dev_priv->marker_seq);
556 } while (*seqno == 0);
558 if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
561 * Don't request hardware to send a fence. The
562 * waiting code in vmwgfx_irq.c will emulate this.
565 vmw_fifo_commit(dev_priv, 0);
569 *fm++ = SVGA_CMD_FENCE;
570 cmd_fence = (struct svga_fifo_cmd_fence *) fm;
571 cmd_fence->fence = *seqno;
572 vmw_fifo_commit_flush(dev_priv, bytes);
573 (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
574 vmw_update_seqno(dev_priv, fifo_state);
581 * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
582 * legacy query commands.
584 * @dev_priv: The device private structure.
585 * @cid: The hardware context id used for the query.
587 * See the vmw_fifo_emit_dummy_query documentation.
589 static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
593 * A query wait without a preceding query end will
594 * actually finish all queries for this cid
595 * without writing to the query result structure.
598 struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
600 SVGA3dCmdHeader header;
601 SVGA3dCmdWaitForQuery body;
604 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
605 if (unlikely(cmd == NULL))
608 cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
609 cmd->header.size = sizeof(cmd->body);
611 cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
613 if (bo->mem.mem_type == TTM_PL_VRAM) {
614 cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
615 cmd->body.guestResult.offset = bo->offset;
617 cmd->body.guestResult.gmrId = bo->mem.start;
618 cmd->body.guestResult.offset = 0;
621 vmw_fifo_commit(dev_priv, sizeof(*cmd));
627 * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
628 * guest-backed resource query commands.
630 * @dev_priv: The device private structure.
631 * @cid: The hardware context id used for the query.
633 * See the vmw_fifo_emit_dummy_query documentation.
635 static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
639 * A query wait without a preceding query end will
640 * actually finish all queries for this cid
641 * without writing to the query result structure.
644 struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
646 SVGA3dCmdHeader header;
647 SVGA3dCmdWaitForGBQuery body;
650 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
651 if (unlikely(cmd == NULL))
654 cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
655 cmd->header.size = sizeof(cmd->body);
657 cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
658 BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
659 cmd->body.mobid = bo->mem.start;
660 cmd->body.offset = 0;
662 vmw_fifo_commit(dev_priv, sizeof(*cmd));
669 * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
670 * appropriate resource query commands.
672 * @dev_priv: The device private structure.
673 * @cid: The hardware context id used for the query.
675 * This function is used to emit a dummy occlusion query with
676 * no primitives rendered between query begin and query end.
677 * It's used to provide a query barrier, in order to know that when
678 * this query is finished, all preceding queries are also finished.
680 * A Query results structure should have been initialized at the start
681 * of the dev_priv->dummy_query_bo buffer object. And that buffer object
682 * must also be either reserved or pinned when this function is called.
684 * Returns -ENOMEM on failure to reserve fifo space.
686 int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
689 if (dev_priv->has_mob)
690 return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);
692 return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);