drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /**************************************************************************
   3  *
   4  * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <linux/console.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/module.h>
  31 #include <linux/pci.h>
  32 #include <linux/mem_encrypt.h>
  33
  34 #include <drm/drm_aperture.h>
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_ioctl.h>
  37 #include <drm/drm_sysfs.h>
  38 #include <drm/ttm/ttm_bo_driver.h>
  39 #include <drm/ttm/ttm_range_manager.h>
  40 #include <drm/ttm/ttm_placement.h>
  41 #include <generated/utsrelease.h>
  42
  43 #include "ttm_object.h"
  44 #include "vmwgfx_binding.h"
  45 #include "vmwgfx_devcaps.h"
  46 #include "vmwgfx_drv.h"
  47 #include "vmwgfx_mksstat.h"
  48
  49 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  50
  51 #define VMW_MIN_INITIAL_WIDTH 800
  52 #define VMW_MIN_INITIAL_HEIGHT 600
  53
  54 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE)
  55
  56
  57 /*
  58  * Fully encoded drm commands. Might move to vmw_drm.h
  59  */
  60
  61 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  62         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  63                  struct drm_vmw_getparam_arg)
  64 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  65         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  66                 union drm_vmw_alloc_dmabuf_arg)
  67 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  68         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  69                 struct drm_vmw_unref_dmabuf_arg)
  70 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  71         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  72                  struct drm_vmw_cursor_bypass_arg)
  73
  74 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  75         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  76                  struct drm_vmw_control_stream_arg)
  77 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  78         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  79                  struct drm_vmw_stream_arg)
  80 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  81         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  82                  struct drm_vmw_stream_arg)
  83
  84 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  85         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  86                 struct drm_vmw_context_arg)
  87 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  88         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  89                 struct drm_vmw_context_arg)
  90 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  91         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  92                  union drm_vmw_surface_create_arg)
  93 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  94         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  95                  struct drm_vmw_surface_arg)
  96 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  97         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  98                  union drm_vmw_surface_reference_arg)
  99 #define DRM_IOCTL_VMW_EXECBUF                                   \
 100         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
 101                 struct drm_vmw_execbuf_arg)
 102 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
 103         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
 104                  struct drm_vmw_get_3d_cap_arg)
 105 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
 106         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
 107                  struct drm_vmw_fence_wait_arg)
 108 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
 109         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
 110                  struct drm_vmw_fence_signaled_arg)
 111 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
 112         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
 113                  struct drm_vmw_fence_arg)
 114 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
 115         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
 116                  struct drm_vmw_fence_event_arg)
 117 #define DRM_IOCTL_VMW_PRESENT                                   \
 118         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
 119                  struct drm_vmw_present_arg)
 120 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
 121         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
 122                  struct drm_vmw_present_readback_arg)
 123 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
 124         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
 125                  struct drm_vmw_update_layout_arg)
 126 #define DRM_IOCTL_VMW_CREATE_SHADER                             \
 127         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,      \
 128                  struct drm_vmw_shader_create_arg)
 129 #define DRM_IOCTL_VMW_UNREF_SHADER                              \
 130         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,        \
 131                  struct drm_vmw_shader_arg)
 132 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE                         \
 133         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,  \
 134                  union drm_vmw_gb_surface_create_arg)
 135 #define DRM_IOCTL_VMW_GB_SURFACE_REF                            \
 136         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,     \
 137                  union drm_vmw_gb_surface_reference_arg)
 138 #define DRM_IOCTL_VMW_SYNCCPU                                   \
 139         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,             \
 140                  struct drm_vmw_synccpu_arg)
 141 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT                   \
 142         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT,    \
 143                 struct drm_vmw_context_arg)
 144 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT                             \
 145         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT,      \
 146                 union drm_vmw_gb_surface_create_ext_arg)
 147 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT                                \
 148         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT,         \
 149                 union drm_vmw_gb_surface_reference_ext_arg)
 150 #define DRM_IOCTL_VMW_MSG                                               \
 151         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG,                        \
 152                 struct drm_vmw_msg_arg)
 153 #define DRM_IOCTL_VMW_MKSSTAT_RESET                             \
 154         DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET)
 155 #define DRM_IOCTL_VMW_MKSSTAT_ADD                               \
 156         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD,        \
 157                 struct drm_vmw_mksstat_add_arg)
 158 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE                            \
 159         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE,      \
 160                 struct drm_vmw_mksstat_remove_arg)
 161
 162 /*
 163  * The core DRM version of this macro doesn't account for
 164  * DRM_COMMAND_BASE.
 165  */
 166
 167 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 168   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
 169
 170 /*
 171  * Ioctl definitions.
 172  */
 173
 174 static const struct drm_ioctl_desc vmw_ioctls[] = {
 175         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 176                       DRM_RENDER_ALLOW),
 177         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl,
 178                       DRM_RENDER_ALLOW),
 179         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
 180                       DRM_RENDER_ALLOW),
 181         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 182                       vmw_kms_cursor_bypass_ioctl,
 183                       DRM_MASTER),
 184
 185         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 186                       DRM_MASTER),
 187         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 188                       DRM_MASTER),
 189         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 190                       DRM_MASTER),
 191
 192         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 193                       DRM_RENDER_ALLOW),
 194         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 195                       DRM_RENDER_ALLOW),
 196         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 197                       DRM_RENDER_ALLOW),
 198         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 199                       DRM_RENDER_ALLOW),
 200         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 201                       DRM_RENDER_ALLOW),
 202         VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
 203                       DRM_RENDER_ALLOW),
 204         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
 205                       DRM_RENDER_ALLOW),
 206         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
 207                       vmw_fence_obj_signaled_ioctl,
 208                       DRM_RENDER_ALLOW),
 209         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
 210                       DRM_RENDER_ALLOW),
 211         VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
 212                       DRM_RENDER_ALLOW),
 213         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
 214                       DRM_RENDER_ALLOW),
 215
 216         /* these allow direct access to the framebuffers mark as master only */
 217         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
 218                       DRM_MASTER | DRM_AUTH),
 219         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
 220                       vmw_present_readback_ioctl,
 221                       DRM_MASTER | DRM_AUTH),
 222         /*
 223          * The permissions of the below ioctl are overridden in
 224          * vmw_generic_ioctl(). We require either
 225          * DRM_MASTER or capable(CAP_SYS_ADMIN).
 226          */
 227         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
 228                       vmw_kms_update_layout_ioctl,
 229                       DRM_RENDER_ALLOW),
 230         VMW_IOCTL_DEF(VMW_CREATE_SHADER,
 231                       vmw_shader_define_ioctl,
 232                       DRM_RENDER_ALLOW),
 233         VMW_IOCTL_DEF(VMW_UNREF_SHADER,
 234                       vmw_shader_destroy_ioctl,
 235                       DRM_RENDER_ALLOW),
 236         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
 237                       vmw_gb_surface_define_ioctl,
 238                       DRM_RENDER_ALLOW),
 239         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
 240                       vmw_gb_surface_reference_ioctl,
 241                       DRM_RENDER_ALLOW),
 242         VMW_IOCTL_DEF(VMW_SYNCCPU,
 243                       vmw_user_bo_synccpu_ioctl,
 244                       DRM_RENDER_ALLOW),
 245         VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
 246                       vmw_extended_context_define_ioctl,
 247                       DRM_RENDER_ALLOW),
 248         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT,
 249                       vmw_gb_surface_define_ext_ioctl,
 250                       DRM_RENDER_ALLOW),
 251         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT,
 252                       vmw_gb_surface_reference_ext_ioctl,
 253                       DRM_RENDER_ALLOW),
 254         VMW_IOCTL_DEF(VMW_MSG,
 255                       vmw_msg_ioctl,
 256                       DRM_RENDER_ALLOW),
 257         VMW_IOCTL_DEF(VMW_MKSSTAT_RESET,
 258                       vmw_mksstat_reset_ioctl,
 259                       DRM_RENDER_ALLOW),
 260         VMW_IOCTL_DEF(VMW_MKSSTAT_ADD,
 261                       vmw_mksstat_add_ioctl,
 262                       DRM_RENDER_ALLOW),
 263         VMW_IOCTL_DEF(VMW_MKSSTAT_REMOVE,
 264                       vmw_mksstat_remove_ioctl,
 265                       DRM_RENDER_ALLOW),
 266 };
 267
 268 static const struct pci_device_id vmw_pci_id_list[] = {
 269         { PCI_DEVICE(0x15ad, VMWGFX_PCI_ID_SVGA2) },
 270         { PCI_DEVICE(0x15ad, VMWGFX_PCI_ID_SVGA3) },
 271         { }
 272 };
 273 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
 274
 275 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
 276 static int vmw_restrict_iommu;
 277 static int vmw_force_coherent;
 278 static int vmw_restrict_dma_mask;
 279 static int vmw_assume_16bpp;
 280
 281 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 282 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 283                               void *ptr);
 284
 285 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 286 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 287 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
 288 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
 289 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
 290 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
 291 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
 292 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
 293 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
 294 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
 295
 296
 297 static void vmw_print_capabilities2(uint32_t capabilities2)
 298 {
 299         DRM_INFO("Capabilities2:\n");
 300         if (capabilities2 & SVGA_CAP2_GROW_OTABLE)
 301                 DRM_INFO("  Grow oTable.\n");
 302         if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)
 303                 DRM_INFO("  IntraSurface copy.\n");
 304         if (capabilities2 & SVGA_CAP2_DX3)
 305                 DRM_INFO("  DX3.\n");
 306 }
 307
 308 static void vmw_print_capabilities(uint32_t capabilities)
 309 {
 310         DRM_INFO("Capabilities:\n");
 311         if (capabilities & SVGA_CAP_RECT_COPY)
 312                 DRM_INFO("  Rect copy.\n");
 313         if (capabilities & SVGA_CAP_CURSOR)
 314                 DRM_INFO("  Cursor.\n");
 315         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 316                 DRM_INFO("  Cursor bypass.\n");
 317         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 318                 DRM_INFO("  Cursor bypass 2.\n");
 319         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 320                 DRM_INFO("  8bit emulation.\n");
 321         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 322                 DRM_INFO("  Alpha cursor.\n");
 323         if (capabilities & SVGA_CAP_3D)
 324                 DRM_INFO("  3D.\n");
 325         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 326                 DRM_INFO("  Extended Fifo.\n");
 327         if (capabilities & SVGA_CAP_MULTIMON)
 328                 DRM_INFO("  Multimon.\n");
 329         if (capabilities & SVGA_CAP_PITCHLOCK)
 330                 DRM_INFO("  Pitchlock.\n");
 331         if (capabilities & SVGA_CAP_IRQMASK)
 332                 DRM_INFO("  Irq mask.\n");
 333         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 334                 DRM_INFO("  Display Topology.\n");
 335         if (capabilities & SVGA_CAP_GMR)
 336                 DRM_INFO("  GMR.\n");
 337         if (capabilities & SVGA_CAP_TRACES)
 338                 DRM_INFO("  Traces.\n");
 339         if (capabilities & SVGA_CAP_GMR2)
 340                 DRM_INFO("  GMR2.\n");
 341         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
 342                 DRM_INFO("  Screen Object 2.\n");
 343         if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
 344                 DRM_INFO("  Command Buffers.\n");
 345         if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
 346                 DRM_INFO("  Command Buffers 2.\n");
 347         if (capabilities & SVGA_CAP_GBOBJECTS)
 348                 DRM_INFO("  Guest Backed Resources.\n");
 349         if (capabilities & SVGA_CAP_DX)
 350                 DRM_INFO("  DX Features.\n");
 351         if (capabilities & SVGA_CAP_HP_CMD_QUEUE)
 352                 DRM_INFO("  HP Command Queue.\n");
 353 }
 354
 355 /**
 356  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
 357  *
 358  * @dev_priv: A device private structure.
 359  *
 360  * This function creates a small buffer object that holds the query
 361  * result for dummy queries emitted as query barriers.
 362  * The function will then map the first page and initialize a pending
 363  * occlusion query result structure, Finally it will unmap the buffer.
 364  * No interruptible waits are done within this function.
 365  *
 366  * Returns an error if bo creation or initialization fails.
 367  */
 368 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
 369 {
 370         int ret;
 371         struct vmw_buffer_object *vbo;
 372         struct ttm_bo_kmap_obj map;
 373         volatile SVGA3dQueryResult *result;
 374         bool dummy;
 375
 376         /*
 377          * Create the vbo as pinned, so that a tryreserve will
 378          * immediately succeed. This is because we're the only
 379          * user of the bo currently.
 380          */
 381         vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
 382         if (!vbo)
 383                 return -ENOMEM;
 384
 385         ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE,
 386                           &vmw_sys_placement, false, true,
 387                           &vmw_bo_bo_free);
 388         if (unlikely(ret != 0))
 389                 return ret;
 390
 391         ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
 392         BUG_ON(ret != 0);
 393         vmw_bo_pin_reserved(vbo, true);
 394
 395         ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
 396         if (likely(ret == 0)) {
 397                 result = ttm_kmap_obj_virtual(&map, &dummy);
 398                 result->totalSize = sizeof(*result);
 399                 result->state = SVGA3D_QUERYSTATE_PENDING;
 400                 result->result32 = 0xff;
 401                 ttm_bo_kunmap(&map);
 402         }
 403         vmw_bo_pin_reserved(vbo, false);
 404         ttm_bo_unreserve(&vbo->base);
 405
 406         if (unlikely(ret != 0)) {
 407                 DRM_ERROR("Dummy query buffer map failed.\n");
 408                 vmw_bo_unreference(&vbo);
 409         } else
 410                 dev_priv->dummy_query_bo = vbo;
 411
 412         return ret;
 413 }
 414
 415 static int vmw_device_init(struct vmw_private *dev_priv)
 416 {
 417         bool uses_fb_traces = false;
 418
 419         DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
 420         DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
 421         DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
 422
 423         dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
 424         dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
 425         dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
 426
 427         vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
 428                   SVGA_REG_ENABLE_HIDE);
 429
 430         uses_fb_traces = !vmw_cmd_supported(dev_priv) &&
 431                          (dev_priv->capabilities & SVGA_CAP_TRACES) != 0;
 432
 433         vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces);
 434         dev_priv->fifo = vmw_fifo_create(dev_priv);
 435         if (IS_ERR(dev_priv->fifo)) {
 436                 int err = PTR_ERR(dev_priv->fifo);
 437                 dev_priv->fifo = NULL;
 438                 return err;
 439         } else if (!dev_priv->fifo) {
 440                 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
 441         }
 442
 443         dev_priv->last_read_seqno = vmw_fence_read(dev_priv);
 444         atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
 445         return 0;
 446 }
 447
 448 static void vmw_device_fini(struct vmw_private *vmw)
 449 {
 450         /*
 451          * Legacy sync
 452          */
 453         vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
 454         while (vmw_read(vmw, SVGA_REG_BUSY) != 0)
 455                 ;
 456
 457         vmw->last_read_seqno = vmw_fence_read(vmw);
 458
 459         vmw_write(vmw, SVGA_REG_CONFIG_DONE,
 460                   vmw->config_done_state);
 461         vmw_write(vmw, SVGA_REG_ENABLE,
 462                   vmw->enable_state);
 463         vmw_write(vmw, SVGA_REG_TRACES,
 464                   vmw->traces_state);
 465
 466         vmw_fifo_destroy(vmw);
 467 }
 468
 469 /**
 470  * vmw_request_device_late - Perform late device setup
 471  *
 472  * @dev_priv: Pointer to device private.
 473  *
 474  * This function performs setup of otables and enables large command
 475  * buffer submission. These tasks are split out to a separate function
 476  * because it reverts vmw_release_device_early and is intended to be used
 477  * by an error path in the hibernation code.
 478  */
 479 static int vmw_request_device_late(struct vmw_private *dev_priv)
 480 {
 481         int ret;
 482
 483         if (dev_priv->has_mob) {
 484                 ret = vmw_otables_setup(dev_priv);
 485                 if (unlikely(ret != 0)) {
 486                         DRM_ERROR("Unable to initialize "
 487                                   "guest Memory OBjects.\n");
 488                         return ret;
 489                 }
 490         }
 491
 492         if (dev_priv->cman) {
 493                 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096);
 494                 if (ret) {
 495                         struct vmw_cmdbuf_man *man = dev_priv->cman;
 496
 497                         dev_priv->cman = NULL;
 498                         vmw_cmdbuf_man_destroy(man);
 499                 }
 500         }
 501
 502         return 0;
 503 }
 504
 505 static int vmw_request_device(struct vmw_private *dev_priv)
 506 {
 507         int ret;
 508
 509         ret = vmw_device_init(dev_priv);
 510         if (unlikely(ret != 0)) {
 511                 DRM_ERROR("Unable to initialize the device.\n");
 512                 return ret;
 513         }
 514         vmw_fence_fifo_up(dev_priv->fman);
 515         dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
 516         if (IS_ERR(dev_priv->cman)) {
 517                 dev_priv->cman = NULL;
 518                 dev_priv->sm_type = VMW_SM_LEGACY;
 519         }
 520
 521         ret = vmw_request_device_late(dev_priv);
 522         if (ret)
 523                 goto out_no_mob;
 524
 525         ret = vmw_dummy_query_bo_create(dev_priv);
 526         if (unlikely(ret != 0))
 527                 goto out_no_query_bo;
 528
 529         return 0;
 530
 531 out_no_query_bo:
 532         if (dev_priv->cman)
 533                 vmw_cmdbuf_remove_pool(dev_priv->cman);
 534         if (dev_priv->has_mob) {
 535                 struct ttm_resource_manager *man;
 536
 537                 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
 538                 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
 539                 vmw_otables_takedown(dev_priv);
 540         }
 541         if (dev_priv->cman)
 542                 vmw_cmdbuf_man_destroy(dev_priv->cman);
 543 out_no_mob:
 544         vmw_fence_fifo_down(dev_priv->fman);
 545         vmw_device_fini(dev_priv);
 546         return ret;
 547 }
 548
 549 /**
 550  * vmw_release_device_early - Early part of fifo takedown.
 551  *
 552  * @dev_priv: Pointer to device private struct.
 553  *
 554  * This is the first part of command submission takedown, to be called before
 555  * buffer management is taken down.
 556  */
 557 static void vmw_release_device_early(struct vmw_private *dev_priv)
 558 {
 559         /*
 560          * Previous destructions should've released
 561          * the pinned bo.
 562          */
 563
 564         BUG_ON(dev_priv->pinned_bo != NULL);
 565
 566         vmw_bo_unreference(&dev_priv->dummy_query_bo);
 567         if (dev_priv->cman)
 568                 vmw_cmdbuf_remove_pool(dev_priv->cman);
 569
 570         if (dev_priv->has_mob) {
 571                 struct ttm_resource_manager *man;
 572
 573                 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
 574                 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
 575                 vmw_otables_takedown(dev_priv);
 576         }
 577 }
 578
 579 /**
 580  * vmw_release_device_late - Late part of fifo takedown.
 581  *
 582  * @dev_priv: Pointer to device private struct.
 583  *
 584  * This is the last part of the command submission takedown, to be called when
 585  * command submission is no longer needed. It may wait on pending fences.
 586  */
 587 static void vmw_release_device_late(struct vmw_private *dev_priv)
 588 {
 589         vmw_fence_fifo_down(dev_priv->fman);
 590         if (dev_priv->cman)
 591                 vmw_cmdbuf_man_destroy(dev_priv->cman);
 592
 593         vmw_device_fini(dev_priv);
 594 }
 595
 596 /*
 597  * Sets the initial_[width|height] fields on the given vmw_private.
 598  *
 599  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
 600  * clamping the value to fb_max_[width|height] fields and the
 601  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 602  * If the values appear to be invalid, set them to
 603  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 604  */
 605 static void vmw_get_initial_size(struct vmw_private *dev_priv)
 606 {
 607         uint32_t width;
 608         uint32_t height;
 609
 610         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
 611         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
 612
 613         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
 614         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
 615
 616         if (width > dev_priv->fb_max_width ||
 617             height > dev_priv->fb_max_height) {
 618
 619                 /*
 620                  * This is a host error and shouldn't occur.
 621                  */
 622
 623                 width = VMW_MIN_INITIAL_WIDTH;
 624                 height = VMW_MIN_INITIAL_HEIGHT;
 625         }
 626
 627         dev_priv->initial_width = width;
 628         dev_priv->initial_height = height;
 629 }
 630
 631 /**
 632  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
 633  * system.
 634  *
 635  * @dev_priv: Pointer to a struct vmw_private
 636  *
 637  * This functions tries to determine what actions need to be taken by the
 638  * driver to make system pages visible to the device.
 639  * If this function decides that DMA is not possible, it returns -EINVAL.
 640  * The driver may then try to disable features of the device that require
 641  * DMA.
 642  */
 643 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
 644 {
 645         static const char *names[vmw_dma_map_max] = {
 646                 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
 647                 [vmw_dma_map_populate] = "Caching DMA mappings.",
 648                 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
 649
 650         /* TTM currently doesn't fully support SEV encryption. */
 651         if (mem_encrypt_active())
 652                 return -EINVAL;
 653
 654         if (vmw_force_coherent)
 655                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 656         else if (vmw_restrict_iommu)
 657                 dev_priv->map_mode = vmw_dma_map_bind;
 658         else
 659                 dev_priv->map_mode = vmw_dma_map_populate;
 660
 661         DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 662         return 0;
 663 }
 664
 665 /**
 666  * vmw_dma_masks - set required page- and dma masks
 667  *
 668  * @dev_priv: Pointer to struct drm-device
 669  *
 670  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
 671  * restriction also for 64-bit systems.
 672  */
 673 static int vmw_dma_masks(struct vmw_private *dev_priv)
 674 {
 675         struct drm_device *dev = &dev_priv->drm;
 676         int ret = 0;
 677
 678         ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
 679         if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) {
 680                 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
 681                 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
 682         }
 683
 684         return ret;
 685 }
 686
 687 static int vmw_vram_manager_init(struct vmw_private *dev_priv)
 688 {
 689         int ret;
 690 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 691         ret = vmw_thp_init(dev_priv);
 692 #else
 693         ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false,
 694                                  dev_priv->vram_size >> PAGE_SHIFT);
 695 #endif
 696         ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false);
 697         return ret;
 698 }
 699
 700 static void vmw_vram_manager_fini(struct vmw_private *dev_priv)
 701 {
 702 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 703         vmw_thp_fini(dev_priv);
 704 #else
 705         ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM);
 706 #endif
 707 }
 708
 709 static int vmw_setup_pci_resources(struct vmw_private *dev,
 710                                    u32 pci_id)
 711 {
 712         resource_size_t rmmio_start;
 713         resource_size_t rmmio_size;
 714         resource_size_t fifo_start;
 715         resource_size_t fifo_size;
 716         int ret;
 717         struct pci_dev *pdev = to_pci_dev(dev->drm.dev);
 718
 719         pci_set_master(pdev);
 720
 721         ret = pci_request_regions(pdev, "vmwgfx probe");
 722         if (ret)
 723                 return ret;
 724
 725         dev->pci_id = pci_id;
 726         if (pci_id == VMWGFX_PCI_ID_SVGA3) {
 727                 rmmio_start = pci_resource_start(pdev, 0);
 728                 rmmio_size = pci_resource_len(pdev, 0);
 729                 dev->vram_start = pci_resource_start(pdev, 2);
 730                 dev->vram_size = pci_resource_len(pdev, 2);
 731
 732                 DRM_INFO("Register MMIO at 0x%pa size is %llu kiB\n",
 733                          &rmmio_start, (uint64_t)rmmio_size / 1024);
 734                 dev->rmmio = devm_ioremap(dev->drm.dev,
 735                                           rmmio_start,
 736                                           rmmio_size);
 737                 if (!dev->rmmio) {
 738                         DRM_ERROR("Failed mapping registers mmio memory.\n");
 739                         pci_release_regions(pdev);
 740                         return -ENOMEM;
 741                 }
 742         } else if (pci_id == VMWGFX_PCI_ID_SVGA2) {
 743                 dev->io_start = pci_resource_start(pdev, 0);
 744                 dev->vram_start = pci_resource_start(pdev, 1);
 745                 dev->vram_size = pci_resource_len(pdev, 1);
 746                 fifo_start = pci_resource_start(pdev, 2);
 747                 fifo_size = pci_resource_len(pdev, 2);
 748
 749                 DRM_INFO("FIFO at %pa size is %llu kiB\n",
 750                          &fifo_start, (uint64_t)fifo_size / 1024);
 751                 dev->fifo_mem = devm_memremap(dev->drm.dev,
 752                                               fifo_start,
 753                                               fifo_size,
 754                                               MEMREMAP_WB);
 755
 756                 if (IS_ERR(dev->fifo_mem)) {
 757                         DRM_ERROR("Failed mapping FIFO memory.\n");
 758                         pci_release_regions(pdev);
 759                         return PTR_ERR(dev->fifo_mem);
 760                 }
 761         } else {
 762                 pci_release_regions(pdev);
 763                 return -EINVAL;
 764         }
 765
 766         /*
 767          * This is approximate size of the vram, the exact size will only
 768          * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource
 769          * size will be equal to or bigger than the size reported by
 770          * SVGA_REG_VRAM_SIZE.
 771          */
 772         DRM_INFO("VRAM at %pa size is %llu kiB\n",
 773                  &dev->vram_start, (uint64_t)dev->vram_size / 1024);
 774
 775         return 0;
 776 }
 777
 778 static int vmw_detect_version(struct vmw_private *dev)
 779 {
 780         uint32_t svga_id;
 781
 782         vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ?
 783                           SVGA_ID_3 : SVGA_ID_2);
 784         svga_id = vmw_read(dev, SVGA_REG_ID);
 785         if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) {
 786                 DRM_ERROR("Unsupported SVGA ID 0x%x on chipset 0x%x\n",
 787                           svga_id, dev->pci_id);
 788                 return -ENOSYS;
 789         }
 790         BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3));
 791         DRM_INFO("Running on SVGA version %d.\n", (svga_id & 0xff));
 792         return 0;
 793 }
 794
 795 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
 796 {
 797         int ret;
 798         enum vmw_res_type i;
 799         bool refuse_dma = false;
 800         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 801
 802         dev_priv->drm.dev_private = dev_priv;
 803
 804         mutex_init(&dev_priv->cmdbuf_mutex);
 805         mutex_init(&dev_priv->binding_mutex);
 806         spin_lock_init(&dev_priv->resource_lock);
 807         spin_lock_init(&dev_priv->hw_lock);
 808         spin_lock_init(&dev_priv->waiter_lock);
 809         spin_lock_init(&dev_priv->cursor_lock);
 810
 811         ret = vmw_setup_pci_resources(dev_priv, pci_id);
 812         if (ret)
 813                 return ret;
 814         ret = vmw_detect_version(dev_priv);
 815         if (ret)
 816                 goto out_no_pci_or_version;
 817
 818
 819         for (i = vmw_res_context; i < vmw_res_max; ++i) {
 820                 idr_init_base(&dev_priv->res_idr[i], 1);
 821                 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
 822         }
 823
 824         init_waitqueue_head(&dev_priv->fence_queue);
 825         init_waitqueue_head(&dev_priv->fifo_queue);
 826         dev_priv->fence_queue_waiters = 0;
 827         dev_priv->fifo_queue_waiters = 0;
 828
 829         dev_priv->used_memory_size = 0;
 830
 831         dev_priv->assume_16bpp = !!vmw_assume_16bpp;
 832
 833         dev_priv->enable_fb = enable_fbdev;
 834
 835
 836         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 837
 838         if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
 839                 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
 840         }
 841
 842
 843         ret = vmw_dma_select_mode(dev_priv);
 844         if (unlikely(ret != 0)) {
 845                 DRM_INFO("Restricting capabilities since DMA not available.\n");
 846                 refuse_dma = true;
 847                 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
 848                         DRM_INFO("Disabling 3D acceleration.\n");
 849         }
 850
 851         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 852         dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 853         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 854         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 855
 856         vmw_get_initial_size(dev_priv);
 857
 858         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 859                 dev_priv->max_gmr_ids =
 860                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 861                 dev_priv->max_gmr_pages =
 862                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
 863                 dev_priv->memory_size =
 864                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
 865                 dev_priv->memory_size -= dev_priv->vram_size;
 866         } else {
 867                 /*
 868                  * An arbitrary limit of 512MiB on surface
 869                  * memory. But all HWV8 hardware supports GMR2.
 870                  */
 871                 dev_priv->memory_size = 512*1024*1024;
 872         }
 873         dev_priv->max_mob_pages = 0;
 874         dev_priv->max_mob_size = 0;
 875         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 876                 uint64_t mem_size;
 877
 878                 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2)
 879                         mem_size = vmw_read(dev_priv,
 880                                             SVGA_REG_GBOBJECT_MEM_SIZE_KB);
 881                 else
 882                         mem_size =
 883                                 vmw_read(dev_priv,
 884                                          SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
 885
 886                 /*
 887                  * Workaround for low memory 2D VMs to compensate for the
 888                  * allocation taken by fbdev
 889                  */
 890                 if (!(dev_priv->capabilities & SVGA_CAP_3D))
 891                         mem_size *= 3;
 892
 893                 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
 894                 dev_priv->max_primary_mem =
 895                         vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);
 896                 dev_priv->max_mob_size =
 897                         vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
 898                 dev_priv->stdu_max_width =
 899                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
 900                 dev_priv->stdu_max_height =
 901                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
 902
 903                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 904                           SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
 905                 dev_priv->texture_max_width = vmw_read(dev_priv,
 906                                                        SVGA_REG_DEV_CAP);
 907                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
 908                           SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
 909                 dev_priv->texture_max_height = vmw_read(dev_priv,
 910                                                         SVGA_REG_DEV_CAP);
 911         } else {
 912                 dev_priv->texture_max_width = 8192;
 913                 dev_priv->texture_max_height = 8192;
 914                 dev_priv->max_primary_mem = dev_priv->vram_size;
 915         }
 916
 917         vmw_print_capabilities(dev_priv->capabilities);
 918         if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER)
 919                 vmw_print_capabilities2(dev_priv->capabilities2);
 920         DRM_INFO("Supports command queues = %d\n",
 921                  vmw_cmd_supported((dev_priv)));
 922
 923         ret = vmw_dma_masks(dev_priv);
 924         if (unlikely(ret != 0))
 925                 goto out_err0;
 926
 927         dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX);
 928
 929         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 930                 DRM_INFO("Max GMR ids is %u\n",
 931                          (unsigned)dev_priv->max_gmr_ids);
 932                 DRM_INFO("Max number of GMR pages is %u\n",
 933                          (unsigned)dev_priv->max_gmr_pages);
 934                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
 935                          (unsigned)dev_priv->memory_size / 1024);
 936         }
 937         DRM_INFO("Maximum display memory size is %llu kiB\n",
 938                  (uint64_t)dev_priv->max_primary_mem / 1024);
 939
 940         /* Need mmio memory to check for fifo pitchlock cap. */
 941         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 942             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 943             !vmw_fifo_have_pitchlock(dev_priv)) {
 944                 ret = -ENOSYS;
 945                 DRM_ERROR("Hardware has no pitchlock\n");
 946                 goto out_err0;
 947         }
 948
 949         dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12,
 950                                                 &vmw_prime_dmabuf_ops);
 951
 952         if (unlikely(dev_priv->tdev == NULL)) {
 953                 DRM_ERROR("Unable to initialize TTM object management.\n");
 954                 ret = -ENOMEM;
 955                 goto out_err0;
 956         }
 957
 958         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 959                 ret = vmw_irq_install(&dev_priv->drm, pdev->irq);
 960                 if (ret != 0) {
 961                         DRM_ERROR("Failed installing irq: %d\n", ret);
 962                         goto out_no_irq;
 963                 }
 964         }
 965
 966         dev_priv->fman = vmw_fence_manager_init(dev_priv);
 967         if (unlikely(dev_priv->fman == NULL)) {
 968                 ret = -ENOMEM;
 969                 goto out_no_fman;
 970         }
 971
 972         drm_vma_offset_manager_init(&dev_priv->vma_manager,
 973                                     DRM_FILE_PAGE_OFFSET_START,
 974                                     DRM_FILE_PAGE_OFFSET_SIZE);
 975         ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver,
 976                               dev_priv->drm.dev,
 977                               dev_priv->drm.anon_inode->i_mapping,
 978                               &dev_priv->vma_manager,
 979                               dev_priv->map_mode == vmw_dma_alloc_coherent,
 980                               false);
 981         if (unlikely(ret != 0)) {
 982                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 983                 goto out_no_bdev;
 984         }
 985
 986         /*
 987          * Enable VRAM, but initially don't use it until SVGA is enabled and
 988          * unhidden.
 989          */
 990
 991         ret = vmw_vram_manager_init(dev_priv);
 992         if (unlikely(ret != 0)) {
 993                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 994                 goto out_no_vram;
 995         }
 996
 997         ret = vmw_devcaps_create(dev_priv);
 998         if (unlikely(ret != 0)) {
 999                 DRM_ERROR("Failed initializing device caps.\n");
1000                 goto out_no_vram;
1001         }
1002
1003         /*
1004          * "Guest Memory Regions" is an aperture like feature with
1005          *  one slot per bo. There is an upper limit of the number of
1006          *  slots as well as the bo size.
1007          */
1008         dev_priv->has_gmr = true;
1009         /* TODO: This is most likely not correct */
1010         if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
1011             refuse_dma ||
1012             vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) {
1013                 DRM_INFO("No GMR memory available. "
1014                          "Graphics memory resources are very limited.\n");
1015                 dev_priv->has_gmr = false;
1016         }
1017
1018         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) {
1019                 dev_priv->has_mob = true;
1020
1021                 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) {
1022                         DRM_INFO("No MOB memory available. "
1023                                  "3D will be disabled.\n");
1024                         dev_priv->has_mob = false;
1025                 }
1026         }
1027
1028         if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {
1029                 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT))
1030                         dev_priv->sm_type = VMW_SM_4;
1031         }
1032
1033         vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN);
1034
1035         /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
1036         if (has_sm4_context(dev_priv) &&
1037             (dev_priv->capabilities2 & SVGA_CAP2_DX2)) {
1038                 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41))
1039                         dev_priv->sm_type = VMW_SM_4_1;
1040                 if (has_sm4_1_context(dev_priv) &&
1041                                 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) {
1042                         if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5))
1043                                 dev_priv->sm_type = VMW_SM_5;
1044                 }
1045         }
1046
1047         ret = vmw_kms_init(dev_priv);
1048         if (unlikely(ret != 0))
1049                 goto out_no_kms;
1050         vmw_overlay_init(dev_priv);
1051
1052         ret = vmw_request_device(dev_priv);
1053         if (ret)
1054                 goto out_no_fifo;
1055
1056         if (dev_priv->sm_type == VMW_SM_5)
1057                 DRM_INFO("SM5 support available.\n");
1058         if (dev_priv->sm_type == VMW_SM_4_1)
1059                 DRM_INFO("SM4_1 support available.\n");
1060         if (dev_priv->sm_type == VMW_SM_4)
1061                 DRM_INFO("SM4 support available.\n");
1062         DRM_INFO("Running without reservation semaphore\n");
1063
1064         vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)",
1065                         VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
1066                         VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE);
1067
1068         if (dev_priv->enable_fb) {
1069                 vmw_fifo_resource_inc(dev_priv);
1070                 vmw_svga_enable(dev_priv);
1071                 vmw_fb_init(dev_priv);
1072         }
1073
1074         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
1075         register_pm_notifier(&dev_priv->pm_nb);
1076
1077         return 0;
1078
1079 out_no_fifo:
1080         vmw_overlay_close(dev_priv);
1081         vmw_kms_close(dev_priv);
1082 out_no_kms:
1083         if (dev_priv->has_mob)
1084                 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1085         if (dev_priv->has_gmr)
1086                 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1087         vmw_devcaps_destroy(dev_priv);
1088         vmw_vram_manager_fini(dev_priv);
1089 out_no_vram:
1090         ttm_device_fini(&dev_priv->bdev);
1091 out_no_bdev:
1092         vmw_fence_manager_takedown(dev_priv->fman);
1093 out_no_fman:
1094         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1095                 vmw_irq_uninstall(&dev_priv->drm);
1096 out_no_irq:
1097         ttm_object_device_release(&dev_priv->tdev);
1098 out_err0:
1099         for (i = vmw_res_context; i < vmw_res_max; ++i)
1100                 idr_destroy(&dev_priv->res_idr[i]);
1101
1102         if (dev_priv->ctx.staged_bindings)
1103                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1104 out_no_pci_or_version:
1105         pci_release_regions(pdev);
1106         return ret;
1107 }
1108
1109 static void vmw_driver_unload(struct drm_device *dev)
1110 {
1111         struct vmw_private *dev_priv = vmw_priv(dev);
1112         struct pci_dev *pdev = to_pci_dev(dev->dev);
1113         enum vmw_res_type i;
1114
1115         unregister_pm_notifier(&dev_priv->pm_nb);
1116
1117         if (dev_priv->ctx.res_ht_initialized)
1118                 drm_ht_remove(&dev_priv->ctx.res_ht);
1119         vfree(dev_priv->ctx.cmd_bounce);
1120         if (dev_priv->enable_fb) {
1121                 vmw_fb_off(dev_priv);
1122                 vmw_fb_close(dev_priv);
1123                 vmw_fifo_resource_dec(dev_priv);
1124                 vmw_svga_disable(dev_priv);
1125         }
1126
1127         vmw_kms_close(dev_priv);
1128         vmw_overlay_close(dev_priv);
1129
1130         if (dev_priv->has_gmr)
1131                 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1132
1133         vmw_release_device_early(dev_priv);
1134         if (dev_priv->has_mob)
1135                 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1136         vmw_devcaps_destroy(dev_priv);
1137         vmw_vram_manager_fini(dev_priv);
1138         ttm_device_fini(&dev_priv->bdev);
1139         drm_vma_offset_manager_destroy(&dev_priv->vma_manager);
1140         vmw_release_device_late(dev_priv);
1141         vmw_fence_manager_takedown(dev_priv->fman);
1142         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1143                 vmw_irq_uninstall(&dev_priv->drm);
1144
1145         ttm_object_device_release(&dev_priv->tdev);
1146         if (dev_priv->ctx.staged_bindings)
1147                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1148
1149         for (i = vmw_res_context; i < vmw_res_max; ++i)
1150                 idr_destroy(&dev_priv->res_idr[i]);
1151
1152         vmw_mksstat_remove_all(dev_priv);
1153
1154         pci_release_regions(pdev);
1155 }
1156
1157 static void vmw_postclose(struct drm_device *dev,
1158                          struct drm_file *file_priv)
1159 {
1160         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1161
1162         ttm_object_file_release(&vmw_fp->tfile);
1163         kfree(vmw_fp);
1164 }
1165
1166 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1167 {
1168         struct vmw_private *dev_priv = vmw_priv(dev);
1169         struct vmw_fpriv *vmw_fp;
1170         int ret = -ENOMEM;
1171
1172         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1173         if (unlikely(!vmw_fp))
1174                 return ret;
1175
1176         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1177         if (unlikely(vmw_fp->tfile == NULL))
1178                 goto out_no_tfile;
1179
1180         file_priv->driver_priv = vmw_fp;
1181
1182         return 0;
1183
1184 out_no_tfile:
1185         kfree(vmw_fp);
1186         return ret;
1187 }
1188
1189 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1190                               unsigned long arg,
1191                               long (*ioctl_func)(struct file *, unsigned int,
1192                                                  unsigned long))
1193 {
1194         struct drm_file *file_priv = filp->private_data;
1195         struct drm_device *dev = file_priv->minor->dev;
1196         unsigned int nr = DRM_IOCTL_NR(cmd);
1197         unsigned int flags;
1198
1199         /*
1200          * Do extra checking on driver private ioctls.
1201          */
1202
1203         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1204             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1205                 const struct drm_ioctl_desc *ioctl =
1206                         &vmw_ioctls[nr - DRM_COMMAND_BASE];
1207
1208                 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1209                         return ioctl_func(filp, cmd, arg);
1210                 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1211                         if (!drm_is_current_master(file_priv) &&
1212                             !capable(CAP_SYS_ADMIN))
1213                                 return -EACCES;
1214                 }
1215
1216                 if (unlikely(ioctl->cmd != cmd))
1217                         goto out_io_encoding;
1218
1219                 flags = ioctl->flags;
1220         } else if (!drm_ioctl_flags(nr, &flags))
1221                 return -EINVAL;
1222
1223         return ioctl_func(filp, cmd, arg);
1224
1225 out_io_encoding:
1226         DRM_ERROR("Invalid command format, ioctl %d\n",
1227                   nr - DRM_COMMAND_BASE);
1228
1229         return -EINVAL;
1230 }
1231
1232 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1233                                unsigned long arg)
1234 {
1235         return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1236 }
1237
1238 #ifdef CONFIG_COMPAT
1239 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1240                              unsigned long arg)
1241 {
1242         return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1243 }
1244 #endif
1245
1246 static void vmw_master_set(struct drm_device *dev,
1247                            struct drm_file *file_priv,
1248                            bool from_open)
1249 {
1250         /*
1251          * Inform a new master that the layout may have changed while
1252          * it was gone.
1253          */
1254         if (!from_open)
1255                 drm_sysfs_hotplug_event(dev);
1256 }
1257
1258 static void vmw_master_drop(struct drm_device *dev,
1259                             struct drm_file *file_priv)
1260 {
1261         struct vmw_private *dev_priv = vmw_priv(dev);
1262
1263         vmw_kms_legacy_hotspot_clear(dev_priv);
1264         if (!dev_priv->enable_fb)
1265                 vmw_svga_disable(dev_priv);
1266 }
1267
1268 /**
1269  * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1270  *
1271  * @dev_priv: Pointer to device private struct.
1272  * Needs the reservation sem to be held in non-exclusive mode.
1273  */
1274 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1275 {
1276         struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1277
1278         if (!ttm_resource_manager_used(man)) {
1279                 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE);
1280                 ttm_resource_manager_set_used(man, true);
1281         }
1282 }
1283
1284 /**
1285  * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1286  *
1287  * @dev_priv: Pointer to device private struct.
1288  */
1289 void vmw_svga_enable(struct vmw_private *dev_priv)
1290 {
1291         __vmw_svga_enable(dev_priv);
1292 }
1293
1294 /**
1295  * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1296  *
1297  * @dev_priv: Pointer to device private struct.
1298  * Needs the reservation sem to be held in exclusive mode.
1299  * Will not empty VRAM. VRAM must be emptied by caller.
1300  */
1301 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1302 {
1303         struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1304
1305         if (ttm_resource_manager_used(man)) {
1306                 ttm_resource_manager_set_used(man, false);
1307                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1308                           SVGA_REG_ENABLE_HIDE |
1309                           SVGA_REG_ENABLE_ENABLE);
1310         }
1311 }
1312
1313 /**
1314  * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1315  * running.
1316  *
1317  * @dev_priv: Pointer to device private struct.
1318  * Will empty VRAM.
1319  */
1320 void vmw_svga_disable(struct vmw_private *dev_priv)
1321 {
1322         struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1323         /*
1324          * Disabling SVGA will turn off device modesetting capabilities, so
1325          * notify KMS about that so that it doesn't cache atomic state that
1326          * isn't valid anymore, for example crtcs turned on.
1327          * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1328          * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1329          * end up with lock order reversal. Thus, a master may actually perform
1330          * a new modeset just after we call vmw_kms_lost_device() and race with
1331          * vmw_svga_disable(), but that should at worst cause atomic KMS state
1332          * to be inconsistent with the device, causing modesetting problems.
1333          *
1334          */
1335         vmw_kms_lost_device(&dev_priv->drm);
1336         if (ttm_resource_manager_used(man)) {
1337                 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man))
1338                         DRM_ERROR("Failed evicting VRAM buffers.\n");
1339                 ttm_resource_manager_set_used(man, false);
1340                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1341                           SVGA_REG_ENABLE_HIDE |
1342                           SVGA_REG_ENABLE_ENABLE);
1343         }
1344 }
1345
1346 static void vmw_remove(struct pci_dev *pdev)
1347 {
1348         struct drm_device *dev = pci_get_drvdata(pdev);
1349
1350         ttm_mem_global_release(&ttm_mem_glob);
1351         drm_dev_unregister(dev);
1352         vmw_driver_unload(dev);
1353 }
1354
1355 static unsigned long
1356 vmw_get_unmapped_area(struct file *file, unsigned long uaddr,
1357                       unsigned long len, unsigned long pgoff,
1358                       unsigned long flags)
1359 {
1360         struct drm_file *file_priv = file->private_data;
1361         struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev);
1362
1363         return drm_get_unmapped_area(file, uaddr, len, pgoff, flags,
1364                                      &dev_priv->vma_manager);
1365 }
1366
1367 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1368                               void *ptr)
1369 {
1370         struct vmw_private *dev_priv =
1371                 container_of(nb, struct vmw_private, pm_nb);
1372
1373         switch (val) {
1374         case PM_HIBERNATION_PREPARE:
1375                 /*
1376                  * Take the reservation sem in write mode, which will make sure
1377                  * there are no other processes holding a buffer object
1378                  * reservation, meaning we should be able to evict all buffer
1379                  * objects if needed.
1380                  * Once user-space processes have been frozen, we can release
1381                  * the lock again.
1382                  */
1383                 dev_priv->suspend_locked = true;
1384                 break;
1385         case PM_POST_HIBERNATION:
1386         case PM_POST_RESTORE:
1387                 if (READ_ONCE(dev_priv->suspend_locked)) {
1388                         dev_priv->suspend_locked = false;
1389                 }
1390                 break;
1391         default:
1392                 break;
1393         }
1394         return 0;
1395 }
1396
1397 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1398 {
1399         struct drm_device *dev = pci_get_drvdata(pdev);
1400         struct vmw_private *dev_priv = vmw_priv(dev);
1401
1402         if (dev_priv->refuse_hibernation)
1403                 return -EBUSY;
1404
1405         pci_save_state(pdev);
1406         pci_disable_device(pdev);
1407         pci_set_power_state(pdev, PCI_D3hot);
1408         return 0;
1409 }
1410
1411 static int vmw_pci_resume(struct pci_dev *pdev)
1412 {
1413         pci_set_power_state(pdev, PCI_D0);
1414         pci_restore_state(pdev);
1415         return pci_enable_device(pdev);
1416 }
1417
1418 static int vmw_pm_suspend(struct device *kdev)
1419 {
1420         struct pci_dev *pdev = to_pci_dev(kdev);
1421         struct pm_message dummy;
1422
1423         dummy.event = 0;
1424
1425         return vmw_pci_suspend(pdev, dummy);
1426 }
1427
1428 static int vmw_pm_resume(struct device *kdev)
1429 {
1430         struct pci_dev *pdev = to_pci_dev(kdev);
1431
1432         return vmw_pci_resume(pdev);
1433 }
1434
1435 static int vmw_pm_freeze(struct device *kdev)
1436 {
1437         struct pci_dev *pdev = to_pci_dev(kdev);
1438         struct drm_device *dev = pci_get_drvdata(pdev);
1439         struct vmw_private *dev_priv = vmw_priv(dev);
1440         struct ttm_operation_ctx ctx = {
1441                 .interruptible = false,
1442                 .no_wait_gpu = false
1443         };
1444         int ret;
1445
1446         /*
1447          * No user-space processes should be running now.
1448          */
1449         ret = vmw_kms_suspend(&dev_priv->drm);
1450         if (ret) {
1451                 DRM_ERROR("Failed to freeze modesetting.\n");
1452                 return ret;
1453         }
1454         if (dev_priv->enable_fb)
1455                 vmw_fb_off(dev_priv);
1456
1457         vmw_execbuf_release_pinned_bo(dev_priv);
1458         vmw_resource_evict_all(dev_priv);
1459         vmw_release_device_early(dev_priv);
1460         while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0);
1461         if (dev_priv->enable_fb)
1462                 vmw_fifo_resource_dec(dev_priv);
1463         if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1464                 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1465                 if (dev_priv->enable_fb)
1466                         vmw_fifo_resource_inc(dev_priv);
1467                 WARN_ON(vmw_request_device_late(dev_priv));
1468                 dev_priv->suspend_locked = false;
1469                 if (dev_priv->suspend_state)
1470                         vmw_kms_resume(dev);
1471                 if (dev_priv->enable_fb)
1472                         vmw_fb_on(dev_priv);
1473                 return -EBUSY;
1474         }
1475
1476         vmw_fence_fifo_down(dev_priv->fman);
1477         __vmw_svga_disable(dev_priv);
1478
1479         vmw_release_device_late(dev_priv);
1480         return 0;
1481 }
1482
1483 static int vmw_pm_restore(struct device *kdev)
1484 {
1485         struct pci_dev *pdev = to_pci_dev(kdev);
1486         struct drm_device *dev = pci_get_drvdata(pdev);
1487         struct vmw_private *dev_priv = vmw_priv(dev);
1488         int ret;
1489
1490         vmw_detect_version(dev_priv);
1491
1492         if (dev_priv->enable_fb)
1493                 vmw_fifo_resource_inc(dev_priv);
1494
1495         ret = vmw_request_device(dev_priv);
1496         if (ret)
1497                 return ret;
1498
1499         if (dev_priv->enable_fb)
1500                 __vmw_svga_enable(dev_priv);
1501
1502         vmw_fence_fifo_up(dev_priv->fman);
1503         dev_priv->suspend_locked = false;
1504         if (dev_priv->suspend_state)
1505                 vmw_kms_resume(&dev_priv->drm);
1506
1507         if (dev_priv->enable_fb)
1508                 vmw_fb_on(dev_priv);
1509
1510         return 0;
1511 }
1512
1513 static const struct dev_pm_ops vmw_pm_ops = {
1514         .freeze = vmw_pm_freeze,
1515         .thaw = vmw_pm_restore,
1516         .restore = vmw_pm_restore,
1517         .suspend = vmw_pm_suspend,
1518         .resume = vmw_pm_resume,
1519 };
1520
1521 static const struct file_operations vmwgfx_driver_fops = {
1522         .owner = THIS_MODULE,
1523         .open = drm_open,
1524         .release = drm_release,
1525         .unlocked_ioctl = vmw_unlocked_ioctl,
1526         .mmap = vmw_mmap,
1527         .poll = drm_poll,
1528         .read = drm_read,
1529 #if defined(CONFIG_COMPAT)
1530         .compat_ioctl = vmw_compat_ioctl,
1531 #endif
1532         .llseek = noop_llseek,
1533         .get_unmapped_area = vmw_get_unmapped_area,
1534 };
1535
1536 static const struct drm_driver driver = {
1537         .driver_features =
1538         DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC,
1539         .ioctls = vmw_ioctls,
1540         .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1541         .master_set = vmw_master_set,
1542         .master_drop = vmw_master_drop,
1543         .open = vmw_driver_open,
1544         .postclose = vmw_postclose,
1545
1546         .dumb_create = vmw_dumb_create,
1547         .dumb_map_offset = vmw_dumb_map_offset,
1548         .dumb_destroy = vmw_dumb_destroy,
1549
1550         .prime_fd_to_handle = vmw_prime_fd_to_handle,
1551         .prime_handle_to_fd = vmw_prime_handle_to_fd,
1552
1553         .fops = &vmwgfx_driver_fops,
1554         .name = VMWGFX_DRIVER_NAME,
1555         .desc = VMWGFX_DRIVER_DESC,
1556         .date = VMWGFX_DRIVER_DATE,
1557         .major = VMWGFX_DRIVER_MAJOR,
1558         .minor = VMWGFX_DRIVER_MINOR,
1559         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1560 };
1561
1562 static struct pci_driver vmw_pci_driver = {
1563         .name = VMWGFX_DRIVER_NAME,
1564         .id_table = vmw_pci_id_list,
1565         .probe = vmw_probe,
1566         .remove = vmw_remove,
1567         .driver = {
1568                 .pm = &vmw_pm_ops
1569         }
1570 };
1571
1572 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1573 {
1574         struct vmw_private *vmw;
1575         int ret;
1576
1577         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver);
1578         if (ret)
1579                 return ret;
1580
1581         ret = pcim_enable_device(pdev);
1582         if (ret)
1583                 return ret;
1584
1585         vmw = devm_drm_dev_alloc(&pdev->dev, &driver,
1586                                  struct vmw_private, drm);
1587         if (IS_ERR(vmw))
1588                 return PTR_ERR(vmw);
1589
1590         pci_set_drvdata(pdev, &vmw->drm);
1591
1592         ret = ttm_mem_global_init(&ttm_mem_glob, &pdev->dev);
1593         if (ret)
1594                 return ret;
1595
1596         ret = vmw_driver_load(vmw, ent->device);
1597         if (ret)
1598                 return ret;
1599
1600         ret = drm_dev_register(&vmw->drm, 0);
1601         if (ret) {
1602                 vmw_driver_unload(&vmw->drm);
1603                 return ret;
1604         }
1605
1606         return 0;
1607 }
1608
1609 static int __init vmwgfx_init(void)
1610 {
1611         int ret;
1612
1613         if (vgacon_text_force())
1614                 return -EINVAL;
1615
1616         ret = pci_register_driver(&vmw_pci_driver);
1617         if (ret)
1618                 DRM_ERROR("Failed initializing DRM.\n");
1619         return ret;
1620 }
1621
1622 static void __exit vmwgfx_exit(void)
1623 {
1624         pci_unregister_driver(&vmw_pci_driver);
1625 }
1626
1627 module_init(vmwgfx_init);
1628 module_exit(vmwgfx_exit);
1629
1630 MODULE_AUTHOR("VMware Inc. and others");
1631 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1632 MODULE_LICENSE("GPL and additional rights");
1633 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1634                __stringify(VMWGFX_DRIVER_MINOR) "."
1635                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1636                "0");