2 * Copyright (C) 2015 Red Hat, Inc.
6 * Dave Airlie <airlied@redhat.com>
7 * Gerd Hoffmann <kraxel@redhat.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE.
30 #include "virtgpu_drv.h"
31 #include "virtgpu_trace.h"
32 #include <linux/virtio.h>
33 #include <linux/virtio_config.h>
34 #include <linux/virtio_ring.h>
36 #define MAX_INLINE_CMD_SIZE 96
37 #define MAX_INLINE_RESP_SIZE 24
38 #define VBUFFER_SIZE (sizeof(struct virtio_gpu_vbuffer) \
39 + MAX_INLINE_CMD_SIZE \
40 + MAX_INLINE_RESP_SIZE)
42 void virtio_gpu_ctrl_ack(struct virtqueue *vq)
44 struct drm_device *dev = vq->vdev->priv;
45 struct virtio_gpu_device *vgdev = dev->dev_private;
47 schedule_work(&vgdev->ctrlq.dequeue_work);
50 void virtio_gpu_cursor_ack(struct virtqueue *vq)
52 struct drm_device *dev = vq->vdev->priv;
53 struct virtio_gpu_device *vgdev = dev->dev_private;
55 schedule_work(&vgdev->cursorq.dequeue_work);
58 int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev)
60 vgdev->vbufs = kmem_cache_create("virtio-gpu-vbufs",
62 __alignof__(struct virtio_gpu_vbuffer),
69 void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev)
71 kmem_cache_destroy(vgdev->vbufs);
75 static struct virtio_gpu_vbuffer*
76 virtio_gpu_get_vbuf(struct virtio_gpu_device *vgdev,
77 int size, int resp_size, void *resp_buf,
78 virtio_gpu_resp_cb resp_cb)
80 struct virtio_gpu_vbuffer *vbuf;
82 vbuf = kmem_cache_zalloc(vgdev->vbufs, GFP_KERNEL);
84 return ERR_PTR(-ENOMEM);
86 BUG_ON(size > MAX_INLINE_CMD_SIZE);
87 vbuf->buf = (void *)vbuf + sizeof(*vbuf);
90 vbuf->resp_cb = resp_cb;
91 vbuf->resp_size = resp_size;
92 if (resp_size <= MAX_INLINE_RESP_SIZE)
93 vbuf->resp_buf = (void *)vbuf->buf + size;
95 vbuf->resp_buf = resp_buf;
96 BUG_ON(!vbuf->resp_buf);
100 static void *virtio_gpu_alloc_cmd(struct virtio_gpu_device *vgdev,
101 struct virtio_gpu_vbuffer **vbuffer_p,
104 struct virtio_gpu_vbuffer *vbuf;
106 vbuf = virtio_gpu_get_vbuf(vgdev, size,
107 sizeof(struct virtio_gpu_ctrl_hdr),
111 return ERR_CAST(vbuf);
117 static struct virtio_gpu_update_cursor*
118 virtio_gpu_alloc_cursor(struct virtio_gpu_device *vgdev,
119 struct virtio_gpu_vbuffer **vbuffer_p)
121 struct virtio_gpu_vbuffer *vbuf;
123 vbuf = virtio_gpu_get_vbuf
124 (vgdev, sizeof(struct virtio_gpu_update_cursor),
128 return ERR_CAST(vbuf);
131 return (struct virtio_gpu_update_cursor *)vbuf->buf;
134 static void *virtio_gpu_alloc_cmd_resp(struct virtio_gpu_device *vgdev,
135 virtio_gpu_resp_cb cb,
136 struct virtio_gpu_vbuffer **vbuffer_p,
137 int cmd_size, int resp_size,
140 struct virtio_gpu_vbuffer *vbuf;
142 vbuf = virtio_gpu_get_vbuf(vgdev, cmd_size,
143 resp_size, resp_buf, cb);
146 return ERR_CAST(vbuf);
149 return (struct virtio_gpu_command *)vbuf->buf;
152 static void free_vbuf(struct virtio_gpu_device *vgdev,
153 struct virtio_gpu_vbuffer *vbuf)
155 if (vbuf->resp_size > MAX_INLINE_RESP_SIZE)
156 kfree(vbuf->resp_buf);
157 kfree(vbuf->data_buf);
158 kmem_cache_free(vgdev->vbufs, vbuf);
161 static void reclaim_vbufs(struct virtqueue *vq, struct list_head *reclaim_list)
163 struct virtio_gpu_vbuffer *vbuf;
167 while ((vbuf = virtqueue_get_buf(vq, &len))) {
168 list_add_tail(&vbuf->list, reclaim_list);
172 DRM_DEBUG("Huh? zero vbufs reclaimed");
175 void virtio_gpu_dequeue_ctrl_func(struct work_struct *work)
177 struct virtio_gpu_device *vgdev =
178 container_of(work, struct virtio_gpu_device,
180 struct list_head reclaim_list;
181 struct virtio_gpu_vbuffer *entry, *tmp;
182 struct virtio_gpu_ctrl_hdr *resp;
185 INIT_LIST_HEAD(&reclaim_list);
186 spin_lock(&vgdev->ctrlq.qlock);
188 virtqueue_disable_cb(vgdev->ctrlq.vq);
189 reclaim_vbufs(vgdev->ctrlq.vq, &reclaim_list);
191 } while (!virtqueue_enable_cb(vgdev->ctrlq.vq));
192 spin_unlock(&vgdev->ctrlq.qlock);
194 list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
195 resp = (struct virtio_gpu_ctrl_hdr *)entry->resp_buf;
197 trace_virtio_gpu_cmd_response(vgdev->ctrlq.vq, resp);
199 if (resp->type != cpu_to_le32(VIRTIO_GPU_RESP_OK_NODATA)) {
200 if (resp->type >= cpu_to_le32(VIRTIO_GPU_RESP_ERR_UNSPEC)) {
201 struct virtio_gpu_ctrl_hdr *cmd;
202 cmd = (struct virtio_gpu_ctrl_hdr *)entry->buf;
203 DRM_ERROR("response 0x%x (command 0x%x)\n",
204 le32_to_cpu(resp->type),
205 le32_to_cpu(cmd->type));
207 DRM_DEBUG("response 0x%x\n", le32_to_cpu(resp->type));
209 if (resp->flags & cpu_to_le32(VIRTIO_GPU_FLAG_FENCE)) {
210 u64 f = le64_to_cpu(resp->fence_id);
213 DRM_ERROR("%s: Oops: fence %llx -> %llx\n",
214 __func__, fence_id, f);
220 entry->resp_cb(vgdev, entry);
222 list_del(&entry->list);
223 free_vbuf(vgdev, entry);
225 wake_up(&vgdev->ctrlq.ack_queue);
228 virtio_gpu_fence_event_process(vgdev, fence_id);
231 void virtio_gpu_dequeue_cursor_func(struct work_struct *work)
233 struct virtio_gpu_device *vgdev =
234 container_of(work, struct virtio_gpu_device,
235 cursorq.dequeue_work);
236 struct list_head reclaim_list;
237 struct virtio_gpu_vbuffer *entry, *tmp;
239 INIT_LIST_HEAD(&reclaim_list);
240 spin_lock(&vgdev->cursorq.qlock);
242 virtqueue_disable_cb(vgdev->cursorq.vq);
243 reclaim_vbufs(vgdev->cursorq.vq, &reclaim_list);
244 } while (!virtqueue_enable_cb(vgdev->cursorq.vq));
245 spin_unlock(&vgdev->cursorq.qlock);
247 list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
248 list_del(&entry->list);
249 free_vbuf(vgdev, entry);
251 wake_up(&vgdev->cursorq.ack_queue);
254 static int virtio_gpu_queue_ctrl_buffer_locked(struct virtio_gpu_device *vgdev,
255 struct virtio_gpu_vbuffer *vbuf)
256 __releases(&vgdev->ctrlq.qlock)
257 __acquires(&vgdev->ctrlq.qlock)
259 struct virtqueue *vq = vgdev->ctrlq.vq;
260 struct scatterlist *sgs[3], vcmd, vout, vresp;
261 int outcnt = 0, incnt = 0;
264 if (!vgdev->vqs_ready)
267 sg_init_one(&vcmd, vbuf->buf, vbuf->size);
268 sgs[outcnt + incnt] = &vcmd;
271 if (vbuf->data_size) {
272 sg_init_one(&vout, vbuf->data_buf, vbuf->data_size);
273 sgs[outcnt + incnt] = &vout;
277 if (vbuf->resp_size) {
278 sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size);
279 sgs[outcnt + incnt] = &vresp;
284 ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC);
285 if (ret == -ENOSPC) {
286 spin_unlock(&vgdev->ctrlq.qlock);
287 wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= outcnt + incnt);
288 spin_lock(&vgdev->ctrlq.qlock);
291 trace_virtio_gpu_cmd_queue(vq,
292 (struct virtio_gpu_ctrl_hdr *)vbuf->buf);
302 static int virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev,
303 struct virtio_gpu_vbuffer *vbuf)
307 spin_lock(&vgdev->ctrlq.qlock);
308 rc = virtio_gpu_queue_ctrl_buffer_locked(vgdev, vbuf);
309 spin_unlock(&vgdev->ctrlq.qlock);
313 static int virtio_gpu_queue_fenced_ctrl_buffer(struct virtio_gpu_device *vgdev,
314 struct virtio_gpu_vbuffer *vbuf,
315 struct virtio_gpu_ctrl_hdr *hdr,
316 struct virtio_gpu_fence *fence)
318 struct virtqueue *vq = vgdev->ctrlq.vq;
322 spin_lock(&vgdev->ctrlq.qlock);
325 * Make sure we have enouth space in the virtqueue. If not
326 * wait here until we have.
328 * Without that virtio_gpu_queue_ctrl_buffer_nolock might have
329 * to wait for free space, which can result in fence ids being
330 * submitted out-of-order.
332 if (vq->num_free < 3) {
333 spin_unlock(&vgdev->ctrlq.qlock);
334 wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= 3);
339 virtio_gpu_fence_emit(vgdev, hdr, fence);
340 rc = virtio_gpu_queue_ctrl_buffer_locked(vgdev, vbuf);
341 spin_unlock(&vgdev->ctrlq.qlock);
345 static int virtio_gpu_queue_cursor(struct virtio_gpu_device *vgdev,
346 struct virtio_gpu_vbuffer *vbuf)
348 struct virtqueue *vq = vgdev->cursorq.vq;
349 struct scatterlist *sgs[1], ccmd;
353 if (!vgdev->vqs_ready)
356 sg_init_one(&ccmd, vbuf->buf, vbuf->size);
360 spin_lock(&vgdev->cursorq.qlock);
362 ret = virtqueue_add_sgs(vq, sgs, outcnt, 0, vbuf, GFP_ATOMIC);
363 if (ret == -ENOSPC) {
364 spin_unlock(&vgdev->cursorq.qlock);
365 wait_event(vgdev->cursorq.ack_queue, vq->num_free >= outcnt);
366 spin_lock(&vgdev->cursorq.qlock);
369 trace_virtio_gpu_cmd_queue(vq,
370 (struct virtio_gpu_ctrl_hdr *)vbuf->buf);
375 spin_unlock(&vgdev->cursorq.qlock);
382 /* just create gem objects for userspace and long lived objects,
383 * just use dma_alloced pages for the queue objects?
386 /* create a basic resource */
387 void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
388 struct virtio_gpu_object *bo,
389 struct virtio_gpu_object_params *params,
390 struct virtio_gpu_fence *fence)
392 struct virtio_gpu_resource_create_2d *cmd_p;
393 struct virtio_gpu_vbuffer *vbuf;
395 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
396 memset(cmd_p, 0, sizeof(*cmd_p));
398 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_2D);
399 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
400 cmd_p->format = cpu_to_le32(params->format);
401 cmd_p->width = cpu_to_le32(params->width);
402 cmd_p->height = cpu_to_le32(params->height);
404 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
408 void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
409 uint32_t resource_id)
411 struct virtio_gpu_resource_unref *cmd_p;
412 struct virtio_gpu_vbuffer *vbuf;
414 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
415 memset(cmd_p, 0, sizeof(*cmd_p));
417 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_UNREF);
418 cmd_p->resource_id = cpu_to_le32(resource_id);
420 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
423 static void virtio_gpu_cmd_resource_inval_backing(struct virtio_gpu_device *vgdev,
424 uint32_t resource_id,
425 struct virtio_gpu_fence *fence)
427 struct virtio_gpu_resource_detach_backing *cmd_p;
428 struct virtio_gpu_vbuffer *vbuf;
430 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
431 memset(cmd_p, 0, sizeof(*cmd_p));
433 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING);
434 cmd_p->resource_id = cpu_to_le32(resource_id);
436 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
439 void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
440 uint32_t scanout_id, uint32_t resource_id,
441 uint32_t width, uint32_t height,
442 uint32_t x, uint32_t y)
444 struct virtio_gpu_set_scanout *cmd_p;
445 struct virtio_gpu_vbuffer *vbuf;
447 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
448 memset(cmd_p, 0, sizeof(*cmd_p));
450 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SET_SCANOUT);
451 cmd_p->resource_id = cpu_to_le32(resource_id);
452 cmd_p->scanout_id = cpu_to_le32(scanout_id);
453 cmd_p->r.width = cpu_to_le32(width);
454 cmd_p->r.height = cpu_to_le32(height);
455 cmd_p->r.x = cpu_to_le32(x);
456 cmd_p->r.y = cpu_to_le32(y);
458 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
461 void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
462 uint32_t resource_id,
463 uint32_t x, uint32_t y,
464 uint32_t width, uint32_t height)
466 struct virtio_gpu_resource_flush *cmd_p;
467 struct virtio_gpu_vbuffer *vbuf;
469 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
470 memset(cmd_p, 0, sizeof(*cmd_p));
472 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_FLUSH);
473 cmd_p->resource_id = cpu_to_le32(resource_id);
474 cmd_p->r.width = cpu_to_le32(width);
475 cmd_p->r.height = cpu_to_le32(height);
476 cmd_p->r.x = cpu_to_le32(x);
477 cmd_p->r.y = cpu_to_le32(y);
479 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
482 void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
483 struct virtio_gpu_object *bo,
485 __le32 width, __le32 height,
487 struct virtio_gpu_fence *fence)
489 struct virtio_gpu_transfer_to_host_2d *cmd_p;
490 struct virtio_gpu_vbuffer *vbuf;
491 bool use_dma_api = !virtio_has_iommu_quirk(vgdev->vdev);
494 dma_sync_sg_for_device(vgdev->vdev->dev.parent,
495 bo->pages->sgl, bo->pages->nents,
498 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
499 memset(cmd_p, 0, sizeof(*cmd_p));
501 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D);
502 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
503 cmd_p->offset = cpu_to_le64(offset);
504 cmd_p->r.width = width;
505 cmd_p->r.height = height;
509 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
513 virtio_gpu_cmd_resource_attach_backing(struct virtio_gpu_device *vgdev,
514 uint32_t resource_id,
515 struct virtio_gpu_mem_entry *ents,
517 struct virtio_gpu_fence *fence)
519 struct virtio_gpu_resource_attach_backing *cmd_p;
520 struct virtio_gpu_vbuffer *vbuf;
522 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
523 memset(cmd_p, 0, sizeof(*cmd_p));
525 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING);
526 cmd_p->resource_id = cpu_to_le32(resource_id);
527 cmd_p->nr_entries = cpu_to_le32(nents);
529 vbuf->data_buf = ents;
530 vbuf->data_size = sizeof(*ents) * nents;
532 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
535 static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev,
536 struct virtio_gpu_vbuffer *vbuf)
538 struct virtio_gpu_resp_display_info *resp =
539 (struct virtio_gpu_resp_display_info *)vbuf->resp_buf;
542 spin_lock(&vgdev->display_info_lock);
543 for (i = 0; i < vgdev->num_scanouts; i++) {
544 vgdev->outputs[i].info = resp->pmodes[i];
545 if (resp->pmodes[i].enabled) {
546 DRM_DEBUG("output %d: %dx%d+%d+%d", i,
547 le32_to_cpu(resp->pmodes[i].r.width),
548 le32_to_cpu(resp->pmodes[i].r.height),
549 le32_to_cpu(resp->pmodes[i].r.x),
550 le32_to_cpu(resp->pmodes[i].r.y));
552 DRM_DEBUG("output %d: disabled", i);
556 vgdev->display_info_pending = false;
557 spin_unlock(&vgdev->display_info_lock);
558 wake_up(&vgdev->resp_wq);
560 if (!drm_helper_hpd_irq_event(vgdev->ddev))
561 drm_kms_helper_hotplug_event(vgdev->ddev);
564 static void virtio_gpu_cmd_get_capset_info_cb(struct virtio_gpu_device *vgdev,
565 struct virtio_gpu_vbuffer *vbuf)
567 struct virtio_gpu_get_capset_info *cmd =
568 (struct virtio_gpu_get_capset_info *)vbuf->buf;
569 struct virtio_gpu_resp_capset_info *resp =
570 (struct virtio_gpu_resp_capset_info *)vbuf->resp_buf;
571 int i = le32_to_cpu(cmd->capset_index);
573 spin_lock(&vgdev->display_info_lock);
574 vgdev->capsets[i].id = le32_to_cpu(resp->capset_id);
575 vgdev->capsets[i].max_version = le32_to_cpu(resp->capset_max_version);
576 vgdev->capsets[i].max_size = le32_to_cpu(resp->capset_max_size);
577 spin_unlock(&vgdev->display_info_lock);
578 wake_up(&vgdev->resp_wq);
581 static void virtio_gpu_cmd_capset_cb(struct virtio_gpu_device *vgdev,
582 struct virtio_gpu_vbuffer *vbuf)
584 struct virtio_gpu_get_capset *cmd =
585 (struct virtio_gpu_get_capset *)vbuf->buf;
586 struct virtio_gpu_resp_capset *resp =
587 (struct virtio_gpu_resp_capset *)vbuf->resp_buf;
588 struct virtio_gpu_drv_cap_cache *cache_ent;
590 spin_lock(&vgdev->display_info_lock);
591 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
592 if (cache_ent->version == le32_to_cpu(cmd->capset_version) &&
593 cache_ent->id == le32_to_cpu(cmd->capset_id)) {
594 memcpy(cache_ent->caps_cache, resp->capset_data,
596 /* Copy must occur before is_valid is signalled. */
598 atomic_set(&cache_ent->is_valid, 1);
602 spin_unlock(&vgdev->display_info_lock);
603 wake_up_all(&vgdev->resp_wq);
606 static int virtio_get_edid_block(void *data, u8 *buf,
607 unsigned int block, size_t len)
609 struct virtio_gpu_resp_edid *resp = data;
610 size_t start = block * EDID_LENGTH;
612 if (start + len > le32_to_cpu(resp->size))
614 memcpy(buf, resp->edid + start, len);
618 static void virtio_gpu_cmd_get_edid_cb(struct virtio_gpu_device *vgdev,
619 struct virtio_gpu_vbuffer *vbuf)
621 struct virtio_gpu_cmd_get_edid *cmd =
622 (struct virtio_gpu_cmd_get_edid *)vbuf->buf;
623 struct virtio_gpu_resp_edid *resp =
624 (struct virtio_gpu_resp_edid *)vbuf->resp_buf;
625 uint32_t scanout = le32_to_cpu(cmd->scanout);
626 struct virtio_gpu_output *output;
627 struct edid *new_edid, *old_edid;
629 if (scanout >= vgdev->num_scanouts)
631 output = vgdev->outputs + scanout;
633 new_edid = drm_do_get_edid(&output->conn, virtio_get_edid_block, resp);
634 drm_connector_update_edid_property(&output->conn, new_edid);
636 spin_lock(&vgdev->display_info_lock);
637 old_edid = output->edid;
638 output->edid = new_edid;
639 spin_unlock(&vgdev->display_info_lock);
642 wake_up(&vgdev->resp_wq);
645 int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev)
647 struct virtio_gpu_ctrl_hdr *cmd_p;
648 struct virtio_gpu_vbuffer *vbuf;
651 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_display_info),
656 cmd_p = virtio_gpu_alloc_cmd_resp
657 (vgdev, &virtio_gpu_cmd_get_display_info_cb, &vbuf,
658 sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_display_info),
660 memset(cmd_p, 0, sizeof(*cmd_p));
662 vgdev->display_info_pending = true;
663 cmd_p->type = cpu_to_le32(VIRTIO_GPU_CMD_GET_DISPLAY_INFO);
664 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
668 int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx)
670 struct virtio_gpu_get_capset_info *cmd_p;
671 struct virtio_gpu_vbuffer *vbuf;
674 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset_info),
679 cmd_p = virtio_gpu_alloc_cmd_resp
680 (vgdev, &virtio_gpu_cmd_get_capset_info_cb, &vbuf,
681 sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_capset_info),
683 memset(cmd_p, 0, sizeof(*cmd_p));
685 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET_INFO);
686 cmd_p->capset_index = cpu_to_le32(idx);
687 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
691 int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
692 int idx, int version,
693 struct virtio_gpu_drv_cap_cache **cache_p)
695 struct virtio_gpu_get_capset *cmd_p;
696 struct virtio_gpu_vbuffer *vbuf;
698 struct virtio_gpu_drv_cap_cache *cache_ent;
699 struct virtio_gpu_drv_cap_cache *search_ent;
704 if (idx >= vgdev->num_capsets)
707 if (version > vgdev->capsets[idx].max_version)
710 cache_ent = kzalloc(sizeof(*cache_ent), GFP_KERNEL);
714 max_size = vgdev->capsets[idx].max_size;
715 cache_ent->caps_cache = kmalloc(max_size, GFP_KERNEL);
716 if (!cache_ent->caps_cache) {
721 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset) + max_size,
724 kfree(cache_ent->caps_cache);
729 cache_ent->version = version;
730 cache_ent->id = vgdev->capsets[idx].id;
731 atomic_set(&cache_ent->is_valid, 0);
732 cache_ent->size = max_size;
733 spin_lock(&vgdev->display_info_lock);
734 /* Search while under lock in case it was added by another task. */
735 list_for_each_entry(search_ent, &vgdev->cap_cache, head) {
736 if (search_ent->id == vgdev->capsets[idx].id &&
737 search_ent->version == version) {
738 *cache_p = search_ent;
743 list_add_tail(&cache_ent->head, &vgdev->cap_cache);
744 spin_unlock(&vgdev->display_info_lock);
747 /* Entry was found, so free everything that was just created. */
749 kfree(cache_ent->caps_cache);
754 cmd_p = virtio_gpu_alloc_cmd_resp
755 (vgdev, &virtio_gpu_cmd_capset_cb, &vbuf, sizeof(*cmd_p),
756 sizeof(struct virtio_gpu_resp_capset) + max_size,
758 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET);
759 cmd_p->capset_id = cpu_to_le32(vgdev->capsets[idx].id);
760 cmd_p->capset_version = cpu_to_le32(version);
761 *cache_p = cache_ent;
762 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
767 int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev)
769 struct virtio_gpu_cmd_get_edid *cmd_p;
770 struct virtio_gpu_vbuffer *vbuf;
774 if (WARN_ON(!vgdev->has_edid))
777 for (scanout = 0; scanout < vgdev->num_scanouts; scanout++) {
778 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_edid),
783 cmd_p = virtio_gpu_alloc_cmd_resp
784 (vgdev, &virtio_gpu_cmd_get_edid_cb, &vbuf,
785 sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_edid),
787 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_EDID);
788 cmd_p->scanout = cpu_to_le32(scanout);
789 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
795 void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
796 uint32_t nlen, const char *name)
798 struct virtio_gpu_ctx_create *cmd_p;
799 struct virtio_gpu_vbuffer *vbuf;
801 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
802 memset(cmd_p, 0, sizeof(*cmd_p));
804 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_CREATE);
805 cmd_p->hdr.ctx_id = cpu_to_le32(id);
806 cmd_p->nlen = cpu_to_le32(nlen);
807 strncpy(cmd_p->debug_name, name, sizeof(cmd_p->debug_name) - 1);
808 cmd_p->debug_name[sizeof(cmd_p->debug_name) - 1] = 0;
809 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
812 void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
815 struct virtio_gpu_ctx_destroy *cmd_p;
816 struct virtio_gpu_vbuffer *vbuf;
818 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
819 memset(cmd_p, 0, sizeof(*cmd_p));
821 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DESTROY);
822 cmd_p->hdr.ctx_id = cpu_to_le32(id);
823 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
826 void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
828 uint32_t resource_id)
830 struct virtio_gpu_ctx_resource *cmd_p;
831 struct virtio_gpu_vbuffer *vbuf;
833 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
834 memset(cmd_p, 0, sizeof(*cmd_p));
836 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE);
837 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
838 cmd_p->resource_id = cpu_to_le32(resource_id);
839 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
843 void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
845 uint32_t resource_id)
847 struct virtio_gpu_ctx_resource *cmd_p;
848 struct virtio_gpu_vbuffer *vbuf;
850 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
851 memset(cmd_p, 0, sizeof(*cmd_p));
853 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE);
854 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
855 cmd_p->resource_id = cpu_to_le32(resource_id);
856 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
860 virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
861 struct virtio_gpu_object *bo,
862 struct virtio_gpu_object_params *params,
863 struct virtio_gpu_fence *fence)
865 struct virtio_gpu_resource_create_3d *cmd_p;
866 struct virtio_gpu_vbuffer *vbuf;
868 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
869 memset(cmd_p, 0, sizeof(*cmd_p));
871 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_3D);
872 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
873 cmd_p->format = cpu_to_le32(params->format);
874 cmd_p->width = cpu_to_le32(params->width);
875 cmd_p->height = cpu_to_le32(params->height);
877 cmd_p->target = cpu_to_le32(params->target);
878 cmd_p->bind = cpu_to_le32(params->bind);
879 cmd_p->depth = cpu_to_le32(params->depth);
880 cmd_p->array_size = cpu_to_le32(params->array_size);
881 cmd_p->last_level = cpu_to_le32(params->last_level);
882 cmd_p->nr_samples = cpu_to_le32(params->nr_samples);
883 cmd_p->flags = cpu_to_le32(params->flags);
885 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
889 void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
890 struct virtio_gpu_object *bo,
892 uint64_t offset, uint32_t level,
893 struct virtio_gpu_box *box,
894 struct virtio_gpu_fence *fence)
896 struct virtio_gpu_transfer_host_3d *cmd_p;
897 struct virtio_gpu_vbuffer *vbuf;
898 bool use_dma_api = !virtio_has_iommu_quirk(vgdev->vdev);
901 dma_sync_sg_for_device(vgdev->vdev->dev.parent,
902 bo->pages->sgl, bo->pages->nents,
905 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
906 memset(cmd_p, 0, sizeof(*cmd_p));
908 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D);
909 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
910 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
912 cmd_p->offset = cpu_to_le64(offset);
913 cmd_p->level = cpu_to_le32(level);
915 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
918 void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
919 uint32_t resource_id, uint32_t ctx_id,
920 uint64_t offset, uint32_t level,
921 struct virtio_gpu_box *box,
922 struct virtio_gpu_fence *fence)
924 struct virtio_gpu_transfer_host_3d *cmd_p;
925 struct virtio_gpu_vbuffer *vbuf;
927 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
928 memset(cmd_p, 0, sizeof(*cmd_p));
930 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D);
931 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
932 cmd_p->resource_id = cpu_to_le32(resource_id);
934 cmd_p->offset = cpu_to_le64(offset);
935 cmd_p->level = cpu_to_le32(level);
937 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
940 void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
941 void *data, uint32_t data_size,
942 uint32_t ctx_id, struct virtio_gpu_fence *fence)
944 struct virtio_gpu_cmd_submit *cmd_p;
945 struct virtio_gpu_vbuffer *vbuf;
947 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
948 memset(cmd_p, 0, sizeof(*cmd_p));
950 vbuf->data_buf = data;
951 vbuf->data_size = data_size;
953 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SUBMIT_3D);
954 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
955 cmd_p->size = cpu_to_le32(data_size);
957 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence);
960 int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
961 struct virtio_gpu_object *obj,
962 struct virtio_gpu_fence *fence)
964 bool use_dma_api = !virtio_has_iommu_quirk(vgdev->vdev);
965 struct virtio_gpu_mem_entry *ents;
966 struct scatterlist *sg;
969 if (WARN_ON_ONCE(!obj->created))
975 ret = virtio_gpu_object_get_sg_table(vgdev, obj);
981 obj->mapped = dma_map_sg(vgdev->vdev->dev.parent,
982 obj->pages->sgl, obj->pages->nents,
986 nents = obj->pages->nents;
989 /* gets freed when the ring has consumed it */
990 ents = kmalloc_array(nents, sizeof(struct virtio_gpu_mem_entry),
993 DRM_ERROR("failed to allocate ent list\n");
997 for_each_sg(obj->pages->sgl, sg, nents, si) {
998 ents[si].addr = cpu_to_le64(use_dma_api
1001 ents[si].length = cpu_to_le32(sg->length);
1002 ents[si].padding = 0;
1005 virtio_gpu_cmd_resource_attach_backing(vgdev, obj->hw_res_handle,
1011 void virtio_gpu_object_detach(struct virtio_gpu_device *vgdev,
1012 struct virtio_gpu_object *obj)
1014 bool use_dma_api = !virtio_has_iommu_quirk(vgdev->vdev);
1016 if (use_dma_api && obj->mapped) {
1017 struct virtio_gpu_fence *fence = virtio_gpu_fence_alloc(vgdev);
1018 /* detach backing and wait for the host process it ... */
1019 virtio_gpu_cmd_resource_inval_backing(vgdev, obj->hw_res_handle, fence);
1020 dma_fence_wait(&fence->f, true);
1021 dma_fence_put(&fence->f);
1023 /* ... then tear down iommu mappings */
1024 dma_unmap_sg(vgdev->vdev->dev.parent,
1025 obj->pages->sgl, obj->mapped,
1029 virtio_gpu_cmd_resource_inval_backing(vgdev, obj->hw_res_handle, NULL);
1033 void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
1034 struct virtio_gpu_output *output)
1036 struct virtio_gpu_vbuffer *vbuf;
1037 struct virtio_gpu_update_cursor *cur_p;
1039 output->cursor.pos.scanout_id = cpu_to_le32(output->index);
1040 cur_p = virtio_gpu_alloc_cursor(vgdev, &vbuf);
1041 memcpy(cur_p, &output->cursor, sizeof(output->cursor));
1042 virtio_gpu_queue_cursor(vgdev, vbuf);