2 * Copyright (C) 2015 Red Hat, Inc.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 #include <linux/file.h>
29 #include <linux/sync_file.h>
31 #include <drm/drm_file.h>
32 #include <drm/ttm/ttm_execbuf_util.h>
33 #include <drm/virtgpu_drm.h>
35 #include "virtgpu_drv.h"
37 static void convert_to_hw_box(struct virtio_gpu_box *dst,
38 const struct drm_virtgpu_3d_box *src)
40 dst->x = cpu_to_le32(src->x);
41 dst->y = cpu_to_le32(src->y);
42 dst->z = cpu_to_le32(src->z);
43 dst->w = cpu_to_le32(src->w);
44 dst->h = cpu_to_le32(src->h);
45 dst->d = cpu_to_le32(src->d);
48 static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
49 struct drm_file *file_priv)
51 struct virtio_gpu_device *vgdev = dev->dev_private;
52 struct drm_virtgpu_map *virtio_gpu_map = data;
54 return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev,
55 virtio_gpu_map->handle,
56 &virtio_gpu_map->offset);
59 int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket,
60 struct list_head *head)
62 struct ttm_operation_ctx ctx = { false, false };
63 struct ttm_validate_buffer *buf;
64 struct ttm_buffer_object *bo;
65 struct virtio_gpu_object *qobj;
68 ret = ttm_eu_reserve_buffers(ticket, head, true, NULL, true);
72 list_for_each_entry(buf, head, head) {
74 qobj = container_of(bo, struct virtio_gpu_object, tbo);
75 ret = ttm_bo_validate(bo, &qobj->placement, &ctx);
77 ttm_eu_backoff_reservation(ticket, head);
84 void virtio_gpu_unref_list(struct list_head *head)
86 struct ttm_validate_buffer *buf;
87 struct ttm_buffer_object *bo;
88 struct virtio_gpu_object *qobj;
90 list_for_each_entry(buf, head, head) {
92 qobj = container_of(bo, struct virtio_gpu_object, tbo);
94 drm_gem_object_put_unlocked(&qobj->gem_base);
99 * Usage of execbuffer:
100 * Relocations need to take into account the full VIRTIO_GPUDrawable size.
101 * However, the command as passed from user space must *not* contain the initial
102 * VIRTIO_GPUReleaseInfo struct (first XXX bytes)
104 static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
105 struct drm_file *drm_file)
107 struct drm_virtgpu_execbuffer *exbuf = data;
108 struct virtio_gpu_device *vgdev = dev->dev_private;
109 struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv;
110 struct drm_gem_object *gobj;
111 struct virtio_gpu_fence *out_fence;
112 struct virtio_gpu_object *qobj;
114 uint32_t *bo_handles = NULL;
115 void __user *user_bo_handles = NULL;
116 struct list_head validate_list;
117 struct ttm_validate_buffer *buflist = NULL;
119 struct ww_acquire_ctx ticket;
120 struct sync_file *sync_file;
121 int in_fence_fd = exbuf->fence_fd;
122 int out_fence_fd = -1;
125 if (vgdev->has_virgl_3d == false)
128 if ((exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS))
131 exbuf->fence_fd = -1;
133 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) {
134 struct dma_fence *in_fence;
136 in_fence = sync_file_get_fence(in_fence_fd);
142 * Wait if the fence is from a foreign context, or if the fence
143 * array contains any fence from a foreign context.
146 if (!dma_fence_match_context(in_fence, vgdev->fence_drv.context))
147 ret = dma_fence_wait(in_fence, true);
149 dma_fence_put(in_fence);
154 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) {
155 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
156 if (out_fence_fd < 0)
160 INIT_LIST_HEAD(&validate_list);
161 if (exbuf->num_bo_handles) {
163 bo_handles = kvmalloc_array(exbuf->num_bo_handles,
164 sizeof(uint32_t), GFP_KERNEL);
165 buflist = kvmalloc_array(exbuf->num_bo_handles,
166 sizeof(struct ttm_validate_buffer),
167 GFP_KERNEL | __GFP_ZERO);
168 if (!bo_handles || !buflist) {
173 user_bo_handles = u64_to_user_ptr(exbuf->bo_handles);
174 if (copy_from_user(bo_handles, user_bo_handles,
175 exbuf->num_bo_handles * sizeof(uint32_t))) {
180 for (i = 0; i < exbuf->num_bo_handles; i++) {
181 gobj = drm_gem_object_lookup(drm_file, bo_handles[i]);
187 qobj = gem_to_virtio_gpu_obj(gobj);
188 buflist[i].bo = &qobj->tbo;
190 list_add(&buflist[i].head, &validate_list);
196 ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
200 buf = memdup_user(u64_to_user_ptr(exbuf->command), exbuf->size);
206 out_fence = virtio_gpu_fence_alloc(vgdev);
212 if (out_fence_fd >= 0) {
213 sync_file = sync_file_create(&out_fence->f);
215 dma_fence_put(&out_fence->f);
220 exbuf->fence_fd = out_fence_fd;
221 fd_install(out_fence_fd, sync_file->file);
224 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
225 vfpriv->ctx_id, out_fence);
227 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &out_fence->f);
229 /* fence the command bo */
230 virtio_gpu_unref_list(&validate_list);
237 ttm_eu_backoff_reservation(&ticket, &validate_list);
239 virtio_gpu_unref_list(&validate_list);
244 if (out_fence_fd >= 0)
245 put_unused_fd(out_fence_fd);
250 static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
251 struct drm_file *file_priv)
253 struct virtio_gpu_device *vgdev = dev->dev_private;
254 struct drm_virtgpu_getparam *param = data;
257 switch (param->param) {
258 case VIRTGPU_PARAM_3D_FEATURES:
259 value = vgdev->has_virgl_3d == true ? 1 : 0;
261 case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
267 if (copy_to_user(u64_to_user_ptr(param->value), &value, sizeof(int)))
273 static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
274 struct drm_file *file_priv)
276 struct virtio_gpu_device *vgdev = dev->dev_private;
277 struct drm_virtgpu_resource_create *rc = data;
278 struct virtio_gpu_fence *fence;
280 struct virtio_gpu_object *qobj;
281 struct drm_gem_object *obj;
283 struct virtio_gpu_object_params params = { 0 };
285 if (vgdev->has_virgl_3d == false) {
288 if (rc->nr_samples > 1)
290 if (rc->last_level > 1)
294 if (rc->array_size > 1)
298 params.format = rc->format;
299 params.width = rc->width;
300 params.height = rc->height;
301 params.size = rc->size;
302 if (vgdev->has_virgl_3d) {
304 params.target = rc->target;
305 params.bind = rc->bind;
306 params.depth = rc->depth;
307 params.array_size = rc->array_size;
308 params.last_level = rc->last_level;
309 params.nr_samples = rc->nr_samples;
310 params.flags = rc->flags;
312 /* allocate a single page size object */
313 if (params.size == 0)
314 params.size = PAGE_SIZE;
316 fence = virtio_gpu_fence_alloc(vgdev);
319 qobj = virtio_gpu_alloc_object(dev, ¶ms, fence);
320 dma_fence_put(&fence->f);
322 return PTR_ERR(qobj);
323 obj = &qobj->gem_base;
325 ret = drm_gem_handle_create(file_priv, obj, &handle);
327 drm_gem_object_release(obj);
330 drm_gem_object_put_unlocked(obj);
332 rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */
333 rc->bo_handle = handle;
337 static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
338 struct drm_file *file_priv)
340 struct drm_virtgpu_resource_info *ri = data;
341 struct drm_gem_object *gobj = NULL;
342 struct virtio_gpu_object *qobj = NULL;
344 gobj = drm_gem_object_lookup(file_priv, ri->bo_handle);
348 qobj = gem_to_virtio_gpu_obj(gobj);
350 ri->size = qobj->gem_base.size;
351 ri->res_handle = qobj->hw_res_handle;
352 drm_gem_object_put_unlocked(gobj);
356 static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
358 struct drm_file *file)
360 struct virtio_gpu_device *vgdev = dev->dev_private;
361 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
362 struct drm_virtgpu_3d_transfer_from_host *args = data;
363 struct ttm_operation_ctx ctx = { true, false };
364 struct drm_gem_object *gobj = NULL;
365 struct virtio_gpu_object *qobj = NULL;
366 struct virtio_gpu_fence *fence;
368 u32 offset = args->offset;
369 struct virtio_gpu_box box;
371 if (vgdev->has_virgl_3d == false)
374 gobj = drm_gem_object_lookup(file, args->bo_handle);
378 qobj = gem_to_virtio_gpu_obj(gobj);
380 ret = virtio_gpu_object_reserve(qobj, false);
384 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
388 convert_to_hw_box(&box, &args->box);
390 fence = virtio_gpu_fence_alloc(vgdev);
395 virtio_gpu_cmd_transfer_from_host_3d
396 (vgdev, qobj->hw_res_handle,
397 vfpriv->ctx_id, offset, args->level,
399 dma_resv_add_excl_fence(qobj->tbo.base.resv,
402 dma_fence_put(&fence->f);
404 virtio_gpu_object_unreserve(qobj);
406 drm_gem_object_put_unlocked(gobj);
410 static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
411 struct drm_file *file)
413 struct virtio_gpu_device *vgdev = dev->dev_private;
414 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
415 struct drm_virtgpu_3d_transfer_to_host *args = data;
416 struct ttm_operation_ctx ctx = { true, false };
417 struct drm_gem_object *gobj = NULL;
418 struct virtio_gpu_object *qobj = NULL;
419 struct virtio_gpu_fence *fence;
420 struct virtio_gpu_box box;
422 u32 offset = args->offset;
424 gobj = drm_gem_object_lookup(file, args->bo_handle);
428 qobj = gem_to_virtio_gpu_obj(gobj);
430 ret = virtio_gpu_object_reserve(qobj, false);
434 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
438 convert_to_hw_box(&box, &args->box);
439 if (!vgdev->has_virgl_3d) {
440 virtio_gpu_cmd_transfer_to_host_2d
441 (vgdev, qobj, offset,
442 box.w, box.h, box.x, box.y, NULL);
444 fence = virtio_gpu_fence_alloc(vgdev);
449 virtio_gpu_cmd_transfer_to_host_3d
451 vfpriv ? vfpriv->ctx_id : 0, offset,
452 args->level, &box, fence);
453 dma_resv_add_excl_fence(qobj->tbo.base.resv,
455 dma_fence_put(&fence->f);
459 virtio_gpu_object_unreserve(qobj);
461 drm_gem_object_put_unlocked(gobj);
465 static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
466 struct drm_file *file)
468 struct drm_virtgpu_3d_wait *args = data;
469 struct drm_gem_object *gobj = NULL;
470 struct virtio_gpu_object *qobj = NULL;
474 gobj = drm_gem_object_lookup(file, args->handle);
478 qobj = gem_to_virtio_gpu_obj(gobj);
480 if (args->flags & VIRTGPU_WAIT_NOWAIT)
482 ret = virtio_gpu_object_wait(qobj, nowait);
484 drm_gem_object_put_unlocked(gobj);
488 static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
489 void *data, struct drm_file *file)
491 struct virtio_gpu_device *vgdev = dev->dev_private;
492 struct drm_virtgpu_get_caps *args = data;
493 unsigned size, host_caps_size;
495 int found_valid = -1;
497 struct virtio_gpu_drv_cap_cache *cache_ent;
500 if (vgdev->num_capsets == 0)
503 /* don't allow userspace to pass 0 */
507 spin_lock(&vgdev->display_info_lock);
508 for (i = 0; i < vgdev->num_capsets; i++) {
509 if (vgdev->capsets[i].id == args->cap_set_id) {
510 if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
517 if (found_valid == -1) {
518 spin_unlock(&vgdev->display_info_lock);
522 host_caps_size = vgdev->capsets[found_valid].max_size;
523 /* only copy to user the minimum of the host caps size or the guest caps size */
524 size = min(args->size, host_caps_size);
526 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
527 if (cache_ent->id == args->cap_set_id &&
528 cache_ent->version == args->cap_set_ver) {
529 spin_unlock(&vgdev->display_info_lock);
533 spin_unlock(&vgdev->display_info_lock);
535 /* not in cache - need to talk to hw */
536 virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
540 ret = wait_event_timeout(vgdev->resp_wq,
541 atomic_read(&cache_ent->is_valid), 5 * HZ);
545 /* is_valid check must proceed before copy of the cache entry. */
548 ptr = cache_ent->caps_cache;
550 if (copy_to_user(u64_to_user_ptr(args->addr), ptr, size))
556 struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
557 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
560 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
563 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
566 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
567 virtio_gpu_resource_create_ioctl,
570 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
573 /* make transfer async to the main ring? - no sure, can we
574 * thread these in the underlying GL
576 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
577 virtio_gpu_transfer_from_host_ioctl,
579 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
580 virtio_gpu_transfer_to_host_ioctl,
583 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
586 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,