2 * Copyright 2004 The Unichrome Project. All Rights Reserved.
3 * Copyright 2005 Thomas Hellstrom. All Rights Reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S), AND/OR THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
24 * Author: Thomas Hellstrom 2004, 2005.
25 * This code was written using docs obtained under NDA from VIA Inc.
27 * Don't run this code directly on an AGP buffer. Due to cache problems it will
31 #include "via_3d_reg.h"
33 #include <drm/via_drm.h>
34 #include <drm/drm_legacy.h>
35 #include "via_verifier.h"
37 #include <linux/kernel.h>
52 check_for_header2_err,
53 check_for_header1_err,
57 check_z_buffer_addr_mode,
58 check_destination_addr0,
59 check_destination_addr1,
60 check_destination_addr_mode,
72 check_texture_addr_mode,
73 check_for_vertex_count,
74 check_number_texunits,
79 * Associates each hazard above with a possible multi-command
80 * sequence. For example an address that is split over multiple
81 * commands and that needs to be checked at the first command
82 * that does not include any part of the address.
85 static drm_via_sequence_t seqs[] = {
118 static hz_init_t init_table1[] = {
119 {0xf2, check_for_header2_err},
120 {0xf0, check_for_header1_err},
121 {0xee, check_for_fire},
122 {0xcc, check_for_dummy},
123 {0xdd, check_for_dd},
125 {0x10, check_z_buffer_addr0},
126 {0x11, check_z_buffer_addr1},
127 {0x12, check_z_buffer_addr_mode},
145 {0x40, check_destination_addr0},
146 {0x41, check_destination_addr1},
147 {0x42, check_destination_addr_mode},
166 {0x7D, check_for_vertex_count}
169 static hz_init_t init_table2[] = {
170 {0xf2, check_for_header2_err},
171 {0xf0, check_for_header1_err},
172 {0xee, check_for_fire},
173 {0xcc, check_for_dummy},
174 {0x00, check_texture_addr0},
175 {0x01, check_texture_addr0},
176 {0x02, check_texture_addr0},
177 {0x03, check_texture_addr0},
178 {0x04, check_texture_addr0},
179 {0x05, check_texture_addr0},
180 {0x06, check_texture_addr0},
181 {0x07, check_texture_addr0},
182 {0x08, check_texture_addr0},
183 {0x09, check_texture_addr0},
184 {0x20, check_texture_addr1},
185 {0x21, check_texture_addr1},
186 {0x22, check_texture_addr1},
187 {0x23, check_texture_addr4},
188 {0x2B, check_texture_addr3},
189 {0x2C, check_texture_addr3},
190 {0x2D, check_texture_addr3},
191 {0x2E, check_texture_addr3},
192 {0x2F, check_texture_addr3},
193 {0x30, check_texture_addr3},
194 {0x31, check_texture_addr3},
195 {0x32, check_texture_addr3},
196 {0x33, check_texture_addr3},
197 {0x34, check_texture_addr3},
198 {0x4B, check_texture_addr5},
199 {0x4C, check_texture_addr6},
200 {0x51, check_texture_addr7},
201 {0x52, check_texture_addr8},
202 {0x77, check_texture_addr2},
206 {0x7B, check_texture_addr_mode},
227 static hz_init_t init_table3[] = {
228 {0xf2, check_for_header2_err},
229 {0xf0, check_for_header1_err},
230 {0xcc, check_for_dummy},
231 {0x00, check_number_texunits}
234 static hazard_t table1[256];
235 static hazard_t table2[256];
236 static hazard_t table3[256];
238 static __inline__ int
239 eat_words(const uint32_t **buf, const uint32_t *buf_end, unsigned num_words)
241 if ((buf_end - *buf) >= num_words) {
245 DRM_ERROR("Illegal termination of DMA command buffer\n");
250 * Partially stolen from drm_memory.h
253 static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t *seq,
254 unsigned long offset,
256 struct drm_device *dev)
258 struct drm_map_list *r_list;
259 drm_local_map_t *map = seq->map_cache;
261 if (map && map->offset <= offset
262 && (offset + size) <= (map->offset + map->size)) {
266 list_for_each_entry(r_list, &dev->maplist, head) {
270 if (map->offset <= offset
271 && (offset + size) <= (map->offset + map->size)
272 && !(map->flags & _DRM_RESTRICTED)
273 && (map->type == _DRM_AGP)) {
274 seq->map_cache = map;
282 * Require that all AGP texture levels reside in the same AGP map which should
283 * be mappable by the client. This is not a big restriction.
284 * FIXME: To actually enforce this security policy strictly, drm_rmmap
285 * would have to wait for dma quiescent before removing an AGP map.
286 * The via_drm_lookup_agp_map call in reality seems to take
287 * very little CPU time.
290 static __inline__ int finish_current_sequence(drm_via_state_t * cur_seq)
292 switch (cur_seq->unfinished) {
294 DRM_DEBUG("Z Buffer start address is 0x%x\n", cur_seq->z_addr);
297 DRM_DEBUG("Destination start address is 0x%x\n",
301 if (cur_seq->agp_texture) {
303 cur_seq->tex_level_lo[cur_seq->texture];
304 unsigned end = cur_seq->tex_level_hi[cur_seq->texture];
305 unsigned long lo = ~0, hi = 0, tmp;
306 uint32_t *addr, *pitch, *height, tex;
316 &(cur_seq->t_addr[tex = cur_seq->texture][start]);
317 pitch = &(cur_seq->pitch[tex][start]);
318 height = &(cur_seq->height[tex][start]);
319 npot = cur_seq->tex_npot[tex];
320 for (i = start; i <= end; ++i) {
325 tmp += (*height++ * *pitch++);
327 tmp += (*height++ << *pitch++);
332 if (!via_drm_lookup_agp_map
333 (cur_seq, lo, hi - lo, cur_seq->dev)) {
335 ("AGP texture is not in allowed map\n");
343 cur_seq->unfinished = no_sequence;
347 static __inline__ int
348 investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq)
350 register uint32_t tmp, *tmp_addr;
352 if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) {
354 if ((ret = finish_current_sequence(cur_seq)))
359 case check_for_header2:
360 if (cmd == HALCYON_HEADER2)
363 case check_for_header1:
364 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
367 case check_for_header2_err:
368 if (cmd == HALCYON_HEADER2)
370 DRM_ERROR("Illegal DMA HALCYON_HEADER2 command\n");
372 case check_for_header1_err:
373 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
375 DRM_ERROR("Illegal DMA HALCYON_HEADER1 command\n");
378 if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD)
380 DRM_ERROR("Illegal DMA HALCYON_FIRECMD command\n");
382 case check_for_dummy:
385 DRM_ERROR("Illegal DMA HC_DUMMY command\n");
388 if (0xdddddddd == cmd)
390 DRM_ERROR("Illegal DMA 0xdddddddd command\n");
392 case check_z_buffer_addr0:
393 cur_seq->unfinished = z_address;
394 cur_seq->z_addr = (cur_seq->z_addr & 0xFF000000) |
397 case check_z_buffer_addr1:
398 cur_seq->unfinished = z_address;
399 cur_seq->z_addr = (cur_seq->z_addr & 0x00FFFFFF) |
400 ((cmd & 0xFF) << 24);
402 case check_z_buffer_addr_mode:
403 cur_seq->unfinished = z_address;
404 if ((cmd & 0x0000C000) == 0)
406 DRM_ERROR("Attempt to place Z buffer in system memory\n");
408 case check_destination_addr0:
409 cur_seq->unfinished = dest_address;
410 cur_seq->d_addr = (cur_seq->d_addr & 0xFF000000) |
413 case check_destination_addr1:
414 cur_seq->unfinished = dest_address;
415 cur_seq->d_addr = (cur_seq->d_addr & 0x00FFFFFF) |
416 ((cmd & 0xFF) << 24);
418 case check_destination_addr_mode:
419 cur_seq->unfinished = dest_address;
420 if ((cmd & 0x0000C000) == 0)
423 ("Attempt to place 3D drawing buffer in system memory\n");
425 case check_texture_addr0:
426 cur_seq->unfinished = tex_address;
428 tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp];
429 *tmp_addr = (*tmp_addr & 0xFF000000) | (cmd & 0x00FFFFFF);
431 case check_texture_addr1:
432 cur_seq->unfinished = tex_address;
433 tmp = ((cmd >> 24) - 0x20);
435 tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp];
436 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24);
438 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF00) << 16);
440 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF0000) << 8);
442 case check_texture_addr2:
443 cur_seq->unfinished = tex_address;
444 cur_seq->tex_level_lo[tmp = cur_seq->texture] = cmd & 0x3F;
445 cur_seq->tex_level_hi[tmp] = (cmd & 0xFC0) >> 6;
447 case check_texture_addr3:
448 cur_seq->unfinished = tex_address;
449 tmp = ((cmd >> 24) - HC_SubA_HTXnL0Pit);
451 (cmd & HC_HTXnEnPit_MASK)) {
452 cur_seq->pitch[cur_seq->texture][tmp] =
453 (cmd & HC_HTXnLnPit_MASK);
454 cur_seq->tex_npot[cur_seq->texture] = 1;
456 cur_seq->pitch[cur_seq->texture][tmp] =
457 (cmd & HC_HTXnLnPitE_MASK) >> HC_HTXnLnPitE_SHIFT;
458 cur_seq->tex_npot[cur_seq->texture] = 0;
459 if (cmd & 0x000FFFFF) {
461 ("Unimplemented texture level 0 pitch mode.\n");
466 case check_texture_addr4:
467 cur_seq->unfinished = tex_address;
468 tmp_addr = &cur_seq->t_addr[cur_seq->texture][9];
469 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24);
471 case check_texture_addr5:
472 case check_texture_addr6:
473 cur_seq->unfinished = tex_address;
475 * Texture width. We don't care since we have the pitch.
478 case check_texture_addr7:
479 cur_seq->unfinished = tex_address;
480 tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
481 tmp_addr[5] = 1 << ((cmd & 0x00F00000) >> 20);
482 tmp_addr[4] = 1 << ((cmd & 0x000F0000) >> 16);
483 tmp_addr[3] = 1 << ((cmd & 0x0000F000) >> 12);
484 tmp_addr[2] = 1 << ((cmd & 0x00000F00) >> 8);
485 tmp_addr[1] = 1 << ((cmd & 0x000000F0) >> 4);
486 tmp_addr[0] = 1 << (cmd & 0x0000000F);
488 case check_texture_addr8:
489 cur_seq->unfinished = tex_address;
490 tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
491 tmp_addr[9] = 1 << ((cmd & 0x0000F000) >> 12);
492 tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8);
493 tmp_addr[7] = 1 << ((cmd & 0x000000F0) >> 4);
494 tmp_addr[6] = 1 << (cmd & 0x0000000F);
496 case check_texture_addr_mode:
497 cur_seq->unfinished = tex_address;
498 if (2 == (tmp = cmd & 0x00000003)) {
500 ("Attempt to fetch texture from system memory.\n");
503 cur_seq->agp_texture = (tmp == 3);
504 cur_seq->tex_palette_size[cur_seq->texture] =
505 (cmd >> 16) & 0x000000007;
507 case check_for_vertex_count:
508 cur_seq->vertex_count = cmd & 0x0000FFFF;
510 case check_number_texunits:
511 cur_seq->multitex = (cmd >> 3) & 1;
514 DRM_ERROR("Illegal DMA data: 0x%x\n", cmd);
520 static __inline__ int
521 via_check_prim_list(uint32_t const **buffer, const uint32_t * buf_end,
522 drm_via_state_t *cur_seq)
524 drm_via_private_t *dev_priv =
525 (drm_via_private_t *) cur_seq->dev->dev_private;
526 uint32_t a_fire, bcmd, dw_count;
529 const uint32_t *buf = *buffer;
531 while (buf < buf_end) {
533 if ((buf_end - buf) < 2) {
535 ("Unexpected termination of primitive list.\n");
539 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdB)
542 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdA) {
543 DRM_ERROR("Expected Vertex List A command, got 0x%x\n",
549 *buf++ | HC_HPLEND_MASK | HC_HPMValidN_MASK |
553 * How many dwords per vertex ?
556 if (cur_seq->agp && ((bcmd & (0xF << 11)) == 0)) {
557 DRM_ERROR("Illegal B command vertex data for AGP.\n");
564 dw_count += (cur_seq->multitex) ? 2 : 1;
566 dw_count += (cur_seq->multitex) ? 2 : 1;
569 if (bcmd & (1 << 10))
571 if (bcmd & (1 << 11))
573 if (bcmd & (1 << 12))
575 if (bcmd & (1 << 13))
577 if (bcmd & (1 << 14))
580 while (buf < buf_end) {
581 if (*buf == a_fire) {
582 if (dev_priv->num_fire_offsets >=
584 DRM_ERROR("Fire offset buffer full.\n");
588 dev_priv->fire_offsets[dev_priv->
589 num_fire_offsets++] =
593 if (buf < buf_end && *buf == a_fire)
597 if ((*buf == HALCYON_HEADER2) ||
598 ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) {
599 DRM_ERROR("Missing Vertex Fire command, "
600 "Stray Vertex Fire command or verifier "
605 if ((ret = eat_words(&buf, buf_end, dw_count)))
608 if (buf >= buf_end && !have_fire) {
609 DRM_ERROR("Missing Vertex Fire command or verifier "
614 if (cur_seq->agp && ((buf - cur_seq->buf_start) & 0x01)) {
615 DRM_ERROR("AGP Primitive list end misaligned.\n");
624 static __inline__ verifier_state_t
625 via_check_header2(uint32_t const **buffer, const uint32_t *buf_end,
626 drm_via_state_t *hc_state)
631 const uint32_t *buf = *buffer;
632 const hazard_t *hz_table;
634 if ((buf_end - buf) < 2) {
636 ("Illegal termination of DMA HALCYON_HEADER2 sequence.\n");
640 cmd = (*buf++ & 0xFFFF0000) >> 16;
643 case HC_ParaType_CmdVdata:
644 if (via_check_prim_list(&buf, buf_end, hc_state))
647 return state_command;
648 case HC_ParaType_NotTex:
651 case HC_ParaType_Tex:
652 hc_state->texture = 0;
655 case (HC_ParaType_Tex | (HC_SubType_Tex1 << 8)):
656 hc_state->texture = 1;
659 case (HC_ParaType_Tex | (HC_SubType_TexGeneral << 8)):
662 case HC_ParaType_Auto:
663 if (eat_words(&buf, buf_end, 2))
666 return state_command;
667 case (HC_ParaType_Palette | (HC_SubType_Stipple << 8)):
668 if (eat_words(&buf, buf_end, 32))
671 return state_command;
672 case (HC_ParaType_Palette | (HC_SubType_TexPalette0 << 8)):
673 case (HC_ParaType_Palette | (HC_SubType_TexPalette1 << 8)):
674 DRM_ERROR("Texture palettes are rejected because of "
675 "lack of info how to determine their size.\n");
677 case (HC_ParaType_Palette | (HC_SubType_FogTable << 8)):
678 DRM_ERROR("Fog factor palettes are rejected because of "
679 "lack of info how to determine their size.\n");
684 * There are some unimplemented HC_ParaTypes here, that
685 * need to be implemented if the Mesa driver is extended.
688 DRM_ERROR("Invalid or unimplemented HALCYON_HEADER2 "
689 "DMA subcommand: 0x%x. Previous dword: 0x%x\n",
695 while (buf < buf_end) {
697 if ((hz = hz_table[cmd >> 24])) {
698 if ((hz_mode = investigate_hazard(cmd, hz, hc_state))) {
705 } else if (hc_state->unfinished &&
706 finish_current_sequence(hc_state)) {
710 if (hc_state->unfinished && finish_current_sequence(hc_state))
713 return state_command;
716 static __inline__ verifier_state_t
717 via_parse_header2(drm_via_private_t *dev_priv, uint32_t const **buffer,
718 const uint32_t *buf_end, int *fire_count)
721 const uint32_t *buf = *buffer;
722 const uint32_t *next_fire;
725 next_fire = dev_priv->fire_offsets[*fire_count];
727 cmd = (*buf & 0xFFFF0000) >> 16;
728 VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++);
730 case HC_ParaType_CmdVdata:
731 while ((buf < buf_end) &&
732 (*fire_count < dev_priv->num_fire_offsets) &&
733 (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB) {
734 while (buf <= next_fire) {
735 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
736 (burst & 63), *buf++);
740 && ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD))
743 if (++(*fire_count) < dev_priv->num_fire_offsets)
744 next_fire = dev_priv->fire_offsets[*fire_count];
748 while (buf < buf_end) {
750 if (*buf == HC_HEADER2 ||
751 (*buf & HALCYON_HEADER1MASK) == HALCYON_HEADER1 ||
752 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5 ||
753 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
756 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
757 (burst & 63), *buf++);
762 return state_command;
765 static __inline__ int verify_mmio_address(uint32_t address)
767 if ((address > 0x3FF) && (address < 0xC00)) {
768 DRM_ERROR("Invalid VIDEO DMA command. "
769 "Attempt to access 3D- or command burst area.\n");
771 } else if ((address > 0xCFF) && (address < 0x1300)) {
772 DRM_ERROR("Invalid VIDEO DMA command. "
773 "Attempt to access PCI DMA area.\n");
775 } else if (address > 0x13FF) {
776 DRM_ERROR("Invalid VIDEO DMA command. "
777 "Attempt to access VGA registers.\n");
783 static __inline__ int
784 verify_video_tail(uint32_t const **buffer, const uint32_t * buf_end,
787 const uint32_t *buf = *buffer;
789 if (buf_end - buf < dwords) {
790 DRM_ERROR("Illegal termination of video command.\n");
795 DRM_ERROR("Illegal video command tail.\n");
803 static __inline__ verifier_state_t
804 via_check_header1(uint32_t const **buffer, const uint32_t * buf_end)
807 const uint32_t *buf = *buffer;
808 verifier_state_t ret = state_command;
810 while (buf < buf_end) {
812 if ((cmd > ((0x3FF >> 2) | HALCYON_HEADER1)) &&
813 (cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) {
814 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
816 DRM_ERROR("Invalid HALCYON_HEADER1 command. "
817 "Attempt to access 3D- or command burst area.\n");
820 } else if (cmd > ((0xCFF >> 2) | HALCYON_HEADER1)) {
821 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
823 DRM_ERROR("Invalid HALCYON_HEADER1 command. "
824 "Attempt to access VGA registers.\n");
835 static __inline__ verifier_state_t
836 via_parse_header1(drm_via_private_t *dev_priv, uint32_t const **buffer,
837 const uint32_t *buf_end)
839 register uint32_t cmd;
840 const uint32_t *buf = *buffer;
842 while (buf < buf_end) {
844 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
846 VIA_WRITE((cmd & ~HALCYON_HEADER1MASK) << 2, *++buf);
850 return state_command;
853 static __inline__ verifier_state_t
854 via_check_vheader5(uint32_t const **buffer, const uint32_t *buf_end)
857 const uint32_t *buf = *buffer;
859 if (buf_end - buf < 4) {
860 DRM_ERROR("Illegal termination of video header5 command\n");
864 data = *buf++ & ~VIA_VIDEOMASK;
865 if (verify_mmio_address(data))
869 if (*buf++ != 0x00F50000) {
870 DRM_ERROR("Illegal header5 header data\n");
873 if (*buf++ != 0x00000000) {
874 DRM_ERROR("Illegal header5 header data\n");
877 if (eat_words(&buf, buf_end, data))
879 if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3)))
882 return state_command;
886 static __inline__ verifier_state_t
887 via_parse_vheader5(drm_via_private_t *dev_priv, uint32_t const **buffer,
888 const uint32_t *buf_end)
890 uint32_t addr, count, i;
891 const uint32_t *buf = *buffer;
893 addr = *buf++ & ~VIA_VIDEOMASK;
897 VIA_WRITE(addr, *buf++);
899 buf += 4 - (count & 3);
901 return state_command;
904 static __inline__ verifier_state_t
905 via_check_vheader6(uint32_t const **buffer, const uint32_t * buf_end)
908 const uint32_t *buf = *buffer;
911 if (buf_end - buf < 4) {
912 DRM_ERROR("Illegal termination of video header6 command\n");
917 if (*buf++ != 0x00F60000) {
918 DRM_ERROR("Illegal header6 header data\n");
921 if (*buf++ != 0x00000000) {
922 DRM_ERROR("Illegal header6 header data\n");
925 if ((buf_end - buf) < (data << 1)) {
926 DRM_ERROR("Illegal termination of video header6 command\n");
929 for (i = 0; i < data; ++i) {
930 if (verify_mmio_address(*buf++))
935 if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3)))
938 return state_command;
941 static __inline__ verifier_state_t
942 via_parse_vheader6(drm_via_private_t *dev_priv, uint32_t const **buffer,
943 const uint32_t *buf_end)
946 uint32_t addr, count, i;
947 const uint32_t *buf = *buffer;
953 VIA_WRITE(addr, *buf++);
957 buf += 4 - (count & 3);
959 return state_command;
963 via_verify_command_stream(const uint32_t * buf, unsigned int size,
964 struct drm_device * dev, int agp)
967 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
968 drm_via_state_t *hc_state = &dev_priv->hc_state;
969 drm_via_state_t saved_state = *hc_state;
971 const uint32_t *buf_end = buf + (size >> 2);
972 verifier_state_t state = state_command;
976 cme_video = (dev_priv->chipset == VIA_PRO_GROUP_A ||
977 dev_priv->chipset == VIA_DX9_0);
979 supported_3d = dev_priv->chipset != VIA_DX9_0;
982 hc_state->unfinished = no_sequence;
983 hc_state->map_cache = NULL;
985 hc_state->buf_start = buf;
986 dev_priv->num_fire_offsets = 0;
988 while (buf < buf_end) {
992 state = via_check_header2(&buf, buf_end, hc_state);
995 state = via_check_header1(&buf, buf_end);
998 state = via_check_vheader5(&buf, buf_end);
1000 case state_vheader6:
1001 state = via_check_vheader6(&buf, buf_end);
1004 if ((HALCYON_HEADER2 == (cmd = *buf)) &&
1006 state = state_header2;
1007 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
1008 state = state_header1;
1010 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
1011 state = state_vheader5;
1013 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
1014 state = state_vheader6;
1015 else if ((cmd == HALCYON_HEADER2) && !supported_3d) {
1016 DRM_ERROR("Accelerated 3D is not supported on this chipset yet.\n");
1017 state = state_error;
1020 ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
1022 state = state_error;
1027 *hc_state = saved_state;
1031 if (state == state_error) {
1032 *hc_state = saved_state;
1039 via_parse_command_stream(struct drm_device *dev, const uint32_t *buf,
1043 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
1045 const uint32_t *buf_end = buf + (size >> 2);
1046 verifier_state_t state = state_command;
1049 while (buf < buf_end) {
1054 via_parse_header2(dev_priv, &buf, buf_end,
1058 state = via_parse_header1(dev_priv, &buf, buf_end);
1060 case state_vheader5:
1061 state = via_parse_vheader5(dev_priv, &buf, buf_end);
1063 case state_vheader6:
1064 state = via_parse_vheader6(dev_priv, &buf, buf_end);
1067 if (HALCYON_HEADER2 == (cmd = *buf))
1068 state = state_header2;
1069 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
1070 state = state_header1;
1071 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
1072 state = state_vheader5;
1073 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
1074 state = state_vheader6;
1077 ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
1079 state = state_error;
1087 if (state == state_error)
1093 setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size)
1097 for (i = 0; i < 256; ++i)
1098 table[i] = forbidden_command;
1100 for (i = 0; i < size; ++i)
1101 table[init_table[i].code] = init_table[i].hz;
1104 void via_init_command_verifier(void)
1106 setup_hazard_table(init_table1, table1, ARRAY_SIZE(init_table1));
1107 setup_hazard_table(init_table2, table2, ARRAY_SIZE(init_table2));
1108 setup_hazard_table(init_table3, table3, ARRAY_SIZE(init_table3));