drivers/gpu/drm/via/via_dma.c

   1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
   7  * All Rights Reserved.
   8  *
   9  * Copyright 2004 The Unichrome project.
  10  * All Rights Reserved.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a
  13  * copy of this software and associated documentation files (the "Software"),
  14  * to deal in the Software without restriction, including without limitation
  15  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  16  * and/or sell copies of the Software, and to permit persons to whom the
  17  * Software is furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice (including the
  20  * next paragraph) shall be included in all copies or substantial portions
  21  * of the Software.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  25  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  26  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  27  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  28  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  29  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  30  *
  31  * Authors:
  32  *    Tungsten Graphics,
  33  *    Erdi Chen,
  34  *    Thomas Hellstrom.
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/uaccess.h>
  39
  40 #include <drm/drm.h>
  41 #include <drm/drm_agpsupport.h>
  42 #include <drm/drm_device.h>
  43 #include <drm/drm_file.h>
  44 #include <drm/via_drm.h>
  45
  46 #include "via_drv.h"
  47 #include "via_3d_reg.h"
  48
  49 #define CMDBUF_ALIGNMENT_SIZE   (0x100)
  50 #define CMDBUF_ALIGNMENT_MASK   (0x0ff)
  51
  52 /* defines for VIA 3D registers */
  53 #define VIA_REG_STATUS          0x400
  54 #define VIA_REG_TRANSET         0x43C
  55 #define VIA_REG_TRANSPACE       0x440
  56
  57 /* VIA_REG_STATUS(0x400): Engine Status */
  58 #define VIA_CMD_RGTR_BUSY       0x00000080      /* Command Regulator is busy */
  59 #define VIA_2D_ENG_BUSY         0x00000001      /* 2D Engine is busy */
  60 #define VIA_3D_ENG_BUSY         0x00000002      /* 3D Engine is busy */
  61 #define VIA_VR_QUEUE_BUSY       0x00020000      /* Virtual Queue is busy */
  62
  63 #define SetReg2DAGP(nReg, nData) {                              \
  64         *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1;  \
  65         *((uint32_t *)(vb) + 1) = (nData);                      \
  66         vb = ((uint32_t *)vb) + 2;                              \
  67         dev_priv->dma_low += 8;                                 \
  68 }
  69
  70 #define via_flush_write_combine() mb()
  71
  72 #define VIA_OUT_RING_QW(w1, w2) do {            \
  73         *vb++ = (w1);                           \
  74         *vb++ = (w2);                           \
  75         dev_priv->dma_low += 8;                 \
  76 } while (0)
  77
  78 static void via_cmdbuf_start(drm_via_private_t *dev_priv);
  79 static void via_cmdbuf_pause(drm_via_private_t *dev_priv);
  80 static void via_cmdbuf_reset(drm_via_private_t *dev_priv);
  81 static void via_cmdbuf_rewind(drm_via_private_t *dev_priv);
  82 static int via_wait_idle(drm_via_private_t *dev_priv);
  83 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
  84
  85 /*
  86  * Free space in command buffer.
  87  */
  88
  89 static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv)
  90 {
  91         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
  92         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
  93
  94         return ((hw_addr <= dev_priv->dma_low) ?
  95                 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
  96                 (hw_addr - dev_priv->dma_low));
  97 }
  98
  99 /*
 100  * How much does the command regulator lag behind?
 101  */
 102
 103 static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv)
 104 {
 105         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 106         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
 107
 108         return ((hw_addr <= dev_priv->dma_low) ?
 109                 (dev_priv->dma_low - hw_addr) :
 110                 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
 111 }
 112
 113 /*
 114  * Check that the given size fits in the buffer, otherwise wait.
 115  */
 116
 117 static inline int
 118 via_cmdbuf_wait(drm_via_private_t *dev_priv, unsigned int size)
 119 {
 120         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 121         uint32_t cur_addr, hw_addr, next_addr;
 122         volatile uint32_t *hw_addr_ptr;
 123         uint32_t count;
 124         hw_addr_ptr = dev_priv->hw_addr_ptr;
 125         cur_addr = dev_priv->dma_low;
 126         next_addr = cur_addr + size + 512 * 1024;
 127         count = 1000000;
 128         do {
 129                 hw_addr = *hw_addr_ptr - agp_base;
 130                 if (count-- == 0) {
 131                         DRM_ERROR
 132                             ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
 133                              hw_addr, cur_addr, next_addr);
 134                         return -1;
 135                 }
 136                 if  ((cur_addr < hw_addr) && (next_addr >= hw_addr))
 137                         msleep(1);
 138         } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
 139         return 0;
 140 }
 141
 142 /*
 143  * Checks whether buffer head has reach the end. Rewind the ring buffer
 144  * when necessary.
 145  *
 146  * Returns virtual pointer to ring buffer.
 147  */
 148
 149 static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
 150                                       unsigned int size)
 151 {
 152         if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
 153             dev_priv->dma_high) {
 154                 via_cmdbuf_rewind(dev_priv);
 155         }
 156         if (via_cmdbuf_wait(dev_priv, size) != 0)
 157                 return NULL;
 158
 159         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 160 }
 161
 162 int via_dma_cleanup(struct drm_device *dev)
 163 {
 164         if (dev->dev_private) {
 165                 drm_via_private_t *dev_priv =
 166                     (drm_via_private_t *) dev->dev_private;
 167
 168                 if (dev_priv->ring.virtual_start) {
 169                         via_cmdbuf_reset(dev_priv);
 170
 171                         drm_legacy_ioremapfree(&dev_priv->ring.map, dev);
 172                         dev_priv->ring.virtual_start = NULL;
 173                 }
 174
 175         }
 176
 177         return 0;
 178 }
 179
 180 static int via_initialize(struct drm_device *dev,
 181                           drm_via_private_t *dev_priv,
 182                           drm_via_dma_init_t *init)
 183 {
 184         if (!dev_priv || !dev_priv->mmio) {
 185                 DRM_ERROR("via_dma_init called before via_map_init\n");
 186                 return -EFAULT;
 187         }
 188
 189         if (dev_priv->ring.virtual_start != NULL) {
 190                 DRM_ERROR("called again without calling cleanup\n");
 191                 return -EFAULT;
 192         }
 193
 194         if (!dev->agp || !dev->agp->base) {
 195                 DRM_ERROR("called with no agp memory available\n");
 196                 return -EFAULT;
 197         }
 198
 199         if (dev_priv->chipset == VIA_DX9_0) {
 200                 DRM_ERROR("AGP DMA is not supported on this chip\n");
 201                 return -EINVAL;
 202         }
 203
 204         dev_priv->ring.map.offset = dev->agp->base + init->offset;
 205         dev_priv->ring.map.size = init->size;
 206         dev_priv->ring.map.type = 0;
 207         dev_priv->ring.map.flags = 0;
 208         dev_priv->ring.map.mtrr = 0;
 209
 210         drm_legacy_ioremap(&dev_priv->ring.map, dev);
 211
 212         if (dev_priv->ring.map.handle == NULL) {
 213                 via_dma_cleanup(dev);
 214                 DRM_ERROR("can not ioremap virtual address for"
 215                           " ring buffer\n");
 216                 return -ENOMEM;
 217         }
 218
 219         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 220
 221         dev_priv->dma_ptr = dev_priv->ring.virtual_start;
 222         dev_priv->dma_low = 0;
 223         dev_priv->dma_high = init->size;
 224         dev_priv->dma_wrap = init->size;
 225         dev_priv->dma_offset = init->offset;
 226         dev_priv->last_pause_ptr = NULL;
 227         dev_priv->hw_addr_ptr =
 228                 (volatile uint32_t *)((char *)dev_priv->mmio->handle +
 229                 init->reg_pause_addr);
 230
 231         via_cmdbuf_start(dev_priv);
 232
 233         return 0;
 234 }
 235
 236 static int via_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
 237 {
 238         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 239         drm_via_dma_init_t *init = data;
 240         int retcode = 0;
 241
 242         switch (init->func) {
 243         case VIA_INIT_DMA:
 244                 if (!capable(CAP_SYS_ADMIN))
 245                         retcode = -EPERM;
 246                 else
 247                         retcode = via_initialize(dev, dev_priv, init);
 248                 break;
 249         case VIA_CLEANUP_DMA:
 250                 if (!capable(CAP_SYS_ADMIN))
 251                         retcode = -EPERM;
 252                 else
 253                         retcode = via_dma_cleanup(dev);
 254                 break;
 255         case VIA_DMA_INITIALIZED:
 256                 retcode = (dev_priv->ring.virtual_start != NULL) ?
 257                         0 : -EFAULT;
 258                 break;
 259         default:
 260                 retcode = -EINVAL;
 261                 break;
 262         }
 263
 264         return retcode;
 265 }
 266
 267 static int via_dispatch_cmdbuffer(struct drm_device *dev, drm_via_cmdbuffer_t *cmd)
 268 {
 269         drm_via_private_t *dev_priv;
 270         uint32_t *vb;
 271         int ret;
 272
 273         dev_priv = (drm_via_private_t *) dev->dev_private;
 274
 275         if (dev_priv->ring.virtual_start == NULL) {
 276                 DRM_ERROR("called without initializing AGP ring buffer.\n");
 277                 return -EFAULT;
 278         }
 279
 280         if (cmd->size > VIA_PCI_BUF_SIZE)
 281                 return -ENOMEM;
 282
 283         if (copy_from_user(dev_priv->pci_buf, cmd->buf, cmd->size))
 284                 return -EFAULT;
 285
 286         /*
 287          * Running this function on AGP memory is dead slow. Therefore
 288          * we run it on a temporary cacheable system memory buffer and
 289          * copy it to AGP memory when ready.
 290          */
 291
 292         if ((ret =
 293              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
 294                                        cmd->size, dev, 1))) {
 295                 return ret;
 296         }
 297
 298         vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
 299         if (vb == NULL)
 300                 return -EAGAIN;
 301
 302         memcpy(vb, dev_priv->pci_buf, cmd->size);
 303
 304         dev_priv->dma_low += cmd->size;
 305
 306         /*
 307          * Small submissions somehow stalls the CPU. (AGP cache effects?)
 308          * pad to greater size.
 309          */
 310
 311         if (cmd->size < 0x100)
 312                 via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
 313         via_cmdbuf_pause(dev_priv);
 314
 315         return 0;
 316 }
 317
 318 int via_driver_dma_quiescent(struct drm_device *dev)
 319 {
 320         drm_via_private_t *dev_priv = dev->dev_private;
 321
 322         if (!via_wait_idle(dev_priv))
 323                 return -EBUSY;
 324         return 0;
 325 }
 326
 327 static int via_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
 328 {
 329
 330         LOCK_TEST_WITH_RETURN(dev, file_priv);
 331
 332         return via_driver_dma_quiescent(dev);
 333 }
 334
 335 static int via_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
 336 {
 337         drm_via_cmdbuffer_t *cmdbuf = data;
 338         int ret;
 339
 340         LOCK_TEST_WITH_RETURN(dev, file_priv);
 341
 342         DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size);
 343
 344         ret = via_dispatch_cmdbuffer(dev, cmdbuf);
 345         return ret;
 346 }
 347
 348 static int via_dispatch_pci_cmdbuffer(struct drm_device *dev,
 349                                       drm_via_cmdbuffer_t *cmd)
 350 {
 351         drm_via_private_t *dev_priv = dev->dev_private;
 352         int ret;
 353
 354         if (cmd->size > VIA_PCI_BUF_SIZE)
 355                 return -ENOMEM;
 356         if (copy_from_user(dev_priv->pci_buf, cmd->buf, cmd->size))
 357                 return -EFAULT;
 358
 359         if ((ret =
 360              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
 361                                        cmd->size, dev, 0))) {
 362                 return ret;
 363         }
 364
 365         ret =
 366             via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
 367                                      cmd->size);
 368         return ret;
 369 }
 370
 371 static int via_pci_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
 372 {
 373         drm_via_cmdbuffer_t *cmdbuf = data;
 374         int ret;
 375
 376         LOCK_TEST_WITH_RETURN(dev, file_priv);
 377
 378         DRM_DEBUG("buf %p size %lu\n", cmdbuf->buf, cmdbuf->size);
 379
 380         ret = via_dispatch_pci_cmdbuffer(dev, cmdbuf);
 381         return ret;
 382 }
 383
 384 static inline uint32_t *via_align_buffer(drm_via_private_t *dev_priv,
 385                                          uint32_t * vb, int qw_count)
 386 {
 387         for (; qw_count > 0; --qw_count)
 388                 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
 389         return vb;
 390 }
 391
 392 /*
 393  * This function is used internally by ring buffer management code.
 394  *
 395  * Returns virtual pointer to ring buffer.
 396  */
 397 static inline uint32_t *via_get_dma(drm_via_private_t *dev_priv)
 398 {
 399         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 400 }
 401
 402 /*
 403  * Hooks a segment of data into the tail of the ring-buffer by
 404  * modifying the pause address stored in the buffer itself. If
 405  * the regulator has already paused, restart it.
 406  */
 407 static int via_hook_segment(drm_via_private_t *dev_priv,
 408                             uint32_t pause_addr_hi, uint32_t pause_addr_lo,
 409                             int no_pci_fire)
 410 {
 411         int paused, count;
 412         volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
 413         uint32_t reader, ptr;
 414         uint32_t diff;
 415
 416         paused = 0;
 417         via_flush_write_combine();
 418         (void) *(volatile uint32_t *)(via_get_dma(dev_priv) - 1);
 419
 420         *paused_at = pause_addr_lo;
 421         via_flush_write_combine();
 422         (void) *paused_at;
 423
 424         reader = *(dev_priv->hw_addr_ptr);
 425         ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
 426                 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
 427
 428         dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
 429
 430         /*
 431          * If there is a possibility that the command reader will
 432          * miss the new pause address and pause on the old one,
 433          * In that case we need to program the new start address
 434          * using PCI.
 435          */
 436
 437         diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
 438         count = 10000000;
 439         while (diff == 0 && count--) {
 440                 paused = (via_read(dev_priv, 0x41c) & 0x80000000);
 441                 if (paused)
 442                         break;
 443                 reader = *(dev_priv->hw_addr_ptr);
 444                 diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
 445         }
 446
 447         paused = via_read(dev_priv, 0x41c) & 0x80000000;
 448
 449         if (paused && !no_pci_fire) {
 450                 reader = *(dev_priv->hw_addr_ptr);
 451                 diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
 452                 diff &= (dev_priv->dma_high - 1);
 453                 if (diff != 0 && diff < (dev_priv->dma_high >> 1)) {
 454                         DRM_ERROR("Paused at incorrect address. "
 455                                   "0x%08x, 0x%08x 0x%08x\n",
 456                                   ptr, reader, dev_priv->dma_diff);
 457                 } else if (diff == 0) {
 458                         /*
 459                          * There is a concern that these writes may stall the PCI bus
 460                          * if the GPU is not idle. However, idling the GPU first
 461                          * doesn't make a difference.
 462                          */
 463
 464                         via_write(dev_priv, VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 465                         via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_hi);
 466                         via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_lo);
 467                         via_read(dev_priv, VIA_REG_TRANSPACE);
 468                 }
 469         }
 470         return paused;
 471 }
 472
 473 static int via_wait_idle(drm_via_private_t *dev_priv)
 474 {
 475         int count = 10000000;
 476
 477         while (!(via_read(dev_priv, VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && --count)
 478                 ;
 479
 480         while (count && (via_read(dev_priv, VIA_REG_STATUS) &
 481                            (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
 482                             VIA_3D_ENG_BUSY)))
 483                 --count;
 484         return count;
 485 }
 486
 487 static uint32_t *via_align_cmd(drm_via_private_t *dev_priv, uint32_t cmd_type,
 488                                uint32_t addr, uint32_t *cmd_addr_hi,
 489                                uint32_t *cmd_addr_lo, int skip_wait)
 490 {
 491         uint32_t agp_base;
 492         uint32_t cmd_addr, addr_lo, addr_hi;
 493         uint32_t *vb;
 494         uint32_t qw_pad_count;
 495
 496         if (!skip_wait)
 497                 via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
 498
 499         vb = via_get_dma(dev_priv);
 500         VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
 501                         (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
 502         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 503         qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
 504             ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
 505
 506         cmd_addr = (addr) ? addr :
 507             agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
 508         addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
 509                    (cmd_addr & HC_HAGPBpL_MASK));
 510         addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
 511
 512         vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
 513         VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
 514         return vb;
 515 }
 516
 517 static void via_cmdbuf_start(drm_via_private_t *dev_priv)
 518 {
 519         uint32_t pause_addr_lo, pause_addr_hi;
 520         uint32_t start_addr, start_addr_lo;
 521         uint32_t end_addr, end_addr_lo;
 522         uint32_t command;
 523         uint32_t agp_base;
 524         uint32_t ptr;
 525         uint32_t reader;
 526         int count;
 527
 528         dev_priv->dma_low = 0;
 529
 530         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 531         start_addr = agp_base;
 532         end_addr = agp_base + dev_priv->dma_high;
 533
 534         start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
 535         end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
 536         command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
 537                    ((end_addr & 0xff000000) >> 16));
 538
 539         dev_priv->last_pause_ptr =
 540             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
 541                           &pause_addr_hi, &pause_addr_lo, 1) - 1;
 542
 543         via_flush_write_combine();
 544         (void) *(volatile uint32_t *)dev_priv->last_pause_ptr;
 545
 546         via_write(dev_priv, VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 547         via_write(dev_priv, VIA_REG_TRANSPACE, command);
 548         via_write(dev_priv, VIA_REG_TRANSPACE, start_addr_lo);
 549         via_write(dev_priv, VIA_REG_TRANSPACE, end_addr_lo);
 550
 551         via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_hi);
 552         via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_lo);
 553         wmb();
 554         via_write(dev_priv, VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
 555         via_read(dev_priv, VIA_REG_TRANSPACE);
 556
 557         dev_priv->dma_diff = 0;
 558
 559         count = 10000000;
 560         while (!(via_read(dev_priv, 0x41c) & 0x80000000) && count--);
 561
 562         reader = *(dev_priv->hw_addr_ptr);
 563         ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
 564             dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
 565
 566         /*
 567          * This is the difference between where we tell the
 568          * command reader to pause and where it actually pauses.
 569          * This differs between hw implementation so we need to
 570          * detect it.
 571          */
 572
 573         dev_priv->dma_diff = ptr - reader;
 574 }
 575
 576 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords)
 577 {
 578         uint32_t *vb;
 579
 580         via_cmdbuf_wait(dev_priv, qwords + 2);
 581         vb = via_get_dma(dev_priv);
 582         VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);
 583         via_align_buffer(dev_priv, vb, qwords);
 584 }
 585
 586 static inline void via_dummy_bitblt(drm_via_private_t *dev_priv)
 587 {
 588         uint32_t *vb = via_get_dma(dev_priv);
 589         SetReg2DAGP(0x0C, (0 | (0 << 16)));
 590         SetReg2DAGP(0x10, 0 | (0 << 16));
 591         SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
 592 }
 593
 594 static void via_cmdbuf_jump(drm_via_private_t *dev_priv)
 595 {
 596         uint32_t pause_addr_lo, pause_addr_hi;
 597         uint32_t jump_addr_lo, jump_addr_hi;
 598         volatile uint32_t *last_pause_ptr;
 599         uint32_t dma_low_save1, dma_low_save2;
 600
 601         via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
 602                       &jump_addr_lo, 0);
 603
 604         dev_priv->dma_wrap = dev_priv->dma_low;
 605
 606         /*
 607          * Wrap command buffer to the beginning.
 608          */
 609
 610         dev_priv->dma_low = 0;
 611         if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0)
 612                 DRM_ERROR("via_cmdbuf_jump failed\n");
 613
 614         via_dummy_bitblt(dev_priv);
 615         via_dummy_bitblt(dev_priv);
 616
 617         last_pause_ptr =
 618             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 619                           &pause_addr_lo, 0) - 1;
 620         via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 621                       &pause_addr_lo, 0);
 622
 623         *last_pause_ptr = pause_addr_lo;
 624         dma_low_save1 = dev_priv->dma_low;
 625
 626         /*
 627          * Now, set a trap that will pause the regulator if it tries to rerun the old
 628          * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause
 629          * and reissues the jump command over PCI, while the regulator has already taken the jump
 630          * and actually paused at the current buffer end).
 631          * There appears to be no other way to detect this condition, since the hw_addr_pointer
 632          * does not seem to get updated immediately when a jump occurs.
 633          */
 634
 635         last_pause_ptr =
 636                 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 637                               &pause_addr_lo, 0) - 1;
 638         via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 639                       &pause_addr_lo, 0);
 640         *last_pause_ptr = pause_addr_lo;
 641
 642         dma_low_save2 = dev_priv->dma_low;
 643         dev_priv->dma_low = dma_low_save1;
 644         via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0);
 645         dev_priv->dma_low = dma_low_save2;
 646         via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
 647 }
 648
 649
 650 static void via_cmdbuf_rewind(drm_via_private_t *dev_priv)
 651 {
 652         via_cmdbuf_jump(dev_priv);
 653 }
 654
 655 static void via_cmdbuf_flush(drm_via_private_t *dev_priv, uint32_t cmd_type)
 656 {
 657         uint32_t pause_addr_lo, pause_addr_hi;
 658
 659         via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
 660         via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
 661 }
 662
 663 static void via_cmdbuf_pause(drm_via_private_t *dev_priv)
 664 {
 665         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
 666 }
 667
 668 static void via_cmdbuf_reset(drm_via_private_t *dev_priv)
 669 {
 670         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
 671         via_wait_idle(dev_priv);
 672 }
 673
 674 /*
 675  * User interface to the space and lag functions.
 676  */
 677
 678 static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *file_priv)
 679 {
 680         drm_via_cmdbuf_size_t *d_siz = data;
 681         int ret = 0;
 682         uint32_t tmp_size, count;
 683         drm_via_private_t *dev_priv;
 684
 685         DRM_DEBUG("\n");
 686         LOCK_TEST_WITH_RETURN(dev, file_priv);
 687
 688         dev_priv = (drm_via_private_t *) dev->dev_private;
 689
 690         if (dev_priv->ring.virtual_start == NULL) {
 691                 DRM_ERROR("called without initializing AGP ring buffer.\n");
 692                 return -EFAULT;
 693         }
 694
 695         count = 1000000;
 696         tmp_size = d_siz->size;
 697         switch (d_siz->func) {
 698         case VIA_CMDBUF_SPACE:
 699                 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size)
 700                        && --count) {
 701                         if (!d_siz->wait)
 702                                 break;
 703                 }
 704                 if (!count) {
 705                         DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
 706                         ret = -EAGAIN;
 707                 }
 708                 break;
 709         case VIA_CMDBUF_LAG:
 710                 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size)
 711                        && --count) {
 712                         if (!d_siz->wait)
 713                                 break;
 714                 }
 715                 if (!count) {
 716                         DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
 717                         ret = -EAGAIN;
 718                 }
 719                 break;
 720         default:
 721                 ret = -EFAULT;
 722         }
 723         d_siz->size = tmp_size;
 724
 725         return ret;
 726 }
 727
 728 const struct drm_ioctl_desc via_ioctls[] = {
 729         DRM_IOCTL_DEF_DRV(VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH),
 730         DRM_IOCTL_DEF_DRV(VIA_FREEMEM, via_mem_free, DRM_AUTH),
 731         DRM_IOCTL_DEF_DRV(VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER),
 732         DRM_IOCTL_DEF_DRV(VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER),
 733         DRM_IOCTL_DEF_DRV(VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER),
 734         DRM_IOCTL_DEF_DRV(VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH),
 735         DRM_IOCTL_DEF_DRV(VIA_DMA_INIT, via_dma_init, DRM_AUTH),
 736         DRM_IOCTL_DEF_DRV(VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH),
 737         DRM_IOCTL_DEF_DRV(VIA_FLUSH, via_flush_ioctl, DRM_AUTH),
 738         DRM_IOCTL_DEF_DRV(VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH),
 739         DRM_IOCTL_DEF_DRV(VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH),
 740         DRM_IOCTL_DEF_DRV(VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH),
 741         DRM_IOCTL_DEF_DRV(VIA_DMA_BLIT, via_dma_blit, DRM_AUTH),
 742         DRM_IOCTL_DEF_DRV(VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH)
 743 };
 744
 745 int via_max_ioctl = ARRAY_SIZE(via_ioctls);