drivers/gpu/drm/vc4/vc4_plane.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 plane module
   8  *
   9  * Each DRM plane is a layer of pixels being scanned out by the HVS.
  10  *
  11  * At atomic modeset check time, we compute the HVS display element
  12  * state that would be necessary for displaying the plane (giving us a
  13  * chance to figure out if a plane configuration is invalid), then at
  14  * atomic flush time the CRTC will ask us to write our element state
  15  * into the region of the HVS that it has allocated for us.
  16  */
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_atomic_uapi.h>
  21 #include <drm/drm_fb_cma_helper.h>
  22 #include <drm/drm_fourcc.h>
  23 #include <drm/drm_gem_framebuffer_helper.h>
  24 #include <drm/drm_plane_helper.h>
  25
  26 #include "uapi/drm/vc4_drm.h"
  27
  28 #include "vc4_drv.h"
  29 #include "vc4_regs.h"
  30
  31 static const struct hvs_format {
  32         u32 drm; /* DRM_FORMAT_* */
  33         u32 hvs; /* HVS_FORMAT_* */
  34         u32 pixel_order;
  35         u32 pixel_order_hvs5;
  36 } hvs_formats[] = {
  37         {
  38                 .drm = DRM_FORMAT_XRGB8888,
  39                 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  40                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  41                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
  42         },
  43         {
  44                 .drm = DRM_FORMAT_ARGB8888,
  45                 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  46                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  47                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
  48         },
  49         {
  50                 .drm = DRM_FORMAT_ABGR8888,
  51                 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  52                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  53                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
  54         },
  55         {
  56                 .drm = DRM_FORMAT_XBGR8888,
  57                 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  58                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  59                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
  60         },
  61         {
  62                 .drm = DRM_FORMAT_RGB565,
  63                 .hvs = HVS_PIXEL_FORMAT_RGB565,
  64                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  65         },
  66         {
  67                 .drm = DRM_FORMAT_BGR565,
  68                 .hvs = HVS_PIXEL_FORMAT_RGB565,
  69                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  70         },
  71         {
  72                 .drm = DRM_FORMAT_ARGB1555,
  73                 .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  74                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  75         },
  76         {
  77                 .drm = DRM_FORMAT_XRGB1555,
  78                 .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  79                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  80         },
  81         {
  82                 .drm = DRM_FORMAT_RGB888,
  83                 .hvs = HVS_PIXEL_FORMAT_RGB888,
  84                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  85         },
  86         {
  87                 .drm = DRM_FORMAT_BGR888,
  88                 .hvs = HVS_PIXEL_FORMAT_RGB888,
  89                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  90         },
  91         {
  92                 .drm = DRM_FORMAT_YUV422,
  93                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  94                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  95         },
  96         {
  97                 .drm = DRM_FORMAT_YVU422,
  98                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  99                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 100         },
 101         {
 102                 .drm = DRM_FORMAT_YUV420,
 103                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
 104                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 105         },
 106         {
 107                 .drm = DRM_FORMAT_YVU420,
 108                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
 109                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 110         },
 111         {
 112                 .drm = DRM_FORMAT_NV12,
 113                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
 114                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 115         },
 116         {
 117                 .drm = DRM_FORMAT_NV21,
 118                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
 119                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 120         },
 121         {
 122                 .drm = DRM_FORMAT_NV16,
 123                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 124                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 125         },
 126         {
 127                 .drm = DRM_FORMAT_NV61,
 128                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 129                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 130         },
 131 };
 132
 133 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
 134 {
 135         unsigned i;
 136
 137         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 138                 if (hvs_formats[i].drm == drm_format)
 139                         return &hvs_formats[i];
 140         }
 141
 142         return NULL;
 143 }
 144
 145 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
 146 {
 147         if (dst == src)
 148                 return VC4_SCALING_NONE;
 149         if (3 * dst >= 2 * src)
 150                 return VC4_SCALING_PPF;
 151         else
 152                 return VC4_SCALING_TPZ;
 153 }
 154
 155 static bool plane_enabled(struct drm_plane_state *state)
 156 {
 157         return state->fb && !WARN_ON(!state->crtc);
 158 }
 159
 160 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
 161 {
 162         struct vc4_plane_state *vc4_state;
 163
 164         if (WARN_ON(!plane->state))
 165                 return NULL;
 166
 167         vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
 168         if (!vc4_state)
 169                 return NULL;
 170
 171         memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
 172         vc4_state->dlist_initialized = 0;
 173
 174         __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
 175
 176         if (vc4_state->dlist) {
 177                 vc4_state->dlist = kmemdup(vc4_state->dlist,
 178                                            vc4_state->dlist_count * 4,
 179                                            GFP_KERNEL);
 180                 if (!vc4_state->dlist) {
 181                         kfree(vc4_state);
 182                         return NULL;
 183                 }
 184                 vc4_state->dlist_size = vc4_state->dlist_count;
 185         }
 186
 187         return &vc4_state->base;
 188 }
 189
 190 static void vc4_plane_destroy_state(struct drm_plane *plane,
 191                                     struct drm_plane_state *state)
 192 {
 193         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 194         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 195
 196         if (drm_mm_node_allocated(&vc4_state->lbm)) {
 197                 unsigned long irqflags;
 198
 199                 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 200                 drm_mm_remove_node(&vc4_state->lbm);
 201                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 202         }
 203
 204         kfree(vc4_state->dlist);
 205         __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
 206         kfree(state);
 207 }
 208
 209 /* Called during init to allocate the plane's atomic state. */
 210 static void vc4_plane_reset(struct drm_plane *plane)
 211 {
 212         struct vc4_plane_state *vc4_state;
 213
 214         WARN_ON(plane->state);
 215
 216         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 217         if (!vc4_state)
 218                 return;
 219
 220         __drm_atomic_helper_plane_reset(plane, &vc4_state->base);
 221 }
 222
 223 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
 224 {
 225         if (vc4_state->dlist_count == vc4_state->dlist_size) {
 226                 u32 new_size = max(4u, vc4_state->dlist_count * 2);
 227                 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL);
 228
 229                 if (!new_dlist)
 230                         return;
 231                 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
 232
 233                 kfree(vc4_state->dlist);
 234                 vc4_state->dlist = new_dlist;
 235                 vc4_state->dlist_size = new_size;
 236         }
 237
 238         vc4_state->dlist[vc4_state->dlist_count++] = val;
 239 }
 240
 241 /* Returns the scl0/scl1 field based on whether the dimensions need to
 242  * be up/down/non-scaled.
 243  *
 244  * This is a replication of a table from the spec.
 245  */
 246 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
 247 {
 248         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 249
 250         switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
 251         case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
 252                 return SCALER_CTL0_SCL_H_PPF_V_PPF;
 253         case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
 254                 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
 255         case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
 256                 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
 257         case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
 258                 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
 259         case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
 260                 return SCALER_CTL0_SCL_H_PPF_V_NONE;
 261         case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
 262                 return SCALER_CTL0_SCL_H_NONE_V_PPF;
 263         case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
 264                 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
 265         case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
 266                 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
 267         default:
 268         case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
 269                 /* The unity case is independently handled by
 270                  * SCALER_CTL0_UNITY.
 271                  */
 272                 return 0;
 273         }
 274 }
 275
 276 static int vc4_plane_margins_adj(struct drm_plane_state *pstate)
 277 {
 278         struct vc4_plane_state *vc4_pstate = to_vc4_plane_state(pstate);
 279         unsigned int left, right, top, bottom, adjhdisplay, adjvdisplay;
 280         struct drm_crtc_state *crtc_state;
 281
 282         crtc_state = drm_atomic_get_new_crtc_state(pstate->state,
 283                                                    pstate->crtc);
 284
 285         vc4_crtc_get_margins(crtc_state, &left, &right, &top, &bottom);
 286         if (!left && !right && !top && !bottom)
 287                 return 0;
 288
 289         if (left + right >= crtc_state->mode.hdisplay ||
 290             top + bottom >= crtc_state->mode.vdisplay)
 291                 return -EINVAL;
 292
 293         adjhdisplay = crtc_state->mode.hdisplay - (left + right);
 294         vc4_pstate->crtc_x = DIV_ROUND_CLOSEST(vc4_pstate->crtc_x *
 295                                                adjhdisplay,
 296                                                crtc_state->mode.hdisplay);
 297         vc4_pstate->crtc_x += left;
 298         if (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - left)
 299                 vc4_pstate->crtc_x = crtc_state->mode.hdisplay - left;
 300
 301         adjvdisplay = crtc_state->mode.vdisplay - (top + bottom);
 302         vc4_pstate->crtc_y = DIV_ROUND_CLOSEST(vc4_pstate->crtc_y *
 303                                                adjvdisplay,
 304                                                crtc_state->mode.vdisplay);
 305         vc4_pstate->crtc_y += top;
 306         if (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - top)
 307                 vc4_pstate->crtc_y = crtc_state->mode.vdisplay - top;
 308
 309         vc4_pstate->crtc_w = DIV_ROUND_CLOSEST(vc4_pstate->crtc_w *
 310                                                adjhdisplay,
 311                                                crtc_state->mode.hdisplay);
 312         vc4_pstate->crtc_h = DIV_ROUND_CLOSEST(vc4_pstate->crtc_h *
 313                                                adjvdisplay,
 314                                                crtc_state->mode.vdisplay);
 315
 316         if (!vc4_pstate->crtc_w || !vc4_pstate->crtc_h)
 317                 return -EINVAL;
 318
 319         return 0;
 320 }
 321
 322 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
 323 {
 324         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 325         struct drm_framebuffer *fb = state->fb;
 326         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 327         u32 subpixel_src_mask = (1 << 16) - 1;
 328         int num_planes = fb->format->num_planes;
 329         struct drm_crtc_state *crtc_state;
 330         u32 h_subsample = fb->format->hsub;
 331         u32 v_subsample = fb->format->vsub;
 332         int i, ret;
 333
 334         crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 335                                                         state->crtc);
 336         if (!crtc_state) {
 337                 DRM_DEBUG_KMS("Invalid crtc state\n");
 338                 return -EINVAL;
 339         }
 340
 341         ret = drm_atomic_helper_check_plane_state(state, crtc_state, 1,
 342                                                   INT_MAX, true, true);
 343         if (ret)
 344                 return ret;
 345
 346         for (i = 0; i < num_planes; i++)
 347                 vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
 348
 349         /* We don't support subpixel source positioning for scaling. */
 350         if ((state->src.x1 & subpixel_src_mask) ||
 351             (state->src.x2 & subpixel_src_mask) ||
 352             (state->src.y1 & subpixel_src_mask) ||
 353             (state->src.y2 & subpixel_src_mask)) {
 354                 return -EINVAL;
 355         }
 356
 357         vc4_state->src_x = state->src.x1 >> 16;
 358         vc4_state->src_y = state->src.y1 >> 16;
 359         vc4_state->src_w[0] = (state->src.x2 - state->src.x1) >> 16;
 360         vc4_state->src_h[0] = (state->src.y2 - state->src.y1) >> 16;
 361
 362         vc4_state->crtc_x = state->dst.x1;
 363         vc4_state->crtc_y = state->dst.y1;
 364         vc4_state->crtc_w = state->dst.x2 - state->dst.x1;
 365         vc4_state->crtc_h = state->dst.y2 - state->dst.y1;
 366
 367         ret = vc4_plane_margins_adj(state);
 368         if (ret)
 369                 return ret;
 370
 371         vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
 372                                                        vc4_state->crtc_w);
 373         vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
 374                                                        vc4_state->crtc_h);
 375
 376         vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
 377                                vc4_state->y_scaling[0] == VC4_SCALING_NONE);
 378
 379         if (num_planes > 1) {
 380                 vc4_state->is_yuv = true;
 381
 382                 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
 383                 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
 384
 385                 vc4_state->x_scaling[1] =
 386                         vc4_get_scaling_mode(vc4_state->src_w[1],
 387                                              vc4_state->crtc_w);
 388                 vc4_state->y_scaling[1] =
 389                         vc4_get_scaling_mode(vc4_state->src_h[1],
 390                                              vc4_state->crtc_h);
 391
 392                 /* YUV conversion requires that horizontal scaling be enabled
 393                  * on the UV plane even if vc4_get_scaling_mode() returned
 394                  * VC4_SCALING_NONE (which can happen when the down-scaling
 395                  * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this
 396                  * case.
 397                  */
 398                 if (vc4_state->x_scaling[1] == VC4_SCALING_NONE)
 399                         vc4_state->x_scaling[1] = VC4_SCALING_PPF;
 400         } else {
 401                 vc4_state->is_yuv = false;
 402                 vc4_state->x_scaling[1] = VC4_SCALING_NONE;
 403                 vc4_state->y_scaling[1] = VC4_SCALING_NONE;
 404         }
 405
 406         return 0;
 407 }
 408
 409 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 410 {
 411         u32 scale, recip;
 412
 413         scale = (1 << 16) * src / dst;
 414
 415         /* The specs note that while the reciprocal would be defined
 416          * as (1<<32)/scale, ~0 is close enough.
 417          */
 418         recip = ~0 / scale;
 419
 420         vc4_dlist_write(vc4_state,
 421                         VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
 422                         VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
 423         vc4_dlist_write(vc4_state,
 424                         VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
 425 }
 426
 427 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 428 {
 429         u32 scale = (1 << 16) * src / dst;
 430
 431         vc4_dlist_write(vc4_state,
 432                         SCALER_PPF_AGC |
 433                         VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
 434                         VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
 435 }
 436
 437 static u32 vc4_lbm_size(struct drm_plane_state *state)
 438 {
 439         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 440         /* This is the worst case number.  One of the two sizes will
 441          * be used depending on the scaling configuration.
 442          */
 443         u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
 444         u32 lbm;
 445
 446         /* LBM is not needed when there's no vertical scaling. */
 447         if (vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
 448             vc4_state->y_scaling[1] == VC4_SCALING_NONE)
 449                 return 0;
 450
 451         if (!vc4_state->is_yuv) {
 452                 if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
 453                         lbm = pix_per_line * 8;
 454                 else {
 455                         /* In special cases, this multiplier might be 12. */
 456                         lbm = pix_per_line * 16;
 457                 }
 458         } else {
 459                 /* There are cases for this going down to a multiplier
 460                  * of 2, but according to the firmware source, the
 461                  * table in the docs is somewhat wrong.
 462                  */
 463                 lbm = pix_per_line * 16;
 464         }
 465
 466         lbm = roundup(lbm, 32);
 467
 468         return lbm;
 469 }
 470
 471 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
 472                                          int channel)
 473 {
 474         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 475
 476         /* Ch0 H-PPF Word 0: Scaling Parameters */
 477         if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
 478                 vc4_write_ppf(vc4_state,
 479                               vc4_state->src_w[channel], vc4_state->crtc_w);
 480         }
 481
 482         /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
 483         if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
 484                 vc4_write_ppf(vc4_state,
 485                               vc4_state->src_h[channel], vc4_state->crtc_h);
 486                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 487         }
 488
 489         /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
 490         if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
 491                 vc4_write_tpz(vc4_state,
 492                               vc4_state->src_w[channel], vc4_state->crtc_w);
 493         }
 494
 495         /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
 496         if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
 497                 vc4_write_tpz(vc4_state,
 498                               vc4_state->src_h[channel], vc4_state->crtc_h);
 499                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 500         }
 501 }
 502
 503 static void vc4_plane_calc_load(struct drm_plane_state *state)
 504 {
 505         unsigned int hvs_load_shift, vrefresh, i;
 506         struct drm_framebuffer *fb = state->fb;
 507         struct vc4_plane_state *vc4_state;
 508         struct drm_crtc_state *crtc_state;
 509         unsigned int vscale_factor;
 510
 511         vc4_state = to_vc4_plane_state(state);
 512         crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 513                                                         state->crtc);
 514         vrefresh = drm_mode_vrefresh(&crtc_state->adjusted_mode);
 515
 516         /* The HVS is able to process 2 pixels/cycle when scaling the source,
 517          * 4 pixels/cycle otherwise.
 518          * Alpha blending step seems to be pipelined and it's always operating
 519          * at 4 pixels/cycle, so the limiting aspect here seems to be the
 520          * scaler block.
 521          * HVS load is expressed in clk-cycles/sec (AKA Hz).
 522          */
 523         if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
 524             vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
 525             vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 526             vc4_state->y_scaling[1] != VC4_SCALING_NONE)
 527                 hvs_load_shift = 1;
 528         else
 529                 hvs_load_shift = 2;
 530
 531         vc4_state->membus_load = 0;
 532         vc4_state->hvs_load = 0;
 533         for (i = 0; i < fb->format->num_planes; i++) {
 534                 /* Even if the bandwidth/plane required for a single frame is
 535                  *
 536                  * vc4_state->src_w[i] * vc4_state->src_h[i] * cpp * vrefresh
 537                  *
 538                  * when downscaling, we have to read more pixels per line in
 539                  * the time frame reserved for a single line, so the bandwidth
 540                  * demand can be punctually higher. To account for that, we
 541                  * calculate the down-scaling factor and multiply the plane
 542                  * load by this number. We're likely over-estimating the read
 543                  * demand, but that's better than under-estimating it.
 544                  */
 545                 vscale_factor = DIV_ROUND_UP(vc4_state->src_h[i],
 546                                              vc4_state->crtc_h);
 547                 vc4_state->membus_load += vc4_state->src_w[i] *
 548                                           vc4_state->src_h[i] * vscale_factor *
 549                                           fb->format->cpp[i];
 550                 vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w;
 551         }
 552
 553         vc4_state->hvs_load *= vrefresh;
 554         vc4_state->hvs_load >>= hvs_load_shift;
 555         vc4_state->membus_load *= vrefresh;
 556 }
 557
 558 static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
 559 {
 560         struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
 561         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 562         unsigned long irqflags;
 563         u32 lbm_size;
 564
 565         lbm_size = vc4_lbm_size(state);
 566         if (!lbm_size)
 567                 return 0;
 568
 569         if (WARN_ON(!vc4_state->lbm_offset))
 570                 return -EINVAL;
 571
 572         /* Allocate the LBM memory that the HVS will use for temporary
 573          * storage due to our scaling/format conversion.
 574          */
 575         if (!drm_mm_node_allocated(&vc4_state->lbm)) {
 576                 int ret;
 577
 578                 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 579                 ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
 580                                                  &vc4_state->lbm,
 581                                                  lbm_size,
 582                                                  vc4->hvs->hvs5 ? 64 : 32,
 583                                                  0, 0);
 584                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 585
 586                 if (ret)
 587                         return ret;
 588         } else {
 589                 WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
 590         }
 591
 592         vc4_state->dlist[vc4_state->lbm_offset] = vc4_state->lbm.start;
 593
 594         return 0;
 595 }
 596
 597 /* Writes out a full display list for an active plane to the plane's
 598  * private dlist state.
 599  */
 600 static int vc4_plane_mode_set(struct drm_plane *plane,
 601                               struct drm_plane_state *state)
 602 {
 603         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 604         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 605         struct drm_framebuffer *fb = state->fb;
 606         u32 ctl0_offset = vc4_state->dlist_count;
 607         const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
 608         u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
 609         int num_planes = fb->format->num_planes;
 610         u32 h_subsample = fb->format->hsub;
 611         u32 v_subsample = fb->format->vsub;
 612         bool mix_plane_alpha;
 613         bool covers_screen;
 614         u32 scl0, scl1, pitch0;
 615         u32 tiling, src_y;
 616         u32 hvs_format = format->hvs;
 617         unsigned int rotation;
 618         int ret, i;
 619
 620         if (vc4_state->dlist_initialized)
 621                 return 0;
 622
 623         ret = vc4_plane_setup_clipping_and_scaling(state);
 624         if (ret)
 625                 return ret;
 626
 627         /* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
 628          * and 4:4:4, scl1 should be set to scl0 so both channels of
 629          * the scaler do the same thing.  For YUV, the Y plane needs
 630          * to be put in channel 1 and Cb/Cr in channel 0, so we swap
 631          * the scl fields here.
 632          */
 633         if (num_planes == 1) {
 634                 scl0 = vc4_get_scl_field(state, 0);
 635                 scl1 = scl0;
 636         } else {
 637                 scl0 = vc4_get_scl_field(state, 1);
 638                 scl1 = vc4_get_scl_field(state, 0);
 639         }
 640
 641         rotation = drm_rotation_simplify(state->rotation,
 642                                          DRM_MODE_ROTATE_0 |
 643                                          DRM_MODE_REFLECT_X |
 644                                          DRM_MODE_REFLECT_Y);
 645
 646         /* We must point to the last line when Y reflection is enabled. */
 647         src_y = vc4_state->src_y;
 648         if (rotation & DRM_MODE_REFLECT_Y)
 649                 src_y += vc4_state->src_h[0] - 1;
 650
 651         switch (base_format_mod) {
 652         case DRM_FORMAT_MOD_LINEAR:
 653                 tiling = SCALER_CTL0_TILING_LINEAR;
 654                 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
 655
 656                 /* Adjust the base pointer to the first pixel to be scanned
 657                  * out.
 658                  */
 659                 for (i = 0; i < num_planes; i++) {
 660                         vc4_state->offsets[i] += src_y /
 661                                                  (i ? v_subsample : 1) *
 662                                                  fb->pitches[i];
 663
 664                         vc4_state->offsets[i] += vc4_state->src_x /
 665                                                  (i ? h_subsample : 1) *
 666                                                  fb->format->cpp[i];
 667                 }
 668
 669                 break;
 670
 671         case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
 672                 u32 tile_size_shift = 12; /* T tiles are 4kb */
 673                 /* Whole-tile offsets, mostly for setting the pitch. */
 674                 u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
 675                 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
 676                 u32 tile_w_mask = (1 << tile_w_shift) - 1;
 677                 /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
 678                  * the height (in pixels) of a 4k tile.
 679                  */
 680                 u32 tile_h_mask = (2 << tile_h_shift) - 1;
 681                 /* For T-tiled, the FB pitch is "how many bytes from one row to
 682                  * the next, such that
 683                  *
 684                  *      pitch * tile_h == tile_size * tiles_per_row
 685                  */
 686                 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
 687                 u32 tiles_l = vc4_state->src_x >> tile_w_shift;
 688                 u32 tiles_r = tiles_w - tiles_l;
 689                 u32 tiles_t = src_y >> tile_h_shift;
 690                 /* Intra-tile offsets, which modify the base address (the
 691                  * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
 692                  * base address).
 693                  */
 694                 u32 tile_y = (src_y >> 4) & 1;
 695                 u32 subtile_y = (src_y >> 2) & 3;
 696                 u32 utile_y = src_y & 3;
 697                 u32 x_off = vc4_state->src_x & tile_w_mask;
 698                 u32 y_off = src_y & tile_h_mask;
 699
 700                 /* When Y reflection is requested we must set the
 701                  * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines
 702                  * after the initial one should be fetched in descending order,
 703                  * which makes sense since we start from the last line and go
 704                  * backward.
 705                  * Don't know why we need y_off = max_y_off - y_off, but it's
 706                  * definitely required (I guess it's also related to the "going
 707                  * backward" situation).
 708                  */
 709                 if (rotation & DRM_MODE_REFLECT_Y) {
 710                         y_off = tile_h_mask - y_off;
 711                         pitch0 = SCALER_PITCH0_TILE_LINE_DIR;
 712                 } else {
 713                         pitch0 = 0;
 714                 }
 715
 716                 tiling = SCALER_CTL0_TILING_256B_OR_T;
 717                 pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
 718                            VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
 719                            VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
 720                            VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
 721                 vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
 722                 vc4_state->offsets[0] += subtile_y << 8;
 723                 vc4_state->offsets[0] += utile_y << 4;
 724
 725                 /* Rows of tiles alternate left-to-right and right-to-left. */
 726                 if (tiles_t & 1) {
 727                         pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
 728                         vc4_state->offsets[0] += (tiles_w - tiles_l) <<
 729                                                  tile_size_shift;
 730                         vc4_state->offsets[0] -= (1 + !tile_y) << 10;
 731                 } else {
 732                         vc4_state->offsets[0] += tiles_l << tile_size_shift;
 733                         vc4_state->offsets[0] += tile_y << 10;
 734                 }
 735
 736                 break;
 737         }
 738
 739         case DRM_FORMAT_MOD_BROADCOM_SAND64:
 740         case DRM_FORMAT_MOD_BROADCOM_SAND128:
 741         case DRM_FORMAT_MOD_BROADCOM_SAND256: {
 742                 uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
 743                 u32 tile_w, tile, x_off, pix_per_tile;
 744
 745                 hvs_format = HVS_PIXEL_FORMAT_H264;
 746
 747                 switch (base_format_mod) {
 748                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
 749                         tiling = SCALER_CTL0_TILING_64B;
 750                         tile_w = 64;
 751                         break;
 752                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
 753                         tiling = SCALER_CTL0_TILING_128B;
 754                         tile_w = 128;
 755                         break;
 756                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
 757                         tiling = SCALER_CTL0_TILING_256B_OR_T;
 758                         tile_w = 256;
 759                         break;
 760                 default:
 761                         break;
 762                 }
 763
 764                 if (param > SCALER_TILE_HEIGHT_MASK) {
 765                         DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
 766                         return -EINVAL;
 767                 }
 768
 769                 pix_per_tile = tile_w / fb->format->cpp[0];
 770                 tile = vc4_state->src_x / pix_per_tile;
 771                 x_off = vc4_state->src_x % pix_per_tile;
 772
 773                 /* Adjust the base pointer to the first pixel to be scanned
 774                  * out.
 775                  */
 776                 for (i = 0; i < num_planes; i++) {
 777                         vc4_state->offsets[i] += param * tile_w * tile;
 778                         vc4_state->offsets[i] += src_y /
 779                                                  (i ? v_subsample : 1) *
 780                                                  tile_w;
 781                         vc4_state->offsets[i] += x_off /
 782                                                  (i ? h_subsample : 1) *
 783                                                  fb->format->cpp[i];
 784                 }
 785
 786                 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
 787                 break;
 788         }
 789
 790         default:
 791                 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
 792                               (long long)fb->modifier);
 793                 return -EINVAL;
 794         }
 795
 796         /* Don't waste cycles mixing with plane alpha if the set alpha
 797          * is opaque or there is no per-pixel alpha information.
 798          * In any case we use the alpha property value as the fixed alpha.
 799          */
 800         mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
 801                           fb->format->has_alpha;
 802
 803         if (!vc4->hvs->hvs5) {
 804         /* Control word */
 805                 vc4_dlist_write(vc4_state,
 806                                 SCALER_CTL0_VALID |
 807                                 (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
 808                                 (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
 809                                 VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
 810                                 (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
 811                                 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
 812                                 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
 813                                 (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
 814                                 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
 815                                 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
 816
 817                 /* Position Word 0: Image Positions and Alpha Value */
 818                 vc4_state->pos0_offset = vc4_state->dlist_count;
 819                 vc4_dlist_write(vc4_state,
 820                                 VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
 821                                 VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
 822                                 VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
 823
 824                 /* Position Word 1: Scaled Image Dimensions. */
 825                 if (!vc4_state->is_unity) {
 826                         vc4_dlist_write(vc4_state,
 827                                         VC4_SET_FIELD(vc4_state->crtc_w,
 828                                                       SCALER_POS1_SCL_WIDTH) |
 829                                         VC4_SET_FIELD(vc4_state->crtc_h,
 830                                                       SCALER_POS1_SCL_HEIGHT));
 831                 }
 832
 833                 /* Position Word 2: Source Image Size, Alpha */
 834                 vc4_state->pos2_offset = vc4_state->dlist_count;
 835                 vc4_dlist_write(vc4_state,
 836                                 VC4_SET_FIELD(fb->format->has_alpha ?
 837                                               SCALER_POS2_ALPHA_MODE_PIPELINE :
 838                                               SCALER_POS2_ALPHA_MODE_FIXED,
 839                                               SCALER_POS2_ALPHA_MODE) |
 840                                 (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
 841                                 (fb->format->has_alpha ?
 842                                                 SCALER_POS2_ALPHA_PREMULT : 0) |
 843                                 VC4_SET_FIELD(vc4_state->src_w[0],
 844                                               SCALER_POS2_WIDTH) |
 845                                 VC4_SET_FIELD(vc4_state->src_h[0],
 846                                               SCALER_POS2_HEIGHT));
 847
 848                 /* Position Word 3: Context.  Written by the HVS. */
 849                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 850
 851         } else {
 852                 u32 hvs_pixel_order = format->pixel_order;
 853
 854                 if (format->pixel_order_hvs5)
 855                         hvs_pixel_order = format->pixel_order_hvs5;
 856
 857                 /* Control word */
 858                 vc4_dlist_write(vc4_state,
 859                                 SCALER_CTL0_VALID |
 860                                 (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
 861                                 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
 862                                 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
 863                                 (vc4_state->is_unity ?
 864                                                 SCALER5_CTL0_UNITY : 0) |
 865                                 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
 866                                 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
 867                                 SCALER5_CTL0_ALPHA_EXPAND |
 868                                 SCALER5_CTL0_RGB_EXPAND);
 869
 870                 /* Position Word 0: Image Positions and Alpha Value */
 871                 vc4_state->pos0_offset = vc4_state->dlist_count;
 872                 vc4_dlist_write(vc4_state,
 873                                 (rotation & DRM_MODE_REFLECT_Y ?
 874                                                 SCALER5_POS0_VFLIP : 0) |
 875                                 VC4_SET_FIELD(vc4_state->crtc_x,
 876                                               SCALER_POS0_START_X) |
 877                                 (rotation & DRM_MODE_REFLECT_X ?
 878                                               SCALER5_POS0_HFLIP : 0) |
 879                                 VC4_SET_FIELD(vc4_state->crtc_y,
 880                                               SCALER5_POS0_START_Y)
 881                                );
 882
 883                 /* Control Word 2 */
 884                 vc4_dlist_write(vc4_state,
 885                                 VC4_SET_FIELD(state->alpha >> 4,
 886                                               SCALER5_CTL2_ALPHA) |
 887                                 fb->format->has_alpha ?
 888                                         SCALER5_CTL2_ALPHA_PREMULT : 0 |
 889                                 (mix_plane_alpha ?
 890                                         SCALER5_CTL2_ALPHA_MIX : 0) |
 891                                 VC4_SET_FIELD(fb->format->has_alpha ?
 892                                       SCALER5_CTL2_ALPHA_MODE_PIPELINE :
 893                                       SCALER5_CTL2_ALPHA_MODE_FIXED,
 894                                       SCALER5_CTL2_ALPHA_MODE)
 895                                );
 896
 897                 /* Position Word 1: Scaled Image Dimensions. */
 898                 if (!vc4_state->is_unity) {
 899                         vc4_dlist_write(vc4_state,
 900                                         VC4_SET_FIELD(vc4_state->crtc_w,
 901                                                       SCALER_POS1_SCL_WIDTH) |
 902                                         VC4_SET_FIELD(vc4_state->crtc_h,
 903                                                       SCALER_POS1_SCL_HEIGHT));
 904                 }
 905
 906                 /* Position Word 2: Source Image Size */
 907                 vc4_state->pos2_offset = vc4_state->dlist_count;
 908                 vc4_dlist_write(vc4_state,
 909                                 VC4_SET_FIELD(vc4_state->src_w[0],
 910                                               SCALER5_POS2_WIDTH) |
 911                                 VC4_SET_FIELD(vc4_state->src_h[0],
 912                                               SCALER5_POS2_HEIGHT));
 913
 914                 /* Position Word 3: Context.  Written by the HVS. */
 915                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 916         }
 917
 918
 919         /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
 920          *
 921          * The pointers may be any byte address.
 922          */
 923         vc4_state->ptr0_offset = vc4_state->dlist_count;
 924         for (i = 0; i < num_planes; i++)
 925                 vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
 926
 927         /* Pointer Context Word 0/1/2: Written by the HVS */
 928         for (i = 0; i < num_planes; i++)
 929                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 930
 931         /* Pitch word 0 */
 932         vc4_dlist_write(vc4_state, pitch0);
 933
 934         /* Pitch word 1/2 */
 935         for (i = 1; i < num_planes; i++) {
 936                 if (hvs_format != HVS_PIXEL_FORMAT_H264) {
 937                         vc4_dlist_write(vc4_state,
 938                                         VC4_SET_FIELD(fb->pitches[i],
 939                                                       SCALER_SRC_PITCH));
 940                 } else {
 941                         vc4_dlist_write(vc4_state, pitch0);
 942                 }
 943         }
 944
 945         /* Colorspace conversion words */
 946         if (vc4_state->is_yuv) {
 947                 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
 948                 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
 949                 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
 950         }
 951
 952         vc4_state->lbm_offset = 0;
 953
 954         if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
 955             vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
 956             vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 957             vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
 958                 /* Reserve a slot for the LBM Base Address. The real value will
 959                  * be set when calling vc4_plane_allocate_lbm().
 960                  */
 961                 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 962                     vc4_state->y_scaling[1] != VC4_SCALING_NONE)
 963                         vc4_state->lbm_offset = vc4_state->dlist_count++;
 964
 965                 if (num_planes > 1) {
 966                         /* Emit Cb/Cr as channel 0 and Y as channel
 967                          * 1. This matches how we set up scl0/scl1
 968                          * above.
 969                          */
 970                         vc4_write_scaling_parameters(state, 1);
 971                 }
 972                 vc4_write_scaling_parameters(state, 0);
 973
 974                 /* If any PPF setup was done, then all the kernel
 975                  * pointers get uploaded.
 976                  */
 977                 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
 978                     vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
 979                     vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
 980                     vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
 981                         u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
 982                                                    SCALER_PPF_KERNEL_OFFSET);
 983
 984                         /* HPPF plane 0 */
 985                         vc4_dlist_write(vc4_state, kernel);
 986                         /* VPPF plane 0 */
 987                         vc4_dlist_write(vc4_state, kernel);
 988                         /* HPPF plane 1 */
 989                         vc4_dlist_write(vc4_state, kernel);
 990                         /* VPPF plane 1 */
 991                         vc4_dlist_write(vc4_state, kernel);
 992                 }
 993         }
 994
 995         vc4_state->dlist[ctl0_offset] |=
 996                 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
 997
 998         /* crtc_* are already clipped coordinates. */
 999         covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
1000                         vc4_state->crtc_w == state->crtc->mode.hdisplay &&
1001                         vc4_state->crtc_h == state->crtc->mode.vdisplay;
1002         /* Background fill might be necessary when the plane has per-pixel
1003          * alpha content or a non-opaque plane alpha and could blend from the
1004          * background or does not cover the entire screen.
1005          */
1006         vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
1007                                    state->alpha != DRM_BLEND_ALPHA_OPAQUE;
1008
1009         /* Flag the dlist as initialized to avoid checking it twice in case
1010          * the async update check already called vc4_plane_mode_set() and
1011          * decided to fallback to sync update because async update was not
1012          * possible.
1013          */
1014         vc4_state->dlist_initialized = 1;
1015
1016         vc4_plane_calc_load(state);
1017
1018         return 0;
1019 }
1020
1021 /* If a modeset involves changing the setup of a plane, the atomic
1022  * infrastructure will call this to validate a proposed plane setup.
1023  * However, if a plane isn't getting updated, this (and the
1024  * corresponding vc4_plane_atomic_update) won't get called.  Thus, we
1025  * compute the dlist here and have all active plane dlists get updated
1026  * in the CRTC's flush.
1027  */
1028 static int vc4_plane_atomic_check(struct drm_plane *plane,
1029                                   struct drm_plane_state *state)
1030 {
1031         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
1032         int ret;
1033
1034         vc4_state->dlist_count = 0;
1035
1036         if (!plane_enabled(state))
1037                 return 0;
1038
1039         ret = vc4_plane_mode_set(plane, state);
1040         if (ret)
1041                 return ret;
1042
1043         return vc4_plane_allocate_lbm(state);
1044 }
1045
1046 static void vc4_plane_atomic_update(struct drm_plane *plane,
1047                                     struct drm_plane_state *old_state)
1048 {
1049         /* No contents here.  Since we don't know where in the CRTC's
1050          * dlist we should be stored, our dlist is uploaded to the
1051          * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
1052          * time.
1053          */
1054 }
1055
1056 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
1057 {
1058         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
1059         int i;
1060
1061         vc4_state->hw_dlist = dlist;
1062
1063         /* Can't memcpy_toio() because it needs to be 32-bit writes. */
1064         for (i = 0; i < vc4_state->dlist_count; i++)
1065                 writel(vc4_state->dlist[i], &dlist[i]);
1066
1067         return vc4_state->dlist_count;
1068 }
1069
1070 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
1071 {
1072         const struct vc4_plane_state *vc4_state =
1073                 container_of(state, typeof(*vc4_state), base);
1074
1075         return vc4_state->dlist_count;
1076 }
1077
1078 /* Updates the plane to immediately (well, once the FIFO needs
1079  * refilling) scan out from at a new framebuffer.
1080  */
1081 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
1082 {
1083         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
1084         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
1085         uint32_t addr;
1086
1087         /* We're skipping the address adjustment for negative origin,
1088          * because this is only called on the primary plane.
1089          */
1090         WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
1091         addr = bo->paddr + fb->offsets[0];
1092
1093         /* Write the new address into the hardware immediately.  The
1094          * scanout will start from this address as soon as the FIFO
1095          * needs to refill with pixels.
1096          */
1097         writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
1098
1099         /* Also update the CPU-side dlist copy, so that any later
1100          * atomic updates that don't do a new modeset on our plane
1101          * also use our updated address.
1102          */
1103         vc4_state->dlist[vc4_state->ptr0_offset] = addr;
1104 }
1105
1106 static void vc4_plane_atomic_async_update(struct drm_plane *plane,
1107                                           struct drm_plane_state *state)
1108 {
1109         struct vc4_plane_state *vc4_state, *new_vc4_state;
1110
1111         swap(plane->state->fb, state->fb);
1112         plane->state->crtc_x = state->crtc_x;
1113         plane->state->crtc_y = state->crtc_y;
1114         plane->state->crtc_w = state->crtc_w;
1115         plane->state->crtc_h = state->crtc_h;
1116         plane->state->src_x = state->src_x;
1117         plane->state->src_y = state->src_y;
1118         plane->state->src_w = state->src_w;
1119         plane->state->src_h = state->src_h;
1120         plane->state->src_h = state->src_h;
1121         plane->state->alpha = state->alpha;
1122         plane->state->pixel_blend_mode = state->pixel_blend_mode;
1123         plane->state->rotation = state->rotation;
1124         plane->state->zpos = state->zpos;
1125         plane->state->normalized_zpos = state->normalized_zpos;
1126         plane->state->color_encoding = state->color_encoding;
1127         plane->state->color_range = state->color_range;
1128         plane->state->src = state->src;
1129         plane->state->dst = state->dst;
1130         plane->state->visible = state->visible;
1131
1132         new_vc4_state = to_vc4_plane_state(state);
1133         vc4_state = to_vc4_plane_state(plane->state);
1134
1135         vc4_state->crtc_x = new_vc4_state->crtc_x;
1136         vc4_state->crtc_y = new_vc4_state->crtc_y;
1137         vc4_state->crtc_h = new_vc4_state->crtc_h;
1138         vc4_state->crtc_w = new_vc4_state->crtc_w;
1139         vc4_state->src_x = new_vc4_state->src_x;
1140         vc4_state->src_y = new_vc4_state->src_y;
1141         memcpy(vc4_state->src_w, new_vc4_state->src_w,
1142                sizeof(vc4_state->src_w));
1143         memcpy(vc4_state->src_h, new_vc4_state->src_h,
1144                sizeof(vc4_state->src_h));
1145         memcpy(vc4_state->x_scaling, new_vc4_state->x_scaling,
1146                sizeof(vc4_state->x_scaling));
1147         memcpy(vc4_state->y_scaling, new_vc4_state->y_scaling,
1148                sizeof(vc4_state->y_scaling));
1149         vc4_state->is_unity = new_vc4_state->is_unity;
1150         vc4_state->is_yuv = new_vc4_state->is_yuv;
1151         memcpy(vc4_state->offsets, new_vc4_state->offsets,
1152                sizeof(vc4_state->offsets));
1153         vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill;
1154
1155         /* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */
1156         vc4_state->dlist[vc4_state->pos0_offset] =
1157                 new_vc4_state->dlist[vc4_state->pos0_offset];
1158         vc4_state->dlist[vc4_state->pos2_offset] =
1159                 new_vc4_state->dlist[vc4_state->pos2_offset];
1160         vc4_state->dlist[vc4_state->ptr0_offset] =
1161                 new_vc4_state->dlist[vc4_state->ptr0_offset];
1162
1163         /* Note that we can't just call vc4_plane_write_dlist()
1164          * because that would smash the context data that the HVS is
1165          * currently using.
1166          */
1167         writel(vc4_state->dlist[vc4_state->pos0_offset],
1168                &vc4_state->hw_dlist[vc4_state->pos0_offset]);
1169         writel(vc4_state->dlist[vc4_state->pos2_offset],
1170                &vc4_state->hw_dlist[vc4_state->pos2_offset]);
1171         writel(vc4_state->dlist[vc4_state->ptr0_offset],
1172                &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
1173 }
1174
1175 static int vc4_plane_atomic_async_check(struct drm_plane *plane,
1176                                         struct drm_plane_state *state)
1177 {
1178         struct vc4_plane_state *old_vc4_state, *new_vc4_state;
1179         int ret;
1180         u32 i;
1181
1182         ret = vc4_plane_mode_set(plane, state);
1183         if (ret)
1184                 return ret;
1185
1186         old_vc4_state = to_vc4_plane_state(plane->state);
1187         new_vc4_state = to_vc4_plane_state(state);
1188         if (old_vc4_state->dlist_count != new_vc4_state->dlist_count ||
1189             old_vc4_state->pos0_offset != new_vc4_state->pos0_offset ||
1190             old_vc4_state->pos2_offset != new_vc4_state->pos2_offset ||
1191             old_vc4_state->ptr0_offset != new_vc4_state->ptr0_offset ||
1192             vc4_lbm_size(plane->state) != vc4_lbm_size(state))
1193                 return -EINVAL;
1194
1195         /* Only pos0, pos2 and ptr0 DWORDS can be updated in an async update
1196          * if anything else has changed, fallback to a sync update.
1197          */
1198         for (i = 0; i < new_vc4_state->dlist_count; i++) {
1199                 if (i == new_vc4_state->pos0_offset ||
1200                     i == new_vc4_state->pos2_offset ||
1201                     i == new_vc4_state->ptr0_offset ||
1202                     (new_vc4_state->lbm_offset &&
1203                      i == new_vc4_state->lbm_offset))
1204                         continue;
1205
1206                 if (new_vc4_state->dlist[i] != old_vc4_state->dlist[i])
1207                         return -EINVAL;
1208         }
1209
1210         return 0;
1211 }
1212
1213 static int vc4_prepare_fb(struct drm_plane *plane,
1214                           struct drm_plane_state *state)
1215 {
1216         struct vc4_bo *bo;
1217         int ret;
1218
1219         if (!state->fb)
1220                 return 0;
1221
1222         bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
1223
1224         drm_gem_fb_prepare_fb(plane, state);
1225
1226         if (plane->state->fb == state->fb)
1227                 return 0;
1228
1229         ret = vc4_bo_inc_usecnt(bo);
1230         if (ret)
1231                 return ret;
1232
1233         return 0;
1234 }
1235
1236 static void vc4_cleanup_fb(struct drm_plane *plane,
1237                            struct drm_plane_state *state)
1238 {
1239         struct vc4_bo *bo;
1240
1241         if (plane->state->fb == state->fb || !state->fb)
1242                 return;
1243
1244         bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
1245         vc4_bo_dec_usecnt(bo);
1246 }
1247
1248 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
1249         .atomic_check = vc4_plane_atomic_check,
1250         .atomic_update = vc4_plane_atomic_update,
1251         .prepare_fb = vc4_prepare_fb,
1252         .cleanup_fb = vc4_cleanup_fb,
1253         .atomic_async_check = vc4_plane_atomic_async_check,
1254         .atomic_async_update = vc4_plane_atomic_async_update,
1255 };
1256
1257 static void vc4_plane_destroy(struct drm_plane *plane)
1258 {
1259         drm_plane_cleanup(plane);
1260 }
1261
1262 static bool vc4_format_mod_supported(struct drm_plane *plane,
1263                                      uint32_t format,
1264                                      uint64_t modifier)
1265 {
1266         /* Support T_TILING for RGB formats only. */
1267         switch (format) {
1268         case DRM_FORMAT_XRGB8888:
1269         case DRM_FORMAT_ARGB8888:
1270         case DRM_FORMAT_ABGR8888:
1271         case DRM_FORMAT_XBGR8888:
1272         case DRM_FORMAT_RGB565:
1273         case DRM_FORMAT_BGR565:
1274         case DRM_FORMAT_ARGB1555:
1275         case DRM_FORMAT_XRGB1555:
1276                 switch (fourcc_mod_broadcom_mod(modifier)) {
1277                 case DRM_FORMAT_MOD_LINEAR:
1278                 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
1279                         return true;
1280                 default:
1281                         return false;
1282                 }
1283         case DRM_FORMAT_NV12:
1284         case DRM_FORMAT_NV21:
1285                 switch (fourcc_mod_broadcom_mod(modifier)) {
1286                 case DRM_FORMAT_MOD_LINEAR:
1287                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
1288                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
1289                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
1290                         return true;
1291                 default:
1292                         return false;
1293                 }
1294         case DRM_FORMAT_RGBX1010102:
1295         case DRM_FORMAT_BGRX1010102:
1296         case DRM_FORMAT_RGBA1010102:
1297         case DRM_FORMAT_BGRA1010102:
1298         case DRM_FORMAT_YUV422:
1299         case DRM_FORMAT_YVU422:
1300         case DRM_FORMAT_YUV420:
1301         case DRM_FORMAT_YVU420:
1302         case DRM_FORMAT_NV16:
1303         case DRM_FORMAT_NV61:
1304         default:
1305                 return (modifier == DRM_FORMAT_MOD_LINEAR);
1306         }
1307 }
1308
1309 static const struct drm_plane_funcs vc4_plane_funcs = {
1310         .update_plane = drm_atomic_helper_update_plane,
1311         .disable_plane = drm_atomic_helper_disable_plane,
1312         .destroy = vc4_plane_destroy,
1313         .set_property = NULL,
1314         .reset = vc4_plane_reset,
1315         .atomic_duplicate_state = vc4_plane_duplicate_state,
1316         .atomic_destroy_state = vc4_plane_destroy_state,
1317         .format_mod_supported = vc4_format_mod_supported,
1318 };
1319
1320 struct drm_plane *vc4_plane_init(struct drm_device *dev,
1321                                  enum drm_plane_type type)
1322 {
1323         struct drm_plane *plane = NULL;
1324         struct vc4_plane *vc4_plane;
1325         u32 formats[ARRAY_SIZE(hvs_formats)];
1326         int ret = 0;
1327         unsigned i;
1328         static const uint64_t modifiers[] = {
1329                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
1330                 DRM_FORMAT_MOD_BROADCOM_SAND128,
1331                 DRM_FORMAT_MOD_BROADCOM_SAND64,
1332                 DRM_FORMAT_MOD_BROADCOM_SAND256,
1333                 DRM_FORMAT_MOD_LINEAR,
1334                 DRM_FORMAT_MOD_INVALID
1335         };
1336
1337         vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
1338                                  GFP_KERNEL);
1339         if (!vc4_plane)
1340                 return ERR_PTR(-ENOMEM);
1341
1342         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++)
1343                 formats[i] = hvs_formats[i].drm;
1344
1345         plane = &vc4_plane->base;
1346         ret = drm_universal_plane_init(dev, plane, 0,
1347                                        &vc4_plane_funcs,
1348                                        formats, ARRAY_SIZE(formats),
1349                                        modifiers, type, NULL);
1350
1351         drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
1352
1353         drm_plane_create_alpha_property(plane);
1354         drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1355                                            DRM_MODE_ROTATE_0 |
1356                                            DRM_MODE_ROTATE_180 |
1357                                            DRM_MODE_REFLECT_X |
1358                                            DRM_MODE_REFLECT_Y);
1359
1360         return plane;
1361 }
1362
1363 int vc4_plane_create_additional_planes(struct drm_device *drm)
1364 {
1365         struct drm_plane *cursor_plane;
1366         struct drm_crtc *crtc;
1367         unsigned int i;
1368
1369         /* Set up some arbitrary number of planes.  We're not limited
1370          * by a set number of physical registers, just the space in
1371          * the HVS (16k) and how small an plane can be (28 bytes).
1372          * However, each plane we set up takes up some memory, and
1373          * increases the cost of looping over planes, which atomic
1374          * modesetting does quite a bit.  As a result, we pick a
1375          * modest number of planes to expose, that should hopefully
1376          * still cover any sane usecase.
1377          */
1378         for (i = 0; i < 8; i++) {
1379                 struct drm_plane *plane =
1380                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1381
1382                 if (IS_ERR(plane))
1383                         continue;
1384
1385                 plane->possible_crtcs =
1386                         GENMASK(drm->mode_config.num_crtc - 1, 0);
1387         }
1388
1389         drm_for_each_crtc(crtc, drm) {
1390                 /* Set up the legacy cursor after overlay initialization,
1391                  * since we overlay planes on the CRTC in the order they were
1392                  * initialized.
1393                  */
1394                 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1395                 if (!IS_ERR(cursor_plane)) {
1396                         cursor_plane->possible_crtcs = drm_crtc_mask(crtc);
1397                         crtc->cursor = cursor_plane;
1398                 }
1399         }
1400
1401         return 0;
1402 }