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25 * DOC: Interrupt management for the V3D engine
27 * We have an interrupt status register (V3D_INTCTL) which reports
28 * interrupts, and where writing 1 bits clears those interrupts.
29 * There are also a pair of interrupt registers
30 * (V3D_INTENA/V3D_INTDIS) where writing a 1 to their bits enables or
31 * disables that specific interrupt, and 0s written are ignored
32 * (reading either one returns the set of enabled interrupts).
34 * When we take a binning flush done interrupt, we need to submit the
35 * next frame for binning and move the finished frame to the render
38 * When we take a render frame interrupt, we need to wake the
39 * processes waiting for some frame to be done, and get the next frame
40 * submitted ASAP (so the hardware doesn't sit idle when there's work
43 * When we take the binner out of memory interrupt, we need to
44 * allocate some new memory and pass it to the binner so that the
45 * current job can make progress.
48 #include <linux/platform_device.h>
50 #include <drm/drm_drv.h>
54 #include "vc4_trace.h"
56 #define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \
60 DECLARE_WAIT_QUEUE_HEAD(render_wait);
63 vc4_overflow_mem_work(struct work_struct *work)
66 container_of(work, struct vc4_dev, overflow_mem_work);
69 struct vc4_exec_info *exec;
70 unsigned long irqflags;
72 mutex_lock(&vc4->bin_bo_lock);
79 bin_bo_slot = vc4_v3d_get_bin_slot(vc4);
80 if (bin_bo_slot < 0) {
81 DRM_ERROR("Couldn't allocate binner overflow mem\n");
85 spin_lock_irqsave(&vc4->job_lock, irqflags);
87 if (vc4->bin_alloc_overflow) {
88 /* If we had overflow memory allocated previously,
89 * then that chunk will free when the current bin job
90 * is done. If we don't have a bin job running, then
91 * the chunk will be done whenever the list of render
94 exec = vc4_first_bin_job(vc4);
96 exec = vc4_last_render_job(vc4);
98 exec->bin_slots |= vc4->bin_alloc_overflow;
100 /* There's nothing queued in the hardware, so
101 * the old slot is free immediately.
103 vc4->bin_alloc_used &= ~vc4->bin_alloc_overflow;
106 vc4->bin_alloc_overflow = BIT(bin_bo_slot);
108 V3D_WRITE(V3D_BPOA, bo->base.dma_addr + bin_bo_slot * vc4->bin_alloc_size);
109 V3D_WRITE(V3D_BPOS, bo->base.base.size);
110 V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM);
111 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
112 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
115 mutex_unlock(&vc4->bin_bo_lock);
119 vc4_irq_finish_bin_job(struct drm_device *dev)
121 struct vc4_dev *vc4 = to_vc4_dev(dev);
122 struct vc4_exec_info *next, *exec = vc4_first_bin_job(vc4);
127 trace_vc4_bcl_end_irq(dev, exec->seqno);
129 vc4_move_job_to_render(dev, exec);
130 next = vc4_first_bin_job(vc4);
132 /* Only submit the next job in the bin list if it matches the perfmon
133 * attached to the one that just finished (or if both jobs don't have
134 * perfmon attached to them).
136 if (next && next->perfmon == exec->perfmon)
137 vc4_submit_next_bin_job(dev);
141 vc4_cancel_bin_job(struct drm_device *dev)
143 struct vc4_dev *vc4 = to_vc4_dev(dev);
144 struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
149 /* Stop the perfmon so that the next bin job can be started. */
151 vc4_perfmon_stop(vc4, exec->perfmon, false);
153 list_move_tail(&exec->head, &vc4->bin_job_list);
154 vc4_submit_next_bin_job(dev);
158 vc4_irq_finish_render_job(struct drm_device *dev)
160 struct vc4_dev *vc4 = to_vc4_dev(dev);
161 struct vc4_exec_info *exec = vc4_first_render_job(vc4);
162 struct vc4_exec_info *nextbin, *nextrender;
167 trace_vc4_rcl_end_irq(dev, exec->seqno);
169 vc4->finished_seqno++;
170 list_move_tail(&exec->head, &vc4->job_done_list);
172 nextbin = vc4_first_bin_job(vc4);
173 nextrender = vc4_first_render_job(vc4);
175 /* Only stop the perfmon if following jobs in the queue don't expect it
178 if (exec->perfmon && !nextrender &&
179 (!nextbin || nextbin->perfmon != exec->perfmon))
180 vc4_perfmon_stop(vc4, exec->perfmon, true);
182 /* If there's a render job waiting, start it. If this is not the case
183 * we may have to unblock the binner if it's been stalled because of
184 * perfmon (this can be checked by comparing the perfmon attached to
185 * the finished renderjob to the one attached to the next bin job: if
186 * they don't match, this means the binner is stalled and should be
190 vc4_submit_next_render_job(dev);
191 else if (nextbin && nextbin->perfmon != exec->perfmon)
192 vc4_submit_next_bin_job(dev);
195 dma_fence_signal_locked(exec->fence);
196 dma_fence_put(exec->fence);
200 wake_up_all(&vc4->job_wait_queue);
201 schedule_work(&vc4->job_done_work);
205 vc4_irq(int irq, void *arg)
207 struct drm_device *dev = arg;
208 struct vc4_dev *vc4 = to_vc4_dev(dev);
210 irqreturn_t status = IRQ_NONE;
213 intctl = V3D_READ(V3D_INTCTL);
215 /* Acknowledge the interrupts we're handling here. The binner
216 * last flush / render frame done interrupt will be cleared,
217 * while OUTOMEM will stay high until the underlying cause is
220 V3D_WRITE(V3D_INTCTL, intctl);
222 if (intctl & V3D_INT_OUTOMEM) {
223 /* Disable OUTOMEM until the work is done. */
224 V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM);
225 schedule_work(&vc4->overflow_mem_work);
226 status = IRQ_HANDLED;
229 if (intctl & V3D_INT_FLDONE) {
230 spin_lock(&vc4->job_lock);
231 vc4_irq_finish_bin_job(dev);
232 spin_unlock(&vc4->job_lock);
233 status = IRQ_HANDLED;
236 if (intctl & V3D_INT_FRDONE) {
237 spin_lock(&vc4->job_lock);
238 vc4_irq_finish_render_job(dev);
239 spin_unlock(&vc4->job_lock);
240 status = IRQ_HANDLED;
247 vc4_irq_prepare(struct drm_device *dev)
249 struct vc4_dev *vc4 = to_vc4_dev(dev);
254 init_waitqueue_head(&vc4->job_wait_queue);
255 INIT_WORK(&vc4->overflow_mem_work, vc4_overflow_mem_work);
257 /* Clear any pending interrupts someone might have left around
260 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
264 vc4_irq_enable(struct drm_device *dev)
266 struct vc4_dev *vc4 = to_vc4_dev(dev);
268 if (WARN_ON_ONCE(vc4->is_vc5))
274 /* Enable the render done interrupts. The out-of-memory interrupt is
275 * enabled as soon as we have a binner BO allocated.
277 V3D_WRITE(V3D_INTENA, V3D_INT_FLDONE | V3D_INT_FRDONE);
281 vc4_irq_disable(struct drm_device *dev)
283 struct vc4_dev *vc4 = to_vc4_dev(dev);
285 if (WARN_ON_ONCE(vc4->is_vc5))
291 /* Disable sending interrupts for our driver's IRQs. */
292 V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS);
294 /* Clear any pending interrupts we might have left. */
295 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
297 /* Finish any interrupt handler still in flight. */
298 synchronize_irq(vc4->irq);
300 cancel_work_sync(&vc4->overflow_mem_work);
303 int vc4_irq_install(struct drm_device *dev, int irq)
305 struct vc4_dev *vc4 = to_vc4_dev(dev);
308 if (WARN_ON_ONCE(vc4->is_vc5))
311 if (irq == IRQ_NOTCONNECTED)
314 vc4_irq_prepare(dev);
316 ret = request_irq(irq, vc4_irq, 0, dev->driver->name, dev);
325 void vc4_irq_uninstall(struct drm_device *dev)
327 struct vc4_dev *vc4 = to_vc4_dev(dev);
329 if (WARN_ON_ONCE(vc4->is_vc5))
332 vc4_irq_disable(dev);
333 free_irq(vc4->irq, dev);
336 /** Reinitializes interrupt registers when a GPU reset is performed. */
337 void vc4_irq_reset(struct drm_device *dev)
339 struct vc4_dev *vc4 = to_vc4_dev(dev);
340 unsigned long irqflags;
342 if (WARN_ON_ONCE(vc4->is_vc5))
345 /* Acknowledge any stale IRQs. */
346 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
349 * Turn all our interrupts on. Binner out of memory is the
350 * only one we expect to trigger at this point, since we've
351 * just come from poweron and haven't supplied any overflow
354 V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
356 spin_lock_irqsave(&vc4->job_lock, irqflags);
357 vc4_cancel_bin_job(dev);
358 vc4_irq_finish_render_job(dev);
359 spin_unlock_irqrestore(&vc4->job_lock, irqflags);