drivers/gpu/drm/vc4/vc4_hvs.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 HVS module.
   8  *
   9  * The Hardware Video Scaler (HVS) is the piece of hardware that does
  10  * translation, scaling, colorspace conversion, and compositing of
  11  * pixels stored in framebuffers into a FIFO of pixels going out to
  12  * the Pixel Valve (CRTC).  It operates at the system clock rate (the
  13  * system audio clock gate, specifically), which is much higher than
  14  * the pixel clock rate.
  15  *
  16  * There is a single global HVS, with multiple output FIFOs that can
  17  * be consumed by the PVs.  This file just manages the resources for
  18  * the HVS, while the vc4_crtc.c code actually drives HVS setup for
  19  * each CRTC.
  20  */
  21
  22 #include <linux/bitfield.h>
  23 #include <linux/clk.h>
  24 #include <linux/component.h>
  25 #include <linux/platform_device.h>
  26
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_vblank.h>
  29
  30 #include "vc4_drv.h"
  31 #include "vc4_regs.h"
  32
  33 static const struct debugfs_reg32 hvs_regs[] = {
  34         VC4_REG32(SCALER_DISPCTRL),
  35         VC4_REG32(SCALER_DISPSTAT),
  36         VC4_REG32(SCALER_DISPID),
  37         VC4_REG32(SCALER_DISPECTRL),
  38         VC4_REG32(SCALER_DISPPROF),
  39         VC4_REG32(SCALER_DISPDITHER),
  40         VC4_REG32(SCALER_DISPEOLN),
  41         VC4_REG32(SCALER_DISPLIST0),
  42         VC4_REG32(SCALER_DISPLIST1),
  43         VC4_REG32(SCALER_DISPLIST2),
  44         VC4_REG32(SCALER_DISPLSTAT),
  45         VC4_REG32(SCALER_DISPLACT0),
  46         VC4_REG32(SCALER_DISPLACT1),
  47         VC4_REG32(SCALER_DISPLACT2),
  48         VC4_REG32(SCALER_DISPCTRL0),
  49         VC4_REG32(SCALER_DISPBKGND0),
  50         VC4_REG32(SCALER_DISPSTAT0),
  51         VC4_REG32(SCALER_DISPBASE0),
  52         VC4_REG32(SCALER_DISPCTRL1),
  53         VC4_REG32(SCALER_DISPBKGND1),
  54         VC4_REG32(SCALER_DISPSTAT1),
  55         VC4_REG32(SCALER_DISPBASE1),
  56         VC4_REG32(SCALER_DISPCTRL2),
  57         VC4_REG32(SCALER_DISPBKGND2),
  58         VC4_REG32(SCALER_DISPSTAT2),
  59         VC4_REG32(SCALER_DISPBASE2),
  60         VC4_REG32(SCALER_DISPALPHA2),
  61         VC4_REG32(SCALER_OLEDOFFS),
  62         VC4_REG32(SCALER_OLEDCOEF0),
  63         VC4_REG32(SCALER_OLEDCOEF1),
  64         VC4_REG32(SCALER_OLEDCOEF2),
  65 };
  66
  67 void vc4_hvs_dump_state(struct drm_device *dev)
  68 {
  69         struct vc4_dev *vc4 = to_vc4_dev(dev);
  70         struct drm_printer p = drm_info_printer(&vc4->hvs->pdev->dev);
  71         int i;
  72
  73         drm_print_regset32(&p, &vc4->hvs->regset);
  74
  75         DRM_INFO("HVS ctx:\n");
  76         for (i = 0; i < 64; i += 4) {
  77                 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
  78                          i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
  79                          readl((u32 __iomem *)vc4->hvs->dlist + i + 0),
  80                          readl((u32 __iomem *)vc4->hvs->dlist + i + 1),
  81                          readl((u32 __iomem *)vc4->hvs->dlist + i + 2),
  82                          readl((u32 __iomem *)vc4->hvs->dlist + i + 3));
  83         }
  84 }
  85
  86 static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data)
  87 {
  88         struct drm_info_node *node = m->private;
  89         struct drm_device *dev = node->minor->dev;
  90         struct vc4_dev *vc4 = to_vc4_dev(dev);
  91         struct drm_printer p = drm_seq_file_printer(m);
  92
  93         drm_printf(&p, "%d\n", atomic_read(&vc4->underrun));
  94
  95         return 0;
  96 }
  97
  98 /* The filter kernel is composed of dwords each containing 3 9-bit
  99  * signed integers packed next to each other.
 100  */
 101 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
 102 #define VC4_PPF_FILTER_WORD(c0, c1, c2)                         \
 103         ((((c0) & 0x1ff) << 0) |                                \
 104          (((c1) & 0x1ff) << 9) |                                \
 105          (((c2) & 0x1ff) << 18))
 106
 107 /* The whole filter kernel is arranged as the coefficients 0-16 going
 108  * up, then a pad, then 17-31 going down and reversed within the
 109  * dwords.  This means that a linear phase kernel (where it's
 110  * symmetrical at the boundary between 15 and 16) has the last 5
 111  * dwords matching the first 5, but reversed.
 112  */
 113 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8,     \
 114                                 c9, c10, c11, c12, c13, c14, c15)       \
 115         {VC4_PPF_FILTER_WORD(c0, c1, c2),                               \
 116          VC4_PPF_FILTER_WORD(c3, c4, c5),                               \
 117          VC4_PPF_FILTER_WORD(c6, c7, c8),                               \
 118          VC4_PPF_FILTER_WORD(c9, c10, c11),                             \
 119          VC4_PPF_FILTER_WORD(c12, c13, c14),                            \
 120          VC4_PPF_FILTER_WORD(c15, c15, 0)}
 121
 122 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6
 123 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
 124
 125 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
 126  * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
 127  */
 128 static const u32 mitchell_netravali_1_3_1_3_kernel[] =
 129         VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
 130                                 50, 82, 119, 155, 187, 213, 227);
 131
 132 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
 133                                         struct drm_mm_node *space,
 134                                         const u32 *kernel)
 135 {
 136         int ret, i;
 137         u32 __iomem *dst_kernel;
 138
 139         ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS);
 140         if (ret) {
 141                 DRM_ERROR("Failed to allocate space for filter kernel: %d\n",
 142                           ret);
 143                 return ret;
 144         }
 145
 146         dst_kernel = hvs->dlist + space->start;
 147
 148         for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
 149                 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS)
 150                         writel(kernel[i], &dst_kernel[i]);
 151                 else {
 152                         writel(kernel[VC4_KERNEL_DWORDS - i - 1],
 153                                &dst_kernel[i]);
 154                 }
 155         }
 156
 157         return 0;
 158 }
 159
 160 static void vc4_hvs_lut_load(struct drm_crtc *crtc)
 161 {
 162         struct drm_device *dev = crtc->dev;
 163         struct vc4_dev *vc4 = to_vc4_dev(dev);
 164         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 165         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 166         u32 i;
 167
 168         /* The LUT memory is laid out with each HVS channel in order,
 169          * each of which takes 256 writes for R, 256 for G, then 256
 170          * for B.
 171          */
 172         HVS_WRITE(SCALER_GAMADDR,
 173                   SCALER_GAMADDR_AUTOINC |
 174                   (vc4_state->assigned_channel * 3 * crtc->gamma_size));
 175
 176         for (i = 0; i < crtc->gamma_size; i++)
 177                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 178         for (i = 0; i < crtc->gamma_size; i++)
 179                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 180         for (i = 0; i < crtc->gamma_size; i++)
 181                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 182 }
 183
 184 static void vc4_hvs_update_gamma_lut(struct drm_crtc *crtc)
 185 {
 186         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 187         struct drm_color_lut *lut = crtc->state->gamma_lut->data;
 188         u32 length = drm_color_lut_size(crtc->state->gamma_lut);
 189         u32 i;
 190
 191         for (i = 0; i < length; i++) {
 192                 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
 193                 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
 194                 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
 195         }
 196
 197         vc4_hvs_lut_load(crtc);
 198 }
 199
 200 u8 vc4_hvs_get_fifo_frame_count(struct drm_device *dev, unsigned int fifo)
 201 {
 202         struct vc4_dev *vc4 = to_vc4_dev(dev);
 203         u8 field = 0;
 204
 205         switch (fifo) {
 206         case 0:
 207                 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
 208                                       SCALER_DISPSTAT1_FRCNT0);
 209                 break;
 210         case 1:
 211                 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
 212                                       SCALER_DISPSTAT1_FRCNT1);
 213                 break;
 214         case 2:
 215                 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2),
 216                                       SCALER_DISPSTAT2_FRCNT2);
 217                 break;
 218         }
 219
 220         return field;
 221 }
 222
 223 int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output)
 224 {
 225         struct vc4_dev *vc4 = to_vc4_dev(dev);
 226         u32 reg;
 227         int ret;
 228
 229         if (!vc4->hvs->hvs5)
 230                 return output;
 231
 232         switch (output) {
 233         case 0:
 234                 return 0;
 235
 236         case 1:
 237                 return 1;
 238
 239         case 2:
 240                 reg = HVS_READ(SCALER_DISPECTRL);
 241                 ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg);
 242                 if (ret == 0)
 243                         return 2;
 244
 245                 return 0;
 246
 247         case 3:
 248                 reg = HVS_READ(SCALER_DISPCTRL);
 249                 ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg);
 250                 if (ret == 3)
 251                         return -EPIPE;
 252
 253                 return ret;
 254
 255         case 4:
 256                 reg = HVS_READ(SCALER_DISPEOLN);
 257                 ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg);
 258                 if (ret == 3)
 259                         return -EPIPE;
 260
 261                 return ret;
 262
 263         case 5:
 264                 reg = HVS_READ(SCALER_DISPDITHER);
 265                 ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg);
 266                 if (ret == 3)
 267                         return -EPIPE;
 268
 269                 return ret;
 270
 271         default:
 272                 return -EPIPE;
 273         }
 274 }
 275
 276 static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc,
 277                                 struct drm_display_mode *mode, bool oneshot)
 278 {
 279         struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
 280         unsigned int chan = vc4_crtc_state->assigned_channel;
 281         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 282         u32 dispbkgndx;
 283         u32 dispctrl;
 284
 285         HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 286         HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
 287         HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 288
 289         /* Turn on the scaler, which will wait for vstart to start
 290          * compositing.
 291          * When feeding the transposer, we should operate in oneshot
 292          * mode.
 293          */
 294         dispctrl = SCALER_DISPCTRLX_ENABLE;
 295
 296         if (!vc4->hvs->hvs5)
 297                 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
 298                                           SCALER_DISPCTRLX_WIDTH) |
 299                             VC4_SET_FIELD(mode->vdisplay,
 300                                           SCALER_DISPCTRLX_HEIGHT) |
 301                             (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
 302         else
 303                 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
 304                                           SCALER5_DISPCTRLX_WIDTH) |
 305                             VC4_SET_FIELD(mode->vdisplay,
 306                                           SCALER5_DISPCTRLX_HEIGHT) |
 307                             (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
 308
 309         HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);
 310
 311         dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan));
 312         dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
 313         dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE;
 314
 315         HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
 316                   SCALER_DISPBKGND_AUTOHS |
 317                   ((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
 318                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 319
 320         /* Reload the LUT, since the SRAMs would have been disabled if
 321          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 322          */
 323         vc4_hvs_lut_load(crtc);
 324
 325         return 0;
 326 }
 327
 328 void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int chan)
 329 {
 330         struct vc4_dev *vc4 = to_vc4_dev(dev);
 331
 332         if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE)
 333                 return;
 334
 335         HVS_WRITE(SCALER_DISPCTRLX(chan),
 336                   HVS_READ(SCALER_DISPCTRLX(chan)) | SCALER_DISPCTRLX_RESET);
 337         HVS_WRITE(SCALER_DISPCTRLX(chan),
 338                   HVS_READ(SCALER_DISPCTRLX(chan)) & ~SCALER_DISPCTRLX_ENABLE);
 339
 340         /* Once we leave, the scaler should be disabled and its fifo empty. */
 341         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 342
 343         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 344                                    SCALER_DISPSTATX_MODE) !=
 345                      SCALER_DISPSTATX_MODE_DISABLED);
 346
 347         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 348                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 349                      SCALER_DISPSTATX_EMPTY);
 350 }
 351
 352 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
 353 {
 354         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
 355         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 356         struct drm_device *dev = crtc->dev;
 357         struct vc4_dev *vc4 = to_vc4_dev(dev);
 358         struct drm_plane *plane;
 359         unsigned long flags;
 360         const struct drm_plane_state *plane_state;
 361         u32 dlist_count = 0;
 362         int ret;
 363
 364         /* The pixelvalve can only feed one encoder (and encoders are
 365          * 1:1 with connectors.)
 366          */
 367         if (hweight32(crtc_state->connector_mask) > 1)
 368                 return -EINVAL;
 369
 370         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state)
 371                 dlist_count += vc4_plane_dlist_size(plane_state);
 372
 373         dlist_count++; /* Account for SCALER_CTL0_END. */
 374
 375         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 376         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 377                                  dlist_count);
 378         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 379         if (ret)
 380                 return ret;
 381
 382         return 0;
 383 }
 384
 385 static void vc4_hvs_update_dlist(struct drm_crtc *crtc)
 386 {
 387         struct drm_device *dev = crtc->dev;
 388         struct vc4_dev *vc4 = to_vc4_dev(dev);
 389         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 390         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 391         unsigned long flags;
 392
 393         if (crtc->state->event) {
 394                 crtc->state->event->pipe = drm_crtc_index(crtc);
 395
 396                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 397
 398                 spin_lock_irqsave(&dev->event_lock, flags);
 399
 400                 if (!vc4_crtc->feeds_txp || vc4_state->txp_armed) {
 401                         vc4_crtc->event = crtc->state->event;
 402                         crtc->state->event = NULL;
 403                 }
 404
 405                 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
 406                           vc4_state->mm.start);
 407
 408                 spin_unlock_irqrestore(&dev->event_lock, flags);
 409         } else {
 410                 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
 411                           vc4_state->mm.start);
 412         }
 413
 414         spin_lock_irqsave(&vc4_crtc->irq_lock, flags);
 415         vc4_crtc->current_dlist = vc4_state->mm.start;
 416         spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags);
 417 }
 418
 419 void vc4_hvs_atomic_begin(struct drm_crtc *crtc,
 420                           struct drm_atomic_state *state)
 421 {
 422         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 423         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 424         unsigned long flags;
 425
 426         spin_lock_irqsave(&vc4_crtc->irq_lock, flags);
 427         vc4_crtc->current_hvs_channel = vc4_state->assigned_channel;
 428         spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags);
 429 }
 430
 431 void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
 432                            struct drm_atomic_state *state)
 433 {
 434         struct drm_device *dev = crtc->dev;
 435         struct vc4_dev *vc4 = to_vc4_dev(dev);
 436         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 437         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 438         bool oneshot = vc4_crtc->feeds_txp;
 439
 440         vc4_hvs_update_dlist(crtc);
 441         vc4_hvs_init_channel(vc4, crtc, mode, oneshot);
 442 }
 443
 444 void vc4_hvs_atomic_disable(struct drm_crtc *crtc,
 445                             struct drm_atomic_state *state)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);
 449         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state);
 450         unsigned int chan = vc4_state->assigned_channel;
 451
 452         vc4_hvs_stop_channel(dev, chan);
 453 }
 454
 455 void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
 456                           struct drm_atomic_state *state)
 457 {
 458         struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
 459                                                                          crtc);
 460         struct drm_device *dev = crtc->dev;
 461         struct vc4_dev *vc4 = to_vc4_dev(dev);
 462         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 463         unsigned int channel = vc4_state->assigned_channel;
 464         struct drm_plane *plane;
 465         struct vc4_plane_state *vc4_plane_state;
 466         bool debug_dump_regs = false;
 467         bool enable_bg_fill = false;
 468         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 469         u32 __iomem *dlist_next = dlist_start;
 470
 471         if (debug_dump_regs) {
 472                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 473                 vc4_hvs_dump_state(dev);
 474         }
 475
 476         /* Copy all the active planes' dlist contents to the hardware dlist. */
 477         drm_atomic_crtc_for_each_plane(plane, crtc) {
 478                 /* Is this the first active plane? */
 479                 if (dlist_next == dlist_start) {
 480                         /* We need to enable background fill when a plane
 481                          * could be alpha blending from the background, i.e.
 482                          * where no other plane is underneath. It suffices to
 483                          * consider the first active plane here since we set
 484                          * needs_bg_fill such that either the first plane
 485                          * already needs it or all planes on top blend from
 486                          * the first or a lower plane.
 487                          */
 488                         vc4_plane_state = to_vc4_plane_state(plane->state);
 489                         enable_bg_fill = vc4_plane_state->needs_bg_fill;
 490                 }
 491
 492                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 493         }
 494
 495         writel(SCALER_CTL0_END, dlist_next);
 496         dlist_next++;
 497
 498         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 499
 500         if (enable_bg_fill)
 501                 /* This sets a black background color fill, as is the case
 502                  * with other DRM drivers.
 503                  */
 504                 HVS_WRITE(SCALER_DISPBKGNDX(channel),
 505                           HVS_READ(SCALER_DISPBKGNDX(channel)) |
 506                           SCALER_DISPBKGND_FILL);
 507
 508         /* Only update DISPLIST if the CRTC was already running and is not
 509          * being disabled.
 510          * vc4_crtc_enable() takes care of updating the dlist just after
 511          * re-enabling VBLANK interrupts and before enabling the engine.
 512          * If the CRTC is being disabled, there's no point in updating this
 513          * information.
 514          */
 515         if (crtc->state->active && old_state->active)
 516                 vc4_hvs_update_dlist(crtc);
 517
 518         if (crtc->state->color_mgmt_changed) {
 519                 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel));
 520
 521                 if (crtc->state->gamma_lut) {
 522                         vc4_hvs_update_gamma_lut(crtc);
 523                         dispbkgndx |= SCALER_DISPBKGND_GAMMA;
 524                 } else {
 525                         /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
 526                          * in hardware, which is the same as a linear lut that
 527                          * DRM expects us to use in absence of a user lut.
 528                          */
 529                         dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
 530                 }
 531                 HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx);
 532         }
 533
 534         if (debug_dump_regs) {
 535                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 536                 vc4_hvs_dump_state(dev);
 537         }
 538 }
 539
 540 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel)
 541 {
 542         struct vc4_dev *vc4 = to_vc4_dev(dev);
 543         u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
 544
 545         dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel);
 546
 547         HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 548 }
 549
 550 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel)
 551 {
 552         struct vc4_dev *vc4 = to_vc4_dev(dev);
 553         u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
 554
 555         dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel);
 556
 557         HVS_WRITE(SCALER_DISPSTAT,
 558                   SCALER_DISPSTAT_EUFLOW(channel));
 559         HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 560 }
 561
 562 static void vc4_hvs_report_underrun(struct drm_device *dev)
 563 {
 564         struct vc4_dev *vc4 = to_vc4_dev(dev);
 565
 566         atomic_inc(&vc4->underrun);
 567         DRM_DEV_ERROR(dev->dev, "HVS underrun\n");
 568 }
 569
 570 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
 571 {
 572         struct drm_device *dev = data;
 573         struct vc4_dev *vc4 = to_vc4_dev(dev);
 574         irqreturn_t irqret = IRQ_NONE;
 575         int channel;
 576         u32 control;
 577         u32 status;
 578
 579         status = HVS_READ(SCALER_DISPSTAT);
 580         control = HVS_READ(SCALER_DISPCTRL);
 581
 582         for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {
 583                 /* Interrupt masking is not always honored, so check it here. */
 584                 if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
 585                     control & SCALER_DISPCTRL_DSPEISLUR(channel)) {
 586                         vc4_hvs_mask_underrun(dev, channel);
 587                         vc4_hvs_report_underrun(dev);
 588
 589                         irqret = IRQ_HANDLED;
 590                 }
 591         }
 592
 593         /* Clear every per-channel interrupt flag. */
 594         HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
 595                                    SCALER_DISPSTAT_IRQMASK(1) |
 596                                    SCALER_DISPSTAT_IRQMASK(2));
 597
 598         return irqret;
 599 }
 600
 601 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
 602 {
 603         struct platform_device *pdev = to_platform_device(dev);
 604         struct drm_device *drm = dev_get_drvdata(master);
 605         struct vc4_dev *vc4 = to_vc4_dev(drm);
 606         struct vc4_hvs *hvs = NULL;
 607         int ret;
 608         u32 dispctrl;
 609
 610         hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
 611         if (!hvs)
 612                 return -ENOMEM;
 613
 614         hvs->pdev = pdev;
 615
 616         if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
 617                 hvs->hvs5 = true;
 618
 619         hvs->regs = vc4_ioremap_regs(pdev, 0);
 620         if (IS_ERR(hvs->regs))
 621                 return PTR_ERR(hvs->regs);
 622
 623         hvs->regset.base = hvs->regs;
 624         hvs->regset.regs = hvs_regs;
 625         hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
 626
 627         if (hvs->hvs5) {
 628                 hvs->core_clk = devm_clk_get(&pdev->dev, NULL);
 629                 if (IS_ERR(hvs->core_clk)) {
 630                         dev_err(&pdev->dev, "Couldn't get core clock\n");
 631                         return PTR_ERR(hvs->core_clk);
 632                 }
 633
 634                 ret = clk_prepare_enable(hvs->core_clk);
 635                 if (ret) {
 636                         dev_err(&pdev->dev, "Couldn't enable the core clock\n");
 637                         return ret;
 638                 }
 639         }
 640
 641         if (!hvs->hvs5)
 642                 hvs->dlist = hvs->regs + SCALER_DLIST_START;
 643         else
 644                 hvs->dlist = hvs->regs + SCALER5_DLIST_START;
 645
 646         spin_lock_init(&hvs->mm_lock);
 647
 648         /* Set up the HVS display list memory manager.  We never
 649          * overwrite the setup from the bootloader (just 128b out of
 650          * our 16K), since we don't want to scramble the screen when
 651          * transitioning from the firmware's boot setup to runtime.
 652          */
 653         drm_mm_init(&hvs->dlist_mm,
 654                     HVS_BOOTLOADER_DLIST_END,
 655                     (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END);
 656
 657         /* Set up the HVS LBM memory manager.  We could have some more
 658          * complicated data structure that allowed reuse of LBM areas
 659          * between planes when they don't overlap on the screen, but
 660          * for now we just allocate globally.
 661          */
 662         if (!hvs->hvs5)
 663                 /* 48k words of 2x12-bit pixels */
 664                 drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024);
 665         else
 666                 /* 60k words of 4x12-bit pixels */
 667                 drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024);
 668
 669         /* Upload filter kernels.  We only have the one for now, so we
 670          * keep it around for the lifetime of the driver.
 671          */
 672         ret = vc4_hvs_upload_linear_kernel(hvs,
 673                                            &hvs->mitchell_netravali_filter,
 674                                            mitchell_netravali_1_3_1_3_kernel);
 675         if (ret)
 676                 return ret;
 677
 678         vc4->hvs = hvs;
 679
 680         dispctrl = HVS_READ(SCALER_DISPCTRL);
 681
 682         dispctrl |= SCALER_DISPCTRL_ENABLE;
 683         dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |
 684                     SCALER_DISPCTRL_DISPEIRQ(1) |
 685                     SCALER_DISPCTRL_DISPEIRQ(2);
 686
 687         /* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
 688          * be unused.
 689          */
 690         dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 691         dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
 692                       SCALER_DISPCTRL_SLVWREIRQ |
 693                       SCALER_DISPCTRL_SLVRDEIRQ |
 694                       SCALER_DISPCTRL_DSPEIEOF(0) |
 695                       SCALER_DISPCTRL_DSPEIEOF(1) |
 696                       SCALER_DISPCTRL_DSPEIEOF(2) |
 697                       SCALER_DISPCTRL_DSPEIEOLN(0) |
 698                       SCALER_DISPCTRL_DSPEIEOLN(1) |
 699                       SCALER_DISPCTRL_DSPEIEOLN(2) |
 700                       SCALER_DISPCTRL_DSPEISLUR(0) |
 701                       SCALER_DISPCTRL_DSPEISLUR(1) |
 702                       SCALER_DISPCTRL_DSPEISLUR(2) |
 703                       SCALER_DISPCTRL_SCLEIRQ);
 704         dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 705
 706         HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 707
 708         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
 709                                vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
 710         if (ret)
 711                 return ret;
 712
 713         vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset);
 714         vc4_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun,
 715                              NULL);
 716
 717         return 0;
 718 }
 719
 720 static void vc4_hvs_unbind(struct device *dev, struct device *master,
 721                            void *data)
 722 {
 723         struct drm_device *drm = dev_get_drvdata(master);
 724         struct vc4_dev *vc4 = to_vc4_dev(drm);
 725         struct vc4_hvs *hvs = vc4->hvs;
 726
 727         if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter))
 728                 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
 729
 730         drm_mm_takedown(&vc4->hvs->dlist_mm);
 731         drm_mm_takedown(&vc4->hvs->lbm_mm);
 732
 733         clk_disable_unprepare(hvs->core_clk);
 734
 735         vc4->hvs = NULL;
 736 }
 737
 738 static const struct component_ops vc4_hvs_ops = {
 739         .bind   = vc4_hvs_bind,
 740         .unbind = vc4_hvs_unbind,
 741 };
 742
 743 static int vc4_hvs_dev_probe(struct platform_device *pdev)
 744 {
 745         return component_add(&pdev->dev, &vc4_hvs_ops);
 746 }
 747
 748 static int vc4_hvs_dev_remove(struct platform_device *pdev)
 749 {
 750         component_del(&pdev->dev, &vc4_hvs_ops);
 751         return 0;
 752 }
 753
 754 static const struct of_device_id vc4_hvs_dt_match[] = {
 755         { .compatible = "brcm,bcm2711-hvs" },
 756         { .compatible = "brcm,bcm2835-hvs" },
 757         {}
 758 };
 759
 760 struct platform_driver vc4_hvs_driver = {
 761         .probe = vc4_hvs_dev_probe,
 762         .remove = vc4_hvs_dev_remove,
 763         .driver = {
 764                 .name = "vc4_hvs",
 765                 .of_match_table = vc4_hvs_dt_match,
 766         },
 767 };