1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom
9 * The Hardware Video Scaler (HVS) is the piece of hardware that does
10 * translation, scaling, colorspace conversion, and compositing of
11 * pixels stored in framebuffers into a FIFO of pixels going out to
12 * the Pixel Valve (CRTC). It operates at the system clock rate (the
13 * system audio clock gate, specifically), which is much higher than
14 * the pixel clock rate.
16 * There is a single global HVS, with multiple output FIFOs that can
17 * be consumed by the PVs. This file just manages the resources for
18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for
22 #include <linux/bitfield.h>
23 #include <linux/clk.h>
24 #include <linux/component.h>
25 #include <linux/platform_device.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_vblank.h>
33 static const struct debugfs_reg32 hvs_regs[] = {
34 VC4_REG32(SCALER_DISPCTRL),
35 VC4_REG32(SCALER_DISPSTAT),
36 VC4_REG32(SCALER_DISPID),
37 VC4_REG32(SCALER_DISPECTRL),
38 VC4_REG32(SCALER_DISPPROF),
39 VC4_REG32(SCALER_DISPDITHER),
40 VC4_REG32(SCALER_DISPEOLN),
41 VC4_REG32(SCALER_DISPLIST0),
42 VC4_REG32(SCALER_DISPLIST1),
43 VC4_REG32(SCALER_DISPLIST2),
44 VC4_REG32(SCALER_DISPLSTAT),
45 VC4_REG32(SCALER_DISPLACT0),
46 VC4_REG32(SCALER_DISPLACT1),
47 VC4_REG32(SCALER_DISPLACT2),
48 VC4_REG32(SCALER_DISPCTRL0),
49 VC4_REG32(SCALER_DISPBKGND0),
50 VC4_REG32(SCALER_DISPSTAT0),
51 VC4_REG32(SCALER_DISPBASE0),
52 VC4_REG32(SCALER_DISPCTRL1),
53 VC4_REG32(SCALER_DISPBKGND1),
54 VC4_REG32(SCALER_DISPSTAT1),
55 VC4_REG32(SCALER_DISPBASE1),
56 VC4_REG32(SCALER_DISPCTRL2),
57 VC4_REG32(SCALER_DISPBKGND2),
58 VC4_REG32(SCALER_DISPSTAT2),
59 VC4_REG32(SCALER_DISPBASE2),
60 VC4_REG32(SCALER_DISPALPHA2),
61 VC4_REG32(SCALER_OLEDOFFS),
62 VC4_REG32(SCALER_OLEDCOEF0),
63 VC4_REG32(SCALER_OLEDCOEF1),
64 VC4_REG32(SCALER_OLEDCOEF2),
67 void vc4_hvs_dump_state(struct drm_device *dev)
69 struct vc4_dev *vc4 = to_vc4_dev(dev);
70 struct drm_printer p = drm_info_printer(&vc4->hvs->pdev->dev);
73 drm_print_regset32(&p, &vc4->hvs->regset);
75 DRM_INFO("HVS ctx:\n");
76 for (i = 0; i < 64; i += 4) {
77 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
78 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
79 readl((u32 __iomem *)vc4->hvs->dlist + i + 0),
80 readl((u32 __iomem *)vc4->hvs->dlist + i + 1),
81 readl((u32 __iomem *)vc4->hvs->dlist + i + 2),
82 readl((u32 __iomem *)vc4->hvs->dlist + i + 3));
86 static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data)
88 struct drm_info_node *node = m->private;
89 struct drm_device *dev = node->minor->dev;
90 struct vc4_dev *vc4 = to_vc4_dev(dev);
91 struct drm_printer p = drm_seq_file_printer(m);
93 drm_printf(&p, "%d\n", atomic_read(&vc4->underrun));
98 /* The filter kernel is composed of dwords each containing 3 9-bit
99 * signed integers packed next to each other.
101 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
102 #define VC4_PPF_FILTER_WORD(c0, c1, c2) \
103 ((((c0) & 0x1ff) << 0) | \
104 (((c1) & 0x1ff) << 9) | \
105 (((c2) & 0x1ff) << 18))
107 /* The whole filter kernel is arranged as the coefficients 0-16 going
108 * up, then a pad, then 17-31 going down and reversed within the
109 * dwords. This means that a linear phase kernel (where it's
110 * symmetrical at the boundary between 15 and 16) has the last 5
111 * dwords matching the first 5, but reversed.
113 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \
114 c9, c10, c11, c12, c13, c14, c15) \
115 {VC4_PPF_FILTER_WORD(c0, c1, c2), \
116 VC4_PPF_FILTER_WORD(c3, c4, c5), \
117 VC4_PPF_FILTER_WORD(c6, c7, c8), \
118 VC4_PPF_FILTER_WORD(c9, c10, c11), \
119 VC4_PPF_FILTER_WORD(c12, c13, c14), \
120 VC4_PPF_FILTER_WORD(c15, c15, 0)}
122 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6
123 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
125 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
126 * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
128 static const u32 mitchell_netravali_1_3_1_3_kernel[] =
129 VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
130 50, 82, 119, 155, 187, 213, 227);
132 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
133 struct drm_mm_node *space,
137 u32 __iomem *dst_kernel;
139 ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS);
141 DRM_ERROR("Failed to allocate space for filter kernel: %d\n",
146 dst_kernel = hvs->dlist + space->start;
148 for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
149 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS)
150 writel(kernel[i], &dst_kernel[i]);
152 writel(kernel[VC4_KERNEL_DWORDS - i - 1],
160 static void vc4_hvs_lut_load(struct drm_crtc *crtc)
162 struct drm_device *dev = crtc->dev;
163 struct vc4_dev *vc4 = to_vc4_dev(dev);
164 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
165 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
168 /* The LUT memory is laid out with each HVS channel in order,
169 * each of which takes 256 writes for R, 256 for G, then 256
172 HVS_WRITE(SCALER_GAMADDR,
173 SCALER_GAMADDR_AUTOINC |
174 (vc4_state->assigned_channel * 3 * crtc->gamma_size));
176 for (i = 0; i < crtc->gamma_size; i++)
177 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
178 for (i = 0; i < crtc->gamma_size; i++)
179 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
180 for (i = 0; i < crtc->gamma_size; i++)
181 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
184 static void vc4_hvs_update_gamma_lut(struct drm_crtc *crtc)
186 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
187 struct drm_color_lut *lut = crtc->state->gamma_lut->data;
188 u32 length = drm_color_lut_size(crtc->state->gamma_lut);
191 for (i = 0; i < length; i++) {
192 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
193 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
194 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
197 vc4_hvs_lut_load(crtc);
200 u8 vc4_hvs_get_fifo_frame_count(struct drm_device *dev, unsigned int fifo)
202 struct vc4_dev *vc4 = to_vc4_dev(dev);
207 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
208 SCALER_DISPSTAT1_FRCNT0);
211 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1),
212 SCALER_DISPSTAT1_FRCNT1);
215 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2),
216 SCALER_DISPSTAT2_FRCNT2);
223 int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output)
225 struct vc4_dev *vc4 = to_vc4_dev(dev);
240 reg = HVS_READ(SCALER_DISPECTRL);
241 ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg);
248 reg = HVS_READ(SCALER_DISPCTRL);
249 ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg);
256 reg = HVS_READ(SCALER_DISPEOLN);
257 ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg);
264 reg = HVS_READ(SCALER_DISPDITHER);
265 ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg);
276 static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc,
277 struct drm_display_mode *mode, bool oneshot)
279 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
280 unsigned int chan = vc4_crtc_state->assigned_channel;
281 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
285 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
286 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
287 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
289 /* Turn on the scaler, which will wait for vstart to start
291 * When feeding the transposer, we should operate in oneshot
294 dispctrl = SCALER_DISPCTRLX_ENABLE;
297 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
298 SCALER_DISPCTRLX_WIDTH) |
299 VC4_SET_FIELD(mode->vdisplay,
300 SCALER_DISPCTRLX_HEIGHT) |
301 (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
303 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
304 SCALER5_DISPCTRLX_WIDTH) |
305 VC4_SET_FIELD(mode->vdisplay,
306 SCALER5_DISPCTRLX_HEIGHT) |
307 (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
309 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);
311 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan));
312 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
313 dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE;
315 HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
316 SCALER_DISPBKGND_AUTOHS |
317 ((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
318 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
320 /* Reload the LUT, since the SRAMs would have been disabled if
321 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
323 vc4_hvs_lut_load(crtc);
328 void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int chan)
330 struct vc4_dev *vc4 = to_vc4_dev(dev);
332 if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE)
335 HVS_WRITE(SCALER_DISPCTRLX(chan),
336 HVS_READ(SCALER_DISPCTRLX(chan)) | SCALER_DISPCTRLX_RESET);
337 HVS_WRITE(SCALER_DISPCTRLX(chan),
338 HVS_READ(SCALER_DISPCTRLX(chan)) & ~SCALER_DISPCTRLX_ENABLE);
340 /* Once we leave, the scaler should be disabled and its fifo empty. */
341 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
343 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
344 SCALER_DISPSTATX_MODE) !=
345 SCALER_DISPSTATX_MODE_DISABLED);
347 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
348 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
349 SCALER_DISPSTATX_EMPTY);
352 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
354 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
355 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
356 struct drm_device *dev = crtc->dev;
357 struct vc4_dev *vc4 = to_vc4_dev(dev);
358 struct drm_plane *plane;
360 const struct drm_plane_state *plane_state;
364 /* The pixelvalve can only feed one encoder (and encoders are
365 * 1:1 with connectors.)
367 if (hweight32(crtc_state->connector_mask) > 1)
370 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state)
371 dlist_count += vc4_plane_dlist_size(plane_state);
373 dlist_count++; /* Account for SCALER_CTL0_END. */
375 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
376 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
378 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
385 static void vc4_hvs_update_dlist(struct drm_crtc *crtc)
387 struct drm_device *dev = crtc->dev;
388 struct vc4_dev *vc4 = to_vc4_dev(dev);
389 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
390 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
393 if (crtc->state->event) {
394 crtc->state->event->pipe = drm_crtc_index(crtc);
396 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
398 spin_lock_irqsave(&dev->event_lock, flags);
400 if (!vc4_crtc->feeds_txp || vc4_state->txp_armed) {
401 vc4_crtc->event = crtc->state->event;
402 crtc->state->event = NULL;
405 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
406 vc4_state->mm.start);
408 spin_unlock_irqrestore(&dev->event_lock, flags);
410 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
411 vc4_state->mm.start);
414 spin_lock_irqsave(&vc4_crtc->irq_lock, flags);
415 vc4_crtc->current_dlist = vc4_state->mm.start;
416 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags);
419 void vc4_hvs_atomic_begin(struct drm_crtc *crtc,
420 struct drm_atomic_state *state)
422 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
423 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
426 spin_lock_irqsave(&vc4_crtc->irq_lock, flags);
427 vc4_crtc->current_hvs_channel = vc4_state->assigned_channel;
428 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags);
431 void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
432 struct drm_atomic_state *state)
434 struct drm_device *dev = crtc->dev;
435 struct vc4_dev *vc4 = to_vc4_dev(dev);
436 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
437 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
438 bool oneshot = vc4_crtc->feeds_txp;
440 vc4_hvs_update_dlist(crtc);
441 vc4_hvs_init_channel(vc4, crtc, mode, oneshot);
444 void vc4_hvs_atomic_disable(struct drm_crtc *crtc,
445 struct drm_atomic_state *state)
447 struct drm_device *dev = crtc->dev;
448 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);
449 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state);
450 unsigned int chan = vc4_state->assigned_channel;
452 vc4_hvs_stop_channel(dev, chan);
455 void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
456 struct drm_atomic_state *state)
458 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
460 struct drm_device *dev = crtc->dev;
461 struct vc4_dev *vc4 = to_vc4_dev(dev);
462 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
463 struct drm_plane *plane;
464 struct vc4_plane_state *vc4_plane_state;
465 bool debug_dump_regs = false;
466 bool enable_bg_fill = false;
467 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
468 u32 __iomem *dlist_next = dlist_start;
470 if (debug_dump_regs) {
471 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
472 vc4_hvs_dump_state(dev);
475 /* Copy all the active planes' dlist contents to the hardware dlist. */
476 drm_atomic_crtc_for_each_plane(plane, crtc) {
477 /* Is this the first active plane? */
478 if (dlist_next == dlist_start) {
479 /* We need to enable background fill when a plane
480 * could be alpha blending from the background, i.e.
481 * where no other plane is underneath. It suffices to
482 * consider the first active plane here since we set
483 * needs_bg_fill such that either the first plane
484 * already needs it or all planes on top blend from
485 * the first or a lower plane.
487 vc4_plane_state = to_vc4_plane_state(plane->state);
488 enable_bg_fill = vc4_plane_state->needs_bg_fill;
491 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
494 writel(SCALER_CTL0_END, dlist_next);
497 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
500 /* This sets a black background color fill, as is the case
501 * with other DRM drivers.
503 HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
504 HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel)) |
505 SCALER_DISPBKGND_FILL);
507 /* Only update DISPLIST if the CRTC was already running and is not
509 * vc4_crtc_enable() takes care of updating the dlist just after
510 * re-enabling VBLANK interrupts and before enabling the engine.
511 * If the CRTC is being disabled, there's no point in updating this
514 if (crtc->state->active && old_state->active)
515 vc4_hvs_update_dlist(crtc);
517 if (crtc->state->color_mgmt_changed) {
518 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel));
520 if (crtc->state->gamma_lut) {
521 vc4_hvs_update_gamma_lut(crtc);
522 dispbkgndx |= SCALER_DISPBKGND_GAMMA;
524 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
525 * in hardware, which is the same as a linear lut that
526 * DRM expects us to use in absence of a user lut.
528 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
530 HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel), dispbkgndx);
533 if (debug_dump_regs) {
534 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
535 vc4_hvs_dump_state(dev);
539 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel)
541 struct vc4_dev *vc4 = to_vc4_dev(dev);
542 u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
544 dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel);
546 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
549 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel)
551 struct vc4_dev *vc4 = to_vc4_dev(dev);
552 u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
554 dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel);
556 HVS_WRITE(SCALER_DISPSTAT,
557 SCALER_DISPSTAT_EUFLOW(channel));
558 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
561 static void vc4_hvs_report_underrun(struct drm_device *dev)
563 struct vc4_dev *vc4 = to_vc4_dev(dev);
565 atomic_inc(&vc4->underrun);
566 DRM_DEV_ERROR(dev->dev, "HVS underrun\n");
569 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
571 struct drm_device *dev = data;
572 struct vc4_dev *vc4 = to_vc4_dev(dev);
573 irqreturn_t irqret = IRQ_NONE;
578 status = HVS_READ(SCALER_DISPSTAT);
579 control = HVS_READ(SCALER_DISPCTRL);
581 for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {
582 /* Interrupt masking is not always honored, so check it here. */
583 if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
584 control & SCALER_DISPCTRL_DSPEISLUR(channel)) {
585 vc4_hvs_mask_underrun(dev, channel);
586 vc4_hvs_report_underrun(dev);
588 irqret = IRQ_HANDLED;
592 /* Clear every per-channel interrupt flag. */
593 HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
594 SCALER_DISPSTAT_IRQMASK(1) |
595 SCALER_DISPSTAT_IRQMASK(2));
600 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
602 struct platform_device *pdev = to_platform_device(dev);
603 struct drm_device *drm = dev_get_drvdata(master);
604 struct vc4_dev *vc4 = to_vc4_dev(drm);
605 struct vc4_hvs *hvs = NULL;
609 hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
615 if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
618 hvs->regs = vc4_ioremap_regs(pdev, 0);
619 if (IS_ERR(hvs->regs))
620 return PTR_ERR(hvs->regs);
622 hvs->regset.base = hvs->regs;
623 hvs->regset.regs = hvs_regs;
624 hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
627 hvs->core_clk = devm_clk_get(&pdev->dev, NULL);
628 if (IS_ERR(hvs->core_clk)) {
629 dev_err(&pdev->dev, "Couldn't get core clock\n");
630 return PTR_ERR(hvs->core_clk);
633 ret = clk_prepare_enable(hvs->core_clk);
635 dev_err(&pdev->dev, "Couldn't enable the core clock\n");
641 hvs->dlist = hvs->regs + SCALER_DLIST_START;
643 hvs->dlist = hvs->regs + SCALER5_DLIST_START;
645 spin_lock_init(&hvs->mm_lock);
647 /* Set up the HVS display list memory manager. We never
648 * overwrite the setup from the bootloader (just 128b out of
649 * our 16K), since we don't want to scramble the screen when
650 * transitioning from the firmware's boot setup to runtime.
652 drm_mm_init(&hvs->dlist_mm,
653 HVS_BOOTLOADER_DLIST_END,
654 (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END);
656 /* Set up the HVS LBM memory manager. We could have some more
657 * complicated data structure that allowed reuse of LBM areas
658 * between planes when they don't overlap on the screen, but
659 * for now we just allocate globally.
662 /* 48k words of 2x12-bit pixels */
663 drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024);
665 /* 60k words of 4x12-bit pixels */
666 drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024);
668 /* Upload filter kernels. We only have the one for now, so we
669 * keep it around for the lifetime of the driver.
671 ret = vc4_hvs_upload_linear_kernel(hvs,
672 &hvs->mitchell_netravali_filter,
673 mitchell_netravali_1_3_1_3_kernel);
679 dispctrl = HVS_READ(SCALER_DISPCTRL);
681 dispctrl |= SCALER_DISPCTRL_ENABLE;
682 dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |
683 SCALER_DISPCTRL_DISPEIRQ(1) |
684 SCALER_DISPCTRL_DISPEIRQ(2);
686 /* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
689 dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
690 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
691 SCALER_DISPCTRL_SLVWREIRQ |
692 SCALER_DISPCTRL_SLVRDEIRQ |
693 SCALER_DISPCTRL_DSPEIEOF(0) |
694 SCALER_DISPCTRL_DSPEIEOF(1) |
695 SCALER_DISPCTRL_DSPEIEOF(2) |
696 SCALER_DISPCTRL_DSPEIEOLN(0) |
697 SCALER_DISPCTRL_DSPEIEOLN(1) |
698 SCALER_DISPCTRL_DSPEIEOLN(2) |
699 SCALER_DISPCTRL_DSPEISLUR(0) |
700 SCALER_DISPCTRL_DSPEISLUR(1) |
701 SCALER_DISPCTRL_DSPEISLUR(2) |
702 SCALER_DISPCTRL_SCLEIRQ);
703 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
705 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
707 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
708 vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
712 vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset);
713 vc4_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun,
719 static void vc4_hvs_unbind(struct device *dev, struct device *master,
722 struct drm_device *drm = dev_get_drvdata(master);
723 struct vc4_dev *vc4 = to_vc4_dev(drm);
724 struct vc4_hvs *hvs = vc4->hvs;
726 if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter))
727 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
729 drm_mm_takedown(&vc4->hvs->dlist_mm);
730 drm_mm_takedown(&vc4->hvs->lbm_mm);
732 clk_disable_unprepare(hvs->core_clk);
737 static const struct component_ops vc4_hvs_ops = {
738 .bind = vc4_hvs_bind,
739 .unbind = vc4_hvs_unbind,
742 static int vc4_hvs_dev_probe(struct platform_device *pdev)
744 return component_add(&pdev->dev, &vc4_hvs_ops);
747 static int vc4_hvs_dev_remove(struct platform_device *pdev)
749 component_del(&pdev->dev, &vc4_hvs_ops);
753 static const struct of_device_id vc4_hvs_dt_match[] = {
754 { .compatible = "brcm,bcm2711-hvs" },
755 { .compatible = "brcm,bcm2835-hvs" },
759 struct platform_driver vc4_hvs_driver = {
760 .probe = vc4_hvs_dev_probe,
761 .remove = vc4_hvs_dev_remove,
764 .of_match_table = vc4_hvs_dt_match,