drivers/gpu/drm/vc4/vc4_hvs.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 HVS module.
  11  *
  12  * The Hardware Video Scaler (HVS) is the piece of hardware that does
  13  * translation, scaling, colorspace conversion, and compositing of
  14  * pixels stored in framebuffers into a FIFO of pixels going out to
  15  * the Pixel Valve (CRTC).  It operates at the system clock rate (the
  16  * system audio clock gate, specifically), which is much higher than
  17  * the pixel clock rate.
  18  *
  19  * There is a single global HVS, with multiple output FIFOs that can
  20  * be consumed by the PVs.  This file just manages the resources for
  21  * the HVS, while the vc4_crtc.c code actually drives HVS setup for
  22  * each CRTC.
  23  */
  24
  25 #include <drm/drm_atomic_helper.h>
  26 #include <linux/component.h>
  27 #include "vc4_drv.h"
  28 #include "vc4_regs.h"
  29
  30 #define HVS_REG(reg) { reg, #reg }
  31 static const struct {
  32         u32 reg;
  33         const char *name;
  34 } hvs_regs[] = {
  35         HVS_REG(SCALER_DISPCTRL),
  36         HVS_REG(SCALER_DISPSTAT),
  37         HVS_REG(SCALER_DISPID),
  38         HVS_REG(SCALER_DISPECTRL),
  39         HVS_REG(SCALER_DISPPROF),
  40         HVS_REG(SCALER_DISPDITHER),
  41         HVS_REG(SCALER_DISPEOLN),
  42         HVS_REG(SCALER_DISPLIST0),
  43         HVS_REG(SCALER_DISPLIST1),
  44         HVS_REG(SCALER_DISPLIST2),
  45         HVS_REG(SCALER_DISPLSTAT),
  46         HVS_REG(SCALER_DISPLACT0),
  47         HVS_REG(SCALER_DISPLACT1),
  48         HVS_REG(SCALER_DISPLACT2),
  49         HVS_REG(SCALER_DISPCTRL0),
  50         HVS_REG(SCALER_DISPBKGND0),
  51         HVS_REG(SCALER_DISPSTAT0),
  52         HVS_REG(SCALER_DISPBASE0),
  53         HVS_REG(SCALER_DISPCTRL1),
  54         HVS_REG(SCALER_DISPBKGND1),
  55         HVS_REG(SCALER_DISPSTAT1),
  56         HVS_REG(SCALER_DISPBASE1),
  57         HVS_REG(SCALER_DISPCTRL2),
  58         HVS_REG(SCALER_DISPBKGND2),
  59         HVS_REG(SCALER_DISPSTAT2),
  60         HVS_REG(SCALER_DISPBASE2),
  61         HVS_REG(SCALER_DISPALPHA2),
  62         HVS_REG(SCALER_OLEDOFFS),
  63         HVS_REG(SCALER_OLEDCOEF0),
  64         HVS_REG(SCALER_OLEDCOEF1),
  65         HVS_REG(SCALER_OLEDCOEF2),
  66 };
  67
  68 void vc4_hvs_dump_state(struct drm_device *dev)
  69 {
  70         struct vc4_dev *vc4 = to_vc4_dev(dev);
  71         int i;
  72
  73         for (i = 0; i < ARRAY_SIZE(hvs_regs); i++) {
  74                 DRM_INFO("0x%04x (%s): 0x%08x\n",
  75                          hvs_regs[i].reg, hvs_regs[i].name,
  76                          HVS_READ(hvs_regs[i].reg));
  77         }
  78
  79         DRM_INFO("HVS ctx:\n");
  80         for (i = 0; i < 64; i += 4) {
  81                 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
  82                          i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
  83                          readl((u32 __iomem *)vc4->hvs->dlist + i + 0),
  84                          readl((u32 __iomem *)vc4->hvs->dlist + i + 1),
  85                          readl((u32 __iomem *)vc4->hvs->dlist + i + 2),
  86                          readl((u32 __iomem *)vc4->hvs->dlist + i + 3));
  87         }
  88 }
  89
  90 #ifdef CONFIG_DEBUG_FS
  91 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused)
  92 {
  93         struct drm_info_node *node = (struct drm_info_node *)m->private;
  94         struct drm_device *dev = node->minor->dev;
  95         struct vc4_dev *vc4 = to_vc4_dev(dev);
  96         int i;
  97
  98         for (i = 0; i < ARRAY_SIZE(hvs_regs); i++) {
  99                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 100                            hvs_regs[i].name, hvs_regs[i].reg,
 101                            HVS_READ(hvs_regs[i].reg));
 102         }
 103
 104         return 0;
 105 }
 106
 107 int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data)
 108 {
 109         struct drm_info_node *node = m->private;
 110         struct drm_device *dev = node->minor->dev;
 111         struct vc4_dev *vc4 = to_vc4_dev(dev);
 112         struct drm_printer p = drm_seq_file_printer(m);
 113
 114         drm_printf(&p, "%d\n", atomic_read(&vc4->underrun));
 115
 116         return 0;
 117 }
 118 #endif
 119
 120 /* The filter kernel is composed of dwords each containing 3 9-bit
 121  * signed integers packed next to each other.
 122  */
 123 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
 124 #define VC4_PPF_FILTER_WORD(c0, c1, c2)                         \
 125         ((((c0) & 0x1ff) << 0) |                                \
 126          (((c1) & 0x1ff) << 9) |                                \
 127          (((c2) & 0x1ff) << 18))
 128
 129 /* The whole filter kernel is arranged as the coefficients 0-16 going
 130  * up, then a pad, then 17-31 going down and reversed within the
 131  * dwords.  This means that a linear phase kernel (where it's
 132  * symmetrical at the boundary between 15 and 16) has the last 5
 133  * dwords matching the first 5, but reversed.
 134  */
 135 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8,     \
 136                                 c9, c10, c11, c12, c13, c14, c15)       \
 137         {VC4_PPF_FILTER_WORD(c0, c1, c2),                               \
 138          VC4_PPF_FILTER_WORD(c3, c4, c5),                               \
 139          VC4_PPF_FILTER_WORD(c6, c7, c8),                               \
 140          VC4_PPF_FILTER_WORD(c9, c10, c11),                             \
 141          VC4_PPF_FILTER_WORD(c12, c13, c14),                            \
 142          VC4_PPF_FILTER_WORD(c15, c15, 0)}
 143
 144 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6
 145 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
 146
 147 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
 148  * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
 149  */
 150 static const u32 mitchell_netravali_1_3_1_3_kernel[] =
 151         VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
 152                                 50, 82, 119, 155, 187, 213, 227);
 153
 154 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
 155                                         struct drm_mm_node *space,
 156                                         const u32 *kernel)
 157 {
 158         int ret, i;
 159         u32 __iomem *dst_kernel;
 160
 161         ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS);
 162         if (ret) {
 163                 DRM_ERROR("Failed to allocate space for filter kernel: %d\n",
 164                           ret);
 165                 return ret;
 166         }
 167
 168         dst_kernel = hvs->dlist + space->start;
 169
 170         for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
 171                 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS)
 172                         writel(kernel[i], &dst_kernel[i]);
 173                 else {
 174                         writel(kernel[VC4_KERNEL_DWORDS - i - 1],
 175                                &dst_kernel[i]);
 176                 }
 177         }
 178
 179         return 0;
 180 }
 181
 182 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel)
 183 {
 184         struct vc4_dev *vc4 = to_vc4_dev(dev);
 185         u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
 186
 187         dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel);
 188
 189         HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 190 }
 191
 192 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel)
 193 {
 194         struct vc4_dev *vc4 = to_vc4_dev(dev);
 195         u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
 196
 197         dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel);
 198
 199         HVS_WRITE(SCALER_DISPSTAT,
 200                   SCALER_DISPSTAT_EUFLOW(channel));
 201         HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 202 }
 203
 204 static void vc4_hvs_report_underrun(struct drm_device *dev)
 205 {
 206         struct vc4_dev *vc4 = to_vc4_dev(dev);
 207
 208         atomic_inc(&vc4->underrun);
 209         DRM_DEV_ERROR(dev->dev, "HVS underrun\n");
 210 }
 211
 212 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
 213 {
 214         struct drm_device *dev = data;
 215         struct vc4_dev *vc4 = to_vc4_dev(dev);
 216         irqreturn_t irqret = IRQ_NONE;
 217         int channel;
 218         u32 control;
 219         u32 status;
 220
 221         status = HVS_READ(SCALER_DISPSTAT);
 222         control = HVS_READ(SCALER_DISPCTRL);
 223
 224         for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {
 225                 /* Interrupt masking is not always honored, so check it here. */
 226                 if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
 227                     control & SCALER_DISPCTRL_DSPEISLUR(channel)) {
 228                         vc4_hvs_mask_underrun(dev, channel);
 229                         vc4_hvs_report_underrun(dev);
 230
 231                         irqret = IRQ_HANDLED;
 232                 }
 233         }
 234
 235         /* Clear every per-channel interrupt flag. */
 236         HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
 237                                    SCALER_DISPSTAT_IRQMASK(1) |
 238                                    SCALER_DISPSTAT_IRQMASK(2));
 239
 240         return irqret;
 241 }
 242
 243 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
 244 {
 245         struct platform_device *pdev = to_platform_device(dev);
 246         struct drm_device *drm = dev_get_drvdata(master);
 247         struct vc4_dev *vc4 = drm->dev_private;
 248         struct vc4_hvs *hvs = NULL;
 249         int ret;
 250         u32 dispctrl;
 251
 252         hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
 253         if (!hvs)
 254                 return -ENOMEM;
 255
 256         hvs->pdev = pdev;
 257
 258         hvs->regs = vc4_ioremap_regs(pdev, 0);
 259         if (IS_ERR(hvs->regs))
 260                 return PTR_ERR(hvs->regs);
 261
 262         hvs->dlist = hvs->regs + SCALER_DLIST_START;
 263
 264         spin_lock_init(&hvs->mm_lock);
 265
 266         /* Set up the HVS display list memory manager.  We never
 267          * overwrite the setup from the bootloader (just 128b out of
 268          * our 16K), since we don't want to scramble the screen when
 269          * transitioning from the firmware's boot setup to runtime.
 270          */
 271         drm_mm_init(&hvs->dlist_mm,
 272                     HVS_BOOTLOADER_DLIST_END,
 273                     (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END);
 274
 275         /* Set up the HVS LBM memory manager.  We could have some more
 276          * complicated data structure that allowed reuse of LBM areas
 277          * between planes when they don't overlap on the screen, but
 278          * for now we just allocate globally.
 279          */
 280         drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
 281
 282         /* Upload filter kernels.  We only have the one for now, so we
 283          * keep it around for the lifetime of the driver.
 284          */
 285         ret = vc4_hvs_upload_linear_kernel(hvs,
 286                                            &hvs->mitchell_netravali_filter,
 287                                            mitchell_netravali_1_3_1_3_kernel);
 288         if (ret)
 289                 return ret;
 290
 291         vc4->hvs = hvs;
 292
 293         dispctrl = HVS_READ(SCALER_DISPCTRL);
 294
 295         dispctrl |= SCALER_DISPCTRL_ENABLE;
 296         dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |
 297                     SCALER_DISPCTRL_DISPEIRQ(1) |
 298                     SCALER_DISPCTRL_DISPEIRQ(2);
 299
 300         /* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
 301          * be unused.
 302          */
 303         dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 304         dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
 305                       SCALER_DISPCTRL_SLVWREIRQ |
 306                       SCALER_DISPCTRL_SLVRDEIRQ |
 307                       SCALER_DISPCTRL_DSPEIEOF(0) |
 308                       SCALER_DISPCTRL_DSPEIEOF(1) |
 309                       SCALER_DISPCTRL_DSPEIEOF(2) |
 310                       SCALER_DISPCTRL_DSPEIEOLN(0) |
 311                       SCALER_DISPCTRL_DSPEIEOLN(1) |
 312                       SCALER_DISPCTRL_DSPEIEOLN(2) |
 313                       SCALER_DISPCTRL_DSPEISLUR(0) |
 314                       SCALER_DISPCTRL_DSPEISLUR(1) |
 315                       SCALER_DISPCTRL_DSPEISLUR(2) |
 316                       SCALER_DISPCTRL_SCLEIRQ);
 317         dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 318
 319         HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 320
 321         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
 322                                vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
 323         if (ret)
 324                 return ret;
 325
 326         return 0;
 327 }
 328
 329 static void vc4_hvs_unbind(struct device *dev, struct device *master,
 330                            void *data)
 331 {
 332         struct drm_device *drm = dev_get_drvdata(master);
 333         struct vc4_dev *vc4 = drm->dev_private;
 334
 335         if (vc4->hvs->mitchell_netravali_filter.allocated)
 336                 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
 337
 338         drm_mm_takedown(&vc4->hvs->dlist_mm);
 339         drm_mm_takedown(&vc4->hvs->lbm_mm);
 340
 341         vc4->hvs = NULL;
 342 }
 343
 344 static const struct component_ops vc4_hvs_ops = {
 345         .bind   = vc4_hvs_bind,
 346         .unbind = vc4_hvs_unbind,
 347 };
 348
 349 static int vc4_hvs_dev_probe(struct platform_device *pdev)
 350 {
 351         return component_add(&pdev->dev, &vc4_hvs_ops);
 352 }
 353
 354 static int vc4_hvs_dev_remove(struct platform_device *pdev)
 355 {
 356         component_del(&pdev->dev, &vc4_hvs_ops);
 357         return 0;
 358 }
 359
 360 static const struct of_device_id vc4_hvs_dt_match[] = {
 361         { .compatible = "brcm,bcm2835-hvs" },
 362         {}
 363 };
 364
 365 struct platform_driver vc4_hvs_driver = {
 366         .probe = vc4_hvs_dev_probe,
 367         .remove = vc4_hvs_dev_remove,
 368         .driver = {
 369                 .name = "vc4_hvs",
 370                 .of_match_table = vc4_hvs_dt_match,
 371         },
 372 };