drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <linux/clk.h>
  38 #include <linux/component.h>
  39 #include <linux/i2c.h>
  40 #include <linux/of_address.h>
  41 #include <linux/of_gpio.h>
  42 #include <linux/of_platform.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/rational.h>
  45 #include <sound/dmaengine_pcm.h>
  46 #include <sound/pcm_drm_eld.h>
  47 #include <sound/pcm_params.h>
  48 #include <sound/soc.h>
  49 #include "media/cec.h"
  50 #include "vc4_drv.h"
  51 #include "vc4_regs.h"
  52
  53 #define HSM_CLOCK_FREQ 163682864
  54 #define CEC_CLOCK_FREQ 40000
  55 #define CEC_CLOCK_DIV  (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
  56
  57 /* HDMI audio information */
  58 struct vc4_hdmi_audio {
  59         struct snd_soc_card card;
  60         struct snd_soc_dai_link link;
  61         struct snd_soc_dai_link_component cpu;
  62         struct snd_soc_dai_link_component codec;
  63         struct snd_soc_dai_link_component platform;
  64         int samplerate;
  65         int channels;
  66         struct snd_dmaengine_dai_dma_data dma_data;
  67         struct snd_pcm_substream *substream;
  68 };
  69
  70 /* General HDMI hardware state. */
  71 struct vc4_hdmi {
  72         struct platform_device *pdev;
  73
  74         struct drm_encoder *encoder;
  75         struct drm_connector *connector;
  76
  77         struct vc4_hdmi_audio audio;
  78
  79         struct i2c_adapter *ddc;
  80         void __iomem *hdmicore_regs;
  81         void __iomem *hd_regs;
  82         int hpd_gpio;
  83         bool hpd_active_low;
  84
  85         struct cec_adapter *cec_adap;
  86         struct cec_msg cec_rx_msg;
  87         bool cec_tx_ok;
  88         bool cec_irq_was_rx;
  89
  90         struct clk *pixel_clock;
  91         struct clk *hsm_clock;
  92
  93         struct debugfs_regset32 hdmi_regset;
  94         struct debugfs_regset32 hd_regset;
  95 };
  96
  97 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
  98 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
  99 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
 100 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
 101
 102 /* VC4 HDMI encoder KMS struct */
 103 struct vc4_hdmi_encoder {
 104         struct vc4_encoder base;
 105         bool hdmi_monitor;
 106         bool limited_rgb_range;
 107 };
 108
 109 static inline struct vc4_hdmi_encoder *
 110 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
 111 {
 112         return container_of(encoder, struct vc4_hdmi_encoder, base.base);
 113 }
 114
 115 /* VC4 HDMI connector KMS struct */
 116 struct vc4_hdmi_connector {
 117         struct drm_connector base;
 118
 119         /* Since the connector is attached to just the one encoder,
 120          * this is the reference to it so we can do the best_encoder()
 121          * hook.
 122          */
 123         struct drm_encoder *encoder;
 124 };
 125
 126 static inline struct vc4_hdmi_connector *
 127 to_vc4_hdmi_connector(struct drm_connector *connector)
 128 {
 129         return container_of(connector, struct vc4_hdmi_connector, base);
 130 }
 131
 132 static const struct debugfs_reg32 hdmi_regs[] = {
 133         VC4_REG32(VC4_HDMI_CORE_REV),
 134         VC4_REG32(VC4_HDMI_SW_RESET_CONTROL),
 135         VC4_REG32(VC4_HDMI_HOTPLUG_INT),
 136         VC4_REG32(VC4_HDMI_HOTPLUG),
 137         VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP),
 138         VC4_REG32(VC4_HDMI_MAI_CONFIG),
 139         VC4_REG32(VC4_HDMI_MAI_FORMAT),
 140         VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG),
 141         VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG),
 142         VC4_REG32(VC4_HDMI_HORZA),
 143         VC4_REG32(VC4_HDMI_HORZB),
 144         VC4_REG32(VC4_HDMI_FIFO_CTL),
 145         VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL),
 146         VC4_REG32(VC4_HDMI_VERTA0),
 147         VC4_REG32(VC4_HDMI_VERTA1),
 148         VC4_REG32(VC4_HDMI_VERTB0),
 149         VC4_REG32(VC4_HDMI_VERTB1),
 150         VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL),
 151         VC4_REG32(VC4_HDMI_TX_PHY_CTL0),
 152
 153         VC4_REG32(VC4_HDMI_CEC_CNTRL_1),
 154         VC4_REG32(VC4_HDMI_CEC_CNTRL_2),
 155         VC4_REG32(VC4_HDMI_CEC_CNTRL_3),
 156         VC4_REG32(VC4_HDMI_CEC_CNTRL_4),
 157         VC4_REG32(VC4_HDMI_CEC_CNTRL_5),
 158         VC4_REG32(VC4_HDMI_CPU_STATUS),
 159         VC4_REG32(VC4_HDMI_CPU_MASK_STATUS),
 160
 161         VC4_REG32(VC4_HDMI_CEC_RX_DATA_1),
 162         VC4_REG32(VC4_HDMI_CEC_RX_DATA_2),
 163         VC4_REG32(VC4_HDMI_CEC_RX_DATA_3),
 164         VC4_REG32(VC4_HDMI_CEC_RX_DATA_4),
 165         VC4_REG32(VC4_HDMI_CEC_TX_DATA_1),
 166         VC4_REG32(VC4_HDMI_CEC_TX_DATA_2),
 167         VC4_REG32(VC4_HDMI_CEC_TX_DATA_3),
 168         VC4_REG32(VC4_HDMI_CEC_TX_DATA_4),
 169 };
 170
 171 static const struct debugfs_reg32 hd_regs[] = {
 172         VC4_REG32(VC4_HD_M_CTL),
 173         VC4_REG32(VC4_HD_MAI_CTL),
 174         VC4_REG32(VC4_HD_MAI_THR),
 175         VC4_REG32(VC4_HD_MAI_FMT),
 176         VC4_REG32(VC4_HD_MAI_SMP),
 177         VC4_REG32(VC4_HD_VID_CTL),
 178         VC4_REG32(VC4_HD_CSC_CTL),
 179         VC4_REG32(VC4_HD_FRAME_COUNT),
 180 };
 181
 182 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 183 {
 184         struct drm_info_node *node = (struct drm_info_node *)m->private;
 185         struct drm_device *dev = node->minor->dev;
 186         struct vc4_dev *vc4 = to_vc4_dev(dev);
 187         struct vc4_hdmi *hdmi = vc4->hdmi;
 188         struct drm_printer p = drm_seq_file_printer(m);
 189
 190         drm_print_regset32(&p, &hdmi->hdmi_regset);
 191         drm_print_regset32(&p, &hdmi->hd_regset);
 192
 193         return 0;
 194 }
 195
 196 static enum drm_connector_status
 197 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 198 {
 199         struct drm_device *dev = connector->dev;
 200         struct vc4_dev *vc4 = to_vc4_dev(dev);
 201
 202         if (vc4->hdmi->hpd_gpio) {
 203                 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
 204                     vc4->hdmi->hpd_active_low)
 205                         return connector_status_connected;
 206                 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
 207                 return connector_status_disconnected;
 208         }
 209
 210         if (drm_probe_ddc(vc4->hdmi->ddc))
 211                 return connector_status_connected;
 212
 213         if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
 214                 return connector_status_connected;
 215         cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
 216         return connector_status_disconnected;
 217 }
 218
 219 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 220 {
 221         drm_connector_unregister(connector);
 222         drm_connector_cleanup(connector);
 223 }
 224
 225 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 226 {
 227         struct vc4_hdmi_connector *vc4_connector =
 228                 to_vc4_hdmi_connector(connector);
 229         struct drm_encoder *encoder = vc4_connector->encoder;
 230         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 231         struct drm_device *dev = connector->dev;
 232         struct vc4_dev *vc4 = to_vc4_dev(dev);
 233         int ret = 0;
 234         struct edid *edid;
 235
 236         edid = drm_get_edid(connector, vc4->hdmi->ddc);
 237         cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
 238         if (!edid)
 239                 return -ENODEV;
 240
 241         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 242
 243         drm_connector_update_edid_property(connector, edid);
 244         ret = drm_add_edid_modes(connector, edid);
 245         kfree(edid);
 246
 247         return ret;
 248 }
 249
 250 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 251 {
 252         drm_atomic_helper_connector_reset(connector);
 253         drm_atomic_helper_connector_tv_reset(connector);
 254 }
 255
 256 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 257         .detect = vc4_hdmi_connector_detect,
 258         .fill_modes = drm_helper_probe_single_connector_modes,
 259         .destroy = vc4_hdmi_connector_destroy,
 260         .reset = vc4_hdmi_connector_reset,
 261         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 262         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 263 };
 264
 265 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 266         .get_modes = vc4_hdmi_connector_get_modes,
 267 };
 268
 269 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
 270                                                      struct drm_encoder *encoder,
 271                                                      struct i2c_adapter *ddc)
 272 {
 273         struct drm_connector *connector;
 274         struct vc4_hdmi_connector *hdmi_connector;
 275         int ret;
 276
 277         hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
 278                                       GFP_KERNEL);
 279         if (!hdmi_connector)
 280                 return ERR_PTR(-ENOMEM);
 281         connector = &hdmi_connector->base;
 282
 283         hdmi_connector->encoder = encoder;
 284
 285         drm_connector_init_with_ddc(dev, connector,
 286                                     &vc4_hdmi_connector_funcs,
 287                                     DRM_MODE_CONNECTOR_HDMIA,
 288                                     ddc);
 289         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 290
 291         /* Create and attach TV margin props to this connector. */
 292         ret = drm_mode_create_tv_margin_properties(dev);
 293         if (ret)
 294                 return ERR_PTR(ret);
 295
 296         drm_connector_attach_tv_margin_properties(connector);
 297
 298         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 299                              DRM_CONNECTOR_POLL_DISCONNECT);
 300
 301         connector->interlace_allowed = 1;
 302         connector->doublescan_allowed = 0;
 303
 304         drm_connector_attach_encoder(connector, encoder);
 305
 306         return connector;
 307 }
 308
 309 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
 310 {
 311         drm_encoder_cleanup(encoder);
 312 }
 313
 314 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
 315         .destroy = vc4_hdmi_encoder_destroy,
 316 };
 317
 318 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 319                                 enum hdmi_infoframe_type type)
 320 {
 321         struct drm_device *dev = encoder->dev;
 322         struct vc4_dev *vc4 = to_vc4_dev(dev);
 323         u32 packet_id = type - 0x80;
 324
 325         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 326                    HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 327
 328         return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
 329                           BIT(packet_id)), 100);
 330 }
 331
 332 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 333                                      union hdmi_infoframe *frame)
 334 {
 335         struct drm_device *dev = encoder->dev;
 336         struct vc4_dev *vc4 = to_vc4_dev(dev);
 337         u32 packet_id = frame->any.type - 0x80;
 338         u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
 339         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 340         ssize_t len, i;
 341         int ret;
 342
 343         WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 344                     VC4_HDMI_RAM_PACKET_ENABLE),
 345                   "Packet RAM has to be on to store the packet.");
 346
 347         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 348         if (len < 0)
 349                 return;
 350
 351         ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
 352         if (ret) {
 353                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 354                 return;
 355         }
 356
 357         for (i = 0; i < len; i += 7) {
 358                 HDMI_WRITE(packet_reg,
 359                            buffer[i + 0] << 0 |
 360                            buffer[i + 1] << 8 |
 361                            buffer[i + 2] << 16);
 362                 packet_reg += 4;
 363
 364                 HDMI_WRITE(packet_reg,
 365                            buffer[i + 3] << 0 |
 366                            buffer[i + 4] << 8 |
 367                            buffer[i + 5] << 16 |
 368                            buffer[i + 6] << 24);
 369                 packet_reg += 4;
 370         }
 371
 372         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 373                    HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 374         ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
 375                         BIT(packet_id)), 100);
 376         if (ret)
 377                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 378 }
 379
 380 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 381 {
 382         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 383         struct vc4_dev *vc4 = encoder->dev->dev_private;
 384         struct vc4_hdmi *hdmi = vc4->hdmi;
 385         struct drm_connector_state *cstate = hdmi->connector->state;
 386         struct drm_crtc *crtc = encoder->crtc;
 387         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 388         union hdmi_infoframe frame;
 389         int ret;
 390
 391         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 392                                                        hdmi->connector, mode);
 393         if (ret < 0) {
 394                 DRM_ERROR("couldn't fill AVI infoframe\n");
 395                 return;
 396         }
 397
 398         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 399                                            hdmi->connector, mode,
 400                                            vc4_encoder->limited_rgb_range ?
 401                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 402                                            HDMI_QUANTIZATION_RANGE_FULL);
 403
 404         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 405
 406         vc4_hdmi_write_infoframe(encoder, &frame);
 407 }
 408
 409 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 410 {
 411         union hdmi_infoframe frame;
 412         int ret;
 413
 414         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 415         if (ret < 0) {
 416                 DRM_ERROR("couldn't fill SPD infoframe\n");
 417                 return;
 418         }
 419
 420         frame.spd.sdi = HDMI_SPD_SDI_PC;
 421
 422         vc4_hdmi_write_infoframe(encoder, &frame);
 423 }
 424
 425 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 426 {
 427         struct drm_device *drm = encoder->dev;
 428         struct vc4_dev *vc4 = drm->dev_private;
 429         struct vc4_hdmi *hdmi = vc4->hdmi;
 430         union hdmi_infoframe frame;
 431         int ret;
 432
 433         ret = hdmi_audio_infoframe_init(&frame.audio);
 434
 435         frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
 436         frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
 437         frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
 438         frame.audio.channels = hdmi->audio.channels;
 439
 440         vc4_hdmi_write_infoframe(encoder, &frame);
 441 }
 442
 443 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 444 {
 445         vc4_hdmi_set_avi_infoframe(encoder);
 446         vc4_hdmi_set_spd_infoframe(encoder);
 447 }
 448
 449 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 450 {
 451         struct drm_device *dev = encoder->dev;
 452         struct vc4_dev *vc4 = to_vc4_dev(dev);
 453         struct vc4_hdmi *hdmi = vc4->hdmi;
 454         int ret;
 455
 456         HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
 457
 458         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 459         HD_WRITE(VC4_HD_VID_CTL,
 460                  HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 461
 462         clk_disable_unprepare(hdmi->pixel_clock);
 463
 464         ret = pm_runtime_put(&hdmi->pdev->dev);
 465         if (ret < 0)
 466                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 467 }
 468
 469 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 470 {
 471         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 472         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 473         struct drm_device *dev = encoder->dev;
 474         struct vc4_dev *vc4 = to_vc4_dev(dev);
 475         struct vc4_hdmi *hdmi = vc4->hdmi;
 476         bool debug_dump_regs = false;
 477         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 478         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 479         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 480         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 481         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 482                                    VC4_HDMI_VERTA_VSP) |
 483                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 484                                    VC4_HDMI_VERTA_VFP) |
 485                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 486         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 487                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 488                                    VC4_HDMI_VERTB_VBP));
 489         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 490                           VC4_SET_FIELD(mode->crtc_vtotal -
 491                                         mode->crtc_vsync_end -
 492                                         interlaced,
 493                                         VC4_HDMI_VERTB_VBP));
 494         u32 csc_ctl;
 495         int ret;
 496
 497         ret = pm_runtime_get_sync(&hdmi->pdev->dev);
 498         if (ret < 0) {
 499                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 500                 return;
 501         }
 502
 503         ret = clk_set_rate(hdmi->pixel_clock,
 504                            mode->clock * 1000 *
 505                            ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
 506         if (ret) {
 507                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 508                 return;
 509         }
 510
 511         ret = clk_prepare_enable(hdmi->pixel_clock);
 512         if (ret) {
 513                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 514                 return;
 515         }
 516
 517         HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
 518                    VC4_HDMI_SW_RESET_HDMI |
 519                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 520
 521         HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
 522
 523         /* PHY should be in reset, like
 524          * vc4_hdmi_encoder_disable() does.
 525          */
 526         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 527
 528         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
 529
 530         if (debug_dump_regs) {
 531                 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev);
 532
 533                 dev_info(&hdmi->pdev->dev, "HDMI regs before:\n");
 534                 drm_print_regset32(&p, &hdmi->hdmi_regset);
 535                 drm_print_regset32(&p, &hdmi->hd_regset);
 536         }
 537
 538         HD_WRITE(VC4_HD_VID_CTL, 0);
 539
 540         HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 541                    HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 542                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 543                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 544
 545         HDMI_WRITE(VC4_HDMI_HORZA,
 546                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 547                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 548                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 549                                  VC4_HDMI_HORZA_HAP));
 550
 551         HDMI_WRITE(VC4_HDMI_HORZB,
 552                    VC4_SET_FIELD((mode->htotal -
 553                                   mode->hsync_end) * pixel_rep,
 554                                  VC4_HDMI_HORZB_HBP) |
 555                    VC4_SET_FIELD((mode->hsync_end -
 556                                   mode->hsync_start) * pixel_rep,
 557                                  VC4_HDMI_HORZB_HSP) |
 558                    VC4_SET_FIELD((mode->hsync_start -
 559                                   mode->hdisplay) * pixel_rep,
 560                                  VC4_HDMI_HORZB_HFP));
 561
 562         HDMI_WRITE(VC4_HDMI_VERTA0, verta);
 563         HDMI_WRITE(VC4_HDMI_VERTA1, verta);
 564
 565         HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
 566         HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
 567
 568         HD_WRITE(VC4_HD_VID_CTL,
 569                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 570                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 571
 572         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 573                                 VC4_HD_CSC_CTL_ORDER);
 574
 575         if (vc4_encoder->hdmi_monitor &&
 576             drm_default_rgb_quant_range(mode) ==
 577             HDMI_QUANTIZATION_RANGE_LIMITED) {
 578                 /* CEA VICs other than #1 requre limited range RGB
 579                  * output unless overridden by an AVI infoframe.
 580                  * Apply a colorspace conversion to squash 0-255 down
 581                  * to 16-235.  The matrix here is:
 582                  *
 583                  * [ 0      0      0.8594 16]
 584                  * [ 0      0.8594 0      16]
 585                  * [ 0.8594 0      0      16]
 586                  * [ 0      0      0       1]
 587                  */
 588                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 589                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 590                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 591                                          VC4_HD_CSC_CTL_MODE);
 592
 593                 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
 594                 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
 595                 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
 596                 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
 597                 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
 598                 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
 599                 vc4_encoder->limited_rgb_range = true;
 600         } else {
 601                 vc4_encoder->limited_rgb_range = false;
 602         }
 603
 604         /* The RGB order applies even when CSC is disabled. */
 605         HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
 606
 607         HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 608
 609         if (debug_dump_regs) {
 610                 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev);
 611
 612                 dev_info(&hdmi->pdev->dev, "HDMI regs after:\n");
 613                 drm_print_regset32(&p, &hdmi->hdmi_regset);
 614                 drm_print_regset32(&p, &hdmi->hd_regset);
 615         }
 616
 617         HD_WRITE(VC4_HD_VID_CTL,
 618                  HD_READ(VC4_HD_VID_CTL) |
 619                  VC4_HD_VID_CTL_ENABLE |
 620                  VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 621                  VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
 622
 623         if (vc4_encoder->hdmi_monitor) {
 624                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 625                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 626                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 627
 628                 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 629                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
 630                 WARN_ONCE(ret, "Timeout waiting for "
 631                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 632         } else {
 633                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 634                            HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 635                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 636                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 637                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 638                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 639
 640                 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 641                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
 642                 WARN_ONCE(ret, "Timeout waiting for "
 643                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 644         }
 645
 646         if (vc4_encoder->hdmi_monitor) {
 647                 u32 drift;
 648
 649                 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 650                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 651                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 652                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 653                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 654
 655                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 656                            VC4_HDMI_RAM_PACKET_ENABLE);
 657
 658                 vc4_hdmi_set_infoframes(encoder);
 659
 660                 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
 661                 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 662
 663                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 664                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 665                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 666                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 667                 usleep_range(1000, 1100);
 668                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 669                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 670                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 671                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 672
 673                 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
 674                                VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 675                 WARN_ONCE(ret, "Timeout waiting for "
 676                           "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 677         }
 678 }
 679
 680 static enum drm_mode_status
 681 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc,
 682                             const struct drm_display_mode *mode)
 683 {
 684         /*
 685          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 686          * be faster than pixel clock, infinitesimally faster, tested in
 687          * simulation. Otherwise, exact value is unimportant for HDMI
 688          * operation." This conflicts with bcm2835's vc4 documentation, which
 689          * states HSM's clock has to be at least 108% of the pixel clock.
 690          *
 691          * Real life tests reveal that vc4's firmware statement holds up, and
 692          * users are able to use pixel clocks closer to HSM's, namely for
 693          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 694          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 695          * 162MHz.
 696          *
 697          * Additionally, the AXI clock needs to be at least 25% of
 698          * pixel clock, but HSM ends up being the limiting factor.
 699          */
 700         if (mode->clock > HSM_CLOCK_FREQ / (1000 * 101 / 100))
 701                 return MODE_CLOCK_HIGH;
 702
 703         return MODE_OK;
 704 }
 705
 706 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 707         .mode_valid = vc4_hdmi_encoder_mode_valid,
 708         .disable = vc4_hdmi_encoder_disable,
 709         .enable = vc4_hdmi_encoder_enable,
 710 };
 711
 712 /* HDMI audio codec callbacks */
 713 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
 714 {
 715         struct drm_device *drm = hdmi->encoder->dev;
 716         struct vc4_dev *vc4 = to_vc4_dev(drm);
 717         u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
 718         unsigned long n, m;
 719
 720         rational_best_approximation(hsm_clock, hdmi->audio.samplerate,
 721                                     VC4_HD_MAI_SMP_N_MASK >>
 722                                     VC4_HD_MAI_SMP_N_SHIFT,
 723                                     (VC4_HD_MAI_SMP_M_MASK >>
 724                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
 725                                     &n, &m);
 726
 727         HD_WRITE(VC4_HD_MAI_SMP,
 728                  VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
 729                  VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
 730 }
 731
 732 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
 733 {
 734         struct drm_encoder *encoder = hdmi->encoder;
 735         struct drm_crtc *crtc = encoder->crtc;
 736         struct drm_device *drm = encoder->dev;
 737         struct vc4_dev *vc4 = to_vc4_dev(drm);
 738         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 739         u32 samplerate = hdmi->audio.samplerate;
 740         u32 n, cts;
 741         u64 tmp;
 742
 743         n = 128 * samplerate / 1000;
 744         tmp = (u64)(mode->clock * 1000) * n;
 745         do_div(tmp, 128 * samplerate);
 746         cts = tmp;
 747
 748         HDMI_WRITE(VC4_HDMI_CRP_CFG,
 749                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
 750                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
 751
 752         /*
 753          * We could get slightly more accurate clocks in some cases by
 754          * providing a CTS_1 value.  The two CTS values are alternated
 755          * between based on the period fields
 756          */
 757         HDMI_WRITE(VC4_HDMI_CTS_0, cts);
 758         HDMI_WRITE(VC4_HDMI_CTS_1, cts);
 759 }
 760
 761 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
 762 {
 763         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
 764
 765         return snd_soc_card_get_drvdata(card);
 766 }
 767
 768 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
 769                                   struct snd_soc_dai *dai)
 770 {
 771         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 772         struct drm_encoder *encoder = hdmi->encoder;
 773         struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
 774         int ret;
 775
 776         if (hdmi->audio.substream && hdmi->audio.substream != substream)
 777                 return -EINVAL;
 778
 779         hdmi->audio.substream = substream;
 780
 781         /*
 782          * If the HDMI encoder hasn't probed, or the encoder is
 783          * currently in DVI mode, treat the codec dai as missing.
 784          */
 785         if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 786                                 VC4_HDMI_RAM_PACKET_ENABLE))
 787                 return -ENODEV;
 788
 789         ret = snd_pcm_hw_constraint_eld(substream->runtime,
 790                                         hdmi->connector->eld);
 791         if (ret)
 792                 return ret;
 793
 794         return 0;
 795 }
 796
 797 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 798 {
 799         return 0;
 800 }
 801
 802 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi)
 803 {
 804         struct drm_encoder *encoder = hdmi->encoder;
 805         struct drm_device *drm = encoder->dev;
 806         struct device *dev = &hdmi->pdev->dev;
 807         struct vc4_dev *vc4 = to_vc4_dev(drm);
 808         int ret;
 809
 810         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
 811         if (ret)
 812                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
 813
 814         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET);
 815         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
 816         HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
 817 }
 818
 819 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
 820                                     struct snd_soc_dai *dai)
 821 {
 822         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 823
 824         if (substream != hdmi->audio.substream)
 825                 return;
 826
 827         vc4_hdmi_audio_reset(hdmi);
 828
 829         hdmi->audio.substream = NULL;
 830 }
 831
 832 /* HDMI audio codec callbacks */
 833 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
 834                                     struct snd_pcm_hw_params *params,
 835                                     struct snd_soc_dai *dai)
 836 {
 837         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 838         struct drm_encoder *encoder = hdmi->encoder;
 839         struct drm_device *drm = encoder->dev;
 840         struct device *dev = &hdmi->pdev->dev;
 841         struct vc4_dev *vc4 = to_vc4_dev(drm);
 842         u32 audio_packet_config, channel_mask;
 843         u32 channel_map, i;
 844
 845         if (substream != hdmi->audio.substream)
 846                 return -EINVAL;
 847
 848         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
 849                 params_rate(params), params_width(params),
 850                 params_channels(params));
 851
 852         hdmi->audio.channels = params_channels(params);
 853         hdmi->audio.samplerate = params_rate(params);
 854
 855         HD_WRITE(VC4_HD_MAI_CTL,
 856                  VC4_HD_MAI_CTL_RESET |
 857                  VC4_HD_MAI_CTL_FLUSH |
 858                  VC4_HD_MAI_CTL_DLATE |
 859                  VC4_HD_MAI_CTL_ERRORE |
 860                  VC4_HD_MAI_CTL_ERRORF);
 861
 862         vc4_hdmi_audio_set_mai_clock(hdmi);
 863
 864         audio_packet_config =
 865                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
 866                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
 867                 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
 868
 869         channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
 870         audio_packet_config |= VC4_SET_FIELD(channel_mask,
 871                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
 872
 873         /* Set the MAI threshold.  This logic mimics the firmware's. */
 874         if (hdmi->audio.samplerate > 96000) {
 875                 HD_WRITE(VC4_HD_MAI_THR,
 876                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
 877                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 878         } else if (hdmi->audio.samplerate > 48000) {
 879                 HD_WRITE(VC4_HD_MAI_THR,
 880                          VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
 881                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 882         } else {
 883                 HD_WRITE(VC4_HD_MAI_THR,
 884                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
 885                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
 886                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
 887                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
 888         }
 889
 890         HDMI_WRITE(VC4_HDMI_MAI_CONFIG,
 891                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
 892                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
 893
 894         channel_map = 0;
 895         for (i = 0; i < 8; i++) {
 896                 if (channel_mask & BIT(i))
 897                         channel_map |= i << (3 * i);
 898         }
 899
 900         HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);
 901         HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
 902         vc4_hdmi_set_n_cts(hdmi);
 903
 904         return 0;
 905 }
 906
 907 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
 908                                   struct snd_soc_dai *dai)
 909 {
 910         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
 911         struct drm_encoder *encoder = hdmi->encoder;
 912         struct drm_device *drm = encoder->dev;
 913         struct vc4_dev *vc4 = to_vc4_dev(drm);
 914
 915         switch (cmd) {
 916         case SNDRV_PCM_TRIGGER_START:
 917                 vc4_hdmi_set_audio_infoframe(encoder);
 918                 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
 919                            HDMI_READ(VC4_HDMI_TX_PHY_CTL0) &
 920                            ~VC4_HDMI_TX_PHY_RNG_PWRDN);
 921                 HD_WRITE(VC4_HD_MAI_CTL,
 922                          VC4_SET_FIELD(hdmi->audio.channels,
 923                                        VC4_HD_MAI_CTL_CHNUM) |
 924                          VC4_HD_MAI_CTL_ENABLE);
 925                 break;
 926         case SNDRV_PCM_TRIGGER_STOP:
 927                 HD_WRITE(VC4_HD_MAI_CTL,
 928                          VC4_HD_MAI_CTL_DLATE |
 929                          VC4_HD_MAI_CTL_ERRORE |
 930                          VC4_HD_MAI_CTL_ERRORF);
 931                 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
 932                            HDMI_READ(VC4_HDMI_TX_PHY_CTL0) |
 933                            VC4_HDMI_TX_PHY_RNG_PWRDN);
 934                 break;
 935         default:
 936                 break;
 937         }
 938
 939         return 0;
 940 }
 941
 942 static inline struct vc4_hdmi *
 943 snd_component_to_hdmi(struct snd_soc_component *component)
 944 {
 945         struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
 946
 947         return snd_soc_card_get_drvdata(card);
 948 }
 949
 950 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
 951                                        struct snd_ctl_elem_info *uinfo)
 952 {
 953         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 954         struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
 955
 956         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 957         uinfo->count = sizeof(hdmi->connector->eld);
 958
 959         return 0;
 960 }
 961
 962 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
 963                                       struct snd_ctl_elem_value *ucontrol)
 964 {
 965         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 966         struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
 967
 968         memcpy(ucontrol->value.bytes.data, hdmi->connector->eld,
 969                sizeof(hdmi->connector->eld));
 970
 971         return 0;
 972 }
 973
 974 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
 975         {
 976                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
 977                           SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 978                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 979                 .name = "ELD",
 980                 .info = vc4_hdmi_audio_eld_ctl_info,
 981                 .get = vc4_hdmi_audio_eld_ctl_get,
 982         },
 983 };
 984
 985 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
 986         SND_SOC_DAPM_OUTPUT("TX"),
 987 };
 988
 989 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
 990         { "TX", NULL, "Playback" },
 991 };
 992
 993 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
 994         .controls               = vc4_hdmi_audio_controls,
 995         .num_controls           = ARRAY_SIZE(vc4_hdmi_audio_controls),
 996         .dapm_widgets           = vc4_hdmi_audio_widgets,
 997         .num_dapm_widgets       = ARRAY_SIZE(vc4_hdmi_audio_widgets),
 998         .dapm_routes            = vc4_hdmi_audio_routes,
 999         .num_dapm_routes        = ARRAY_SIZE(vc4_hdmi_audio_routes),
1000         .idle_bias_on           = 1,
1001         .use_pmdown_time        = 1,
1002         .endianness             = 1,
1003         .non_legacy_dai_naming  = 1,
1004 };
1005
1006 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1007         .startup = vc4_hdmi_audio_startup,
1008         .shutdown = vc4_hdmi_audio_shutdown,
1009         .hw_params = vc4_hdmi_audio_hw_params,
1010         .set_fmt = vc4_hdmi_audio_set_fmt,
1011         .trigger = vc4_hdmi_audio_trigger,
1012 };
1013
1014 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1015         .name = "vc4-hdmi-hifi",
1016         .playback = {
1017                 .stream_name = "Playback",
1018                 .channels_min = 2,
1019                 .channels_max = 8,
1020                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1021                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1022                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1023                          SNDRV_PCM_RATE_192000,
1024                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1025         },
1026 };
1027
1028 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1029         .name = "vc4-hdmi-cpu-dai-component",
1030 };
1031
1032 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1033 {
1034         struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
1035
1036         snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL);
1037
1038         return 0;
1039 }
1040
1041 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1042         .name = "vc4-hdmi-cpu-dai",
1043         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1044         .playback = {
1045                 .stream_name = "Playback",
1046                 .channels_min = 1,
1047                 .channels_max = 8,
1048                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1049                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1050                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1051                          SNDRV_PCM_RATE_192000,
1052                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1053         },
1054         .ops = &vc4_hdmi_audio_dai_ops,
1055 };
1056
1057 static const struct snd_dmaengine_pcm_config pcm_conf = {
1058         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1059         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1060 };
1061
1062 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi)
1063 {
1064         struct snd_soc_dai_link *dai_link = &hdmi->audio.link;
1065         struct snd_soc_card *card = &hdmi->audio.card;
1066         struct device *dev = &hdmi->pdev->dev;
1067         const __be32 *addr;
1068         int ret;
1069
1070         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1071                 dev_warn(dev,
1072                          "'dmas' DT property is missing, no HDMI audio\n");
1073                 return 0;
1074         }
1075
1076         /*
1077          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1078          * the bus address specified in the DT, because the physical address
1079          * (the one returned by platform_get_resource()) is not appropriate
1080          * for DMA transfers.
1081          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1082          */
1083         addr = of_get_address(dev->of_node, 1, NULL, NULL);
1084         hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA;
1085         hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1086         hdmi->audio.dma_data.maxburst = 2;
1087
1088         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1089         if (ret) {
1090                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1091                 return ret;
1092         }
1093
1094         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1095                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1096         if (ret) {
1097                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1098                 return ret;
1099         }
1100
1101         /* register component and codec dai */
1102         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1103                                      &vc4_hdmi_audio_codec_dai_drv, 1);
1104         if (ret) {
1105                 dev_err(dev, "Could not register component: %d\n", ret);
1106                 return ret;
1107         }
1108
1109         dai_link->cpus          = &hdmi->audio.cpu;
1110         dai_link->codecs        = &hdmi->audio.codec;
1111         dai_link->platforms     = &hdmi->audio.platform;
1112
1113         dai_link->num_cpus      = 1;
1114         dai_link->num_codecs    = 1;
1115         dai_link->num_platforms = 1;
1116
1117         dai_link->name = "MAI";
1118         dai_link->stream_name = "MAI PCM";
1119         dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1120         dai_link->cpus->dai_name = dev_name(dev);
1121         dai_link->codecs->name = dev_name(dev);
1122         dai_link->platforms->name = dev_name(dev);
1123
1124         card->dai_link = dai_link;
1125         card->num_links = 1;
1126         card->name = "vc4-hdmi";
1127         card->dev = dev;
1128
1129         /*
1130          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1131          * stores a pointer to the snd card object in dev->driver_data. This
1132          * means we cannot use it for something else. The hdmi back-pointer is
1133          * now stored in card->drvdata and should be retrieved with
1134          * snd_soc_card_get_drvdata() if needed.
1135          */
1136         snd_soc_card_set_drvdata(card, hdmi);
1137         ret = devm_snd_soc_register_card(dev, card);
1138         if (ret)
1139                 dev_err(dev, "Could not register sound card: %d\n", ret);
1140
1141         return ret;
1142
1143 }
1144
1145 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1146 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1147 {
1148         struct vc4_dev *vc4 = priv;
1149         struct vc4_hdmi *hdmi = vc4->hdmi;
1150
1151         if (hdmi->cec_irq_was_rx) {
1152                 if (hdmi->cec_rx_msg.len)
1153                         cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg);
1154         } else if (hdmi->cec_tx_ok) {
1155                 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK,
1156                                   0, 0, 0, 0);
1157         } else {
1158                 /*
1159                  * This CEC implementation makes 1 retry, so if we
1160                  * get a NACK, then that means it made 2 attempts.
1161                  */
1162                 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK,
1163                                   0, 2, 0, 0);
1164         }
1165         return IRQ_HANDLED;
1166 }
1167
1168 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
1169 {
1170         struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
1171         unsigned int i;
1172
1173         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1174                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1175         for (i = 0; i < msg->len; i += 4) {
1176                 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i);
1177
1178                 msg->msg[i] = val & 0xff;
1179                 msg->msg[i + 1] = (val >> 8) & 0xff;
1180                 msg->msg[i + 2] = (val >> 16) & 0xff;
1181                 msg->msg[i + 3] = (val >> 24) & 0xff;
1182         }
1183 }
1184
1185 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1186 {
1187         struct vc4_dev *vc4 = priv;
1188         struct vc4_hdmi *hdmi = vc4->hdmi;
1189         u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
1190         u32 cntrl1, cntrl5;
1191
1192         if (!(stat & VC4_HDMI_CPU_CEC))
1193                 return IRQ_NONE;
1194         hdmi->cec_rx_msg.len = 0;
1195         cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1196         cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1197         hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1198         if (hdmi->cec_irq_was_rx) {
1199                 vc4_cec_read_msg(vc4, cntrl1);
1200                 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1201                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1202                 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1203         } else {
1204                 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1205                 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1206         }
1207         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1208         HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1209
1210         return IRQ_WAKE_THREAD;
1211 }
1212
1213 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1214 {
1215         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1216         /* clock period in microseconds */
1217         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1218         u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1219
1220         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1221                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1222                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1223         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1224                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1225
1226         if (enable) {
1227                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1228                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1229                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);
1230                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,
1231                          ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1232                          ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1233                          ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1234                          ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1235                          ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1236                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,
1237                          ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1238                          ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1239                          ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1240                          ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1241                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,
1242                          ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1243                          ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1244                          ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1245                          ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1246
1247                 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1248         } else {
1249                 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1250                 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1251                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1252         }
1253         return 0;
1254 }
1255
1256 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1257 {
1258         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1259
1260         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
1261                    (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1262                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1263         return 0;
1264 }
1265
1266 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1267                                       u32 signal_free_time, struct cec_msg *msg)
1268 {
1269         struct vc4_dev *vc4 = cec_get_drvdata(adap);
1270         u32 val;
1271         unsigned int i;
1272
1273         for (i = 0; i < msg->len; i += 4)
1274                 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,
1275                            (msg->msg[i]) |
1276                            (msg->msg[i + 1] << 8) |
1277                            (msg->msg[i + 2] << 16) |
1278                            (msg->msg[i + 3] << 24));
1279
1280         val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1281         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1282         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1283         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1284         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1285         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1286
1287         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1288         return 0;
1289 }
1290
1291 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1292         .adap_enable = vc4_hdmi_cec_adap_enable,
1293         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1294         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1295 };
1296 #endif
1297
1298 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1299 {
1300 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1301         struct cec_connector_info conn_info;
1302 #endif
1303         struct platform_device *pdev = to_platform_device(dev);
1304         struct drm_device *drm = dev_get_drvdata(master);
1305         struct vc4_dev *vc4 = drm->dev_private;
1306         struct vc4_hdmi *hdmi;
1307         struct vc4_hdmi_encoder *vc4_hdmi_encoder;
1308         struct device_node *ddc_node;
1309         u32 value;
1310         int ret;
1311
1312         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1313         if (!hdmi)
1314                 return -ENOMEM;
1315
1316         vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
1317                                         GFP_KERNEL);
1318         if (!vc4_hdmi_encoder)
1319                 return -ENOMEM;
1320         vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
1321         hdmi->encoder = &vc4_hdmi_encoder->base.base;
1322
1323         hdmi->pdev = pdev;
1324         hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1325         if (IS_ERR(hdmi->hdmicore_regs))
1326                 return PTR_ERR(hdmi->hdmicore_regs);
1327
1328         hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1329         if (IS_ERR(hdmi->hd_regs))
1330                 return PTR_ERR(hdmi->hd_regs);
1331
1332         hdmi->hdmi_regset.base = hdmi->hdmicore_regs;
1333         hdmi->hdmi_regset.regs = hdmi_regs;
1334         hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs);
1335         hdmi->hd_regset.base = hdmi->hd_regs;
1336         hdmi->hd_regset.regs = hd_regs;
1337         hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs);
1338
1339         hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1340         if (IS_ERR(hdmi->pixel_clock)) {
1341                 DRM_ERROR("Failed to get pixel clock\n");
1342                 return PTR_ERR(hdmi->pixel_clock);
1343         }
1344         hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1345         if (IS_ERR(hdmi->hsm_clock)) {
1346                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1347                 return PTR_ERR(hdmi->hsm_clock);
1348         }
1349
1350         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1351         if (!ddc_node) {
1352                 DRM_ERROR("Failed to find ddc node in device tree\n");
1353                 return -ENODEV;
1354         }
1355
1356         hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1357         of_node_put(ddc_node);
1358         if (!hdmi->ddc) {
1359                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1360                 return -EPROBE_DEFER;
1361         }
1362
1363         /* This is the rate that is set by the firmware.  The number
1364          * needs to be a bit higher than the pixel clock rate
1365          * (generally 148.5Mhz).
1366          */
1367         ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ);
1368         if (ret) {
1369                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1370                 goto err_put_i2c;
1371         }
1372
1373         ret = clk_prepare_enable(hdmi->hsm_clock);
1374         if (ret) {
1375                 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1376                           ret);
1377                 goto err_put_i2c;
1378         }
1379
1380         /* Only use the GPIO HPD pin if present in the DT, otherwise
1381          * we'll use the HDMI core's register.
1382          */
1383         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1384                 enum of_gpio_flags hpd_gpio_flags;
1385
1386                 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1387                                                          "hpd-gpios", 0,
1388                                                          &hpd_gpio_flags);
1389                 if (hdmi->hpd_gpio < 0) {
1390                         ret = hdmi->hpd_gpio;
1391                         goto err_unprepare_hsm;
1392                 }
1393
1394                 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1395         }
1396
1397         vc4->hdmi = hdmi;
1398
1399         /* HDMI core must be enabled. */
1400         if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
1401                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
1402                 udelay(1);
1403                 HD_WRITE(VC4_HD_M_CTL, 0);
1404
1405                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
1406         }
1407         pm_runtime_enable(dev);
1408
1409         drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
1410                          DRM_MODE_ENCODER_TMDS, NULL);
1411         drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
1412
1413         hdmi->connector =
1414                 vc4_hdmi_connector_init(drm, hdmi->encoder, hdmi->ddc);
1415         if (IS_ERR(hdmi->connector)) {
1416                 ret = PTR_ERR(hdmi->connector);
1417                 goto err_destroy_encoder;
1418         }
1419 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1420         hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1421                                               vc4, "vc4",
1422                                               CEC_CAP_DEFAULTS |
1423                                               CEC_CAP_CONNECTOR_INFO, 1);
1424         ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
1425         if (ret < 0)
1426                 goto err_destroy_conn;
1427
1428         cec_fill_conn_info_from_drm(&conn_info, hdmi->connector);
1429         cec_s_conn_info(hdmi->cec_adap, &conn_info);
1430
1431         HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);
1432         value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1433         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1434         /*
1435          * Set the logical address to Unregistered and set the clock
1436          * divider: the hsm_clock rate and this divider setting will
1437          * give a 40 kHz CEC clock.
1438          */
1439         value |= VC4_HDMI_CEC_ADDR_MASK |
1440                  (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1441         HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);
1442         ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1443                                         vc4_cec_irq_handler,
1444                                         vc4_cec_irq_handler_thread, 0,
1445                                         "vc4 hdmi cec", vc4);
1446         if (ret)
1447                 goto err_delete_cec_adap;
1448         ret = cec_register_adapter(hdmi->cec_adap, dev);
1449         if (ret < 0)
1450                 goto err_delete_cec_adap;
1451 #endif
1452
1453         ret = vc4_hdmi_audio_init(hdmi);
1454         if (ret)
1455                 goto err_destroy_encoder;
1456
1457         vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, hdmi);
1458
1459         return 0;
1460
1461 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1462 err_delete_cec_adap:
1463         cec_delete_adapter(hdmi->cec_adap);
1464 err_destroy_conn:
1465         vc4_hdmi_connector_destroy(hdmi->connector);
1466 #endif
1467 err_destroy_encoder:
1468         vc4_hdmi_encoder_destroy(hdmi->encoder);
1469 err_unprepare_hsm:
1470         clk_disable_unprepare(hdmi->hsm_clock);
1471         pm_runtime_disable(dev);
1472 err_put_i2c:
1473         put_device(&hdmi->ddc->dev);
1474
1475         return ret;
1476 }
1477
1478 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1479                             void *data)
1480 {
1481         struct drm_device *drm = dev_get_drvdata(master);
1482         struct vc4_dev *vc4 = drm->dev_private;
1483         struct vc4_hdmi *hdmi = vc4->hdmi;
1484
1485         cec_unregister_adapter(hdmi->cec_adap);
1486         vc4_hdmi_connector_destroy(hdmi->connector);
1487         vc4_hdmi_encoder_destroy(hdmi->encoder);
1488
1489         clk_disable_unprepare(hdmi->hsm_clock);
1490         pm_runtime_disable(dev);
1491
1492         put_device(&hdmi->ddc->dev);
1493
1494         vc4->hdmi = NULL;
1495 }
1496
1497 static const struct component_ops vc4_hdmi_ops = {
1498         .bind   = vc4_hdmi_bind,
1499         .unbind = vc4_hdmi_unbind,
1500 };
1501
1502 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1503 {
1504         return component_add(&pdev->dev, &vc4_hdmi_ops);
1505 }
1506
1507 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1508 {
1509         component_del(&pdev->dev, &vc4_hdmi_ops);
1510         return 0;
1511 }
1512
1513 static const struct of_device_id vc4_hdmi_dt_match[] = {
1514         { .compatible = "brcm,bcm2835-hdmi" },
1515         {}
1516 };
1517
1518 struct platform_driver vc4_hdmi_driver = {
1519         .probe = vc4_hdmi_dev_probe,
1520         .remove = vc4_hdmi_dev_remove,
1521         .driver = {
1522                 .name = "vc4_hdmi",
1523                 .of_match_table = vc4_hdmi_dt_match,
1524         },
1525 };