1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
10 * DOC: VC4 Falcon HDMI module
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_probe_helper.h>
37 #include <drm/drm_simple_kms_helper.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <linux/clk.h>
40 #include <linux/component.h>
41 #include <linux/i2c.h>
42 #include <linux/of_address.h>
43 #include <linux/of_gpio.h>
44 #include <linux/of_platform.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/rational.h>
47 #include <linux/reset.h>
48 #include <sound/dmaengine_pcm.h>
49 #include <sound/pcm_drm_eld.h>
50 #include <sound/pcm_params.h>
51 #include <sound/soc.h>
52 #include "media/cec.h"
55 #include "vc4_hdmi_regs.h"
58 #define VC5_HDMI_HORZA_HFP_SHIFT 16
59 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
60 #define VC5_HDMI_HORZA_VPOS BIT(15)
61 #define VC5_HDMI_HORZA_HPOS BIT(14)
62 #define VC5_HDMI_HORZA_HAP_SHIFT 0
63 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
65 #define VC5_HDMI_HORZB_HBP_SHIFT 16
66 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
67 #define VC5_HDMI_HORZB_HSP_SHIFT 0
68 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
70 #define VC5_HDMI_VERTA_VSP_SHIFT 24
71 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
72 #define VC5_HDMI_VERTA_VFP_SHIFT 16
73 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
74 #define VC5_HDMI_VERTA_VAL_SHIFT 0
75 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
77 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
78 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
80 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
82 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
85 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
88 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
90 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
93 # define VC4_HD_M_SW_RST BIT(2)
94 # define VC4_HD_M_ENABLE BIT(0)
96 #define CEC_CLOCK_FREQ 40000
98 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
100 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
102 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
105 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
107 struct drm_info_node *node = (struct drm_info_node *)m->private;
108 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
109 struct drm_printer p = drm_seq_file_printer(m);
111 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
112 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
117 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
119 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
121 HDMI_WRITE(HDMI_M_CTL, 0);
123 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
125 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
126 VC4_HDMI_SW_RESET_HDMI |
127 VC4_HDMI_SW_RESET_FORMAT_DETECT);
129 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
132 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
134 reset_control_reset(vc4_hdmi->reset);
136 HDMI_WRITE(HDMI_DVP_CTL, 0);
138 HDMI_WRITE(HDMI_CLOCK_STOP,
139 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
142 #ifdef CONFIG_DRM_VC4_HDMI_CEC
143 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
148 value = HDMI_READ(HDMI_CEC_CNTRL_1);
149 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
152 * Set the clock divider: the hsm_clock rate and this divider
153 * setting will give a 40 kHz CEC clock.
155 clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
156 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
157 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
160 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
163 static enum drm_connector_status
164 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
166 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
167 bool connected = false;
169 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
171 if (vc4_hdmi->hpd_gpio &&
172 gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) {
174 } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
176 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
181 if (connector->status != connector_status_connected) {
182 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
185 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
186 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
191 pm_runtime_put(&vc4_hdmi->pdev->dev);
192 return connector_status_connected;
195 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
196 pm_runtime_put(&vc4_hdmi->pdev->dev);
197 return connector_status_disconnected;
200 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
202 drm_connector_unregister(connector);
203 drm_connector_cleanup(connector);
206 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
208 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
209 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
213 edid = drm_get_edid(connector, vc4_hdmi->ddc);
214 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
218 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
220 drm_connector_update_edid_property(connector, edid);
221 ret = drm_add_edid_modes(connector, edid);
224 if (vc4_hdmi->disable_4kp60) {
225 struct drm_device *drm = connector->dev;
226 struct drm_display_mode *mode;
228 list_for_each_entry(mode, &connector->probed_modes, head) {
229 if (vc4_hdmi_mode_needs_scrambling(mode)) {
230 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
231 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
239 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
240 struct drm_atomic_state *state)
242 struct drm_connector_state *old_state =
243 drm_atomic_get_old_connector_state(state, connector);
244 struct drm_connector_state *new_state =
245 drm_atomic_get_new_connector_state(state, connector);
246 struct drm_crtc *crtc = new_state->crtc;
251 if (old_state->colorspace != new_state->colorspace ||
252 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
253 struct drm_crtc_state *crtc_state;
255 crtc_state = drm_atomic_get_crtc_state(state, crtc);
256 if (IS_ERR(crtc_state))
257 return PTR_ERR(crtc_state);
259 crtc_state->mode_changed = true;
265 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
267 struct vc4_hdmi_connector_state *old_state =
268 conn_state_to_vc4_hdmi_conn_state(connector->state);
269 struct vc4_hdmi_connector_state *new_state =
270 kzalloc(sizeof(*new_state), GFP_KERNEL);
272 if (connector->state)
273 __drm_atomic_helper_connector_destroy_state(connector->state);
276 __drm_atomic_helper_connector_reset(connector, &new_state->base);
281 new_state->base.max_bpc = 8;
282 new_state->base.max_requested_bpc = 8;
283 drm_atomic_helper_connector_tv_reset(connector);
286 static struct drm_connector_state *
287 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
289 struct drm_connector_state *conn_state = connector->state;
290 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
291 struct vc4_hdmi_connector_state *new_state;
293 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
297 new_state->pixel_rate = vc4_state->pixel_rate;
298 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
300 return &new_state->base;
303 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
304 .detect = vc4_hdmi_connector_detect,
305 .fill_modes = drm_helper_probe_single_connector_modes,
306 .destroy = vc4_hdmi_connector_destroy,
307 .reset = vc4_hdmi_connector_reset,
308 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
309 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
312 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
313 .get_modes = vc4_hdmi_connector_get_modes,
314 .atomic_check = vc4_hdmi_connector_atomic_check,
317 static int vc4_hdmi_connector_init(struct drm_device *dev,
318 struct vc4_hdmi *vc4_hdmi)
320 struct drm_connector *connector = &vc4_hdmi->connector;
321 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
324 drm_connector_init_with_ddc(dev, connector,
325 &vc4_hdmi_connector_funcs,
326 DRM_MODE_CONNECTOR_HDMIA,
328 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
331 * Some of the properties below require access to state, like bpc.
332 * Allocate some default initial connector state with our reset helper.
334 if (connector->funcs->reset)
335 connector->funcs->reset(connector);
337 /* Create and attach TV margin props to this connector. */
338 ret = drm_mode_create_tv_margin_properties(dev);
342 ret = drm_mode_create_hdmi_colorspace_property(connector);
346 drm_connector_attach_colorspace_property(connector);
347 drm_connector_attach_tv_margin_properties(connector);
348 drm_connector_attach_max_bpc_property(connector, 8, 12);
350 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
351 DRM_CONNECTOR_POLL_DISCONNECT);
353 connector->interlace_allowed = 1;
354 connector->doublescan_allowed = 0;
356 if (vc4_hdmi->variant->supports_hdr)
357 drm_connector_attach_hdr_output_metadata_property(connector);
359 drm_connector_attach_encoder(connector, encoder);
364 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
365 enum hdmi_infoframe_type type,
368 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
369 u32 packet_id = type - 0x80;
371 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
372 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
377 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
378 BIT(packet_id)), 100);
381 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
382 union hdmi_infoframe *frame)
384 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
385 u32 packet_id = frame->any.type - 0x80;
386 const struct vc4_hdmi_register *ram_packet_start =
387 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
388 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
389 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
390 ram_packet_start->reg);
391 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
395 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
396 VC4_HDMI_RAM_PACKET_ENABLE),
397 "Packet RAM has to be on to store the packet.");
399 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
403 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
405 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
409 for (i = 0; i < len; i += 7) {
410 writel(buffer[i + 0] << 0 |
416 writel(buffer[i + 3] << 0 |
418 buffer[i + 5] << 16 |
424 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
425 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
426 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
427 BIT(packet_id)), 100);
429 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
432 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
434 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
435 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
436 struct drm_connector *connector = &vc4_hdmi->connector;
437 struct drm_connector_state *cstate = connector->state;
438 struct drm_crtc *crtc = encoder->crtc;
439 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
440 union hdmi_infoframe frame;
443 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
446 DRM_ERROR("couldn't fill AVI infoframe\n");
450 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
452 vc4_encoder->limited_rgb_range ?
453 HDMI_QUANTIZATION_RANGE_LIMITED :
454 HDMI_QUANTIZATION_RANGE_FULL);
455 drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
456 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
458 vc4_hdmi_write_infoframe(encoder, &frame);
461 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
463 union hdmi_infoframe frame;
466 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
468 DRM_ERROR("couldn't fill SPD infoframe\n");
472 frame.spd.sdi = HDMI_SPD_SDI_PC;
474 vc4_hdmi_write_infoframe(encoder, &frame);
477 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
479 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
480 union hdmi_infoframe frame;
482 hdmi_audio_infoframe_init(&frame.audio);
484 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
485 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
486 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
487 frame.audio.channels = vc4_hdmi->audio.channels;
489 vc4_hdmi_write_infoframe(encoder, &frame);
492 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
494 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
495 struct drm_connector *connector = &vc4_hdmi->connector;
496 struct drm_connector_state *conn_state = connector->state;
497 union hdmi_infoframe frame;
499 if (!vc4_hdmi->variant->supports_hdr)
502 if (!conn_state->hdr_output_metadata)
505 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
508 vc4_hdmi_write_infoframe(encoder, &frame);
511 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
513 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
515 vc4_hdmi_set_avi_infoframe(encoder);
516 vc4_hdmi_set_spd_infoframe(encoder);
518 * If audio was streaming, then we need to reenabled the audio
519 * infoframe here during encoder_enable.
521 if (vc4_hdmi->audio.streaming)
522 vc4_hdmi_set_audio_infoframe(encoder);
524 vc4_hdmi_set_hdr_infoframe(encoder);
527 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
528 struct drm_display_mode *mode)
530 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
531 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
532 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
534 if (!vc4_encoder->hdmi_monitor)
537 if (!display->hdmi.scdc.supported ||
538 !display->hdmi.scdc.scrambling.supported)
544 #define SCRAMBLING_POLLING_DELAY_MS 1000
546 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
548 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
549 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
551 if (!vc4_hdmi_supports_scrambling(encoder, mode))
554 if (!vc4_hdmi_mode_needs_scrambling(mode))
557 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
558 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
560 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
561 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
563 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
564 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
567 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
569 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
570 struct drm_crtc *crtc = encoder->crtc;
573 * At boot, encoder->crtc will be NULL. Since we don't know the
574 * state of the scrambler and in order to avoid any
575 * inconsistency, let's disable it all the time.
577 if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
580 if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
583 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
584 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
586 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
587 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
589 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
590 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
593 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
595 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
599 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
602 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
603 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
605 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
606 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
609 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
610 struct drm_atomic_state *state)
612 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
614 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
616 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
617 VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
619 HDMI_WRITE(HDMI_VID_CTL,
620 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
622 vc4_hdmi_disable_scrambling(encoder);
625 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
626 struct drm_atomic_state *state)
628 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
631 if (vc4_hdmi->variant->phy_disable)
632 vc4_hdmi->variant->phy_disable(vc4_hdmi);
634 HDMI_WRITE(HDMI_VID_CTL,
635 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
637 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
638 clk_disable_unprepare(vc4_hdmi->pixel_clock);
640 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
642 DRM_ERROR("Failed to release power domain: %d\n", ret);
645 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
649 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
653 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
654 VC4_HD_CSC_CTL_ORDER);
657 /* CEA VICs other than #1 requre limited range RGB
658 * output unless overridden by an AVI infoframe.
659 * Apply a colorspace conversion to squash 0-255 down
660 * to 16-235. The matrix here is:
667 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
668 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
669 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
670 VC4_HD_CSC_CTL_MODE);
672 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
673 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
674 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
675 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
676 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
677 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
680 /* The RGB order applies even when CSC is disabled. */
681 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
684 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
688 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
691 /* CEA VICs other than #1 requre limited range RGB
692 * output unless overridden by an AVI infoframe.
693 * Apply a colorspace conversion to squash 0-255 down
694 * to 16-235. The matrix here is:
700 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
702 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
703 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
704 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
705 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
706 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
707 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
709 /* Still use the matrix for full range, but make it unity.
710 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
712 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
713 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
714 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
715 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
716 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
717 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
720 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
723 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
724 struct drm_connector_state *state,
725 struct drm_display_mode *mode)
727 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
728 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
729 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
730 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
731 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
732 VC4_HDMI_VERTA_VSP) |
733 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
734 VC4_HDMI_VERTA_VFP) |
735 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
736 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
737 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
738 VC4_HDMI_VERTB_VBP));
739 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
740 VC4_SET_FIELD(mode->crtc_vtotal -
741 mode->crtc_vsync_end -
743 VC4_HDMI_VERTB_VBP));
745 HDMI_WRITE(HDMI_HORZA,
746 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
747 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
748 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
749 VC4_HDMI_HORZA_HAP));
751 HDMI_WRITE(HDMI_HORZB,
752 VC4_SET_FIELD((mode->htotal -
753 mode->hsync_end) * pixel_rep,
754 VC4_HDMI_HORZB_HBP) |
755 VC4_SET_FIELD((mode->hsync_end -
756 mode->hsync_start) * pixel_rep,
757 VC4_HDMI_HORZB_HSP) |
758 VC4_SET_FIELD((mode->hsync_start -
759 mode->hdisplay) * pixel_rep,
760 VC4_HDMI_HORZB_HFP));
762 HDMI_WRITE(HDMI_VERTA0, verta);
763 HDMI_WRITE(HDMI_VERTA1, verta);
765 HDMI_WRITE(HDMI_VERTB0, vertb_even);
766 HDMI_WRITE(HDMI_VERTB1, vertb);
769 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
770 struct drm_connector_state *state,
771 struct drm_display_mode *mode)
773 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
774 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
775 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
776 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
777 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
778 VC5_HDMI_VERTA_VSP) |
779 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
780 VC5_HDMI_VERTA_VFP) |
781 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
782 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
783 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
784 VC4_HDMI_VERTB_VBP));
785 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
786 VC4_SET_FIELD(mode->crtc_vtotal -
787 mode->crtc_vsync_end -
789 VC4_HDMI_VERTB_VBP));
794 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
795 HDMI_WRITE(HDMI_HORZA,
796 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
797 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
798 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
799 VC5_HDMI_HORZA_HAP) |
800 VC4_SET_FIELD((mode->hsync_start -
801 mode->hdisplay) * pixel_rep,
802 VC5_HDMI_HORZA_HFP));
804 HDMI_WRITE(HDMI_HORZB,
805 VC4_SET_FIELD((mode->htotal -
806 mode->hsync_end) * pixel_rep,
807 VC5_HDMI_HORZB_HBP) |
808 VC4_SET_FIELD((mode->hsync_end -
809 mode->hsync_start) * pixel_rep,
810 VC5_HDMI_HORZB_HSP));
812 HDMI_WRITE(HDMI_VERTA0, verta);
813 HDMI_WRITE(HDMI_VERTA1, verta);
815 HDMI_WRITE(HDMI_VERTB0, vertb_even);
816 HDMI_WRITE(HDMI_VERTB1, vertb);
818 switch (state->max_bpc) {
834 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
835 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
836 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
837 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
838 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
839 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
841 reg = HDMI_READ(HDMI_GCP_WORD_1);
842 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
843 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
844 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
846 reg = HDMI_READ(HDMI_GCP_CONFIG);
847 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
848 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
849 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
851 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
854 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
859 drift = HDMI_READ(HDMI_FIFO_CTL);
860 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
862 HDMI_WRITE(HDMI_FIFO_CTL,
863 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
864 HDMI_WRITE(HDMI_FIFO_CTL,
865 drift | VC4_HDMI_FIFO_CTL_RECENTER);
866 usleep_range(1000, 1100);
867 HDMI_WRITE(HDMI_FIFO_CTL,
868 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
869 HDMI_WRITE(HDMI_FIFO_CTL,
870 drift | VC4_HDMI_FIFO_CTL_RECENTER);
872 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
873 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
874 WARN_ONCE(ret, "Timeout waiting for "
875 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
878 static struct drm_connector_state *
879 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
880 struct drm_atomic_state *state)
882 struct drm_connector_state *conn_state;
883 struct drm_connector *connector;
886 for_each_new_connector_in_state(state, connector, conn_state, i) {
887 if (conn_state->best_encoder == encoder)
894 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
895 struct drm_atomic_state *state)
897 struct drm_connector_state *conn_state =
898 vc4_hdmi_encoder_get_connector_state(encoder, state);
899 struct vc4_hdmi_connector_state *vc4_conn_state =
900 conn_state_to_vc4_hdmi_conn_state(conn_state);
901 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
902 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
903 unsigned long bvb_rate, pixel_rate, hsm_rate;
906 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
908 DRM_ERROR("Failed to retain power domain: %d\n", ret);
912 pixel_rate = vc4_conn_state->pixel_rate;
913 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
915 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
919 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
921 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
926 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
927 * be faster than pixel clock, infinitesimally faster, tested in
928 * simulation. Otherwise, exact value is unimportant for HDMI
929 * operation." This conflicts with bcm2835's vc4 documentation, which
930 * states HSM's clock has to be at least 108% of the pixel clock.
932 * Real life tests reveal that vc4's firmware statement holds up, and
933 * users are able to use pixel clocks closer to HSM's, namely for
934 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
935 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
938 * Additionally, the AXI clock needs to be at least 25% of
939 * pixel clock, but HSM ends up being the limiting factor.
941 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
942 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
944 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
948 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
950 if (pixel_rate > 297000000)
951 bvb_rate = 300000000;
952 else if (pixel_rate > 148500000)
953 bvb_rate = 150000000;
957 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
959 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
960 clk_disable_unprepare(vc4_hdmi->pixel_clock);
964 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
966 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
967 clk_disable_unprepare(vc4_hdmi->pixel_clock);
971 if (vc4_hdmi->variant->phy_init)
972 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
974 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
975 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
976 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
977 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
979 if (vc4_hdmi->variant->set_timings)
980 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
983 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
984 struct drm_atomic_state *state)
986 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
987 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
988 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
990 if (vc4_encoder->hdmi_monitor &&
991 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
992 if (vc4_hdmi->variant->csc_setup)
993 vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
995 vc4_encoder->limited_rgb_range = true;
997 if (vc4_hdmi->variant->csc_setup)
998 vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1000 vc4_encoder->limited_rgb_range = false;
1003 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1006 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1007 struct drm_atomic_state *state)
1009 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1010 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1011 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1012 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1013 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1016 HDMI_WRITE(HDMI_VID_CTL,
1017 VC4_HD_VID_CTL_ENABLE |
1018 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1019 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1020 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1021 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1023 HDMI_WRITE(HDMI_VID_CTL,
1024 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1026 if (vc4_encoder->hdmi_monitor) {
1027 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1028 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1029 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1031 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1032 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1033 WARN_ONCE(ret, "Timeout waiting for "
1034 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1036 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1037 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1038 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1039 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1040 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1041 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1043 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1044 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1045 WARN_ONCE(ret, "Timeout waiting for "
1046 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1049 if (vc4_encoder->hdmi_monitor) {
1050 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1051 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1052 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1053 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1054 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1056 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1057 VC4_HDMI_RAM_PACKET_ENABLE);
1059 vc4_hdmi_set_infoframes(encoder);
1062 vc4_hdmi_recenter_fifo(vc4_hdmi);
1063 vc4_hdmi_enable_scrambling(encoder);
1066 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1070 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1071 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1073 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1074 struct drm_crtc_state *crtc_state,
1075 struct drm_connector_state *conn_state)
1077 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1078 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1079 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1080 unsigned long long pixel_rate = mode->clock * 1000;
1081 unsigned long long tmds_rate;
1083 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1084 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1085 (mode->hsync_end % 2) || (mode->htotal % 2)))
1089 * The 1440p@60 pixel rate is in the same range than the first
1090 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1091 * bandwidth). Slightly lower the frequency to bring it out of
1094 tmds_rate = pixel_rate * 10;
1095 if (vc4_hdmi->disable_wifi_frequencies &&
1096 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1097 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1098 mode->clock = 238560;
1099 pixel_rate = mode->clock * 1000;
1102 if (conn_state->max_bpc == 12) {
1103 pixel_rate = pixel_rate * 150;
1104 do_div(pixel_rate, 100);
1105 } else if (conn_state->max_bpc == 10) {
1106 pixel_rate = pixel_rate * 125;
1107 do_div(pixel_rate, 100);
1110 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1111 pixel_rate = pixel_rate * 2;
1113 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1116 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1119 vc4_state->pixel_rate = pixel_rate;
1124 static enum drm_mode_status
1125 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1126 const struct drm_display_mode *mode)
1128 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1130 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1131 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1132 (mode->hsync_end % 2) || (mode->htotal % 2)))
1133 return MODE_H_ILLEGAL;
1135 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1136 return MODE_CLOCK_HIGH;
1138 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1139 return MODE_CLOCK_HIGH;
1144 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1145 .atomic_check = vc4_hdmi_encoder_atomic_check,
1146 .mode_valid = vc4_hdmi_encoder_mode_valid,
1147 .disable = vc4_hdmi_encoder_disable,
1148 .enable = vc4_hdmi_encoder_enable,
1151 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1154 u32 channel_map = 0;
1156 for (i = 0; i < 8; i++) {
1157 if (channel_mask & BIT(i))
1158 channel_map |= i << (3 * i);
1163 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1166 u32 channel_map = 0;
1168 for (i = 0; i < 8; i++) {
1169 if (channel_mask & BIT(i))
1170 channel_map |= i << (4 * i);
1175 /* HDMI audio codec callbacks */
1176 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
1178 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1181 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
1182 VC4_HD_MAI_SMP_N_MASK >>
1183 VC4_HD_MAI_SMP_N_SHIFT,
1184 (VC4_HD_MAI_SMP_M_MASK >>
1185 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1188 HDMI_WRITE(HDMI_MAI_SMP,
1189 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1190 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1193 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
1195 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1196 struct drm_crtc *crtc = encoder->crtc;
1197 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1198 u32 samplerate = vc4_hdmi->audio.samplerate;
1202 n = 128 * samplerate / 1000;
1203 tmp = (u64)(mode->clock * 1000) * n;
1204 do_div(tmp, 128 * samplerate);
1207 HDMI_WRITE(HDMI_CRP_CFG,
1208 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1209 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1212 * We could get slightly more accurate clocks in some cases by
1213 * providing a CTS_1 value. The two CTS values are alternated
1214 * between based on the period fields
1216 HDMI_WRITE(HDMI_CTS_0, cts);
1217 HDMI_WRITE(HDMI_CTS_1, cts);
1220 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1222 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1224 return snd_soc_card_get_drvdata(card);
1227 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
1228 struct snd_soc_dai *dai)
1230 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1231 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1232 struct drm_connector *connector = &vc4_hdmi->connector;
1235 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
1238 vc4_hdmi->audio.substream = substream;
1241 * If the HDMI encoder hasn't probed, or the encoder is
1242 * currently in DVI mode, treat the codec dai as missing.
1244 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1245 VC4_HDMI_RAM_PACKET_ENABLE))
1248 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);
1255 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1260 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1262 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1263 struct device *dev = &vc4_hdmi->pdev->dev;
1266 vc4_hdmi->audio.streaming = false;
1267 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1269 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1271 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1272 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1273 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1276 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
1277 struct snd_soc_dai *dai)
1279 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1281 if (substream != vc4_hdmi->audio.substream)
1284 vc4_hdmi_audio_reset(vc4_hdmi);
1286 vc4_hdmi->audio.substream = NULL;
1289 /* HDMI audio codec callbacks */
1290 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1291 struct snd_pcm_hw_params *params,
1292 struct snd_soc_dai *dai)
1294 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1295 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1296 struct device *dev = &vc4_hdmi->pdev->dev;
1297 u32 audio_packet_config, channel_mask;
1300 if (substream != vc4_hdmi->audio.substream)
1303 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1304 params_rate(params), params_width(params),
1305 params_channels(params));
1307 vc4_hdmi->audio.channels = params_channels(params);
1308 vc4_hdmi->audio.samplerate = params_rate(params);
1310 HDMI_WRITE(HDMI_MAI_CTL,
1311 VC4_HD_MAI_CTL_RESET |
1312 VC4_HD_MAI_CTL_FLUSH |
1313 VC4_HD_MAI_CTL_DLATE |
1314 VC4_HD_MAI_CTL_ERRORE |
1315 VC4_HD_MAI_CTL_ERRORF);
1317 vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
1319 /* The B frame identifier should match the value used by alsa-lib (8) */
1320 audio_packet_config =
1321 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1322 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1323 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1325 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
1326 audio_packet_config |= VC4_SET_FIELD(channel_mask,
1327 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1329 /* Set the MAI threshold. This logic mimics the firmware's. */
1330 if (vc4_hdmi->audio.samplerate > 96000) {
1331 HDMI_WRITE(HDMI_MAI_THR,
1332 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
1333 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1334 } else if (vc4_hdmi->audio.samplerate > 48000) {
1335 HDMI_WRITE(HDMI_MAI_THR,
1336 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
1337 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1339 HDMI_WRITE(HDMI_MAI_THR,
1340 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1341 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1342 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1343 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1346 HDMI_WRITE(HDMI_MAI_CONFIG,
1347 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1348 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1350 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1351 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1352 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1353 vc4_hdmi_set_n_cts(vc4_hdmi);
1355 vc4_hdmi_set_audio_infoframe(encoder);
1360 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1361 struct snd_soc_dai *dai)
1363 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1366 case SNDRV_PCM_TRIGGER_START:
1367 vc4_hdmi->audio.streaming = true;
1369 if (vc4_hdmi->variant->phy_rng_enable)
1370 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1372 HDMI_WRITE(HDMI_MAI_CTL,
1373 VC4_SET_FIELD(vc4_hdmi->audio.channels,
1374 VC4_HD_MAI_CTL_CHNUM) |
1375 VC4_HD_MAI_CTL_ENABLE);
1377 case SNDRV_PCM_TRIGGER_STOP:
1378 HDMI_WRITE(HDMI_MAI_CTL,
1379 VC4_HD_MAI_CTL_DLATE |
1380 VC4_HD_MAI_CTL_ERRORE |
1381 VC4_HD_MAI_CTL_ERRORF);
1383 if (vc4_hdmi->variant->phy_rng_disable)
1384 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1386 vc4_hdmi->audio.streaming = false;
1396 static inline struct vc4_hdmi *
1397 snd_component_to_hdmi(struct snd_soc_component *component)
1399 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
1401 return snd_soc_card_get_drvdata(card);
1404 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
1405 struct snd_ctl_elem_info *uinfo)
1407 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1408 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1409 struct drm_connector *connector = &vc4_hdmi->connector;
1411 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1412 uinfo->count = sizeof(connector->eld);
1417 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
1418 struct snd_ctl_elem_value *ucontrol)
1420 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1421 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1422 struct drm_connector *connector = &vc4_hdmi->connector;
1424 memcpy(ucontrol->value.bytes.data, connector->eld,
1425 sizeof(connector->eld));
1430 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
1432 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1433 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1434 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1436 .info = vc4_hdmi_audio_eld_ctl_info,
1437 .get = vc4_hdmi_audio_eld_ctl_get,
1441 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1442 SND_SOC_DAPM_OUTPUT("TX"),
1445 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1446 { "TX", NULL, "Playback" },
1449 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1450 .name = "vc4-hdmi-codec-dai-component",
1451 .controls = vc4_hdmi_audio_controls,
1452 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
1453 .dapm_widgets = vc4_hdmi_audio_widgets,
1454 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1455 .dapm_routes = vc4_hdmi_audio_routes,
1456 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
1458 .use_pmdown_time = 1,
1460 .non_legacy_dai_naming = 1,
1463 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1464 .startup = vc4_hdmi_audio_startup,
1465 .shutdown = vc4_hdmi_audio_shutdown,
1466 .hw_params = vc4_hdmi_audio_hw_params,
1467 .set_fmt = vc4_hdmi_audio_set_fmt,
1468 .trigger = vc4_hdmi_audio_trigger,
1471 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1472 .name = "vc4-hdmi-hifi",
1474 .stream_name = "Playback",
1477 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1478 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1479 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1480 SNDRV_PCM_RATE_192000,
1481 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1485 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1486 .name = "vc4-hdmi-cpu-dai-component",
1489 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1491 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1493 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1498 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1499 .name = "vc4-hdmi-cpu-dai",
1500 .probe = vc4_hdmi_audio_cpu_dai_probe,
1502 .stream_name = "Playback",
1505 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1506 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1507 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1508 SNDRV_PCM_RATE_192000,
1509 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1511 .ops = &vc4_hdmi_audio_dai_ops,
1514 static const struct snd_dmaengine_pcm_config pcm_conf = {
1515 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1516 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1519 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1521 const struct vc4_hdmi_register *mai_data =
1522 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1523 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1524 struct snd_soc_card *card = &vc4_hdmi->audio.card;
1525 struct device *dev = &vc4_hdmi->pdev->dev;
1530 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1532 "'dmas' DT property is missing, no HDMI audio\n");
1536 if (mai_data->reg != VC4_HD) {
1537 WARN_ONCE(true, "MAI isn't in the HD block\n");
1542 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1543 * the bus address specified in the DT, because the physical address
1544 * (the one returned by platform_get_resource()) is not appropriate
1545 * for DMA transfers.
1546 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1548 index = of_property_match_string(dev->of_node, "reg-names", "hd");
1549 /* Before BCM2711, we don't have a named register range */
1553 addr = of_get_address(dev->of_node, index, NULL, NULL);
1555 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1556 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1557 vc4_hdmi->audio.dma_data.maxburst = 2;
1559 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1561 dev_err(dev, "Could not register PCM component: %d\n", ret);
1565 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1566 &vc4_hdmi_audio_cpu_dai_drv, 1);
1568 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1572 /* register component and codec dai */
1573 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1574 &vc4_hdmi_audio_codec_dai_drv, 1);
1576 dev_err(dev, "Could not register component: %d\n", ret);
1580 dai_link->cpus = &vc4_hdmi->audio.cpu;
1581 dai_link->codecs = &vc4_hdmi->audio.codec;
1582 dai_link->platforms = &vc4_hdmi->audio.platform;
1584 dai_link->num_cpus = 1;
1585 dai_link->num_codecs = 1;
1586 dai_link->num_platforms = 1;
1588 dai_link->name = "MAI";
1589 dai_link->stream_name = "MAI PCM";
1590 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1591 dai_link->cpus->dai_name = dev_name(dev);
1592 dai_link->codecs->name = dev_name(dev);
1593 dai_link->platforms->name = dev_name(dev);
1595 card->dai_link = dai_link;
1596 card->num_links = 1;
1597 card->name = vc4_hdmi->variant->card_name;
1598 card->driver_name = "vc4-hdmi";
1600 card->owner = THIS_MODULE;
1603 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1604 * stores a pointer to the snd card object in dev->driver_data. This
1605 * means we cannot use it for something else. The hdmi back-pointer is
1606 * now stored in card->drvdata and should be retrieved with
1607 * snd_soc_card_get_drvdata() if needed.
1609 snd_soc_card_set_drvdata(card, vc4_hdmi);
1610 ret = devm_snd_soc_register_card(dev, card);
1612 dev_err(dev, "Could not register sound card: %d\n", ret);
1618 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1619 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1621 struct vc4_hdmi *vc4_hdmi = priv;
1623 if (vc4_hdmi->cec_rx_msg.len)
1624 cec_received_msg(vc4_hdmi->cec_adap,
1625 &vc4_hdmi->cec_rx_msg);
1630 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1632 struct vc4_hdmi *vc4_hdmi = priv;
1634 if (vc4_hdmi->cec_tx_ok) {
1635 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1639 * This CEC implementation makes 1 retry, so if we
1640 * get a NACK, then that means it made 2 attempts.
1642 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1648 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1650 struct vc4_hdmi *vc4_hdmi = priv;
1653 if (vc4_hdmi->cec_irq_was_rx)
1654 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1656 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1661 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1663 struct drm_device *dev = vc4_hdmi->connector.dev;
1664 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1667 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1668 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1670 if (msg->len > 16) {
1671 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1675 for (i = 0; i < msg->len; i += 4) {
1676 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1678 msg->msg[i] = val & 0xff;
1679 msg->msg[i + 1] = (val >> 8) & 0xff;
1680 msg->msg[i + 2] = (val >> 16) & 0xff;
1681 msg->msg[i + 3] = (val >> 24) & 0xff;
1685 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1687 struct vc4_hdmi *vc4_hdmi = priv;
1690 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1691 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1692 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1693 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1695 return IRQ_WAKE_THREAD;
1698 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1700 struct vc4_hdmi *vc4_hdmi = priv;
1703 vc4_hdmi->cec_rx_msg.len = 0;
1704 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1705 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1706 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1707 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1708 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1710 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1712 return IRQ_WAKE_THREAD;
1715 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1717 struct vc4_hdmi *vc4_hdmi = priv;
1718 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1722 if (!(stat & VC4_HDMI_CPU_CEC))
1725 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1726 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1727 if (vc4_hdmi->cec_irq_was_rx)
1728 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1730 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1732 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1736 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1738 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1739 /* clock period in microseconds */
1740 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1741 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1743 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1744 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1745 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1746 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1747 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1750 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1751 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1752 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1753 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1754 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1755 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1756 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1757 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1758 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1759 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1760 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1761 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1762 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1763 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1764 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1765 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1766 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1767 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1768 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1770 if (!vc4_hdmi->variant->external_irq_controller)
1771 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1773 if (!vc4_hdmi->variant->external_irq_controller)
1774 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1775 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1776 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1781 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1783 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1785 HDMI_WRITE(HDMI_CEC_CNTRL_1,
1786 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1787 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1791 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1792 u32 signal_free_time, struct cec_msg *msg)
1794 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1795 struct drm_device *dev = vc4_hdmi->connector.dev;
1799 if (msg->len > 16) {
1800 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1804 for (i = 0; i < msg->len; i += 4)
1805 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1807 (msg->msg[i + 1] << 8) |
1808 (msg->msg[i + 2] << 16) |
1809 (msg->msg[i + 3] << 24));
1811 val = HDMI_READ(HDMI_CEC_CNTRL_1);
1812 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1813 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1814 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1815 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1816 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1818 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1822 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1823 .adap_enable = vc4_hdmi_cec_adap_enable,
1824 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1825 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1828 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1830 struct cec_connector_info conn_info;
1831 struct platform_device *pdev = vc4_hdmi->pdev;
1832 struct device *dev = &pdev->dev;
1836 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1837 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1841 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1844 CEC_CAP_CONNECTOR_INFO, 1);
1845 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1849 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1850 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1852 value = HDMI_READ(HDMI_CEC_CNTRL_1);
1853 /* Set the logical address to Unregistered */
1854 value |= VC4_HDMI_CEC_ADDR_MASK;
1855 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1857 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1859 if (vc4_hdmi->variant->external_irq_controller) {
1860 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
1861 vc4_cec_irq_handler_rx_bare,
1862 vc4_cec_irq_handler_rx_thread, 0,
1863 "vc4 hdmi cec rx", vc4_hdmi);
1865 goto err_delete_cec_adap;
1867 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
1868 vc4_cec_irq_handler_tx_bare,
1869 vc4_cec_irq_handler_tx_thread, 0,
1870 "vc4 hdmi cec tx", vc4_hdmi);
1872 goto err_remove_cec_rx_handler;
1874 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1876 ret = request_threaded_irq(platform_get_irq(pdev, 0),
1877 vc4_cec_irq_handler,
1878 vc4_cec_irq_handler_thread, 0,
1879 "vc4 hdmi cec", vc4_hdmi);
1881 goto err_delete_cec_adap;
1884 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1886 goto err_remove_handlers;
1890 err_remove_handlers:
1891 if (vc4_hdmi->variant->external_irq_controller)
1892 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1894 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1896 err_remove_cec_rx_handler:
1897 if (vc4_hdmi->variant->external_irq_controller)
1898 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1900 err_delete_cec_adap:
1901 cec_delete_adapter(vc4_hdmi->cec_adap);
1906 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1908 struct platform_device *pdev = vc4_hdmi->pdev;
1910 if (vc4_hdmi->variant->external_irq_controller) {
1911 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1912 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1914 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1917 cec_unregister_adapter(vc4_hdmi->cec_adap);
1920 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1925 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1929 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1930 struct debugfs_regset32 *regset,
1931 enum vc4_hdmi_regs reg)
1933 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1934 struct debugfs_reg32 *regs, *new_regs;
1935 unsigned int count = 0;
1938 regs = kcalloc(variant->num_registers, sizeof(*regs),
1943 for (i = 0; i < variant->num_registers; i++) {
1944 const struct vc4_hdmi_register *field = &variant->registers[i];
1946 if (field->reg != reg)
1949 regs[count].name = field->name;
1950 regs[count].offset = field->offset;
1954 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1958 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1959 regset->regs = new_regs;
1960 regset->nregs = count;
1965 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1967 struct platform_device *pdev = vc4_hdmi->pdev;
1968 struct device *dev = &pdev->dev;
1971 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1972 if (IS_ERR(vc4_hdmi->hdmicore_regs))
1973 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1975 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1976 if (IS_ERR(vc4_hdmi->hd_regs))
1977 return PTR_ERR(vc4_hdmi->hd_regs);
1979 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1983 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1987 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1988 if (IS_ERR(vc4_hdmi->pixel_clock)) {
1989 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1990 if (ret != -EPROBE_DEFER)
1991 DRM_ERROR("Failed to get pixel clock\n");
1995 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1996 if (IS_ERR(vc4_hdmi->hsm_clock)) {
1997 DRM_ERROR("Failed to get HDMI state machine clock\n");
1998 return PTR_ERR(vc4_hdmi->hsm_clock);
2000 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2001 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2006 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2008 struct platform_device *pdev = vc4_hdmi->pdev;
2009 struct device *dev = &pdev->dev;
2010 struct resource *res;
2012 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2016 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2017 resource_size(res));
2018 if (!vc4_hdmi->hdmicore_regs)
2021 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2025 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2026 if (!vc4_hdmi->hd_regs)
2029 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2033 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2034 if (!vc4_hdmi->cec_regs)
2037 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2041 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2042 if (!vc4_hdmi->csc_regs)
2045 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2049 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2050 if (!vc4_hdmi->dvp_regs)
2053 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2057 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2058 if (!vc4_hdmi->phy_regs)
2061 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2065 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2066 if (!vc4_hdmi->ram_regs)
2069 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2073 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2074 if (!vc4_hdmi->rm_regs)
2077 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2078 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2079 DRM_ERROR("Failed to get HDMI state machine clock\n");
2080 return PTR_ERR(vc4_hdmi->hsm_clock);
2083 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2084 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2085 DRM_ERROR("Failed to get pixel bvb clock\n");
2086 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2089 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2090 if (IS_ERR(vc4_hdmi->audio_clock)) {
2091 DRM_ERROR("Failed to get audio clock\n");
2092 return PTR_ERR(vc4_hdmi->audio_clock);
2095 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2096 if (IS_ERR(vc4_hdmi->cec_clock)) {
2097 DRM_ERROR("Failed to get CEC clock\n");
2098 return PTR_ERR(vc4_hdmi->cec_clock);
2101 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2102 if (IS_ERR(vc4_hdmi->reset)) {
2103 DRM_ERROR("Failed to get HDMI reset line\n");
2104 return PTR_ERR(vc4_hdmi->reset);
2111 static int vc4_hdmi_runtime_suspend(struct device *dev)
2113 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2115 clk_disable_unprepare(vc4_hdmi->hsm_clock);
2120 static int vc4_hdmi_runtime_resume(struct device *dev)
2122 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2125 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2133 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2135 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2136 struct platform_device *pdev = to_platform_device(dev);
2137 struct drm_device *drm = dev_get_drvdata(master);
2138 struct vc4_hdmi *vc4_hdmi;
2139 struct drm_encoder *encoder;
2140 struct device_node *ddc_node;
2143 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2146 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2148 dev_set_drvdata(dev, vc4_hdmi);
2149 encoder = &vc4_hdmi->encoder.base.base;
2150 vc4_hdmi->encoder.base.type = variant->encoder_type;
2151 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2152 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2153 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2154 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2155 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2156 vc4_hdmi->pdev = pdev;
2157 vc4_hdmi->variant = variant;
2159 ret = variant->init_resources(vc4_hdmi);
2163 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2165 DRM_ERROR("Failed to find ddc node in device tree\n");
2169 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2170 of_node_put(ddc_node);
2171 if (!vc4_hdmi->ddc) {
2172 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2173 return -EPROBE_DEFER;
2176 /* Only use the GPIO HPD pin if present in the DT, otherwise
2177 * we'll use the HDMI core's register.
2179 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2180 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2181 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2185 vc4_hdmi->disable_wifi_frequencies =
2186 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2188 if (variant->max_pixel_clock == 600000000) {
2189 struct vc4_dev *vc4 = to_vc4_dev(drm);
2190 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2192 if (max_rate < 550000000)
2193 vc4_hdmi->disable_4kp60 = true;
2196 if (vc4_hdmi->variant->reset)
2197 vc4_hdmi->variant->reset(vc4_hdmi);
2199 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2200 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2201 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2202 clk_prepare_enable(vc4_hdmi->pixel_clock);
2203 clk_prepare_enable(vc4_hdmi->hsm_clock);
2204 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2207 pm_runtime_enable(dev);
2209 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2210 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2212 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2214 goto err_destroy_encoder;
2216 ret = vc4_hdmi_cec_init(vc4_hdmi);
2218 goto err_destroy_conn;
2220 ret = vc4_hdmi_audio_init(vc4_hdmi);
2224 vc4_debugfs_add_file(drm, variant->debugfs_name,
2225 vc4_hdmi_debugfs_regs,
2231 vc4_hdmi_cec_exit(vc4_hdmi);
2233 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2234 err_destroy_encoder:
2235 drm_encoder_cleanup(encoder);
2236 pm_runtime_disable(dev);
2238 put_device(&vc4_hdmi->ddc->dev);
2243 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2246 struct vc4_hdmi *vc4_hdmi;
2249 * ASoC makes it a bit hard to retrieve a pointer to the
2250 * vc4_hdmi structure. Registering the card will overwrite our
2251 * device drvdata with a pointer to the snd_soc_card structure,
2252 * which can then be used to retrieve whatever drvdata we want
2255 * However, that doesn't fly in the case where we wouldn't
2256 * register an ASoC card (because of an old DT that is missing
2257 * the dmas properties for example), then the card isn't
2258 * registered and the device drvdata wouldn't be set.
2260 * We can deal with both cases by making sure a snd_soc_card
2261 * pointer and a vc4_hdmi structure are pointing to the same
2262 * memory address, so we can treat them indistinctly without any
2265 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2266 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2267 vc4_hdmi = dev_get_drvdata(dev);
2269 kfree(vc4_hdmi->hdmi_regset.regs);
2270 kfree(vc4_hdmi->hd_regset.regs);
2272 vc4_hdmi_cec_exit(vc4_hdmi);
2273 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2274 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2276 pm_runtime_disable(dev);
2278 put_device(&vc4_hdmi->ddc->dev);
2281 static const struct component_ops vc4_hdmi_ops = {
2282 .bind = vc4_hdmi_bind,
2283 .unbind = vc4_hdmi_unbind,
2286 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2288 return component_add(&pdev->dev, &vc4_hdmi_ops);
2291 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2293 component_del(&pdev->dev, &vc4_hdmi_ops);
2297 static const struct vc4_hdmi_variant bcm2835_variant = {
2298 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2299 .debugfs_name = "hdmi_regs",
2300 .card_name = "vc4-hdmi",
2301 .max_pixel_clock = 162000000,
2302 .registers = vc4_hdmi_fields,
2303 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
2305 .init_resources = vc4_hdmi_init_resources,
2306 .csc_setup = vc4_hdmi_csc_setup,
2307 .reset = vc4_hdmi_reset,
2308 .set_timings = vc4_hdmi_set_timings,
2309 .phy_init = vc4_hdmi_phy_init,
2310 .phy_disable = vc4_hdmi_phy_disable,
2311 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
2312 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
2313 .channel_map = vc4_hdmi_channel_map,
2314 .supports_hdr = false,
2317 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2318 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2319 .debugfs_name = "hdmi0_regs",
2320 .card_name = "vc4-hdmi-0",
2321 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2322 .registers = vc5_hdmi_hdmi0_fields,
2323 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2324 .phy_lane_mapping = {
2330 .unsupported_odd_h_timings = true,
2331 .external_irq_controller = true,
2333 .init_resources = vc5_hdmi_init_resources,
2334 .csc_setup = vc5_hdmi_csc_setup,
2335 .reset = vc5_hdmi_reset,
2336 .set_timings = vc5_hdmi_set_timings,
2337 .phy_init = vc5_hdmi_phy_init,
2338 .phy_disable = vc5_hdmi_phy_disable,
2339 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2340 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2341 .channel_map = vc5_hdmi_channel_map,
2342 .supports_hdr = true,
2345 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2346 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
2347 .debugfs_name = "hdmi1_regs",
2348 .card_name = "vc4-hdmi-1",
2349 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2350 .registers = vc5_hdmi_hdmi1_fields,
2351 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2352 .phy_lane_mapping = {
2358 .unsupported_odd_h_timings = true,
2359 .external_irq_controller = true,
2361 .init_resources = vc5_hdmi_init_resources,
2362 .csc_setup = vc5_hdmi_csc_setup,
2363 .reset = vc5_hdmi_reset,
2364 .set_timings = vc5_hdmi_set_timings,
2365 .phy_init = vc5_hdmi_phy_init,
2366 .phy_disable = vc5_hdmi_phy_disable,
2367 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2368 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2369 .channel_map = vc5_hdmi_channel_map,
2370 .supports_hdr = true,
2373 static const struct of_device_id vc4_hdmi_dt_match[] = {
2374 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2375 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2376 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2380 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2381 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2382 vc4_hdmi_runtime_resume,
2386 struct platform_driver vc4_hdmi_driver = {
2387 .probe = vc4_hdmi_dev_probe,
2388 .remove = vc4_hdmi_dev_remove,
2391 .of_match_table = vc4_hdmi_dt_match,
2392 .pm = &vc4_hdmi_pm_ops,