drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/display/drm_hdmi_helper.h>
  35 #include <drm/display/drm_scdc_helper.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_drv.h>
  38 #include <drm/drm_probe_helper.h>
  39 #include <drm/drm_simple_kms_helper.h>
  40 #include <linux/clk.h>
  41 #include <linux/component.h>
  42 #include <linux/gpio/consumer.h>
  43 #include <linux/i2c.h>
  44 #include <linux/of_address.h>
  45 #include <linux/of_platform.h>
  46 #include <linux/pm_runtime.h>
  47 #include <linux/rational.h>
  48 #include <linux/reset.h>
  49 #include <sound/dmaengine_pcm.h>
  50 #include <sound/hdmi-codec.h>
  51 #include <sound/pcm_drm_eld.h>
  52 #include <sound/pcm_params.h>
  53 #include <sound/soc.h>
  54 #include "media/cec.h"
  55 #include "vc4_drv.h"
  56 #include "vc4_hdmi.h"
  57 #include "vc4_hdmi_regs.h"
  58 #include "vc4_regs.h"
  59
  60 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  61 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  62 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  63 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  64 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  65 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  66
  67 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  68 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  69 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  70 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  71
  72 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  73 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  74 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  75 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  76 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  77 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  78
  79 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  80 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  81
  82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  86
  87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  88
  89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  91
  92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  94
  95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  96
  97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  99
 100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK   VC4_MASK(7, 0)
 101 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE     BIT(0)
 102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE   BIT(4)
 103
 104 # define VC4_HD_M_SW_RST                        BIT(2)
 105 # define VC4_HD_M_ENABLE                        BIT(0)
 106
 107 #define HSM_MIN_CLOCK_FREQ      120000000
 108 #define CEC_CLOCK_FREQ 40000
 109
 110 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 111
 112 static const char * const output_format_str[] = {
 113         [VC4_HDMI_OUTPUT_RGB]           = "RGB",
 114         [VC4_HDMI_OUTPUT_YUV420]        = "YUV 4:2:0",
 115         [VC4_HDMI_OUTPUT_YUV422]        = "YUV 4:2:2",
 116         [VC4_HDMI_OUTPUT_YUV444]        = "YUV 4:4:4",
 117 };
 118
 119 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
 120 {
 121         if (fmt >= ARRAY_SIZE(output_format_str))
 122                 return "invalid";
 123
 124         return output_format_str[fmt];
 125 }
 126
 127 static unsigned long long
 128 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
 129                                     unsigned int bpc, enum vc4_hdmi_output_format fmt);
 130
 131 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
 132 {
 133         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 134
 135         lockdep_assert_held(&vc4_hdmi->mutex);
 136
 137         if (!display->is_hdmi)
 138                 return false;
 139
 140         if (!display->hdmi.scdc.supported ||
 141             !display->hdmi.scdc.scrambling.supported)
 142                 return false;
 143
 144         return true;
 145 }
 146
 147 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
 148                                            unsigned int bpc,
 149                                            enum vc4_hdmi_output_format fmt)
 150 {
 151         unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
 152
 153         return clock > HDMI_14_MAX_TMDS_CLK;
 154 }
 155
 156 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
 157                                        const struct drm_display_mode *mode)
 158 {
 159         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 160
 161         return !display->is_hdmi ||
 162                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 163 }
 164
 165 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 166 {
 167         struct drm_debugfs_entry *entry = m->private;
 168         struct vc4_hdmi *vc4_hdmi = entry->file.data;
 169         struct drm_device *drm = vc4_hdmi->connector.dev;
 170         struct drm_printer p = drm_seq_file_printer(m);
 171         int idx;
 172
 173         if (!drm_dev_enter(drm, &idx))
 174                 return -ENODEV;
 175
 176         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 177         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 178         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 179         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 180         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 181         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 182         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 183         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 184
 185         drm_dev_exit(idx);
 186
 187         return 0;
 188 }
 189
 190 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 191 {
 192         struct drm_device *drm = vc4_hdmi->connector.dev;
 193         unsigned long flags;
 194         int idx;
 195
 196         /*
 197          * We can be called by our bind callback, when the
 198          * connector->dev pointer might not be initialised yet.
 199          */
 200         if (drm && !drm_dev_enter(drm, &idx))
 201                 return;
 202
 203         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 204
 205         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 206         udelay(1);
 207         HDMI_WRITE(HDMI_M_CTL, 0);
 208
 209         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 210
 211         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 212                    VC4_HDMI_SW_RESET_HDMI |
 213                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 214
 215         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 216
 217         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 218
 219         if (drm)
 220                 drm_dev_exit(idx);
 221 }
 222
 223 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 224 {
 225         struct drm_device *drm = vc4_hdmi->connector.dev;
 226         unsigned long flags;
 227         int idx;
 228
 229         /*
 230          * We can be called by our bind callback, when the
 231          * connector->dev pointer might not be initialised yet.
 232          */
 233         if (drm && !drm_dev_enter(drm, &idx))
 234                 return;
 235
 236         reset_control_reset(vc4_hdmi->reset);
 237
 238         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 239
 240         HDMI_WRITE(HDMI_DVP_CTL, 0);
 241
 242         HDMI_WRITE(HDMI_CLOCK_STOP,
 243                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 244
 245         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 246
 247         if (drm)
 248                 drm_dev_exit(idx);
 249 }
 250
 251 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 252 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 253 {
 254         struct drm_device *drm = vc4_hdmi->connector.dev;
 255         unsigned long cec_rate;
 256         unsigned long flags;
 257         u16 clk_cnt;
 258         u32 value;
 259         int idx;
 260
 261         /*
 262          * This function is called by our runtime_resume implementation
 263          * and thus at bind time, when we haven't registered our
 264          * connector yet and thus don't have a pointer to the DRM
 265          * device.
 266          */
 267         if (drm && !drm_dev_enter(drm, &idx))
 268                 return;
 269
 270         cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 271
 272         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 273
 274         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 275         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 276
 277         /*
 278          * Set the clock divider: the hsm_clock rate and this divider
 279          * setting will give a 40 kHz CEC clock.
 280          */
 281         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 282         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 283         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 284
 285         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 286
 287         if (drm)
 288                 drm_dev_exit(idx);
 289 }
 290 #else
 291 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 292 #endif
 293
 294 static int reset_pipe(struct drm_crtc *crtc,
 295                         struct drm_modeset_acquire_ctx *ctx)
 296 {
 297         struct drm_atomic_state *state;
 298         struct drm_crtc_state *crtc_state;
 299         int ret;
 300
 301         state = drm_atomic_state_alloc(crtc->dev);
 302         if (!state)
 303                 return -ENOMEM;
 304
 305         state->acquire_ctx = ctx;
 306
 307         crtc_state = drm_atomic_get_crtc_state(state, crtc);
 308         if (IS_ERR(crtc_state)) {
 309                 ret = PTR_ERR(crtc_state);
 310                 goto out;
 311         }
 312
 313         crtc_state->connectors_changed = true;
 314
 315         ret = drm_atomic_commit(state);
 316 out:
 317         drm_atomic_state_put(state);
 318
 319         return ret;
 320 }
 321
 322 static int vc4_hdmi_reset_link(struct drm_connector *connector,
 323                                struct drm_modeset_acquire_ctx *ctx)
 324 {
 325         struct drm_device *drm;
 326         struct vc4_hdmi *vc4_hdmi;
 327         struct drm_connector_state *conn_state;
 328         struct drm_crtc_state *crtc_state;
 329         struct drm_crtc *crtc;
 330         bool scrambling_needed;
 331         u8 config;
 332         int ret;
 333
 334         if (!connector)
 335                 return 0;
 336
 337         drm = connector->dev;
 338         ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
 339         if (ret)
 340                 return ret;
 341
 342         conn_state = connector->state;
 343         crtc = conn_state->crtc;
 344         if (!crtc)
 345                 return 0;
 346
 347         ret = drm_modeset_lock(&crtc->mutex, ctx);
 348         if (ret)
 349                 return ret;
 350
 351         crtc_state = crtc->state;
 352         if (!crtc_state->active)
 353                 return 0;
 354
 355         vc4_hdmi = connector_to_vc4_hdmi(connector);
 356         mutex_lock(&vc4_hdmi->mutex);
 357
 358         if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
 359                 mutex_unlock(&vc4_hdmi->mutex);
 360                 return 0;
 361         }
 362
 363         scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
 364                                                            vc4_hdmi->output_bpc,
 365                                                            vc4_hdmi->output_format);
 366         if (!scrambling_needed) {
 367                 mutex_unlock(&vc4_hdmi->mutex);
 368                 return 0;
 369         }
 370
 371         if (conn_state->commit &&
 372             !try_wait_for_completion(&conn_state->commit->hw_done)) {
 373                 mutex_unlock(&vc4_hdmi->mutex);
 374                 return 0;
 375         }
 376
 377         ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
 378         if (ret < 0) {
 379                 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
 380                 mutex_unlock(&vc4_hdmi->mutex);
 381                 return 0;
 382         }
 383
 384         if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
 385                 mutex_unlock(&vc4_hdmi->mutex);
 386                 return 0;
 387         }
 388
 389         mutex_unlock(&vc4_hdmi->mutex);
 390
 391         /*
 392          * HDMI 2.0 says that one should not send scrambled data
 393          * prior to configuring the sink scrambling, and that
 394          * TMDS clock/data transmission should be suspended when
 395          * changing the TMDS clock rate in the sink. So let's
 396          * just do a full modeset here, even though some sinks
 397          * would be perfectly happy if were to just reconfigure
 398          * the SCDC settings on the fly.
 399          */
 400         return reset_pipe(crtc, ctx);
 401 }
 402
 403 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
 404                                     struct drm_modeset_acquire_ctx *ctx,
 405                                     enum drm_connector_status status)
 406 {
 407         struct drm_connector *connector = &vc4_hdmi->connector;
 408         struct edid *edid;
 409         int ret;
 410
 411         /*
 412          * NOTE: This function should really be called with
 413          * vc4_hdmi->mutex held, but doing so results in reentrancy
 414          * issues since cec_s_phys_addr_from_edid might call
 415          * .adap_enable, which leads to that funtion being called with
 416          * our mutex held.
 417          *
 418          * A similar situation occurs with vc4_hdmi_reset_link() that
 419          * will call into our KMS hooks if the scrambling was enabled.
 420          *
 421          * Concurrency isn't an issue at the moment since we don't share
 422          * any state with any of the other frameworks so we can ignore
 423          * the lock for now.
 424          */
 425
 426         if (status == connector_status_disconnected) {
 427                 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 428                 return;
 429         }
 430
 431         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 432         if (!edid)
 433                 return;
 434
 435         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 436         kfree(edid);
 437
 438         for (;;) {
 439                 ret = vc4_hdmi_reset_link(connector, ctx);
 440                 if (ret == -EDEADLK) {
 441                         drm_modeset_backoff(ctx);
 442                         continue;
 443                 }
 444
 445                 break;
 446         }
 447 }
 448
 449 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
 450                                          struct drm_modeset_acquire_ctx *ctx,
 451                                          bool force)
 452 {
 453         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 454         enum drm_connector_status status = connector_status_disconnected;
 455
 456         /*
 457          * NOTE: This function should really take vc4_hdmi->mutex, but
 458          * doing so results in reentrancy issues since
 459          * vc4_hdmi_handle_hotplug() can call into other functions that
 460          * would take the mutex while it's held here.
 461          *
 462          * Concurrency isn't an issue at the moment since we don't share
 463          * any state with any of the other frameworks so we can ignore
 464          * the lock for now.
 465          */
 466
 467         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 468
 469         if (vc4_hdmi->hpd_gpio) {
 470                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 471                         status = connector_status_connected;
 472         } else {
 473                 if (vc4_hdmi->variant->hp_detect &&
 474                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 475                         status = connector_status_connected;
 476         }
 477
 478         vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
 479         pm_runtime_put(&vc4_hdmi->pdev->dev);
 480
 481         return status;
 482 }
 483
 484 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 485 {
 486         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 487         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
 488         int ret = 0;
 489         struct edid *edid;
 490
 491         /*
 492          * NOTE: This function should really take vc4_hdmi->mutex, but
 493          * doing so results in reentrancy issues since
 494          * cec_s_phys_addr_from_edid might call .adap_enable, which
 495          * leads to that funtion being called with our mutex held.
 496          *
 497          * Concurrency isn't an issue at the moment since we don't share
 498          * any state with any of the other frameworks so we can ignore
 499          * the lock for now.
 500          */
 501
 502         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 503         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 504         if (!edid)
 505                 return -ENODEV;
 506
 507         drm_connector_update_edid_property(connector, edid);
 508         ret = drm_add_edid_modes(connector, edid);
 509         kfree(edid);
 510
 511         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
 512                 struct drm_device *drm = connector->dev;
 513                 const struct drm_display_mode *mode;
 514
 515                 list_for_each_entry(mode, &connector->probed_modes, head) {
 516                         if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
 517                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 518                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 519                         }
 520                 }
 521         }
 522
 523         return ret;
 524 }
 525
 526 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 527                                            struct drm_atomic_state *state)
 528 {
 529         struct drm_connector_state *old_state =
 530                 drm_atomic_get_old_connector_state(state, connector);
 531         struct drm_connector_state *new_state =
 532                 drm_atomic_get_new_connector_state(state, connector);
 533         struct drm_crtc *crtc = new_state->crtc;
 534
 535         if (!crtc)
 536                 return 0;
 537
 538         if (old_state->colorspace != new_state->colorspace ||
 539             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 540                 struct drm_crtc_state *crtc_state;
 541
 542                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 543                 if (IS_ERR(crtc_state))
 544                         return PTR_ERR(crtc_state);
 545
 546                 crtc_state->mode_changed = true;
 547         }
 548
 549         return 0;
 550 }
 551
 552 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 553 {
 554         struct vc4_hdmi_connector_state *old_state =
 555                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 556         struct vc4_hdmi_connector_state *new_state =
 557                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 558
 559         if (connector->state)
 560                 __drm_atomic_helper_connector_destroy_state(connector->state);
 561
 562         kfree(old_state);
 563         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 564
 565         if (!new_state)
 566                 return;
 567
 568         new_state->base.max_bpc = 8;
 569         new_state->base.max_requested_bpc = 8;
 570         new_state->output_format = VC4_HDMI_OUTPUT_RGB;
 571         drm_atomic_helper_connector_tv_margins_reset(connector);
 572 }
 573
 574 static struct drm_connector_state *
 575 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 576 {
 577         struct drm_connector_state *conn_state = connector->state;
 578         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 579         struct vc4_hdmi_connector_state *new_state;
 580
 581         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 582         if (!new_state)
 583                 return NULL;
 584
 585         new_state->tmds_char_rate = vc4_state->tmds_char_rate;
 586         new_state->output_bpc = vc4_state->output_bpc;
 587         new_state->output_format = vc4_state->output_format;
 588         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 589
 590         return &new_state->base;
 591 }
 592
 593 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 594         .fill_modes = drm_helper_probe_single_connector_modes,
 595         .reset = vc4_hdmi_connector_reset,
 596         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 597         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 598 };
 599
 600 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 601         .detect_ctx = vc4_hdmi_connector_detect_ctx,
 602         .get_modes = vc4_hdmi_connector_get_modes,
 603         .atomic_check = vc4_hdmi_connector_atomic_check,
 604 };
 605
 606 static int vc4_hdmi_connector_init(struct drm_device *dev,
 607                                    struct vc4_hdmi *vc4_hdmi)
 608 {
 609         struct drm_connector *connector = &vc4_hdmi->connector;
 610         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
 611         int ret;
 612
 613         ret = drmm_connector_init(dev, connector,
 614                                   &vc4_hdmi_connector_funcs,
 615                                   DRM_MODE_CONNECTOR_HDMIA,
 616                                   vc4_hdmi->ddc);
 617         if (ret)
 618                 return ret;
 619
 620         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 621
 622         /*
 623          * Some of the properties below require access to state, like bpc.
 624          * Allocate some default initial connector state with our reset helper.
 625          */
 626         if (connector->funcs->reset)
 627                 connector->funcs->reset(connector);
 628
 629         /* Create and attach TV margin props to this connector. */
 630         ret = drm_mode_create_tv_margin_properties(dev);
 631         if (ret)
 632                 return ret;
 633
 634         ret = drm_mode_create_hdmi_colorspace_property(connector);
 635         if (ret)
 636                 return ret;
 637
 638         drm_connector_attach_colorspace_property(connector);
 639         drm_connector_attach_tv_margin_properties(connector);
 640         drm_connector_attach_max_bpc_property(connector, 8, 12);
 641
 642         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 643                              DRM_CONNECTOR_POLL_DISCONNECT);
 644
 645         connector->interlace_allowed = 1;
 646         connector->doublescan_allowed = 0;
 647         connector->stereo_allowed = 1;
 648
 649         if (vc4_hdmi->variant->supports_hdr)
 650                 drm_connector_attach_hdr_output_metadata_property(connector);
 651
 652         drm_connector_attach_encoder(connector, encoder);
 653
 654         return 0;
 655 }
 656
 657 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 658                                 enum hdmi_infoframe_type type,
 659                                 bool poll)
 660 {
 661         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 662         struct drm_device *drm = vc4_hdmi->connector.dev;
 663         u32 packet_id = type - 0x80;
 664         unsigned long flags;
 665         int ret = 0;
 666         int idx;
 667
 668         if (!drm_dev_enter(drm, &idx))
 669                 return -ENODEV;
 670
 671         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 672         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 673                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 674         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 675
 676         if (poll) {
 677                 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 678                                  BIT(packet_id)), 100);
 679         }
 680
 681         drm_dev_exit(idx);
 682         return ret;
 683 }
 684
 685 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 686                                      union hdmi_infoframe *frame)
 687 {
 688         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 689         struct drm_device *drm = vc4_hdmi->connector.dev;
 690         u32 packet_id = frame->any.type - 0x80;
 691         const struct vc4_hdmi_register *ram_packet_start =
 692                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 693         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 694         u32 packet_reg_next = ram_packet_start->offset +
 695                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 696         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 697                                                        ram_packet_start->reg);
 698         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 699         unsigned long flags;
 700         ssize_t len, i;
 701         int ret;
 702         int idx;
 703
 704         if (!drm_dev_enter(drm, &idx))
 705                 return;
 706
 707         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 708                     VC4_HDMI_RAM_PACKET_ENABLE),
 709                   "Packet RAM has to be on to store the packet.");
 710
 711         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 712         if (len < 0)
 713                 goto out;
 714
 715         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 716         if (ret) {
 717                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 718                 goto out;
 719         }
 720
 721         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 722
 723         for (i = 0; i < len; i += 7) {
 724                 writel(buffer[i + 0] << 0 |
 725                        buffer[i + 1] << 8 |
 726                        buffer[i + 2] << 16,
 727                        base + packet_reg);
 728                 packet_reg += 4;
 729
 730                 writel(buffer[i + 3] << 0 |
 731                        buffer[i + 4] << 8 |
 732                        buffer[i + 5] << 16 |
 733                        buffer[i + 6] << 24,
 734                        base + packet_reg);
 735                 packet_reg += 4;
 736         }
 737
 738         /*
 739          * clear remainder of packet ram as it's included in the
 740          * infoframe and triggers a checksum error on hdmi analyser
 741          */
 742         for (; packet_reg < packet_reg_next; packet_reg += 4)
 743                 writel(0, base + packet_reg);
 744
 745         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 746                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 747
 748         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 749
 750         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 751                         BIT(packet_id)), 100);
 752         if (ret)
 753                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 754
 755 out:
 756         drm_dev_exit(idx);
 757 }
 758
 759 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
 760                                               enum vc4_hdmi_output_format fmt)
 761 {
 762         switch (fmt) {
 763         case VC4_HDMI_OUTPUT_RGB:
 764                 frame->colorspace = HDMI_COLORSPACE_RGB;
 765                 break;
 766
 767         case VC4_HDMI_OUTPUT_YUV420:
 768                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 769                 break;
 770
 771         case VC4_HDMI_OUTPUT_YUV422:
 772                 frame->colorspace = HDMI_COLORSPACE_YUV422;
 773                 break;
 774
 775         case VC4_HDMI_OUTPUT_YUV444:
 776                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 777                 break;
 778
 779         default:
 780                 break;
 781         }
 782 }
 783
 784 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 785 {
 786         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 787         struct drm_connector *connector = &vc4_hdmi->connector;
 788         struct drm_connector_state *cstate = connector->state;
 789         struct vc4_hdmi_connector_state *vc4_state =
 790                 conn_state_to_vc4_hdmi_conn_state(cstate);
 791         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 792         union hdmi_infoframe frame;
 793         int ret;
 794
 795         lockdep_assert_held(&vc4_hdmi->mutex);
 796
 797         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 798                                                        connector, mode);
 799         if (ret < 0) {
 800                 DRM_ERROR("couldn't fill AVI infoframe\n");
 801                 return;
 802         }
 803
 804         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 805                                            connector, mode,
 806                                            vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
 807                                            HDMI_QUANTIZATION_RANGE_FULL :
 808                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 809         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 810         vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
 811         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 812
 813         vc4_hdmi_write_infoframe(encoder, &frame);
 814 }
 815
 816 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 817 {
 818         union hdmi_infoframe frame;
 819         int ret;
 820
 821         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 822         if (ret < 0) {
 823                 DRM_ERROR("couldn't fill SPD infoframe\n");
 824                 return;
 825         }
 826
 827         frame.spd.sdi = HDMI_SPD_SDI_PC;
 828
 829         vc4_hdmi_write_infoframe(encoder, &frame);
 830 }
 831
 832 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 833 {
 834         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 835         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 836         union hdmi_infoframe frame;
 837
 838         memcpy(&frame.audio, audio, sizeof(*audio));
 839
 840         if (vc4_hdmi->packet_ram_enabled)
 841                 vc4_hdmi_write_infoframe(encoder, &frame);
 842 }
 843
 844 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 845 {
 846         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 847         struct drm_connector *connector = &vc4_hdmi->connector;
 848         struct drm_connector_state *conn_state = connector->state;
 849         union hdmi_infoframe frame;
 850
 851         lockdep_assert_held(&vc4_hdmi->mutex);
 852
 853         if (!vc4_hdmi->variant->supports_hdr)
 854                 return;
 855
 856         if (!conn_state->hdr_output_metadata)
 857                 return;
 858
 859         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 860                 return;
 861
 862         vc4_hdmi_write_infoframe(encoder, &frame);
 863 }
 864
 865 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 866 {
 867         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 868
 869         lockdep_assert_held(&vc4_hdmi->mutex);
 870
 871         vc4_hdmi_set_avi_infoframe(encoder);
 872         vc4_hdmi_set_spd_infoframe(encoder);
 873         /*
 874          * If audio was streaming, then we need to reenabled the audio
 875          * infoframe here during encoder_enable.
 876          */
 877         if (vc4_hdmi->audio.streaming)
 878                 vc4_hdmi_set_audio_infoframe(encoder);
 879
 880         vc4_hdmi_set_hdr_infoframe(encoder);
 881 }
 882
 883 #define SCRAMBLING_POLLING_DELAY_MS     1000
 884
 885 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 886 {
 887         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 888         struct drm_device *drm = vc4_hdmi->connector.dev;
 889         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 890         unsigned long flags;
 891         int idx;
 892
 893         lockdep_assert_held(&vc4_hdmi->mutex);
 894
 895         if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
 896                 return;
 897
 898         if (!vc4_hdmi_mode_needs_scrambling(mode,
 899                                             vc4_hdmi->output_bpc,
 900                                             vc4_hdmi->output_format))
 901                 return;
 902
 903         if (!drm_dev_enter(drm, &idx))
 904                 return;
 905
 906         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 907         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 908
 909         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 910         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 911                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 912         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 913
 914         drm_dev_exit(idx);
 915
 916         vc4_hdmi->scdc_enabled = true;
 917
 918         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 919                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 920 }
 921
 922 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 923 {
 924         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 925         struct drm_device *drm = vc4_hdmi->connector.dev;
 926         unsigned long flags;
 927         int idx;
 928
 929         lockdep_assert_held(&vc4_hdmi->mutex);
 930
 931         if (!vc4_hdmi->scdc_enabled)
 932                 return;
 933
 934         vc4_hdmi->scdc_enabled = false;
 935
 936         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 937                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 938
 939         if (!drm_dev_enter(drm, &idx))
 940                 return;
 941
 942         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 943         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 944                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 945         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 946
 947         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 948         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 949
 950         drm_dev_exit(idx);
 951 }
 952
 953 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 954 {
 955         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 956                                                  struct vc4_hdmi,
 957                                                  scrambling_work);
 958
 959         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 960                 return;
 961
 962         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 963         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 964
 965         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 966                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 967 }
 968
 969 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 970                                                struct drm_atomic_state *state)
 971 {
 972         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 973         struct drm_device *drm = vc4_hdmi->connector.dev;
 974         unsigned long flags;
 975         int idx;
 976
 977         mutex_lock(&vc4_hdmi->mutex);
 978
 979         vc4_hdmi->packet_ram_enabled = false;
 980
 981         if (!drm_dev_enter(drm, &idx))
 982                 goto out;
 983
 984         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 985
 986         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 987
 988         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 989
 990         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 991
 992         mdelay(1);
 993
 994         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 995         HDMI_WRITE(HDMI_VID_CTL,
 996                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 997         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 998
 999         vc4_hdmi_disable_scrambling(encoder);
1000
1001         drm_dev_exit(idx);
1002
1003 out:
1004         mutex_unlock(&vc4_hdmi->mutex);
1005 }
1006
1007 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
1008                                                  struct drm_atomic_state *state)
1009 {
1010         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1011         struct drm_device *drm = vc4_hdmi->connector.dev;
1012         unsigned long flags;
1013         int ret;
1014         int idx;
1015
1016         mutex_lock(&vc4_hdmi->mutex);
1017
1018         if (!drm_dev_enter(drm, &idx))
1019                 goto out;
1020
1021         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1022         HDMI_WRITE(HDMI_VID_CTL,
1023                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
1024         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1025
1026         if (vc4_hdmi->variant->phy_disable)
1027                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
1028
1029         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
1030         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1031
1032         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1033         if (ret < 0)
1034                 DRM_ERROR("Failed to release power domain: %d\n", ret);
1035
1036         drm_dev_exit(idx);
1037
1038 out:
1039         mutex_unlock(&vc4_hdmi->mutex);
1040 }
1041
1042 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1043                                struct drm_connector_state *state,
1044                                const struct drm_display_mode *mode)
1045 {
1046         struct drm_device *drm = vc4_hdmi->connector.dev;
1047         unsigned long flags;
1048         u32 csc_ctl;
1049         int idx;
1050
1051         if (!drm_dev_enter(drm, &idx))
1052                 return;
1053
1054         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1055
1056         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1057                                 VC4_HD_CSC_CTL_ORDER);
1058
1059         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
1060                 /* CEA VICs other than #1 requre limited range RGB
1061                  * output unless overridden by an AVI infoframe.
1062                  * Apply a colorspace conversion to squash 0-255 down
1063                  * to 16-235.  The matrix here is:
1064                  *
1065                  * [ 0      0      0.8594 16]
1066                  * [ 0      0.8594 0      16]
1067                  * [ 0.8594 0      0      16]
1068                  * [ 0      0      0       1]
1069                  */
1070                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1071                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1072                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1073                                          VC4_HD_CSC_CTL_MODE);
1074
1075                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1076                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1077                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1078                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1079                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1080                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1081         }
1082
1083         /* The RGB order applies even when CSC is disabled. */
1084         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1085
1086         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1087
1088         drm_dev_exit(idx);
1089 }
1090
1091 /*
1092  * If we need to output Full Range RGB, then use the unity matrix
1093  *
1094  * [ 1      0      0      0]
1095  * [ 0      1      0      0]
1096  * [ 0      0      1      0]
1097  *
1098  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1099  */
1100 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
1101         { 0x2000, 0x0000, 0x0000, 0x0000 },
1102         { 0x0000, 0x2000, 0x0000, 0x0000 },
1103         { 0x0000, 0x0000, 0x2000, 0x0000 },
1104 };
1105
1106 /*
1107  * CEA VICs other than #1 require limited range RGB output unless
1108  * overridden by an AVI infoframe. Apply a colorspace conversion to
1109  * squash 0-255 down to 16-235. The matrix here is:
1110  *
1111  * [ 0.8594 0      0      16]
1112  * [ 0      0.8594 0      16]
1113  * [ 0      0      0.8594 16]
1114  *
1115  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1116  */
1117 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
1118         { 0x1b80, 0x0000, 0x0000, 0x0400 },
1119         { 0x0000, 0x1b80, 0x0000, 0x0400 },
1120         { 0x0000, 0x0000, 0x1b80, 0x0400 },
1121 };
1122
1123 /*
1124  * Conversion between Full Range RGB and Full Range YUV422 using the
1125  * BT.709 Colorspace
1126  *
1127  *
1128  * [  0.181906  0.611804  0.061758  16  ]
1129  * [ -0.100268 -0.337232  0.437500  128 ]
1130  * [  0.437500 -0.397386 -0.040114  128 ]
1131  *
1132  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1133  */
1134 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = {
1135         { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1136         { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1137         { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1138 };
1139
1140 /*
1141  * Conversion between Full Range RGB and Full Range YUV444 using the
1142  * BT.709 Colorspace
1143  *
1144  * [ -0.100268 -0.337232  0.437500  128 ]
1145  * [  0.437500 -0.397386 -0.040114  128 ]
1146  * [  0.181906  0.611804  0.061758  16  ]
1147  *
1148  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1149  */
1150 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = {
1151         { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1152         { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1153         { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1154 };
1155
1156 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1157                                     const u16 coeffs[3][4])
1158 {
1159         lockdep_assert_held(&vc4_hdmi->hw_lock);
1160
1161         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1162         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1163         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1164         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1165         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1166         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1167 }
1168
1169 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1170                                struct drm_connector_state *state,
1171                                const struct drm_display_mode *mode)
1172 {
1173         struct drm_device *drm = vc4_hdmi->connector.dev;
1174         struct vc4_hdmi_connector_state *vc4_state =
1175                 conn_state_to_vc4_hdmi_conn_state(state);
1176         unsigned long flags;
1177         u32 if_cfg = 0;
1178         u32 if_xbar = 0x543210;
1179         u32 csc_chan_ctl = 0;
1180         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1181                                                                VC5_MT_CP_CSC_CTL_MODE);
1182         int idx;
1183
1184         if (!drm_dev_enter(drm, &idx))
1185                 return;
1186
1187         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1188
1189         switch (vc4_state->output_format) {
1190         case VC4_HDMI_OUTPUT_YUV444:
1191                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709);
1192                 break;
1193
1194         case VC4_HDMI_OUTPUT_YUV422:
1195                 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1196                                          VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1197                         VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1198                         VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1199
1200                 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1201                                               VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1202
1203                 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1204                                         VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1205
1206                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709);
1207                 break;
1208
1209         case VC4_HDMI_OUTPUT_RGB:
1210                 if_xbar = 0x354021;
1211
1212                 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
1213                         vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
1214                 else
1215                         vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
1216                 break;
1217
1218         default:
1219                 break;
1220         }
1221
1222         HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1223         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1224         HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1225         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1226
1227         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1228
1229         drm_dev_exit(idx);
1230 }
1231
1232 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1233                                  struct drm_connector_state *state,
1234                                  const struct drm_display_mode *mode)
1235 {
1236         struct drm_device *drm = vc4_hdmi->connector.dev;
1237         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1238         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1239         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1240         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1241         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1242                                    VC4_HDMI_VERTA_VSP) |
1243                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1244                                    VC4_HDMI_VERTA_VFP) |
1245                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1246         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1247                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1248                                    interlaced,
1249                                    VC4_HDMI_VERTB_VBP));
1250         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1251                           VC4_SET_FIELD(mode->crtc_vtotal -
1252                                         mode->crtc_vsync_end,
1253                                         VC4_HDMI_VERTB_VBP));
1254         unsigned long flags;
1255         u32 reg;
1256         int idx;
1257
1258         if (!drm_dev_enter(drm, &idx))
1259                 return;
1260
1261         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1262
1263         HDMI_WRITE(HDMI_HORZA,
1264                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1265                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1266                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1267                                  VC4_HDMI_HORZA_HAP));
1268
1269         HDMI_WRITE(HDMI_HORZB,
1270                    VC4_SET_FIELD((mode->htotal -
1271                                   mode->hsync_end) * pixel_rep,
1272                                  VC4_HDMI_HORZB_HBP) |
1273                    VC4_SET_FIELD((mode->hsync_end -
1274                                   mode->hsync_start) * pixel_rep,
1275                                  VC4_HDMI_HORZB_HSP) |
1276                    VC4_SET_FIELD((mode->hsync_start -
1277                                   mode->hdisplay) * pixel_rep,
1278                                  VC4_HDMI_HORZB_HFP));
1279
1280         HDMI_WRITE(HDMI_VERTA0, verta);
1281         HDMI_WRITE(HDMI_VERTA1, verta);
1282
1283         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1284         HDMI_WRITE(HDMI_VERTB1, vertb);
1285
1286         reg = HDMI_READ(HDMI_MISC_CONTROL);
1287         reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1288         reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1289         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1290
1291         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1292
1293         drm_dev_exit(idx);
1294 }
1295
1296 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1297                                  struct drm_connector_state *state,
1298                                  const struct drm_display_mode *mode)
1299 {
1300         struct drm_device *drm = vc4_hdmi->connector.dev;
1301         const struct vc4_hdmi_connector_state *vc4_state =
1302                 conn_state_to_vc4_hdmi_conn_state(state);
1303         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1304         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1305         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1306         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1307         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1308                                    VC5_HDMI_VERTA_VSP) |
1309                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1310                                    VC5_HDMI_VERTA_VFP) |
1311                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1312         u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1313                                    VC5_HDMI_VERTB_VSPO) |
1314                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1315                                    interlaced,
1316                                    VC4_HDMI_VERTB_VBP));
1317         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1318                           VC4_SET_FIELD(mode->crtc_vtotal -
1319                                         mode->crtc_vsync_end,
1320                                         VC4_HDMI_VERTB_VBP));
1321         unsigned long flags;
1322         unsigned char gcp;
1323         u32 reg;
1324         int idx;
1325
1326         if (!drm_dev_enter(drm, &idx))
1327                 return;
1328
1329         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1330
1331         HDMI_WRITE(HDMI_HORZA,
1332                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1333                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1334                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1335                                  VC5_HDMI_HORZA_HAP) |
1336                    VC4_SET_FIELD((mode->hsync_start -
1337                                   mode->hdisplay) * pixel_rep,
1338                                  VC5_HDMI_HORZA_HFP));
1339
1340         HDMI_WRITE(HDMI_HORZB,
1341                    VC4_SET_FIELD((mode->htotal -
1342                                   mode->hsync_end) * pixel_rep,
1343                                  VC5_HDMI_HORZB_HBP) |
1344                    VC4_SET_FIELD((mode->hsync_end -
1345                                   mode->hsync_start) * pixel_rep,
1346                                  VC5_HDMI_HORZB_HSP));
1347
1348         HDMI_WRITE(HDMI_VERTA0, verta);
1349         HDMI_WRITE(HDMI_VERTA1, verta);
1350
1351         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1352         HDMI_WRITE(HDMI_VERTB1, vertb);
1353
1354         switch (vc4_state->output_bpc) {
1355         case 12:
1356                 gcp = 6;
1357                 break;
1358         case 10:
1359                 gcp = 5;
1360                 break;
1361         case 8:
1362         default:
1363                 gcp = 0;
1364                 break;
1365         }
1366
1367         /*
1368          * YCC422 is always 36-bit and not considered deep colour so
1369          * doesn't signal in GCP.
1370          */
1371         if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1372                 gcp = 0;
1373         }
1374
1375         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1376         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1377                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1378         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1379                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1380         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1381
1382         reg = HDMI_READ(HDMI_GCP_WORD_1);
1383         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1384         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1385         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1386         reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1387         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1388
1389         reg = HDMI_READ(HDMI_GCP_CONFIG);
1390         reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1391         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1392
1393         reg = HDMI_READ(HDMI_MISC_CONTROL);
1394         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1395         reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1396         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1397
1398         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1399
1400         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1401
1402         drm_dev_exit(idx);
1403 }
1404
1405 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1406 {
1407         struct drm_device *drm = vc4_hdmi->connector.dev;
1408         unsigned long flags;
1409         u32 drift;
1410         int ret;
1411         int idx;
1412
1413         if (!drm_dev_enter(drm, &idx))
1414                 return;
1415
1416         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1417
1418         drift = HDMI_READ(HDMI_FIFO_CTL);
1419         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1420
1421         HDMI_WRITE(HDMI_FIFO_CTL,
1422                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1423         HDMI_WRITE(HDMI_FIFO_CTL,
1424                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1425
1426         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1427
1428         usleep_range(1000, 1100);
1429
1430         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1431
1432         HDMI_WRITE(HDMI_FIFO_CTL,
1433                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1434         HDMI_WRITE(HDMI_FIFO_CTL,
1435                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1436
1437         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1438
1439         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1440                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1441         WARN_ONCE(ret, "Timeout waiting for "
1442                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1443
1444         drm_dev_exit(idx);
1445 }
1446
1447 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1448                                                 struct drm_atomic_state *state)
1449 {
1450         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1451         struct drm_device *drm = vc4_hdmi->connector.dev;
1452         struct drm_connector *connector = &vc4_hdmi->connector;
1453         struct drm_connector_state *conn_state =
1454                 drm_atomic_get_new_connector_state(state, connector);
1455         struct vc4_hdmi_connector_state *vc4_conn_state =
1456                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1457         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1458         unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1459         unsigned long bvb_rate, hsm_rate;
1460         unsigned long flags;
1461         int ret;
1462         int idx;
1463
1464         mutex_lock(&vc4_hdmi->mutex);
1465
1466         if (!drm_dev_enter(drm, &idx))
1467                 goto out;
1468
1469         /*
1470          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1471          * be faster than pixel clock, infinitesimally faster, tested in
1472          * simulation. Otherwise, exact value is unimportant for HDMI
1473          * operation." This conflicts with bcm2835's vc4 documentation, which
1474          * states HSM's clock has to be at least 108% of the pixel clock.
1475          *
1476          * Real life tests reveal that vc4's firmware statement holds up, and
1477          * users are able to use pixel clocks closer to HSM's, namely for
1478          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1479          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1480          * 162MHz.
1481          *
1482          * Additionally, the AXI clock needs to be at least 25% of
1483          * pixel clock, but HSM ends up being the limiting factor.
1484          */
1485         hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101);
1486         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1487         if (ret) {
1488                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1489                 goto err_dev_exit;
1490         }
1491
1492         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1493         if (ret < 0) {
1494                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1495                 goto err_dev_exit;
1496         }
1497
1498         ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1499         if (ret) {
1500                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1501                 goto err_put_runtime_pm;
1502         }
1503
1504         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1505         if (ret) {
1506                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1507                 goto err_put_runtime_pm;
1508         }
1509
1510
1511         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1512
1513         if (tmds_char_rate > 297000000)
1514                 bvb_rate = 300000000;
1515         else if (tmds_char_rate > 148500000)
1516                 bvb_rate = 150000000;
1517         else
1518                 bvb_rate = 75000000;
1519
1520         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1521         if (ret) {
1522                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1523                 goto err_disable_pixel_clock;
1524         }
1525
1526         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1527         if (ret) {
1528                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1529                 goto err_disable_pixel_clock;
1530         }
1531
1532         if (vc4_hdmi->variant->phy_init)
1533                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1534
1535         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1536
1537         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1538                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1539                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1540                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1541
1542         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1543
1544         if (vc4_hdmi->variant->set_timings)
1545                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1546
1547         drm_dev_exit(idx);
1548
1549         mutex_unlock(&vc4_hdmi->mutex);
1550
1551         return;
1552
1553 err_disable_pixel_clock:
1554         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1555 err_put_runtime_pm:
1556         pm_runtime_put(&vc4_hdmi->pdev->dev);
1557 err_dev_exit:
1558         drm_dev_exit(idx);
1559 out:
1560         mutex_unlock(&vc4_hdmi->mutex);
1561         return;
1562 }
1563
1564 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1565                                              struct drm_atomic_state *state)
1566 {
1567         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1568         struct drm_device *drm = vc4_hdmi->connector.dev;
1569         struct drm_connector *connector = &vc4_hdmi->connector;
1570         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1571         struct drm_connector_state *conn_state =
1572                 drm_atomic_get_new_connector_state(state, connector);
1573         unsigned long flags;
1574         int idx;
1575
1576         mutex_lock(&vc4_hdmi->mutex);
1577
1578         if (!drm_dev_enter(drm, &idx))
1579                 goto out;
1580
1581         if (vc4_hdmi->variant->csc_setup)
1582                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1583
1584         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1585         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1586         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1587
1588         drm_dev_exit(idx);
1589
1590 out:
1591         mutex_unlock(&vc4_hdmi->mutex);
1592 }
1593
1594 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1595                                               struct drm_atomic_state *state)
1596 {
1597         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1598         struct drm_device *drm = vc4_hdmi->connector.dev;
1599         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1600         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1601         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1602         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1603         unsigned long flags;
1604         int ret;
1605         int idx;
1606
1607         mutex_lock(&vc4_hdmi->mutex);
1608
1609         if (!drm_dev_enter(drm, &idx))
1610                 goto out;
1611
1612         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1613
1614         HDMI_WRITE(HDMI_VID_CTL,
1615                    VC4_HD_VID_CTL_ENABLE |
1616                    VC4_HD_VID_CTL_CLRRGB |
1617                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1618                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1619                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1620                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1621
1622         HDMI_WRITE(HDMI_VID_CTL,
1623                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1624
1625         if (display->is_hdmi) {
1626                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1627                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1628                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1629
1630                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1631
1632                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1633                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1634                 WARN_ONCE(ret, "Timeout waiting for "
1635                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1636         } else {
1637                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1638                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1639                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1640                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1641                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1642                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1643
1644                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1645
1646                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1647                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1648                 WARN_ONCE(ret, "Timeout waiting for "
1649                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1650         }
1651
1652         if (display->is_hdmi) {
1653                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1654
1655                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1656                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1657
1658                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1659                            VC4_HDMI_RAM_PACKET_ENABLE);
1660
1661                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1662                 vc4_hdmi->packet_ram_enabled = true;
1663
1664                 vc4_hdmi_set_infoframes(encoder);
1665         }
1666
1667         vc4_hdmi_recenter_fifo(vc4_hdmi);
1668         vc4_hdmi_enable_scrambling(encoder);
1669
1670         drm_dev_exit(idx);
1671
1672 out:
1673         mutex_unlock(&vc4_hdmi->mutex);
1674 }
1675
1676 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1677                                              struct drm_crtc_state *crtc_state,
1678                                              struct drm_connector_state *conn_state)
1679 {
1680         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1681         struct vc4_hdmi_connector_state *vc4_state =
1682                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1683
1684         mutex_lock(&vc4_hdmi->mutex);
1685         drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1686                       &crtc_state->adjusted_mode);
1687         vc4_hdmi->output_bpc = vc4_state->output_bpc;
1688         vc4_hdmi->output_format = vc4_state->output_format;
1689         mutex_unlock(&vc4_hdmi->mutex);
1690 }
1691
1692 static bool
1693 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1694                                   const struct drm_display_info *info,
1695                                   const struct drm_display_mode *mode,
1696                                   unsigned int format, unsigned int bpc)
1697 {
1698         struct drm_device *dev = vc4_hdmi->connector.dev;
1699         u8 vic = drm_match_cea_mode(mode);
1700
1701         if (vic == 1 && bpc != 8) {
1702                 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1703                 return false;
1704         }
1705
1706         if (!info->is_hdmi &&
1707             (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1708                 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1709                 return false;
1710         }
1711
1712         switch (format) {
1713         case VC4_HDMI_OUTPUT_RGB:
1714                 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1715
1716                 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1717                         return false;
1718
1719                 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1720                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1721                         return false;
1722                 }
1723
1724                 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1725                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1726                         return false;
1727                 }
1728
1729                 drm_dbg(dev, "RGB format supported in that configuration.\n");
1730
1731                 return true;
1732
1733         case VC4_HDMI_OUTPUT_YUV422:
1734                 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1735
1736                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1737                         drm_dbg(dev, "Sink doesn't support YUV422.\n");
1738                         return false;
1739                 }
1740
1741                 if (bpc != 12) {
1742                         drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1743                         return false;
1744                 }
1745
1746                 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1747
1748                 return true;
1749
1750         case VC4_HDMI_OUTPUT_YUV444:
1751                 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1752
1753                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1754                         drm_dbg(dev, "Sink doesn't support YUV444.\n");
1755                         return false;
1756                 }
1757
1758                 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1759                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1760                         return false;
1761                 }
1762
1763                 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1764                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1765                         return false;
1766                 }
1767
1768                 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1769
1770                 return true;
1771         }
1772
1773         return false;
1774 }
1775
1776 static enum drm_mode_status
1777 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1778                              const struct drm_display_mode *mode,
1779                              unsigned long long clock)
1780 {
1781         const struct drm_connector *connector = &vc4_hdmi->connector;
1782         const struct drm_display_info *info = &connector->display_info;
1783         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1784
1785         if (clock > vc4_hdmi->variant->max_pixel_clock)
1786                 return MODE_CLOCK_HIGH;
1787
1788         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1789                 return MODE_CLOCK_HIGH;
1790
1791         /* 4096x2160@60 is not reliable without overclocking core */
1792         if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1793             mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1794             drm_mode_vrefresh(mode) >= 50)
1795                 return MODE_CLOCK_HIGH;
1796
1797         if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1798                 return MODE_CLOCK_HIGH;
1799
1800         return MODE_OK;
1801 }
1802
1803 static unsigned long long
1804 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1805                                     unsigned int bpc,
1806                                     enum vc4_hdmi_output_format fmt)
1807 {
1808         unsigned long long clock = mode->clock * 1000ULL;
1809
1810         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1811                 clock = clock * 2;
1812
1813         if (fmt == VC4_HDMI_OUTPUT_YUV422)
1814                 bpc = 8;
1815
1816         clock = clock * bpc;
1817         do_div(clock, 8);
1818
1819         return clock;
1820 }
1821
1822 static int
1823 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1824                                struct vc4_hdmi_connector_state *vc4_state,
1825                                const struct drm_display_mode *mode,
1826                                unsigned int bpc, unsigned int fmt)
1827 {
1828         unsigned long long clock;
1829
1830         clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
1831         if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK)
1832                 return -EINVAL;
1833
1834         vc4_state->tmds_char_rate = clock;
1835
1836         return 0;
1837 }
1838
1839 static int
1840 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
1841                                 struct vc4_hdmi_connector_state *vc4_state,
1842                                 const struct drm_display_mode *mode,
1843                                 unsigned int bpc)
1844 {
1845         struct drm_device *dev = vc4_hdmi->connector.dev;
1846         const struct drm_connector *connector = &vc4_hdmi->connector;
1847         const struct drm_display_info *info = &connector->display_info;
1848         unsigned int format;
1849
1850         drm_dbg(dev, "Trying with an RGB output\n");
1851
1852         format = VC4_HDMI_OUTPUT_RGB;
1853         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1854                 int ret;
1855
1856                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1857                                                      mode, bpc, format);
1858                 if (!ret) {
1859                         vc4_state->output_format = format;
1860                         return 0;
1861                 }
1862         }
1863
1864         drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
1865
1866         format = VC4_HDMI_OUTPUT_YUV422;
1867         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1868                 int ret;
1869
1870                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1871                                                      mode, bpc, format);
1872                 if (!ret) {
1873                         vc4_state->output_format = format;
1874                         return 0;
1875                 }
1876         }
1877
1878         drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
1879
1880         return -EINVAL;
1881 }
1882
1883 static int
1884 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
1885                                 struct vc4_hdmi_connector_state *vc4_state,
1886                                 const struct drm_display_mode *mode)
1887 {
1888         struct drm_device *dev = vc4_hdmi->connector.dev;
1889         struct drm_connector_state *conn_state = &vc4_state->base;
1890         unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
1891         unsigned int bpc;
1892         int ret;
1893
1894         for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
1895                 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
1896
1897                 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
1898                                                       mode, bpc);
1899                 if (ret)
1900                         continue;
1901
1902                 vc4_state->output_bpc = bpc;
1903
1904                 drm_dbg(dev,
1905                         "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
1906                         mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1907                         vc4_state->output_bpc,
1908                         vc4_hdmi_output_fmt_str(vc4_state->output_format),
1909                         vc4_state->tmds_char_rate);
1910
1911                 break;
1912         }
1913
1914         return ret;
1915 }
1916
1917 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1918 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1919
1920 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1921                                          struct drm_crtc_state *crtc_state,
1922                                          struct drm_connector_state *conn_state)
1923 {
1924         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1925         struct drm_connector *connector = &vc4_hdmi->connector;
1926         struct drm_connector_state *old_conn_state =
1927                 drm_atomic_get_old_connector_state(conn_state->state, connector);
1928         struct vc4_hdmi_connector_state *old_vc4_state =
1929                 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
1930         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1931         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1932         unsigned long long tmds_char_rate = mode->clock * 1000;
1933         unsigned long long tmds_bit_rate;
1934         int ret;
1935
1936         if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1937                 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1938                         /* Only try to fixup DBLCLK modes to get 480i and 576i
1939                          * working.
1940                          * A generic solution for all modes with odd horizontal
1941                          * timing values seems impossible based on trying to
1942                          * solve it for 1366x768 monitors.
1943                          */
1944                         if ((mode->hsync_start - mode->hdisplay) & 1)
1945                                 mode->hsync_start--;
1946                         if ((mode->hsync_end - mode->hsync_start) & 1)
1947                                 mode->hsync_end--;
1948                 }
1949
1950                 /* Now check whether we still have odd values remaining */
1951                 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1952                     (mode->hsync_end % 2) || (mode->htotal % 2))
1953                         return -EINVAL;
1954         }
1955
1956         /*
1957          * The 1440p@60 pixel rate is in the same range than the first
1958          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1959          * bandwidth). Slightly lower the frequency to bring it out of
1960          * the WiFi range.
1961          */
1962         tmds_bit_rate = tmds_char_rate * 10;
1963         if (vc4_hdmi->disable_wifi_frequencies &&
1964             (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1965              tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1966                 mode->clock = 238560;
1967                 tmds_char_rate = mode->clock * 1000;
1968         }
1969
1970         ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
1971         if (ret)
1972                 return ret;
1973
1974         /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
1975         if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
1976             vc4_state->output_format != old_vc4_state->output_format)
1977                 crtc_state->mode_changed = true;
1978
1979         return 0;
1980 }
1981
1982 static enum drm_mode_status
1983 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1984                             const struct drm_display_mode *mode)
1985 {
1986         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1987
1988         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1989             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1990             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1991              (mode->hsync_end % 2) || (mode->htotal % 2)))
1992                 return MODE_H_ILLEGAL;
1993
1994         return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000);
1995 }
1996
1997 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1998         .atomic_check = vc4_hdmi_encoder_atomic_check,
1999         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
2000         .mode_valid = vc4_hdmi_encoder_mode_valid,
2001 };
2002
2003 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
2004 {
2005         struct drm_device *drm = encoder->dev;
2006         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2007         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2008
2009         drm_debugfs_add_file(drm, variant->debugfs_name,
2010                              vc4_hdmi_debugfs_regs, vc4_hdmi);
2011
2012         return 0;
2013 }
2014
2015 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
2016         .late_register = vc4_hdmi_late_register,
2017 };
2018
2019 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2020 {
2021         int i;
2022         u32 channel_map = 0;
2023
2024         for (i = 0; i < 8; i++) {
2025                 if (channel_mask & BIT(i))
2026                         channel_map |= i << (3 * i);
2027         }
2028         return channel_map;
2029 }
2030
2031 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2032 {
2033         int i;
2034         u32 channel_map = 0;
2035
2036         for (i = 0; i < 8; i++) {
2037                 if (channel_mask & BIT(i))
2038                         channel_map |= i << (4 * i);
2039         }
2040         return channel_map;
2041 }
2042
2043 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2044 {
2045         struct drm_device *drm = vc4_hdmi->connector.dev;
2046         unsigned long flags;
2047         u32 hotplug;
2048         int idx;
2049
2050         if (!drm_dev_enter(drm, &idx))
2051                 return false;
2052
2053         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2054         hotplug = HDMI_READ(HDMI_HOTPLUG);
2055         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2056
2057         drm_dev_exit(idx);
2058
2059         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2060 }
2061
2062 /* HDMI audio codec callbacks */
2063 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2064                                          unsigned int samplerate)
2065 {
2066         struct drm_device *drm = vc4_hdmi->connector.dev;
2067         u32 hsm_clock;
2068         unsigned long flags;
2069         unsigned long n, m;
2070         int idx;
2071
2072         if (!drm_dev_enter(drm, &idx))
2073                 return;
2074
2075         hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2076         rational_best_approximation(hsm_clock, samplerate,
2077                                     VC4_HD_MAI_SMP_N_MASK >>
2078                                     VC4_HD_MAI_SMP_N_SHIFT,
2079                                     (VC4_HD_MAI_SMP_M_MASK >>
2080                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
2081                                     &n, &m);
2082
2083         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2084         HDMI_WRITE(HDMI_MAI_SMP,
2085                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2086                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2087         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2088
2089         drm_dev_exit(idx);
2090 }
2091
2092 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2093 {
2094         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2095         u32 n, cts;
2096         u64 tmp;
2097
2098         lockdep_assert_held(&vc4_hdmi->mutex);
2099         lockdep_assert_held(&vc4_hdmi->hw_lock);
2100
2101         n = 128 * samplerate / 1000;
2102         tmp = (u64)(mode->clock * 1000) * n;
2103         do_div(tmp, 128 * samplerate);
2104         cts = tmp;
2105
2106         HDMI_WRITE(HDMI_CRP_CFG,
2107                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2108                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2109
2110         /*
2111          * We could get slightly more accurate clocks in some cases by
2112          * providing a CTS_1 value.  The two CTS values are alternated
2113          * between based on the period fields
2114          */
2115         HDMI_WRITE(HDMI_CTS_0, cts);
2116         HDMI_WRITE(HDMI_CTS_1, cts);
2117 }
2118
2119 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2120 {
2121         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2122
2123         return snd_soc_card_get_drvdata(card);
2124 }
2125
2126 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2127 {
2128         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
2129
2130         lockdep_assert_held(&vc4_hdmi->mutex);
2131
2132         /*
2133          * If the encoder is currently in DVI mode, treat the codec DAI
2134          * as missing.
2135          */
2136         if (!display->is_hdmi)
2137                 return false;
2138
2139         return true;
2140 }
2141
2142 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2143 {
2144         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2145         struct drm_device *drm = vc4_hdmi->connector.dev;
2146         unsigned long flags;
2147         int ret = 0;
2148         int idx;
2149
2150         mutex_lock(&vc4_hdmi->mutex);
2151
2152         if (!drm_dev_enter(drm, &idx)) {
2153                 ret = -ENODEV;
2154                 goto out;
2155         }
2156
2157         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2158                 ret = -ENODEV;
2159                 goto out_dev_exit;
2160         }
2161
2162         vc4_hdmi->audio.streaming = true;
2163
2164         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2165         HDMI_WRITE(HDMI_MAI_CTL,
2166                    VC4_HD_MAI_CTL_RESET |
2167                    VC4_HD_MAI_CTL_FLUSH |
2168                    VC4_HD_MAI_CTL_DLATE |
2169                    VC4_HD_MAI_CTL_ERRORE |
2170                    VC4_HD_MAI_CTL_ERRORF);
2171         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2172
2173         if (vc4_hdmi->variant->phy_rng_enable)
2174                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2175
2176 out_dev_exit:
2177         drm_dev_exit(idx);
2178 out:
2179         mutex_unlock(&vc4_hdmi->mutex);
2180
2181         return ret;
2182 }
2183
2184 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2185 {
2186         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2187         struct device *dev = &vc4_hdmi->pdev->dev;
2188         unsigned long flags;
2189         int ret;
2190
2191         lockdep_assert_held(&vc4_hdmi->mutex);
2192
2193         vc4_hdmi->audio.streaming = false;
2194         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2195         if (ret)
2196                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2197
2198         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2199
2200         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2201         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2202         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2203
2204         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2205 }
2206
2207 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2208 {
2209         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2210         struct drm_device *drm = vc4_hdmi->connector.dev;
2211         unsigned long flags;
2212         int idx;
2213
2214         mutex_lock(&vc4_hdmi->mutex);
2215
2216         if (!drm_dev_enter(drm, &idx))
2217                 goto out;
2218
2219         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2220
2221         HDMI_WRITE(HDMI_MAI_CTL,
2222                    VC4_HD_MAI_CTL_DLATE |
2223                    VC4_HD_MAI_CTL_ERRORE |
2224                    VC4_HD_MAI_CTL_ERRORF);
2225
2226         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2227
2228         if (vc4_hdmi->variant->phy_rng_disable)
2229                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2230
2231         vc4_hdmi->audio.streaming = false;
2232         vc4_hdmi_audio_reset(vc4_hdmi);
2233
2234         drm_dev_exit(idx);
2235
2236 out:
2237         mutex_unlock(&vc4_hdmi->mutex);
2238 }
2239
2240 static int sample_rate_to_mai_fmt(int samplerate)
2241 {
2242         switch (samplerate) {
2243         case 8000:
2244                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2245         case 11025:
2246                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2247         case 12000:
2248                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2249         case 16000:
2250                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2251         case 22050:
2252                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2253         case 24000:
2254                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2255         case 32000:
2256                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2257         case 44100:
2258                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2259         case 48000:
2260                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2261         case 64000:
2262                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2263         case 88200:
2264                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2265         case 96000:
2266                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2267         case 128000:
2268                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2269         case 176400:
2270                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2271         case 192000:
2272                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2273         default:
2274                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2275         }
2276 }
2277
2278 /* HDMI audio codec callbacks */
2279 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2280                                   struct hdmi_codec_daifmt *daifmt,
2281                                   struct hdmi_codec_params *params)
2282 {
2283         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2284         struct drm_device *drm = vc4_hdmi->connector.dev;
2285         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2286         unsigned int sample_rate = params->sample_rate;
2287         unsigned int channels = params->channels;
2288         unsigned long flags;
2289         u32 audio_packet_config, channel_mask;
2290         u32 channel_map;
2291         u32 mai_audio_format;
2292         u32 mai_sample_rate;
2293         int ret = 0;
2294         int idx;
2295
2296         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2297                 sample_rate, params->sample_width, channels);
2298
2299         mutex_lock(&vc4_hdmi->mutex);
2300
2301         if (!drm_dev_enter(drm, &idx)) {
2302                 ret = -ENODEV;
2303                 goto out;
2304         }
2305
2306         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2307                 ret = -EINVAL;
2308                 goto out_dev_exit;
2309         }
2310
2311         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2312
2313         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2314         HDMI_WRITE(HDMI_MAI_CTL,
2315                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2316                    VC4_HD_MAI_CTL_WHOLSMP |
2317                    VC4_HD_MAI_CTL_CHALIGN |
2318                    VC4_HD_MAI_CTL_ENABLE);
2319
2320         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2321         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2322             params->channels == 8)
2323                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2324         else
2325                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2326         HDMI_WRITE(HDMI_MAI_FMT,
2327                    VC4_SET_FIELD(mai_sample_rate,
2328                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2329                    VC4_SET_FIELD(mai_audio_format,
2330                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2331
2332         /* The B frame identifier should match the value used by alsa-lib (8) */
2333         audio_packet_config =
2334                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2335                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2336                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2337
2338         channel_mask = GENMASK(channels - 1, 0);
2339         audio_packet_config |= VC4_SET_FIELD(channel_mask,
2340                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2341
2342         /* Set the MAI threshold */
2343         HDMI_WRITE(HDMI_MAI_THR,
2344                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2345                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2346                    VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2347                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2348
2349         HDMI_WRITE(HDMI_MAI_CONFIG,
2350                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2351                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2352                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2353
2354         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2355         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2356         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2357
2358         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2359
2360         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2361
2362         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
2363         vc4_hdmi_set_audio_infoframe(encoder);
2364
2365 out_dev_exit:
2366         drm_dev_exit(idx);
2367 out:
2368         mutex_unlock(&vc4_hdmi->mutex);
2369
2370         return ret;
2371 }
2372
2373 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2374         .name = "vc4-hdmi-cpu-dai-component",
2375         .legacy_dai_naming = 1,
2376 };
2377
2378 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2379 {
2380         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2381
2382         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2383
2384         return 0;
2385 }
2386
2387 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2388         .name = "vc4-hdmi-cpu-dai",
2389         .probe  = vc4_hdmi_audio_cpu_dai_probe,
2390         .playback = {
2391                 .stream_name = "Playback",
2392                 .channels_min = 1,
2393                 .channels_max = 8,
2394                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2395                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2396                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2397                          SNDRV_PCM_RATE_192000,
2398                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2399         },
2400 };
2401
2402 static const struct snd_dmaengine_pcm_config pcm_conf = {
2403         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2404         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2405 };
2406
2407 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2408                                   uint8_t *buf, size_t len)
2409 {
2410         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2411         struct drm_connector *connector = &vc4_hdmi->connector;
2412
2413         mutex_lock(&vc4_hdmi->mutex);
2414         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2415         mutex_unlock(&vc4_hdmi->mutex);
2416
2417         return 0;
2418 }
2419
2420 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2421         .get_eld = vc4_hdmi_audio_get_eld,
2422         .prepare = vc4_hdmi_audio_prepare,
2423         .audio_shutdown = vc4_hdmi_audio_shutdown,
2424         .audio_startup = vc4_hdmi_audio_startup,
2425 };
2426
2427 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2428         .ops = &vc4_hdmi_codec_ops,
2429         .max_i2s_channels = 8,
2430         .i2s = 1,
2431 };
2432
2433 static void vc4_hdmi_audio_codec_release(void *ptr)
2434 {
2435         struct vc4_hdmi *vc4_hdmi = ptr;
2436
2437         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2438         vc4_hdmi->audio.codec_pdev = NULL;
2439 }
2440
2441 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2442 {
2443         const struct vc4_hdmi_register *mai_data =
2444                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2445         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2446         struct snd_soc_card *card = &vc4_hdmi->audio.card;
2447         struct device *dev = &vc4_hdmi->pdev->dev;
2448         struct platform_device *codec_pdev;
2449         const __be32 *addr;
2450         int index, len;
2451         int ret;
2452
2453         /*
2454          * ASoC makes it a bit hard to retrieve a pointer to the
2455          * vc4_hdmi structure. Registering the card will overwrite our
2456          * device drvdata with a pointer to the snd_soc_card structure,
2457          * which can then be used to retrieve whatever drvdata we want
2458          * to associate.
2459          *
2460          * However, that doesn't fly in the case where we wouldn't
2461          * register an ASoC card (because of an old DT that is missing
2462          * the dmas properties for example), then the card isn't
2463          * registered and the device drvdata wouldn't be set.
2464          *
2465          * We can deal with both cases by making sure a snd_soc_card
2466          * pointer and a vc4_hdmi structure are pointing to the same
2467          * memory address, so we can treat them indistinctly without any
2468          * issue.
2469          */
2470         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2471         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2472
2473         if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2474                 dev_warn(dev,
2475                          "'dmas' DT property is missing or empty, no HDMI audio\n");
2476                 return 0;
2477         }
2478
2479         if (mai_data->reg != VC4_HD) {
2480                 WARN_ONCE(true, "MAI isn't in the HD block\n");
2481                 return -EINVAL;
2482         }
2483
2484         /*
2485          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2486          * the bus address specified in the DT, because the physical address
2487          * (the one returned by platform_get_resource()) is not appropriate
2488          * for DMA transfers.
2489          * This VC/MMU should probably be exposed to avoid this kind of hacks.
2490          */
2491         index = of_property_match_string(dev->of_node, "reg-names", "hd");
2492         /* Before BCM2711, we don't have a named register range */
2493         if (index < 0)
2494                 index = 1;
2495
2496         addr = of_get_address(dev->of_node, index, NULL, NULL);
2497
2498         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2499         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2500         vc4_hdmi->audio.dma_data.maxburst = 2;
2501
2502         /*
2503          * NOTE: Strictly speaking, we should probably use a DRM-managed
2504          * registration there to avoid removing all the audio components
2505          * by the time the driver doesn't have any user anymore.
2506          *
2507          * However, the ASoC core uses a number of devm_kzalloc calls
2508          * when registering, even when using non-device-managed
2509          * functions (such as in snd_soc_register_component()).
2510          *
2511          * If we call snd_soc_unregister_component() in a DRM-managed
2512          * action, the device-managed actions have already been executed
2513          * and thus we would access memory that has been freed.
2514          *
2515          * Using device-managed hooks here probably leaves us open to a
2516          * bunch of issues if userspace still has a handle on the ALSA
2517          * device when the device is removed. However, this is mitigated
2518          * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2519          * path to prevent the access to the device resources if it
2520          * isn't there anymore.
2521          *
2522          * Then, the vc4_hdmi structure is DRM-managed and thus only
2523          * freed whenever the last user has closed the DRM device file.
2524          * It should thus outlive ALSA in most situations.
2525          */
2526         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2527         if (ret) {
2528                 dev_err(dev, "Could not register PCM component: %d\n", ret);
2529                 return ret;
2530         }
2531
2532         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2533                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
2534         if (ret) {
2535                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2536                 return ret;
2537         }
2538
2539         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2540                                                    PLATFORM_DEVID_AUTO,
2541                                                    &vc4_hdmi_codec_pdata,
2542                                                    sizeof(vc4_hdmi_codec_pdata));
2543         if (IS_ERR(codec_pdev)) {
2544                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2545                 return PTR_ERR(codec_pdev);
2546         }
2547         vc4_hdmi->audio.codec_pdev = codec_pdev;
2548
2549         ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2550         if (ret)
2551                 return ret;
2552
2553         dai_link->cpus          = &vc4_hdmi->audio.cpu;
2554         dai_link->codecs        = &vc4_hdmi->audio.codec;
2555         dai_link->platforms     = &vc4_hdmi->audio.platform;
2556
2557         dai_link->num_cpus      = 1;
2558         dai_link->num_codecs    = 1;
2559         dai_link->num_platforms = 1;
2560
2561         dai_link->name = "MAI";
2562         dai_link->stream_name = "MAI PCM";
2563         dai_link->codecs->dai_name = "i2s-hifi";
2564         dai_link->cpus->dai_name = dev_name(dev);
2565         dai_link->codecs->name = dev_name(&codec_pdev->dev);
2566         dai_link->platforms->name = dev_name(dev);
2567
2568         card->dai_link = dai_link;
2569         card->num_links = 1;
2570         card->name = vc4_hdmi->variant->card_name;
2571         card->driver_name = "vc4-hdmi";
2572         card->dev = dev;
2573         card->owner = THIS_MODULE;
2574
2575         /*
2576          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2577          * stores a pointer to the snd card object in dev->driver_data. This
2578          * means we cannot use it for something else. The hdmi back-pointer is
2579          * now stored in card->drvdata and should be retrieved with
2580          * snd_soc_card_get_drvdata() if needed.
2581          */
2582         snd_soc_card_set_drvdata(card, vc4_hdmi);
2583         ret = devm_snd_soc_register_card(dev, card);
2584         if (ret)
2585                 dev_err_probe(dev, ret, "Could not register sound card\n");
2586
2587         return ret;
2588
2589 }
2590
2591 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2592 {
2593         struct vc4_hdmi *vc4_hdmi = priv;
2594         struct drm_connector *connector = &vc4_hdmi->connector;
2595         struct drm_device *dev = connector->dev;
2596
2597         if (dev && dev->registered)
2598                 drm_connector_helper_hpd_irq_event(connector);
2599
2600         return IRQ_HANDLED;
2601 }
2602
2603 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2604 {
2605         struct drm_connector *connector = &vc4_hdmi->connector;
2606         struct platform_device *pdev = vc4_hdmi->pdev;
2607         int ret;
2608
2609         if (vc4_hdmi->variant->external_irq_controller) {
2610                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2611                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2612
2613                 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2614                                                 NULL,
2615                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2616                                                 "vc4 hdmi hpd connected", vc4_hdmi);
2617                 if (ret)
2618                         return ret;
2619
2620                 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2621                                                 NULL,
2622                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2623                                                 "vc4 hdmi hpd disconnected", vc4_hdmi);
2624                 if (ret)
2625                         return ret;
2626
2627                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2628         }
2629
2630         return 0;
2631 }
2632
2633 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2634 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2635 {
2636         struct vc4_hdmi *vc4_hdmi = priv;
2637
2638         if (vc4_hdmi->cec_rx_msg.len)
2639                 cec_received_msg(vc4_hdmi->cec_adap,
2640                                  &vc4_hdmi->cec_rx_msg);
2641
2642         return IRQ_HANDLED;
2643 }
2644
2645 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2646 {
2647         struct vc4_hdmi *vc4_hdmi = priv;
2648
2649         if (vc4_hdmi->cec_tx_ok) {
2650                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2651                                   0, 0, 0, 0);
2652         } else {
2653                 /*
2654                  * This CEC implementation makes 1 retry, so if we
2655                  * get a NACK, then that means it made 2 attempts.
2656                  */
2657                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2658                                   0, 2, 0, 0);
2659         }
2660         return IRQ_HANDLED;
2661 }
2662
2663 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2664 {
2665         struct vc4_hdmi *vc4_hdmi = priv;
2666         irqreturn_t ret;
2667
2668         if (vc4_hdmi->cec_irq_was_rx)
2669                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2670         else
2671                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2672
2673         return ret;
2674 }
2675
2676 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2677 {
2678         struct drm_device *dev = vc4_hdmi->connector.dev;
2679         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2680         unsigned int i;
2681
2682         lockdep_assert_held(&vc4_hdmi->hw_lock);
2683
2684         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2685                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2686
2687         if (msg->len > 16) {
2688                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2689                 return;
2690         }
2691
2692         for (i = 0; i < msg->len; i += 4) {
2693                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2694
2695                 msg->msg[i] = val & 0xff;
2696                 msg->msg[i + 1] = (val >> 8) & 0xff;
2697                 msg->msg[i + 2] = (val >> 16) & 0xff;
2698                 msg->msg[i + 3] = (val >> 24) & 0xff;
2699         }
2700 }
2701
2702 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2703 {
2704         u32 cntrl1;
2705
2706         /*
2707          * We don't need to protect the register access using
2708          * drm_dev_enter() there because the interrupt handler lifetime
2709          * is tied to the device itself, and not to the DRM device.
2710          *
2711          * So when the device will be gone, one of the first thing we
2712          * will be doing will be to unregister the interrupt handler,
2713          * and then unregister the DRM device. drm_dev_enter() would
2714          * thus always succeed if we are here.
2715          */
2716
2717         lockdep_assert_held(&vc4_hdmi->hw_lock);
2718
2719         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2720         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2721         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2722         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2723
2724         return IRQ_WAKE_THREAD;
2725 }
2726
2727 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2728 {
2729         struct vc4_hdmi *vc4_hdmi = priv;
2730         irqreturn_t ret;
2731
2732         spin_lock(&vc4_hdmi->hw_lock);
2733         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2734         spin_unlock(&vc4_hdmi->hw_lock);
2735
2736         return ret;
2737 }
2738
2739 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2740 {
2741         u32 cntrl1;
2742
2743         lockdep_assert_held(&vc4_hdmi->hw_lock);
2744
2745         /*
2746          * We don't need to protect the register access using
2747          * drm_dev_enter() there because the interrupt handler lifetime
2748          * is tied to the device itself, and not to the DRM device.
2749          *
2750          * So when the device will be gone, one of the first thing we
2751          * will be doing will be to unregister the interrupt handler,
2752          * and then unregister the DRM device. drm_dev_enter() would
2753          * thus always succeed if we are here.
2754          */
2755
2756         vc4_hdmi->cec_rx_msg.len = 0;
2757         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2758         vc4_cec_read_msg(vc4_hdmi, cntrl1);
2759         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2760         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2761         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2762
2763         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2764
2765         return IRQ_WAKE_THREAD;
2766 }
2767
2768 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2769 {
2770         struct vc4_hdmi *vc4_hdmi = priv;
2771         irqreturn_t ret;
2772
2773         spin_lock(&vc4_hdmi->hw_lock);
2774         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2775         spin_unlock(&vc4_hdmi->hw_lock);
2776
2777         return ret;
2778 }
2779
2780 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2781 {
2782         struct vc4_hdmi *vc4_hdmi = priv;
2783         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2784         irqreturn_t ret;
2785         u32 cntrl5;
2786
2787         /*
2788          * We don't need to protect the register access using
2789          * drm_dev_enter() there because the interrupt handler lifetime
2790          * is tied to the device itself, and not to the DRM device.
2791          *
2792          * So when the device will be gone, one of the first thing we
2793          * will be doing will be to unregister the interrupt handler,
2794          * and then unregister the DRM device. drm_dev_enter() would
2795          * thus always succeed if we are here.
2796          */
2797
2798         if (!(stat & VC4_HDMI_CPU_CEC))
2799                 return IRQ_NONE;
2800
2801         spin_lock(&vc4_hdmi->hw_lock);
2802         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2803         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2804         if (vc4_hdmi->cec_irq_was_rx)
2805                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2806         else
2807                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2808
2809         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2810         spin_unlock(&vc4_hdmi->hw_lock);
2811
2812         return ret;
2813 }
2814
2815 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2816 {
2817         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2818         struct drm_device *drm = vc4_hdmi->connector.dev;
2819         /* clock period in microseconds */
2820         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2821         unsigned long flags;
2822         u32 val;
2823         int ret;
2824         int idx;
2825
2826         if (!drm_dev_enter(drm, &idx))
2827                 /*
2828                  * We can't return an error code, because the CEC
2829                  * framework will emit WARN_ON messages at unbind
2830                  * otherwise.
2831                  */
2832                 return 0;
2833
2834         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2835         if (ret) {
2836                 drm_dev_exit(idx);
2837                 return ret;
2838         }
2839
2840         mutex_lock(&vc4_hdmi->mutex);
2841
2842         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2843
2844         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2845         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2846                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2847                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2848         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2849                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2850
2851         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2852                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2853         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2854         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2855                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2856                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2857                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2858                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2859                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2860         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2861                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2862                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2863                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2864                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2865         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2866                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2867                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2868                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2869                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2870
2871         if (!vc4_hdmi->variant->external_irq_controller)
2872                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2873
2874         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2875
2876         mutex_unlock(&vc4_hdmi->mutex);
2877         drm_dev_exit(idx);
2878
2879         return 0;
2880 }
2881
2882 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2883 {
2884         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2885         struct drm_device *drm = vc4_hdmi->connector.dev;
2886         unsigned long flags;
2887         int idx;
2888
2889         if (!drm_dev_enter(drm, &idx))
2890                 /*
2891                  * We can't return an error code, because the CEC
2892                  * framework will emit WARN_ON messages at unbind
2893                  * otherwise.
2894                  */
2895                 return 0;
2896
2897         mutex_lock(&vc4_hdmi->mutex);
2898
2899         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2900
2901         if (!vc4_hdmi->variant->external_irq_controller)
2902                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2903
2904         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2905                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2906
2907         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2908
2909         mutex_unlock(&vc4_hdmi->mutex);
2910
2911         pm_runtime_put(&vc4_hdmi->pdev->dev);
2912
2913         drm_dev_exit(idx);
2914
2915         return 0;
2916 }
2917
2918 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2919 {
2920         if (enable)
2921                 return vc4_hdmi_cec_enable(adap);
2922         else
2923                 return vc4_hdmi_cec_disable(adap);
2924 }
2925
2926 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2927 {
2928         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2929         struct drm_device *drm = vc4_hdmi->connector.dev;
2930         unsigned long flags;
2931         int idx;
2932
2933         if (!drm_dev_enter(drm, &idx))
2934                 /*
2935                  * We can't return an error code, because the CEC
2936                  * framework will emit WARN_ON messages at unbind
2937                  * otherwise.
2938                  */
2939                 return 0;
2940
2941         mutex_lock(&vc4_hdmi->mutex);
2942         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2943         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2944                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2945                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2946         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2947         mutex_unlock(&vc4_hdmi->mutex);
2948
2949         drm_dev_exit(idx);
2950
2951         return 0;
2952 }
2953
2954 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2955                                       u32 signal_free_time, struct cec_msg *msg)
2956 {
2957         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2958         struct drm_device *dev = vc4_hdmi->connector.dev;
2959         unsigned long flags;
2960         u32 val;
2961         unsigned int i;
2962         int idx;
2963
2964         if (!drm_dev_enter(dev, &idx))
2965                 return -ENODEV;
2966
2967         if (msg->len > 16) {
2968                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2969                 drm_dev_exit(idx);
2970                 return -ENOMEM;
2971         }
2972
2973         mutex_lock(&vc4_hdmi->mutex);
2974
2975         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2976
2977         for (i = 0; i < msg->len; i += 4)
2978                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2979                            (msg->msg[i]) |
2980                            (msg->msg[i + 1] << 8) |
2981                            (msg->msg[i + 2] << 16) |
2982                            (msg->msg[i + 3] << 24));
2983
2984         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2985         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2986         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2987         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2988         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2989         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2990
2991         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2992
2993         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2994         mutex_unlock(&vc4_hdmi->mutex);
2995         drm_dev_exit(idx);
2996
2997         return 0;
2998 }
2999
3000 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
3001         .adap_enable = vc4_hdmi_cec_adap_enable,
3002         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
3003         .adap_transmit = vc4_hdmi_cec_adap_transmit,
3004 };
3005
3006 static void vc4_hdmi_cec_release(void *ptr)
3007 {
3008         struct vc4_hdmi *vc4_hdmi = ptr;
3009
3010         cec_unregister_adapter(vc4_hdmi->cec_adap);
3011         vc4_hdmi->cec_adap = NULL;
3012 }
3013
3014 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3015 {
3016         struct cec_connector_info conn_info;
3017         struct platform_device *pdev = vc4_hdmi->pdev;
3018         struct device *dev = &pdev->dev;
3019         int ret;
3020
3021         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
3022                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
3023                 return 0;
3024         }
3025
3026         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3027                                                   vc4_hdmi,
3028                                                   vc4_hdmi->variant->card_name,
3029                                                   CEC_CAP_DEFAULTS |
3030                                                   CEC_CAP_CONNECTOR_INFO, 1);
3031         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3032         if (ret < 0)
3033                 return ret;
3034
3035         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3036         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3037
3038         if (vc4_hdmi->variant->external_irq_controller) {
3039                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3040                                                 vc4_cec_irq_handler_rx_bare,
3041                                                 vc4_cec_irq_handler_rx_thread, 0,
3042                                                 "vc4 hdmi cec rx", vc4_hdmi);
3043                 if (ret)
3044                         goto err_delete_cec_adap;
3045
3046                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3047                                                 vc4_cec_irq_handler_tx_bare,
3048                                                 vc4_cec_irq_handler_tx_thread, 0,
3049                                                 "vc4 hdmi cec tx", vc4_hdmi);
3050                 if (ret)
3051                         goto err_delete_cec_adap;
3052         } else {
3053                 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3054                                                 vc4_cec_irq_handler,
3055                                                 vc4_cec_irq_handler_thread, 0,
3056                                                 "vc4 hdmi cec", vc4_hdmi);
3057                 if (ret)
3058                         goto err_delete_cec_adap;
3059         }
3060
3061         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3062         if (ret < 0)
3063                 goto err_delete_cec_adap;
3064
3065         /*
3066          * NOTE: Strictly speaking, we should probably use a DRM-managed
3067          * registration there to avoid removing the CEC adapter by the
3068          * time the DRM driver doesn't have any user anymore.
3069          *
3070          * However, the CEC framework already cleans up the CEC adapter
3071          * only when the last user has closed its file descriptor, so we
3072          * don't need to handle it in DRM.
3073          *
3074          * By the time the device-managed hook is executed, we will give
3075          * up our reference to the CEC adapter and therefore don't
3076          * really care when it's actually freed.
3077          *
3078          * There's still a problematic sequence: if we unregister our
3079          * CEC adapter, but the userspace keeps a handle on the CEC
3080          * adapter but not the DRM device for some reason. In such a
3081          * case, our vc4_hdmi structure will be freed, but the
3082          * cec_adapter structure will have a dangling pointer to what
3083          * used to be our HDMI controller. If we get a CEC call at that
3084          * moment, we could end up with a use-after-free. Fortunately,
3085          * the CEC framework already handles this too, by calling
3086          * cec_is_registered() in cec_ioctl() and cec_poll().
3087          */
3088         ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3089         if (ret)
3090                 return ret;
3091
3092         return 0;
3093
3094 err_delete_cec_adap:
3095         cec_delete_adapter(vc4_hdmi->cec_adap);
3096
3097         return ret;
3098 }
3099 #else
3100 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3101 {
3102         return 0;
3103 }
3104 #endif
3105
3106 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3107 {
3108         struct debugfs_reg32 *regs = ptr;
3109
3110         kfree(regs);
3111 }
3112
3113 static int vc4_hdmi_build_regset(struct drm_device *drm,
3114                                  struct vc4_hdmi *vc4_hdmi,
3115                                  struct debugfs_regset32 *regset,
3116                                  enum vc4_hdmi_regs reg)
3117 {
3118         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3119         struct debugfs_reg32 *regs, *new_regs;
3120         unsigned int count = 0;
3121         unsigned int i;
3122         int ret;
3123
3124         regs = kcalloc(variant->num_registers, sizeof(*regs),
3125                        GFP_KERNEL);
3126         if (!regs)
3127                 return -ENOMEM;
3128
3129         for (i = 0; i < variant->num_registers; i++) {
3130                 const struct vc4_hdmi_register *field = &variant->registers[i];
3131
3132                 if (field->reg != reg)
3133                         continue;
3134
3135                 regs[count].name = field->name;
3136                 regs[count].offset = field->offset;
3137                 count++;
3138         }
3139
3140         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3141         if (!new_regs)
3142                 return -ENOMEM;
3143
3144         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3145         regset->regs = new_regs;
3146         regset->nregs = count;
3147
3148         ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3149         if (ret)
3150                 return ret;
3151
3152         return 0;
3153 }
3154
3155 static int vc4_hdmi_init_resources(struct drm_device *drm,
3156                                    struct vc4_hdmi *vc4_hdmi)
3157 {
3158         struct platform_device *pdev = vc4_hdmi->pdev;
3159         struct device *dev = &pdev->dev;
3160         int ret;
3161
3162         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3163         if (IS_ERR(vc4_hdmi->hdmicore_regs))
3164                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3165
3166         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3167         if (IS_ERR(vc4_hdmi->hd_regs))
3168                 return PTR_ERR(vc4_hdmi->hd_regs);
3169
3170         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3171         if (ret)
3172                 return ret;
3173
3174         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3175         if (ret)
3176                 return ret;
3177
3178         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3179         if (IS_ERR(vc4_hdmi->pixel_clock)) {
3180                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3181                 if (ret != -EPROBE_DEFER)
3182                         DRM_ERROR("Failed to get pixel clock\n");
3183                 return ret;
3184         }
3185
3186         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3187         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3188                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3189                 return PTR_ERR(vc4_hdmi->hsm_clock);
3190         }
3191
3192         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3193         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3194
3195         vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi");
3196         if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) {
3197                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3198                 return PTR_ERR(vc4_hdmi->hsm_rpm_clock);
3199         }
3200
3201         return 0;
3202 }
3203
3204 static int vc5_hdmi_init_resources(struct drm_device *drm,
3205                                    struct vc4_hdmi *vc4_hdmi)
3206 {
3207         struct platform_device *pdev = vc4_hdmi->pdev;
3208         struct device *dev = &pdev->dev;
3209         struct resource *res;
3210         int ret;
3211
3212         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3213         if (!res)
3214                 return -ENODEV;
3215
3216         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3217                                                resource_size(res));
3218         if (!vc4_hdmi->hdmicore_regs)
3219                 return -ENOMEM;
3220
3221         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3222         if (!res)
3223                 return -ENODEV;
3224
3225         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3226         if (!vc4_hdmi->hd_regs)
3227                 return -ENOMEM;
3228
3229         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3230         if (!res)
3231                 return -ENODEV;
3232
3233         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3234         if (!vc4_hdmi->cec_regs)
3235                 return -ENOMEM;
3236
3237         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3238         if (!res)
3239                 return -ENODEV;
3240
3241         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3242         if (!vc4_hdmi->csc_regs)
3243                 return -ENOMEM;
3244
3245         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3246         if (!res)
3247                 return -ENODEV;
3248
3249         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3250         if (!vc4_hdmi->dvp_regs)
3251                 return -ENOMEM;
3252
3253         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3254         if (!res)
3255                 return -ENODEV;
3256
3257         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3258         if (!vc4_hdmi->phy_regs)
3259                 return -ENOMEM;
3260
3261         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3262         if (!res)
3263                 return -ENODEV;
3264
3265         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3266         if (!vc4_hdmi->ram_regs)
3267                 return -ENOMEM;
3268
3269         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3270         if (!res)
3271                 return -ENODEV;
3272
3273         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3274         if (!vc4_hdmi->rm_regs)
3275                 return -ENOMEM;
3276
3277         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3278         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3279                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3280                 return PTR_ERR(vc4_hdmi->hsm_clock);
3281         }
3282
3283         vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi");
3284         if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) {
3285                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3286                 return PTR_ERR(vc4_hdmi->hsm_rpm_clock);
3287         }
3288
3289         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3290         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3291                 DRM_ERROR("Failed to get pixel bvb clock\n");
3292                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3293         }
3294
3295         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3296         if (IS_ERR(vc4_hdmi->audio_clock)) {
3297                 DRM_ERROR("Failed to get audio clock\n");
3298                 return PTR_ERR(vc4_hdmi->audio_clock);
3299         }
3300
3301         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3302         if (IS_ERR(vc4_hdmi->cec_clock)) {
3303                 DRM_ERROR("Failed to get CEC clock\n");
3304                 return PTR_ERR(vc4_hdmi->cec_clock);
3305         }
3306
3307         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3308         if (IS_ERR(vc4_hdmi->reset)) {
3309                 DRM_ERROR("Failed to get HDMI reset line\n");
3310                 return PTR_ERR(vc4_hdmi->reset);
3311         }
3312
3313         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3314         if (ret)
3315                 return ret;
3316
3317         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3318         if (ret)
3319                 return ret;
3320
3321         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3322         if (ret)
3323                 return ret;
3324
3325         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3326         if (ret)
3327                 return ret;
3328
3329         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3330         if (ret)
3331                 return ret;
3332
3333         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3334         if (ret)
3335                 return ret;
3336
3337         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3338         if (ret)
3339                 return ret;
3340
3341         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3342         if (ret)
3343                 return ret;
3344
3345         return 0;
3346 }
3347
3348 static int vc4_hdmi_runtime_suspend(struct device *dev)
3349 {
3350         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3351
3352         clk_disable_unprepare(vc4_hdmi->hsm_rpm_clock);
3353
3354         return 0;
3355 }
3356
3357 static int vc4_hdmi_runtime_resume(struct device *dev)
3358 {
3359         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3360         unsigned long __maybe_unused flags;
3361         u32 __maybe_unused value;
3362         unsigned long rate;
3363         int ret;
3364
3365         /*
3366          * The HSM clock is in the HDMI power domain, so we need to set
3367          * its frequency while the power domain is active so that it
3368          * keeps its rate.
3369          */
3370         ret = clk_set_min_rate(vc4_hdmi->hsm_rpm_clock, HSM_MIN_CLOCK_FREQ);
3371         if (ret)
3372                 return ret;
3373
3374         ret = clk_prepare_enable(vc4_hdmi->hsm_rpm_clock);
3375         if (ret)
3376                 return ret;
3377
3378         /*
3379          * Whenever the RaspberryPi boots without an HDMI monitor
3380          * plugged in, the firmware won't have initialized the HSM clock
3381          * rate and it will be reported as 0.
3382          *
3383          * If we try to access a register of the controller in such a
3384          * case, it will lead to a silent CPU stall. Let's make sure we
3385          * prevent such a case.
3386          */
3387         rate = clk_get_rate(vc4_hdmi->hsm_rpm_clock);
3388         if (!rate) {
3389                 ret = -EINVAL;
3390                 goto err_disable_clk;
3391         }
3392
3393         if (vc4_hdmi->variant->reset)
3394                 vc4_hdmi->variant->reset(vc4_hdmi);
3395
3396 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3397         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3398         value = HDMI_READ(HDMI_CEC_CNTRL_1);
3399         /* Set the logical address to Unregistered */
3400         value |= VC4_HDMI_CEC_ADDR_MASK;
3401         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3402         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3403
3404         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3405
3406         if (!vc4_hdmi->variant->external_irq_controller) {
3407                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3408                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3409                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3410         }
3411 #endif
3412
3413         return 0;
3414
3415 err_disable_clk:
3416         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3417         return ret;
3418 }
3419
3420 static void vc4_hdmi_put_ddc_device(void *ptr)
3421 {
3422         struct vc4_hdmi *vc4_hdmi = ptr;
3423
3424         put_device(&vc4_hdmi->ddc->dev);
3425 }
3426
3427 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3428 {
3429         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3430         struct platform_device *pdev = to_platform_device(dev);
3431         struct drm_device *drm = dev_get_drvdata(master);
3432         struct vc4_hdmi *vc4_hdmi;
3433         struct drm_encoder *encoder;
3434         struct device_node *ddc_node;
3435         int ret;
3436
3437         vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3438         if (!vc4_hdmi)
3439                 return -ENOMEM;
3440
3441         ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3442         if (ret)
3443                 return ret;
3444
3445         spin_lock_init(&vc4_hdmi->hw_lock);
3446         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3447
3448         dev_set_drvdata(dev, vc4_hdmi);
3449         encoder = &vc4_hdmi->encoder.base;
3450         vc4_hdmi->encoder.type = variant->encoder_type;
3451         vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3452         vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3453         vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3454         vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3455         vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3456         vc4_hdmi->pdev = pdev;
3457         vc4_hdmi->variant = variant;
3458
3459         /*
3460          * Since we don't know the state of the controller and its
3461          * display (if any), let's assume it's always enabled.
3462          * vc4_hdmi_disable_scrambling() will thus run at boot, make
3463          * sure it's disabled, and avoid any inconsistency.
3464          */
3465         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3466                 vc4_hdmi->scdc_enabled = true;
3467
3468         ret = variant->init_resources(drm, vc4_hdmi);
3469         if (ret)
3470                 return ret;
3471
3472         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3473         if (!ddc_node) {
3474                 DRM_ERROR("Failed to find ddc node in device tree\n");
3475                 return -ENODEV;
3476         }
3477
3478         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3479         of_node_put(ddc_node);
3480         if (!vc4_hdmi->ddc) {
3481                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3482                 return -EPROBE_DEFER;
3483         }
3484
3485         ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3486         if (ret)
3487                 return ret;
3488
3489         /* Only use the GPIO HPD pin if present in the DT, otherwise
3490          * we'll use the HDMI core's register.
3491          */
3492         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3493         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3494                 return PTR_ERR(vc4_hdmi->hpd_gpio);
3495         }
3496
3497         vc4_hdmi->disable_wifi_frequencies =
3498                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3499
3500         ret = devm_pm_runtime_enable(dev);
3501         if (ret)
3502                 return ret;
3503
3504         /*
3505          *  We need to have the device powered up at this point to call
3506          *  our reset hook and for the CEC init.
3507          */
3508         ret = pm_runtime_resume_and_get(dev);
3509         if (ret)
3510                 return ret;
3511
3512         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3513              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3514             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3515                 clk_prepare_enable(vc4_hdmi->pixel_clock);
3516                 clk_prepare_enable(vc4_hdmi->hsm_clock);
3517                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3518         }
3519
3520         ret = drmm_encoder_init(drm, encoder,
3521                                 &vc4_hdmi_encoder_funcs,
3522                                 DRM_MODE_ENCODER_TMDS,
3523                                 NULL);
3524         if (ret)
3525                 goto err_put_runtime_pm;
3526
3527         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3528
3529         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3530         if (ret)
3531                 goto err_put_runtime_pm;
3532
3533         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3534         if (ret)
3535                 goto err_put_runtime_pm;
3536
3537         ret = vc4_hdmi_cec_init(vc4_hdmi);
3538         if (ret)
3539                 goto err_put_runtime_pm;
3540
3541         ret = vc4_hdmi_audio_init(vc4_hdmi);
3542         if (ret)
3543                 goto err_put_runtime_pm;
3544
3545         pm_runtime_put_sync(dev);
3546
3547         return 0;
3548
3549 err_put_runtime_pm:
3550         pm_runtime_put_sync(dev);
3551
3552         return ret;
3553 }
3554
3555 static const struct component_ops vc4_hdmi_ops = {
3556         .bind   = vc4_hdmi_bind,
3557 };
3558
3559 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3560 {
3561         return component_add(&pdev->dev, &vc4_hdmi_ops);
3562 }
3563
3564 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3565 {
3566         component_del(&pdev->dev, &vc4_hdmi_ops);
3567         return 0;
3568 }
3569
3570 static const struct vc4_hdmi_variant bcm2835_variant = {
3571         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3572         .debugfs_name           = "hdmi_regs",
3573         .card_name              = "vc4-hdmi",
3574         .max_pixel_clock        = 162000000,
3575         .registers              = vc4_hdmi_fields,
3576         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
3577
3578         .init_resources         = vc4_hdmi_init_resources,
3579         .csc_setup              = vc4_hdmi_csc_setup,
3580         .reset                  = vc4_hdmi_reset,
3581         .set_timings            = vc4_hdmi_set_timings,
3582         .phy_init               = vc4_hdmi_phy_init,
3583         .phy_disable            = vc4_hdmi_phy_disable,
3584         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
3585         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
3586         .channel_map            = vc4_hdmi_channel_map,
3587         .supports_hdr           = false,
3588 };
3589
3590 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3591         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3592         .debugfs_name           = "hdmi0_regs",
3593         .card_name              = "vc4-hdmi-0",
3594         .max_pixel_clock        = 600000000,
3595         .registers              = vc5_hdmi_hdmi0_fields,
3596         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3597         .phy_lane_mapping       = {
3598                 PHY_LANE_0,
3599                 PHY_LANE_1,
3600                 PHY_LANE_2,
3601                 PHY_LANE_CK,
3602         },
3603         .unsupported_odd_h_timings      = true,
3604         .external_irq_controller        = true,
3605
3606         .init_resources         = vc5_hdmi_init_resources,
3607         .csc_setup              = vc5_hdmi_csc_setup,
3608         .reset                  = vc5_hdmi_reset,
3609         .set_timings            = vc5_hdmi_set_timings,
3610         .phy_init               = vc5_hdmi_phy_init,
3611         .phy_disable            = vc5_hdmi_phy_disable,
3612         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3613         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3614         .channel_map            = vc5_hdmi_channel_map,
3615         .supports_hdr           = true,
3616         .hp_detect              = vc5_hdmi_hp_detect,
3617 };
3618
3619 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3620         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3621         .debugfs_name           = "hdmi1_regs",
3622         .card_name              = "vc4-hdmi-1",
3623         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
3624         .registers              = vc5_hdmi_hdmi1_fields,
3625         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3626         .phy_lane_mapping       = {
3627                 PHY_LANE_1,
3628                 PHY_LANE_0,
3629                 PHY_LANE_CK,
3630                 PHY_LANE_2,
3631         },
3632         .unsupported_odd_h_timings      = true,
3633         .external_irq_controller        = true,
3634
3635         .init_resources         = vc5_hdmi_init_resources,
3636         .csc_setup              = vc5_hdmi_csc_setup,
3637         .reset                  = vc5_hdmi_reset,
3638         .set_timings            = vc5_hdmi_set_timings,
3639         .phy_init               = vc5_hdmi_phy_init,
3640         .phy_disable            = vc5_hdmi_phy_disable,
3641         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3642         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3643         .channel_map            = vc5_hdmi_channel_map,
3644         .supports_hdr           = true,
3645         .hp_detect              = vc5_hdmi_hp_detect,
3646 };
3647
3648 static const struct of_device_id vc4_hdmi_dt_match[] = {
3649         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3650         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3651         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3652         {}
3653 };
3654
3655 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3656         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3657                            vc4_hdmi_runtime_resume,
3658                            NULL)
3659 };
3660
3661 struct platform_driver vc4_hdmi_driver = {
3662         .probe = vc4_hdmi_dev_probe,
3663         .remove = vc4_hdmi_dev_remove,
3664         .driver = {
3665                 .name = "vc4_hdmi",
3666                 .of_match_table = vc4_hdmi_dt_match,
3667                 .pm = &vc4_hdmi_pm_ops,
3668         },
3669 };