drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/i2c.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/rational.h>
  47 #include <linux/reset.h>
  48 #include <sound/dmaengine_pcm.h>
  49 #include <sound/hdmi-codec.h>
  50 #include <sound/pcm_drm_eld.h>
  51 #include <sound/pcm_params.h>
  52 #include <sound/soc.h>
  53 #include "media/cec.h"
  54 #include "vc4_drv.h"
  55 #include "vc4_hdmi.h"
  56 #include "vc4_hdmi_regs.h"
  57 #include "vc4_regs.h"
  58
  59 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  60 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  61 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  62 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  63 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  64 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  65
  66 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  67 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  68 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  69 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  70
  71 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  72 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  73 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  74 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  75 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  76 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  77
  78 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  79 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  80
  81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  82
  83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  85
  86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  88
  89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  90
  91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  93
  94 # define VC4_HD_M_SW_RST                        BIT(2)
  95 # define VC4_HD_M_ENABLE                        BIT(0)
  96
  97 #define HSM_MIN_CLOCK_FREQ      120000000
  98 #define CEC_CLOCK_FREQ 40000
  99
 100 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 101
 102 static unsigned long long
 103 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
 104                                     unsigned int bpc);
 105
 106 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
 107                                            unsigned int bpc)
 108 {
 109         unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc);
 110
 111         return clock > HDMI_14_MAX_TMDS_CLK;
 112 }
 113
 114 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
 115                                        const struct drm_display_mode *mode)
 116 {
 117         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 118
 119         return !vc4_encoder->hdmi_monitor ||
 120                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 121 }
 122
 123 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 124 {
 125         struct drm_info_node *node = (struct drm_info_node *)m->private;
 126         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 127         struct drm_printer p = drm_seq_file_printer(m);
 128
 129         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 130         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 131
 132         return 0;
 133 }
 134
 135 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 136 {
 137         unsigned long flags;
 138
 139         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 140
 141         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 142         udelay(1);
 143         HDMI_WRITE(HDMI_M_CTL, 0);
 144
 145         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 146
 147         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 148                    VC4_HDMI_SW_RESET_HDMI |
 149                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 150
 151         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 152
 153         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 154 }
 155
 156 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 157 {
 158         unsigned long flags;
 159
 160         reset_control_reset(vc4_hdmi->reset);
 161
 162         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 163
 164         HDMI_WRITE(HDMI_DVP_CTL, 0);
 165
 166         HDMI_WRITE(HDMI_CLOCK_STOP,
 167                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 168
 169         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 170 }
 171
 172 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 173 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 174 {
 175         unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 176         unsigned long flags;
 177         u16 clk_cnt;
 178         u32 value;
 179
 180         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 181
 182         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 183         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 184
 185         /*
 186          * Set the clock divider: the hsm_clock rate and this divider
 187          * setting will give a 40 kHz CEC clock.
 188          */
 189         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 190         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 191         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 192
 193         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 194 }
 195 #else
 196 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 197 #endif
 198
 199 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 200
 201 static enum drm_connector_status
 202 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 203 {
 204         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 205         bool connected = false;
 206
 207         mutex_lock(&vc4_hdmi->mutex);
 208
 209         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 210
 211         if (vc4_hdmi->hpd_gpio) {
 212                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 213                         connected = true;
 214         } else {
 215                 unsigned long flags;
 216                 u32 hotplug;
 217
 218                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 219                 hotplug = HDMI_READ(HDMI_HOTPLUG);
 220                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 221
 222                 if (hotplug & VC4_HDMI_HOTPLUG_CONNECTED)
 223                         connected = true;
 224         }
 225
 226         if (connected) {
 227                 if (connector->status != connector_status_connected) {
 228                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 229
 230                         if (edid) {
 231                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 232                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 233                                 kfree(edid);
 234                         }
 235                 }
 236
 237                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
 238                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 239                 mutex_unlock(&vc4_hdmi->mutex);
 240                 return connector_status_connected;
 241         }
 242
 243         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 244         pm_runtime_put(&vc4_hdmi->pdev->dev);
 245         mutex_unlock(&vc4_hdmi->mutex);
 246         return connector_status_disconnected;
 247 }
 248
 249 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 250 {
 251         drm_connector_unregister(connector);
 252         drm_connector_cleanup(connector);
 253 }
 254
 255 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 256 {
 257         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 258         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 259         int ret = 0;
 260         struct edid *edid;
 261
 262         mutex_lock(&vc4_hdmi->mutex);
 263
 264         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 265         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 266         if (!edid) {
 267                 ret = -ENODEV;
 268                 goto out;
 269         }
 270
 271         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 272
 273         drm_connector_update_edid_property(connector, edid);
 274         ret = drm_add_edid_modes(connector, edid);
 275         kfree(edid);
 276
 277         if (vc4_hdmi->disable_4kp60) {
 278                 struct drm_device *drm = connector->dev;
 279                 struct drm_display_mode *mode;
 280
 281                 list_for_each_entry(mode, &connector->probed_modes, head) {
 282                         if (vc4_hdmi_mode_needs_scrambling(mode, 8)) {
 283                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 284                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 285                         }
 286                 }
 287         }
 288
 289 out:
 290         mutex_unlock(&vc4_hdmi->mutex);
 291
 292         return ret;
 293 }
 294
 295 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 296                                            struct drm_atomic_state *state)
 297 {
 298         struct drm_connector_state *old_state =
 299                 drm_atomic_get_old_connector_state(state, connector);
 300         struct drm_connector_state *new_state =
 301                 drm_atomic_get_new_connector_state(state, connector);
 302         struct drm_crtc *crtc = new_state->crtc;
 303
 304         if (!crtc)
 305                 return 0;
 306
 307         if (old_state->colorspace != new_state->colorspace ||
 308             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 309                 struct drm_crtc_state *crtc_state;
 310
 311                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 312                 if (IS_ERR(crtc_state))
 313                         return PTR_ERR(crtc_state);
 314
 315                 crtc_state->mode_changed = true;
 316         }
 317
 318         return 0;
 319 }
 320
 321 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 322 {
 323         struct vc4_hdmi_connector_state *old_state =
 324                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 325         struct vc4_hdmi_connector_state *new_state =
 326                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 327
 328         if (connector->state)
 329                 __drm_atomic_helper_connector_destroy_state(connector->state);
 330
 331         kfree(old_state);
 332         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 333
 334         if (!new_state)
 335                 return;
 336
 337         new_state->base.max_bpc = 8;
 338         new_state->base.max_requested_bpc = 8;
 339         drm_atomic_helper_connector_tv_reset(connector);
 340 }
 341
 342 static struct drm_connector_state *
 343 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 344 {
 345         struct drm_connector_state *conn_state = connector->state;
 346         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 347         struct vc4_hdmi_connector_state *new_state;
 348
 349         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 350         if (!new_state)
 351                 return NULL;
 352
 353         new_state->tmds_char_rate = vc4_state->tmds_char_rate;
 354         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 355
 356         return &new_state->base;
 357 }
 358
 359 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 360         .detect = vc4_hdmi_connector_detect,
 361         .fill_modes = drm_helper_probe_single_connector_modes,
 362         .destroy = vc4_hdmi_connector_destroy,
 363         .reset = vc4_hdmi_connector_reset,
 364         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 365         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 366 };
 367
 368 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 369         .get_modes = vc4_hdmi_connector_get_modes,
 370         .atomic_check = vc4_hdmi_connector_atomic_check,
 371 };
 372
 373 static int vc4_hdmi_connector_init(struct drm_device *dev,
 374                                    struct vc4_hdmi *vc4_hdmi)
 375 {
 376         struct drm_connector *connector = &vc4_hdmi->connector;
 377         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 378         int ret;
 379
 380         drm_connector_init_with_ddc(dev, connector,
 381                                     &vc4_hdmi_connector_funcs,
 382                                     DRM_MODE_CONNECTOR_HDMIA,
 383                                     vc4_hdmi->ddc);
 384         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 385
 386         /*
 387          * Some of the properties below require access to state, like bpc.
 388          * Allocate some default initial connector state with our reset helper.
 389          */
 390         if (connector->funcs->reset)
 391                 connector->funcs->reset(connector);
 392
 393         /* Create and attach TV margin props to this connector. */
 394         ret = drm_mode_create_tv_margin_properties(dev);
 395         if (ret)
 396                 return ret;
 397
 398         ret = drm_mode_create_hdmi_colorspace_property(connector);
 399         if (ret)
 400                 return ret;
 401
 402         drm_connector_attach_colorspace_property(connector);
 403         drm_connector_attach_tv_margin_properties(connector);
 404         drm_connector_attach_max_bpc_property(connector, 8, 12);
 405
 406         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 407                              DRM_CONNECTOR_POLL_DISCONNECT);
 408
 409         connector->interlace_allowed = 1;
 410         connector->doublescan_allowed = 0;
 411
 412         if (vc4_hdmi->variant->supports_hdr)
 413                 drm_connector_attach_hdr_output_metadata_property(connector);
 414
 415         drm_connector_attach_encoder(connector, encoder);
 416
 417         return 0;
 418 }
 419
 420 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 421                                 enum hdmi_infoframe_type type,
 422                                 bool poll)
 423 {
 424         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 425         u32 packet_id = type - 0x80;
 426         unsigned long flags;
 427
 428         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 429         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 430                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 431         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 432
 433         if (!poll)
 434                 return 0;
 435
 436         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 437                           BIT(packet_id)), 100);
 438 }
 439
 440 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 441                                      union hdmi_infoframe *frame)
 442 {
 443         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 444         u32 packet_id = frame->any.type - 0x80;
 445         const struct vc4_hdmi_register *ram_packet_start =
 446                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 447         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 448         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 449                                                        ram_packet_start->reg);
 450         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 451         unsigned long flags;
 452         ssize_t len, i;
 453         int ret;
 454
 455         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 456                     VC4_HDMI_RAM_PACKET_ENABLE),
 457                   "Packet RAM has to be on to store the packet.");
 458
 459         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 460         if (len < 0)
 461                 return;
 462
 463         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 464         if (ret) {
 465                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 466                 return;
 467         }
 468
 469         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 470
 471         for (i = 0; i < len; i += 7) {
 472                 writel(buffer[i + 0] << 0 |
 473                        buffer[i + 1] << 8 |
 474                        buffer[i + 2] << 16,
 475                        base + packet_reg);
 476                 packet_reg += 4;
 477
 478                 writel(buffer[i + 3] << 0 |
 479                        buffer[i + 4] << 8 |
 480                        buffer[i + 5] << 16 |
 481                        buffer[i + 6] << 24,
 482                        base + packet_reg);
 483                 packet_reg += 4;
 484         }
 485
 486         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 487                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 488
 489         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 490
 491         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 492                         BIT(packet_id)), 100);
 493         if (ret)
 494                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 495 }
 496
 497 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 498 {
 499         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 500         struct drm_connector *connector = &vc4_hdmi->connector;
 501         struct drm_connector_state *cstate = connector->state;
 502         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 503         union hdmi_infoframe frame;
 504         int ret;
 505
 506         lockdep_assert_held(&vc4_hdmi->mutex);
 507
 508         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 509                                                        connector, mode);
 510         if (ret < 0) {
 511                 DRM_ERROR("couldn't fill AVI infoframe\n");
 512                 return;
 513         }
 514
 515         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 516                                            connector, mode,
 517                                            vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
 518                                            HDMI_QUANTIZATION_RANGE_FULL :
 519                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 520         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 521         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 522
 523         vc4_hdmi_write_infoframe(encoder, &frame);
 524 }
 525
 526 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 527 {
 528         union hdmi_infoframe frame;
 529         int ret;
 530
 531         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 532         if (ret < 0) {
 533                 DRM_ERROR("couldn't fill SPD infoframe\n");
 534                 return;
 535         }
 536
 537         frame.spd.sdi = HDMI_SPD_SDI_PC;
 538
 539         vc4_hdmi_write_infoframe(encoder, &frame);
 540 }
 541
 542 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 543 {
 544         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 545         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 546         union hdmi_infoframe frame;
 547
 548         memcpy(&frame.audio, audio, sizeof(*audio));
 549         vc4_hdmi_write_infoframe(encoder, &frame);
 550 }
 551
 552 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 553 {
 554         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 555         struct drm_connector *connector = &vc4_hdmi->connector;
 556         struct drm_connector_state *conn_state = connector->state;
 557         union hdmi_infoframe frame;
 558
 559         lockdep_assert_held(&vc4_hdmi->mutex);
 560
 561         if (!vc4_hdmi->variant->supports_hdr)
 562                 return;
 563
 564         if (!conn_state->hdr_output_metadata)
 565                 return;
 566
 567         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 568                 return;
 569
 570         vc4_hdmi_write_infoframe(encoder, &frame);
 571 }
 572
 573 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 574 {
 575         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 576
 577         lockdep_assert_held(&vc4_hdmi->mutex);
 578
 579         vc4_hdmi_set_avi_infoframe(encoder);
 580         vc4_hdmi_set_spd_infoframe(encoder);
 581         /*
 582          * If audio was streaming, then we need to reenabled the audio
 583          * infoframe here during encoder_enable.
 584          */
 585         if (vc4_hdmi->audio.streaming)
 586                 vc4_hdmi_set_audio_infoframe(encoder);
 587
 588         vc4_hdmi_set_hdr_infoframe(encoder);
 589 }
 590
 591 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 592                                          struct drm_display_mode *mode)
 593 {
 594         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 595         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 596         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 597
 598         lockdep_assert_held(&vc4_hdmi->mutex);
 599
 600         if (!vc4_encoder->hdmi_monitor)
 601                 return false;
 602
 603         if (!display->hdmi.scdc.supported ||
 604             !display->hdmi.scdc.scrambling.supported)
 605                 return false;
 606
 607         return true;
 608 }
 609
 610 #define SCRAMBLING_POLLING_DELAY_MS     1000
 611
 612 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 613 {
 614         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 615         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 616         unsigned long flags;
 617
 618         lockdep_assert_held(&vc4_hdmi->mutex);
 619
 620         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 621                 return;
 622
 623         if (!vc4_hdmi_mode_needs_scrambling(mode, vc4_hdmi->output_bpc))
 624                 return;
 625
 626         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 627         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 628
 629         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 630         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 631                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 632         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 633
 634         vc4_hdmi->scdc_enabled = true;
 635
 636         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 637                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 638 }
 639
 640 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 641 {
 642         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 643         unsigned long flags;
 644
 645         lockdep_assert_held(&vc4_hdmi->mutex);
 646
 647         if (!vc4_hdmi->scdc_enabled)
 648                 return;
 649
 650         vc4_hdmi->scdc_enabled = false;
 651
 652         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 653                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 654
 655         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 656         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 657                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 658         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 659
 660         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 661         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 662 }
 663
 664 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 665 {
 666         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 667                                                  struct vc4_hdmi,
 668                                                  scrambling_work);
 669
 670         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 671                 return;
 672
 673         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 674         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 675
 676         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 677                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 678 }
 679
 680 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 681                                                struct drm_atomic_state *state)
 682 {
 683         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 684         unsigned long flags;
 685
 686         mutex_lock(&vc4_hdmi->mutex);
 687
 688         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 689
 690         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 691
 692         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 693
 694         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 695
 696         mdelay(1);
 697
 698         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 699         HDMI_WRITE(HDMI_VID_CTL,
 700                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 701         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 702
 703         vc4_hdmi_disable_scrambling(encoder);
 704
 705         mutex_unlock(&vc4_hdmi->mutex);
 706 }
 707
 708 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 709                                                  struct drm_atomic_state *state)
 710 {
 711         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 712         unsigned long flags;
 713         int ret;
 714
 715         mutex_lock(&vc4_hdmi->mutex);
 716
 717         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 718         HDMI_WRITE(HDMI_VID_CTL,
 719                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 720         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 721
 722         if (vc4_hdmi->variant->phy_disable)
 723                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 724
 725         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 726         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 727
 728         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 729         if (ret < 0)
 730                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 731
 732         mutex_unlock(&vc4_hdmi->mutex);
 733 }
 734
 735 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 736 {
 737         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 738
 739         mutex_lock(&vc4_hdmi->mutex);
 740         vc4_hdmi->output_enabled = false;
 741         mutex_unlock(&vc4_hdmi->mutex);
 742 }
 743
 744 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 745                                struct drm_connector_state *state,
 746                                const struct drm_display_mode *mode)
 747 {
 748         unsigned long flags;
 749         u32 csc_ctl;
 750
 751         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 752
 753         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 754                                 VC4_HD_CSC_CTL_ORDER);
 755
 756         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
 757                 /* CEA VICs other than #1 requre limited range RGB
 758                  * output unless overridden by an AVI infoframe.
 759                  * Apply a colorspace conversion to squash 0-255 down
 760                  * to 16-235.  The matrix here is:
 761                  *
 762                  * [ 0      0      0.8594 16]
 763                  * [ 0      0.8594 0      16]
 764                  * [ 0.8594 0      0      16]
 765                  * [ 0      0      0       1]
 766                  */
 767                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 768                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 769                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 770                                          VC4_HD_CSC_CTL_MODE);
 771
 772                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 773                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 774                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 775                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 776                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 777                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 778         }
 779
 780         /* The RGB order applies even when CSC is disabled. */
 781         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 782
 783         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 784 }
 785
 786 /*
 787  * If we need to output Full Range RGB, then use the unity matrix
 788  *
 789  * [ 1      0      0      0]
 790  * [ 0      1      0      0]
 791  * [ 0      0      1      0]
 792  *
 793  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 794  */
 795 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
 796         { 0x2000, 0x0000, 0x0000, 0x0000 },
 797         { 0x0000, 0x2000, 0x0000, 0x0000 },
 798         { 0x0000, 0x0000, 0x2000, 0x0000 },
 799 };
 800
 801 /*
 802  * CEA VICs other than #1 require limited range RGB output unless
 803  * overridden by an AVI infoframe. Apply a colorspace conversion to
 804  * squash 0-255 down to 16-235. The matrix here is:
 805  *
 806  * [ 0.8594 0      0      16]
 807  * [ 0      0.8594 0      16]
 808  * [ 0      0      0.8594 16]
 809  *
 810  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 811  */
 812 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
 813         { 0x1b80, 0x0000, 0x0000, 0x0400 },
 814         { 0x0000, 0x1b80, 0x0000, 0x0400 },
 815         { 0x0000, 0x0000, 0x1b80, 0x0400 },
 816 };
 817
 818 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
 819                                     const u16 coeffs[3][4])
 820 {
 821         lockdep_assert_held(&vc4_hdmi->hw_lock);
 822
 823         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
 824         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
 825         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
 826         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
 827         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
 828         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
 829 }
 830
 831 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 832                                struct drm_connector_state *state,
 833                                const struct drm_display_mode *mode)
 834 {
 835         unsigned long flags;
 836         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 837                                                                VC5_MT_CP_CSC_CTL_MODE);
 838
 839         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 840
 841         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 842
 843         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
 844                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
 845         else
 846                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
 847
 848         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 849
 850         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 851 }
 852
 853 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 854                                  struct drm_connector_state *state,
 855                                  struct drm_display_mode *mode)
 856 {
 857         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 858         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 859         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 860         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 861         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 862                                    VC4_HDMI_VERTA_VSP) |
 863                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 864                                    VC4_HDMI_VERTA_VFP) |
 865                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 866         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 867                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 868                                    VC4_HDMI_VERTB_VBP));
 869         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 870                           VC4_SET_FIELD(mode->crtc_vtotal -
 871                                         mode->crtc_vsync_end -
 872                                         interlaced,
 873                                         VC4_HDMI_VERTB_VBP));
 874         unsigned long flags;
 875
 876         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 877
 878         HDMI_WRITE(HDMI_HORZA,
 879                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 880                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 881                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 882                                  VC4_HDMI_HORZA_HAP));
 883
 884         HDMI_WRITE(HDMI_HORZB,
 885                    VC4_SET_FIELD((mode->htotal -
 886                                   mode->hsync_end) * pixel_rep,
 887                                  VC4_HDMI_HORZB_HBP) |
 888                    VC4_SET_FIELD((mode->hsync_end -
 889                                   mode->hsync_start) * pixel_rep,
 890                                  VC4_HDMI_HORZB_HSP) |
 891                    VC4_SET_FIELD((mode->hsync_start -
 892                                   mode->hdisplay) * pixel_rep,
 893                                  VC4_HDMI_HORZB_HFP));
 894
 895         HDMI_WRITE(HDMI_VERTA0, verta);
 896         HDMI_WRITE(HDMI_VERTA1, verta);
 897
 898         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 899         HDMI_WRITE(HDMI_VERTB1, vertb);
 900
 901         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 902 }
 903
 904 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 905                                  struct drm_connector_state *state,
 906                                  struct drm_display_mode *mode)
 907 {
 908         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 909         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 910         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 911         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 912         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 913                                    VC5_HDMI_VERTA_VSP) |
 914                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 915                                    VC5_HDMI_VERTA_VFP) |
 916                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 917         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 918                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 919                                    VC4_HDMI_VERTB_VBP));
 920         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 921                           VC4_SET_FIELD(mode->crtc_vtotal -
 922                                         mode->crtc_vsync_end -
 923                                         interlaced,
 924                                         VC4_HDMI_VERTB_VBP));
 925         unsigned long flags;
 926         unsigned char gcp;
 927         bool gcp_en;
 928         u32 reg;
 929
 930         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 931
 932         HDMI_WRITE(HDMI_HORZA,
 933                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 934                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 935                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 936                                  VC5_HDMI_HORZA_HAP) |
 937                    VC4_SET_FIELD((mode->hsync_start -
 938                                   mode->hdisplay) * pixel_rep,
 939                                  VC5_HDMI_HORZA_HFP));
 940
 941         HDMI_WRITE(HDMI_HORZB,
 942                    VC4_SET_FIELD((mode->htotal -
 943                                   mode->hsync_end) * pixel_rep,
 944                                  VC5_HDMI_HORZB_HBP) |
 945                    VC4_SET_FIELD((mode->hsync_end -
 946                                   mode->hsync_start) * pixel_rep,
 947                                  VC5_HDMI_HORZB_HSP));
 948
 949         HDMI_WRITE(HDMI_VERTA0, verta);
 950         HDMI_WRITE(HDMI_VERTA1, verta);
 951
 952         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 953         HDMI_WRITE(HDMI_VERTB1, vertb);
 954
 955         switch (state->max_bpc) {
 956         case 12:
 957                 gcp = 6;
 958                 gcp_en = true;
 959                 break;
 960         case 10:
 961                 gcp = 5;
 962                 gcp_en = true;
 963                 break;
 964         case 8:
 965         default:
 966                 gcp = 4;
 967                 gcp_en = false;
 968                 break;
 969         }
 970
 971         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 972         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 973                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 974         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 975                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 976         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 977
 978         reg = HDMI_READ(HDMI_GCP_WORD_1);
 979         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 980         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 981         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 982
 983         reg = HDMI_READ(HDMI_GCP_CONFIG);
 984         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 985         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 986         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 987
 988         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 989
 990         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 991 }
 992
 993 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 994 {
 995         unsigned long flags;
 996         u32 drift;
 997         int ret;
 998
 999         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1000
1001         drift = HDMI_READ(HDMI_FIFO_CTL);
1002         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1003
1004         HDMI_WRITE(HDMI_FIFO_CTL,
1005                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1006         HDMI_WRITE(HDMI_FIFO_CTL,
1007                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1008
1009         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1010
1011         usleep_range(1000, 1100);
1012
1013         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1014
1015         HDMI_WRITE(HDMI_FIFO_CTL,
1016                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1017         HDMI_WRITE(HDMI_FIFO_CTL,
1018                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1019
1020         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1021
1022         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1023                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1024         WARN_ONCE(ret, "Timeout waiting for "
1025                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1026 }
1027
1028 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1029                                                 struct drm_atomic_state *state)
1030 {
1031         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1032         struct drm_connector *connector = &vc4_hdmi->connector;
1033         struct drm_connector_state *conn_state =
1034                 drm_atomic_get_new_connector_state(state, connector);
1035         struct vc4_hdmi_connector_state *vc4_conn_state =
1036                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1037         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1038         unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1039         unsigned long bvb_rate, hsm_rate;
1040         unsigned long flags;
1041         int ret;
1042
1043         mutex_lock(&vc4_hdmi->mutex);
1044
1045         /*
1046          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1047          * be faster than pixel clock, infinitesimally faster, tested in
1048          * simulation. Otherwise, exact value is unimportant for HDMI
1049          * operation." This conflicts with bcm2835's vc4 documentation, which
1050          * states HSM's clock has to be at least 108% of the pixel clock.
1051          *
1052          * Real life tests reveal that vc4's firmware statement holds up, and
1053          * users are able to use pixel clocks closer to HSM's, namely for
1054          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1055          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1056          * 162MHz.
1057          *
1058          * Additionally, the AXI clock needs to be at least 25% of
1059          * pixel clock, but HSM ends up being the limiting factor.
1060          */
1061         hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101);
1062         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1063         if (ret) {
1064                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1065                 goto out;
1066         }
1067
1068         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1069         if (ret < 0) {
1070                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1071                 goto out;
1072         }
1073
1074         ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1075         if (ret) {
1076                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1077                 goto err_put_runtime_pm;
1078         }
1079
1080         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1081         if (ret) {
1082                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1083                 goto err_put_runtime_pm;
1084         }
1085
1086
1087         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1088
1089         if (tmds_char_rate > 297000000)
1090                 bvb_rate = 300000000;
1091         else if (tmds_char_rate > 148500000)
1092                 bvb_rate = 150000000;
1093         else
1094                 bvb_rate = 75000000;
1095
1096         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1097         if (ret) {
1098                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1099                 goto err_disable_pixel_clock;
1100         }
1101
1102         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1103         if (ret) {
1104                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1105                 goto err_disable_pixel_clock;
1106         }
1107
1108         if (vc4_hdmi->variant->phy_init)
1109                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1110
1111         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1112
1113         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1114                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1115                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1116                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1117
1118         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1119
1120         if (vc4_hdmi->variant->set_timings)
1121                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1122
1123         mutex_unlock(&vc4_hdmi->mutex);
1124
1125         return;
1126
1127 err_disable_pixel_clock:
1128         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1129 err_put_runtime_pm:
1130         pm_runtime_put(&vc4_hdmi->pdev->dev);
1131 out:
1132         mutex_unlock(&vc4_hdmi->mutex);
1133         return;
1134 }
1135
1136 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1137                                              struct drm_atomic_state *state)
1138 {
1139         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1140         struct drm_connector *connector = &vc4_hdmi->connector;
1141         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1142         struct drm_connector_state *conn_state =
1143                 drm_atomic_get_new_connector_state(state, connector);
1144         unsigned long flags;
1145
1146         mutex_lock(&vc4_hdmi->mutex);
1147
1148         if (vc4_hdmi->variant->csc_setup)
1149                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1150
1151         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1152         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1153         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1154
1155         mutex_unlock(&vc4_hdmi->mutex);
1156 }
1157
1158 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1159                                               struct drm_atomic_state *state)
1160 {
1161         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1162         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1163         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1164         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1165         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1166         unsigned long flags;
1167         int ret;
1168
1169         mutex_lock(&vc4_hdmi->mutex);
1170
1171         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1172
1173         HDMI_WRITE(HDMI_VID_CTL,
1174                    VC4_HD_VID_CTL_ENABLE |
1175                    VC4_HD_VID_CTL_CLRRGB |
1176                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1177                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1178                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1179                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1180
1181         HDMI_WRITE(HDMI_VID_CTL,
1182                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1183
1184         if (vc4_encoder->hdmi_monitor) {
1185                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1186                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1187                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1188
1189                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1190
1191                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1192                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1193                 WARN_ONCE(ret, "Timeout waiting for "
1194                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1195         } else {
1196                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1197                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1198                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1199                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1200                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1201                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1202
1203                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1204
1205                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1206                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1207                 WARN_ONCE(ret, "Timeout waiting for "
1208                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1209         }
1210
1211         if (vc4_encoder->hdmi_monitor) {
1212                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1213
1214                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1215                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1216                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1217                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1218                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1219
1220                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1221                            VC4_HDMI_RAM_PACKET_ENABLE);
1222
1223                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1224
1225                 vc4_hdmi_set_infoframes(encoder);
1226         }
1227
1228         vc4_hdmi_recenter_fifo(vc4_hdmi);
1229         vc4_hdmi_enable_scrambling(encoder);
1230
1231         mutex_unlock(&vc4_hdmi->mutex);
1232 }
1233
1234 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1235 {
1236         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1237
1238         mutex_lock(&vc4_hdmi->mutex);
1239         vc4_hdmi->output_enabled = true;
1240         mutex_unlock(&vc4_hdmi->mutex);
1241 }
1242
1243 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1244                                              struct drm_crtc_state *crtc_state,
1245                                              struct drm_connector_state *conn_state)
1246 {
1247         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1248
1249         mutex_lock(&vc4_hdmi->mutex);
1250         drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1251                       &crtc_state->adjusted_mode);
1252         vc4_hdmi->output_bpc = conn_state->max_bpc;
1253         mutex_unlock(&vc4_hdmi->mutex);
1254 }
1255
1256 static enum drm_mode_status
1257 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1258                              unsigned long long clock)
1259 {
1260         const struct drm_connector *connector = &vc4_hdmi->connector;
1261         const struct drm_display_info *info = &connector->display_info;
1262
1263         if (clock > vc4_hdmi->variant->max_pixel_clock)
1264                 return MODE_CLOCK_HIGH;
1265
1266         if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK)
1267                 return MODE_CLOCK_HIGH;
1268
1269         if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1270                 return MODE_CLOCK_HIGH;
1271
1272         return MODE_OK;
1273 }
1274
1275 static unsigned long long
1276 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1277                                     unsigned int bpc)
1278 {
1279         unsigned long long clock = mode->clock * 1000;
1280
1281         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1282                 clock = clock * 2;
1283
1284         clock = clock * bpc;
1285         do_div(clock, 8);
1286
1287         return clock;
1288 }
1289
1290 static int
1291 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1292                                struct vc4_hdmi_connector_state *vc4_state,
1293                                const struct drm_display_mode *mode,
1294                                unsigned int bpc)
1295 {
1296         unsigned long long clock;
1297
1298         clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc);
1299         if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
1300                 return -EINVAL;
1301
1302         vc4_state->tmds_char_rate = clock;
1303
1304         return 0;
1305 }
1306
1307 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1308 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1309
1310 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1311                                          struct drm_crtc_state *crtc_state,
1312                                          struct drm_connector_state *conn_state)
1313 {
1314         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1315         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1316         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1317         unsigned long long tmds_char_rate = mode->clock * 1000;
1318         unsigned long long tmds_bit_rate;
1319         int ret;
1320
1321         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1322             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1323              (mode->hsync_end % 2) || (mode->htotal % 2)))
1324                 return -EINVAL;
1325
1326         /*
1327          * The 1440p@60 pixel rate is in the same range than the first
1328          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1329          * bandwidth). Slightly lower the frequency to bring it out of
1330          * the WiFi range.
1331          */
1332         tmds_bit_rate = tmds_char_rate * 10;
1333         if (vc4_hdmi->disable_wifi_frequencies &&
1334             (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1335              tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1336                 mode->clock = 238560;
1337                 tmds_char_rate = mode->clock * 1000;
1338         }
1339
1340         ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, mode,
1341                                              conn_state->max_bpc);
1342         if (ret)
1343                 return ret;
1344
1345         return 0;
1346 }
1347
1348 static enum drm_mode_status
1349 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1350                             const struct drm_display_mode *mode)
1351 {
1352         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1353
1354         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1355             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1356              (mode->hsync_end % 2) || (mode->htotal % 2)))
1357                 return MODE_H_ILLEGAL;
1358
1359         return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000);
1360 }
1361
1362 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1363         .atomic_check = vc4_hdmi_encoder_atomic_check,
1364         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1365         .mode_valid = vc4_hdmi_encoder_mode_valid,
1366         .disable = vc4_hdmi_encoder_disable,
1367         .enable = vc4_hdmi_encoder_enable,
1368 };
1369
1370 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1371 {
1372         int i;
1373         u32 channel_map = 0;
1374
1375         for (i = 0; i < 8; i++) {
1376                 if (channel_mask & BIT(i))
1377                         channel_map |= i << (3 * i);
1378         }
1379         return channel_map;
1380 }
1381
1382 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1383 {
1384         int i;
1385         u32 channel_map = 0;
1386
1387         for (i = 0; i < 8; i++) {
1388                 if (channel_mask & BIT(i))
1389                         channel_map |= i << (4 * i);
1390         }
1391         return channel_map;
1392 }
1393
1394 /* HDMI audio codec callbacks */
1395 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1396                                          unsigned int samplerate)
1397 {
1398         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1399         unsigned long flags;
1400         unsigned long n, m;
1401
1402         rational_best_approximation(hsm_clock, samplerate,
1403                                     VC4_HD_MAI_SMP_N_MASK >>
1404                                     VC4_HD_MAI_SMP_N_SHIFT,
1405                                     (VC4_HD_MAI_SMP_M_MASK >>
1406                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1407                                     &n, &m);
1408
1409         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1410         HDMI_WRITE(HDMI_MAI_SMP,
1411                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1412                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1413         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1414 }
1415
1416 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1417 {
1418         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1419         u32 n, cts;
1420         u64 tmp;
1421
1422         lockdep_assert_held(&vc4_hdmi->mutex);
1423         lockdep_assert_held(&vc4_hdmi->hw_lock);
1424
1425         n = 128 * samplerate / 1000;
1426         tmp = (u64)(mode->clock * 1000) * n;
1427         do_div(tmp, 128 * samplerate);
1428         cts = tmp;
1429
1430         HDMI_WRITE(HDMI_CRP_CFG,
1431                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1432                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1433
1434         /*
1435          * We could get slightly more accurate clocks in some cases by
1436          * providing a CTS_1 value.  The two CTS values are alternated
1437          * between based on the period fields
1438          */
1439         HDMI_WRITE(HDMI_CTS_0, cts);
1440         HDMI_WRITE(HDMI_CTS_1, cts);
1441 }
1442
1443 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1444 {
1445         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1446
1447         return snd_soc_card_get_drvdata(card);
1448 }
1449
1450 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1451 {
1452         lockdep_assert_held(&vc4_hdmi->mutex);
1453
1454         /*
1455          * If the controller is disabled, prevent any ALSA output.
1456          */
1457         if (!vc4_hdmi->output_enabled)
1458                 return false;
1459
1460         /*
1461          * If the encoder is currently in DVI mode, treat the codec DAI
1462          * as missing.
1463          */
1464         if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE))
1465                 return false;
1466
1467         return true;
1468 }
1469
1470 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1471 {
1472         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1473         unsigned long flags;
1474
1475         mutex_lock(&vc4_hdmi->mutex);
1476
1477         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1478                 mutex_unlock(&vc4_hdmi->mutex);
1479                 return -ENODEV;
1480         }
1481
1482         vc4_hdmi->audio.streaming = true;
1483
1484         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1485         HDMI_WRITE(HDMI_MAI_CTL,
1486                    VC4_HD_MAI_CTL_RESET |
1487                    VC4_HD_MAI_CTL_FLUSH |
1488                    VC4_HD_MAI_CTL_DLATE |
1489                    VC4_HD_MAI_CTL_ERRORE |
1490                    VC4_HD_MAI_CTL_ERRORF);
1491         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1492
1493         if (vc4_hdmi->variant->phy_rng_enable)
1494                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1495
1496         mutex_unlock(&vc4_hdmi->mutex);
1497
1498         return 0;
1499 }
1500
1501 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1502 {
1503         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1504         struct device *dev = &vc4_hdmi->pdev->dev;
1505         unsigned long flags;
1506         int ret;
1507
1508         lockdep_assert_held(&vc4_hdmi->mutex);
1509
1510         vc4_hdmi->audio.streaming = false;
1511         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1512         if (ret)
1513                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1514
1515         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1516
1517         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1518         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1519         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1520
1521         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1522 }
1523
1524 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1525 {
1526         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1527         unsigned long flags;
1528
1529         mutex_lock(&vc4_hdmi->mutex);
1530
1531         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1532
1533         HDMI_WRITE(HDMI_MAI_CTL,
1534                    VC4_HD_MAI_CTL_DLATE |
1535                    VC4_HD_MAI_CTL_ERRORE |
1536                    VC4_HD_MAI_CTL_ERRORF);
1537
1538         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1539
1540         if (vc4_hdmi->variant->phy_rng_disable)
1541                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1542
1543         vc4_hdmi->audio.streaming = false;
1544         vc4_hdmi_audio_reset(vc4_hdmi);
1545
1546         mutex_unlock(&vc4_hdmi->mutex);
1547 }
1548
1549 static int sample_rate_to_mai_fmt(int samplerate)
1550 {
1551         switch (samplerate) {
1552         case 8000:
1553                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1554         case 11025:
1555                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1556         case 12000:
1557                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1558         case 16000:
1559                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1560         case 22050:
1561                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1562         case 24000:
1563                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1564         case 32000:
1565                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1566         case 44100:
1567                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1568         case 48000:
1569                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1570         case 64000:
1571                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1572         case 88200:
1573                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1574         case 96000:
1575                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1576         case 128000:
1577                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1578         case 176400:
1579                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1580         case 192000:
1581                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1582         default:
1583                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1584         }
1585 }
1586
1587 /* HDMI audio codec callbacks */
1588 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1589                                   struct hdmi_codec_daifmt *daifmt,
1590                                   struct hdmi_codec_params *params)
1591 {
1592         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1593         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1594         unsigned int sample_rate = params->sample_rate;
1595         unsigned int channels = params->channels;
1596         unsigned long flags;
1597         u32 audio_packet_config, channel_mask;
1598         u32 channel_map;
1599         u32 mai_audio_format;
1600         u32 mai_sample_rate;
1601
1602         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1603                 sample_rate, params->sample_width, channels);
1604
1605         mutex_lock(&vc4_hdmi->mutex);
1606
1607         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1608                 mutex_unlock(&vc4_hdmi->mutex);
1609                 return -EINVAL;
1610         }
1611
1612         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1613
1614         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1615         HDMI_WRITE(HDMI_MAI_CTL,
1616                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1617                    VC4_HD_MAI_CTL_WHOLSMP |
1618                    VC4_HD_MAI_CTL_CHALIGN |
1619                    VC4_HD_MAI_CTL_ENABLE);
1620
1621         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1622         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1623             params->channels == 8)
1624                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1625         else
1626                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1627         HDMI_WRITE(HDMI_MAI_FMT,
1628                    VC4_SET_FIELD(mai_sample_rate,
1629                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1630                    VC4_SET_FIELD(mai_audio_format,
1631                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1632
1633         /* The B frame identifier should match the value used by alsa-lib (8) */
1634         audio_packet_config =
1635                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1636                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1637                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1638
1639         channel_mask = GENMASK(channels - 1, 0);
1640         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1641                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1642
1643         /* Set the MAI threshold */
1644         HDMI_WRITE(HDMI_MAI_THR,
1645                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1646                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1647                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1648                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1649
1650         HDMI_WRITE(HDMI_MAI_CONFIG,
1651                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1652                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1653                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1654
1655         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1656         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1657         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1658
1659         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1660
1661         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1662
1663         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1664         vc4_hdmi_set_audio_infoframe(encoder);
1665
1666         mutex_unlock(&vc4_hdmi->mutex);
1667
1668         return 0;
1669 }
1670
1671 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1672         .name = "vc4-hdmi-cpu-dai-component",
1673 };
1674
1675 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1676 {
1677         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1678
1679         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1680
1681         return 0;
1682 }
1683
1684 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1685         .name = "vc4-hdmi-cpu-dai",
1686         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1687         .playback = {
1688                 .stream_name = "Playback",
1689                 .channels_min = 1,
1690                 .channels_max = 8,
1691                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1692                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1693                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1694                          SNDRV_PCM_RATE_192000,
1695                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1696         },
1697 };
1698
1699 static const struct snd_dmaengine_pcm_config pcm_conf = {
1700         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1701         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1702 };
1703
1704 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1705                                   uint8_t *buf, size_t len)
1706 {
1707         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1708         struct drm_connector *connector = &vc4_hdmi->connector;
1709
1710         mutex_lock(&vc4_hdmi->mutex);
1711         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1712         mutex_unlock(&vc4_hdmi->mutex);
1713
1714         return 0;
1715 }
1716
1717 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1718         .get_eld = vc4_hdmi_audio_get_eld,
1719         .prepare = vc4_hdmi_audio_prepare,
1720         .audio_shutdown = vc4_hdmi_audio_shutdown,
1721         .audio_startup = vc4_hdmi_audio_startup,
1722 };
1723
1724 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1725         .ops = &vc4_hdmi_codec_ops,
1726         .max_i2s_channels = 8,
1727         .i2s = 1,
1728 };
1729
1730 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1731 {
1732         const struct vc4_hdmi_register *mai_data =
1733                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1734         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1735         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1736         struct device *dev = &vc4_hdmi->pdev->dev;
1737         struct platform_device *codec_pdev;
1738         const __be32 *addr;
1739         int index;
1740         int ret;
1741
1742         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1743                 dev_warn(dev,
1744                          "'dmas' DT property is missing, no HDMI audio\n");
1745                 return 0;
1746         }
1747
1748         if (mai_data->reg != VC4_HD) {
1749                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1750                 return -EINVAL;
1751         }
1752
1753         /*
1754          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1755          * the bus address specified in the DT, because the physical address
1756          * (the one returned by platform_get_resource()) is not appropriate
1757          * for DMA transfers.
1758          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1759          */
1760         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1761         /* Before BCM2711, we don't have a named register range */
1762         if (index < 0)
1763                 index = 1;
1764
1765         addr = of_get_address(dev->of_node, index, NULL, NULL);
1766
1767         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1768         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1769         vc4_hdmi->audio.dma_data.maxburst = 2;
1770
1771         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1772         if (ret) {
1773                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1774                 return ret;
1775         }
1776
1777         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1778                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1779         if (ret) {
1780                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1781                 return ret;
1782         }
1783
1784         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1785                                                    PLATFORM_DEVID_AUTO,
1786                                                    &vc4_hdmi_codec_pdata,
1787                                                    sizeof(vc4_hdmi_codec_pdata));
1788         if (IS_ERR(codec_pdev)) {
1789                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1790                 return PTR_ERR(codec_pdev);
1791         }
1792
1793         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1794         dai_link->codecs        = &vc4_hdmi->audio.codec;
1795         dai_link->platforms     = &vc4_hdmi->audio.platform;
1796
1797         dai_link->num_cpus      = 1;
1798         dai_link->num_codecs    = 1;
1799         dai_link->num_platforms = 1;
1800
1801         dai_link->name = "MAI";
1802         dai_link->stream_name = "MAI PCM";
1803         dai_link->codecs->dai_name = "i2s-hifi";
1804         dai_link->cpus->dai_name = dev_name(dev);
1805         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1806         dai_link->platforms->name = dev_name(dev);
1807
1808         card->dai_link = dai_link;
1809         card->num_links = 1;
1810         card->name = vc4_hdmi->variant->card_name;
1811         card->driver_name = "vc4-hdmi";
1812         card->dev = dev;
1813         card->owner = THIS_MODULE;
1814
1815         /*
1816          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1817          * stores a pointer to the snd card object in dev->driver_data. This
1818          * means we cannot use it for something else. The hdmi back-pointer is
1819          * now stored in card->drvdata and should be retrieved with
1820          * snd_soc_card_get_drvdata() if needed.
1821          */
1822         snd_soc_card_set_drvdata(card, vc4_hdmi);
1823         ret = devm_snd_soc_register_card(dev, card);
1824         if (ret)
1825                 dev_err_probe(dev, ret, "Could not register sound card\n");
1826
1827         return ret;
1828
1829 }
1830
1831 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1832 {
1833         struct vc4_hdmi *vc4_hdmi = priv;
1834         struct drm_connector *connector = &vc4_hdmi->connector;
1835         struct drm_device *dev = connector->dev;
1836
1837         if (dev && dev->registered)
1838                 drm_connector_helper_hpd_irq_event(connector);
1839
1840         return IRQ_HANDLED;
1841 }
1842
1843 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1844 {
1845         struct drm_connector *connector = &vc4_hdmi->connector;
1846         struct platform_device *pdev = vc4_hdmi->pdev;
1847         int ret;
1848
1849         if (vc4_hdmi->variant->external_irq_controller) {
1850                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1851                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1852
1853                 ret = request_threaded_irq(hpd_con,
1854                                            NULL,
1855                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1856                                            "vc4 hdmi hpd connected", vc4_hdmi);
1857                 if (ret)
1858                         return ret;
1859
1860                 ret = request_threaded_irq(hpd_rm,
1861                                            NULL,
1862                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1863                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1864                 if (ret) {
1865                         free_irq(hpd_con, vc4_hdmi);
1866                         return ret;
1867                 }
1868
1869                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1870         }
1871
1872         return 0;
1873 }
1874
1875 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1876 {
1877         struct platform_device *pdev = vc4_hdmi->pdev;
1878
1879         if (vc4_hdmi->variant->external_irq_controller) {
1880                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1881                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1882         }
1883 }
1884
1885 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1886 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1887 {
1888         struct vc4_hdmi *vc4_hdmi = priv;
1889
1890         if (vc4_hdmi->cec_rx_msg.len)
1891                 cec_received_msg(vc4_hdmi->cec_adap,
1892                                  &vc4_hdmi->cec_rx_msg);
1893
1894         return IRQ_HANDLED;
1895 }
1896
1897 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1898 {
1899         struct vc4_hdmi *vc4_hdmi = priv;
1900
1901         if (vc4_hdmi->cec_tx_ok) {
1902                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1903                                   0, 0, 0, 0);
1904         } else {
1905                 /*
1906                  * This CEC implementation makes 1 retry, so if we
1907                  * get a NACK, then that means it made 2 attempts.
1908                  */
1909                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1910                                   0, 2, 0, 0);
1911         }
1912         return IRQ_HANDLED;
1913 }
1914
1915 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1916 {
1917         struct vc4_hdmi *vc4_hdmi = priv;
1918         irqreturn_t ret;
1919
1920         if (vc4_hdmi->cec_irq_was_rx)
1921                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1922         else
1923                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1924
1925         return ret;
1926 }
1927
1928 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1929 {
1930         struct drm_device *dev = vc4_hdmi->connector.dev;
1931         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1932         unsigned int i;
1933
1934         lockdep_assert_held(&vc4_hdmi->hw_lock);
1935
1936         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1937                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1938
1939         if (msg->len > 16) {
1940                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1941                 return;
1942         }
1943
1944         for (i = 0; i < msg->len; i += 4) {
1945                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1946
1947                 msg->msg[i] = val & 0xff;
1948                 msg->msg[i + 1] = (val >> 8) & 0xff;
1949                 msg->msg[i + 2] = (val >> 16) & 0xff;
1950                 msg->msg[i + 3] = (val >> 24) & 0xff;
1951         }
1952 }
1953
1954 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1955 {
1956         u32 cntrl1;
1957
1958         lockdep_assert_held(&vc4_hdmi->hw_lock);
1959
1960         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1961         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1962         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1963         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1964
1965         return IRQ_WAKE_THREAD;
1966 }
1967
1968 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1969 {
1970         struct vc4_hdmi *vc4_hdmi = priv;
1971         irqreturn_t ret;
1972
1973         spin_lock(&vc4_hdmi->hw_lock);
1974         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1975         spin_unlock(&vc4_hdmi->hw_lock);
1976
1977         return ret;
1978 }
1979
1980 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1981 {
1982         u32 cntrl1;
1983
1984         lockdep_assert_held(&vc4_hdmi->hw_lock);
1985
1986         vc4_hdmi->cec_rx_msg.len = 0;
1987         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1988         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1989         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1990         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1991         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1992
1993         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1994
1995         return IRQ_WAKE_THREAD;
1996 }
1997
1998 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1999 {
2000         struct vc4_hdmi *vc4_hdmi = priv;
2001         irqreturn_t ret;
2002
2003         spin_lock(&vc4_hdmi->hw_lock);
2004         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2005         spin_unlock(&vc4_hdmi->hw_lock);
2006
2007         return ret;
2008 }
2009
2010 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2011 {
2012         struct vc4_hdmi *vc4_hdmi = priv;
2013         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2014         irqreturn_t ret;
2015         u32 cntrl5;
2016
2017         if (!(stat & VC4_HDMI_CPU_CEC))
2018                 return IRQ_NONE;
2019
2020         spin_lock(&vc4_hdmi->hw_lock);
2021         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2022         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2023         if (vc4_hdmi->cec_irq_was_rx)
2024                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2025         else
2026                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2027
2028         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2029         spin_unlock(&vc4_hdmi->hw_lock);
2030
2031         return ret;
2032 }
2033
2034 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2035 {
2036         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2037         /* clock period in microseconds */
2038         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2039         unsigned long flags;
2040         u32 val;
2041         int ret;
2042
2043         /*
2044          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2045          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2046          * .detect or .get_modes might call .adap_enable, which leads to this
2047          * function being called with that mutex held.
2048          *
2049          * Concurrency is not an issue for the moment since we don't share any
2050          * state with KMS, so we can ignore the lock for now, but we need to
2051          * keep it in mind if we were to change that assumption.
2052          */
2053
2054         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2055         if (ret)
2056                 return ret;
2057
2058         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2059
2060         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2061         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2062                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2063                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2064         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2065                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2066
2067         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2068                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2069         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2070         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2071                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2072                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2073                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2074                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2075                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2076         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2077                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2078                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2079                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2080                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2081         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2082                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2083                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2084                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2085                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2086
2087         if (!vc4_hdmi->variant->external_irq_controller)
2088                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2089
2090         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2091
2092         return 0;
2093 }
2094
2095 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2096 {
2097         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2098         unsigned long flags;
2099
2100         /*
2101          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2102          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2103          * .detect or .get_modes might call .adap_enable, which leads to this
2104          * function being called with that mutex held.
2105          *
2106          * Concurrency is not an issue for the moment since we don't share any
2107          * state with KMS, so we can ignore the lock for now, but we need to
2108          * keep it in mind if we were to change that assumption.
2109          */
2110
2111         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2112
2113         if (!vc4_hdmi->variant->external_irq_controller)
2114                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2115
2116         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2117                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2118
2119         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2120
2121         pm_runtime_put(&vc4_hdmi->pdev->dev);
2122
2123         return 0;
2124 }
2125
2126 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2127 {
2128         if (enable)
2129                 return vc4_hdmi_cec_enable(adap);
2130         else
2131                 return vc4_hdmi_cec_disable(adap);
2132 }
2133
2134 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2135 {
2136         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2137         unsigned long flags;
2138
2139         /*
2140          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2141          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2142          * .detect or .get_modes might call .adap_enable, which leads to this
2143          * function being called with that mutex held.
2144          *
2145          * Concurrency is not an issue for the moment since we don't share any
2146          * state with KMS, so we can ignore the lock for now, but we need to
2147          * keep it in mind if we were to change that assumption.
2148          */
2149
2150         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2151         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2152                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2153                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2154         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2155
2156         return 0;
2157 }
2158
2159 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2160                                       u32 signal_free_time, struct cec_msg *msg)
2161 {
2162         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2163         struct drm_device *dev = vc4_hdmi->connector.dev;
2164         unsigned long flags;
2165         u32 val;
2166         unsigned int i;
2167
2168         /*
2169          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2170          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2171          * .detect or .get_modes might call .adap_enable, which leads to this
2172          * function being called with that mutex held.
2173          *
2174          * Concurrency is not an issue for the moment since we don't share any
2175          * state with KMS, so we can ignore the lock for now, but we need to
2176          * keep it in mind if we were to change that assumption.
2177          */
2178
2179         if (msg->len > 16) {
2180                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2181                 return -ENOMEM;
2182         }
2183
2184         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2185
2186         for (i = 0; i < msg->len; i += 4)
2187                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2188                            (msg->msg[i]) |
2189                            (msg->msg[i + 1] << 8) |
2190                            (msg->msg[i + 2] << 16) |
2191                            (msg->msg[i + 3] << 24));
2192
2193         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2194         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2195         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2196         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2197         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2198         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2199
2200         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2201
2202         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2203
2204         return 0;
2205 }
2206
2207 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2208         .adap_enable = vc4_hdmi_cec_adap_enable,
2209         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2210         .adap_transmit = vc4_hdmi_cec_adap_transmit,
2211 };
2212
2213 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2214 {
2215         struct cec_connector_info conn_info;
2216         struct platform_device *pdev = vc4_hdmi->pdev;
2217         struct device *dev = &pdev->dev;
2218         unsigned long flags;
2219         u32 value;
2220         int ret;
2221
2222         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2223                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2224                 return 0;
2225         }
2226
2227         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2228                                                   vc4_hdmi, "vc4",
2229                                                   CEC_CAP_DEFAULTS |
2230                                                   CEC_CAP_CONNECTOR_INFO, 1);
2231         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2232         if (ret < 0)
2233                 return ret;
2234
2235         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2236         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2237
2238         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2239         value = HDMI_READ(HDMI_CEC_CNTRL_1);
2240         /* Set the logical address to Unregistered */
2241         value |= VC4_HDMI_CEC_ADDR_MASK;
2242         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
2243         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2244
2245         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
2246
2247         if (vc4_hdmi->variant->external_irq_controller) {
2248                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
2249                                            vc4_cec_irq_handler_rx_bare,
2250                                            vc4_cec_irq_handler_rx_thread, 0,
2251                                            "vc4 hdmi cec rx", vc4_hdmi);
2252                 if (ret)
2253                         goto err_delete_cec_adap;
2254
2255                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
2256                                            vc4_cec_irq_handler_tx_bare,
2257                                            vc4_cec_irq_handler_tx_thread, 0,
2258                                            "vc4 hdmi cec tx", vc4_hdmi);
2259                 if (ret)
2260                         goto err_remove_cec_rx_handler;
2261         } else {
2262                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2263                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2264                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2265
2266                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
2267                                            vc4_cec_irq_handler,
2268                                            vc4_cec_irq_handler_thread, 0,
2269                                            "vc4 hdmi cec", vc4_hdmi);
2270                 if (ret)
2271                         goto err_delete_cec_adap;
2272         }
2273
2274         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2275         if (ret < 0)
2276                 goto err_remove_handlers;
2277
2278         return 0;
2279
2280 err_remove_handlers:
2281         if (vc4_hdmi->variant->external_irq_controller)
2282                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2283         else
2284                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2285
2286 err_remove_cec_rx_handler:
2287         if (vc4_hdmi->variant->external_irq_controller)
2288                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2289
2290 err_delete_cec_adap:
2291         cec_delete_adapter(vc4_hdmi->cec_adap);
2292
2293         return ret;
2294 }
2295
2296 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
2297 {
2298         struct platform_device *pdev = vc4_hdmi->pdev;
2299
2300         if (vc4_hdmi->variant->external_irq_controller) {
2301                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2302                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2303         } else {
2304                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2305         }
2306
2307         cec_unregister_adapter(vc4_hdmi->cec_adap);
2308 }
2309 #else
2310 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2311 {
2312         return 0;
2313 }
2314
2315 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
2316
2317 #endif
2318
2319 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
2320                                  struct debugfs_regset32 *regset,
2321                                  enum vc4_hdmi_regs reg)
2322 {
2323         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2324         struct debugfs_reg32 *regs, *new_regs;
2325         unsigned int count = 0;
2326         unsigned int i;
2327
2328         regs = kcalloc(variant->num_registers, sizeof(*regs),
2329                        GFP_KERNEL);
2330         if (!regs)
2331                 return -ENOMEM;
2332
2333         for (i = 0; i < variant->num_registers; i++) {
2334                 const struct vc4_hdmi_register *field = &variant->registers[i];
2335
2336                 if (field->reg != reg)
2337                         continue;
2338
2339                 regs[count].name = field->name;
2340                 regs[count].offset = field->offset;
2341                 count++;
2342         }
2343
2344         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2345         if (!new_regs)
2346                 return -ENOMEM;
2347
2348         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2349         regset->regs = new_regs;
2350         regset->nregs = count;
2351
2352         return 0;
2353 }
2354
2355 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2356 {
2357         struct platform_device *pdev = vc4_hdmi->pdev;
2358         struct device *dev = &pdev->dev;
2359         int ret;
2360
2361         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2362         if (IS_ERR(vc4_hdmi->hdmicore_regs))
2363                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2364
2365         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2366         if (IS_ERR(vc4_hdmi->hd_regs))
2367                 return PTR_ERR(vc4_hdmi->hd_regs);
2368
2369         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2370         if (ret)
2371                 return ret;
2372
2373         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2374         if (ret)
2375                 return ret;
2376
2377         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2378         if (IS_ERR(vc4_hdmi->pixel_clock)) {
2379                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2380                 if (ret != -EPROBE_DEFER)
2381                         DRM_ERROR("Failed to get pixel clock\n");
2382                 return ret;
2383         }
2384
2385         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2386         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2387                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2388                 return PTR_ERR(vc4_hdmi->hsm_clock);
2389         }
2390         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2391         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2392
2393         return 0;
2394 }
2395
2396 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2397 {
2398         struct platform_device *pdev = vc4_hdmi->pdev;
2399         struct device *dev = &pdev->dev;
2400         struct resource *res;
2401
2402         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2403         if (!res)
2404                 return -ENODEV;
2405
2406         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2407                                                resource_size(res));
2408         if (!vc4_hdmi->hdmicore_regs)
2409                 return -ENOMEM;
2410
2411         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2412         if (!res)
2413                 return -ENODEV;
2414
2415         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2416         if (!vc4_hdmi->hd_regs)
2417                 return -ENOMEM;
2418
2419         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2420         if (!res)
2421                 return -ENODEV;
2422
2423         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2424         if (!vc4_hdmi->cec_regs)
2425                 return -ENOMEM;
2426
2427         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2428         if (!res)
2429                 return -ENODEV;
2430
2431         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2432         if (!vc4_hdmi->csc_regs)
2433                 return -ENOMEM;
2434
2435         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2436         if (!res)
2437                 return -ENODEV;
2438
2439         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2440         if (!vc4_hdmi->dvp_regs)
2441                 return -ENOMEM;
2442
2443         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2444         if (!res)
2445                 return -ENODEV;
2446
2447         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2448         if (!vc4_hdmi->phy_regs)
2449                 return -ENOMEM;
2450
2451         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2452         if (!res)
2453                 return -ENODEV;
2454
2455         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2456         if (!vc4_hdmi->ram_regs)
2457                 return -ENOMEM;
2458
2459         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2460         if (!res)
2461                 return -ENODEV;
2462
2463         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2464         if (!vc4_hdmi->rm_regs)
2465                 return -ENOMEM;
2466
2467         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2468         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2469                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2470                 return PTR_ERR(vc4_hdmi->hsm_clock);
2471         }
2472
2473         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2474         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2475                 DRM_ERROR("Failed to get pixel bvb clock\n");
2476                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2477         }
2478
2479         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2480         if (IS_ERR(vc4_hdmi->audio_clock)) {
2481                 DRM_ERROR("Failed to get audio clock\n");
2482                 return PTR_ERR(vc4_hdmi->audio_clock);
2483         }
2484
2485         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2486         if (IS_ERR(vc4_hdmi->cec_clock)) {
2487                 DRM_ERROR("Failed to get CEC clock\n");
2488                 return PTR_ERR(vc4_hdmi->cec_clock);
2489         }
2490
2491         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2492         if (IS_ERR(vc4_hdmi->reset)) {
2493                 DRM_ERROR("Failed to get HDMI reset line\n");
2494                 return PTR_ERR(vc4_hdmi->reset);
2495         }
2496
2497         return 0;
2498 }
2499
2500 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2501 {
2502         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2503
2504         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2505
2506         return 0;
2507 }
2508
2509 static int vc4_hdmi_runtime_resume(struct device *dev)
2510 {
2511         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2512         int ret;
2513
2514         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2515         if (ret)
2516                 return ret;
2517
2518         return 0;
2519 }
2520
2521 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2522 {
2523         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2524         struct platform_device *pdev = to_platform_device(dev);
2525         struct drm_device *drm = dev_get_drvdata(master);
2526         struct vc4_hdmi *vc4_hdmi;
2527         struct drm_encoder *encoder;
2528         struct device_node *ddc_node;
2529         int ret;
2530
2531         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2532         if (!vc4_hdmi)
2533                 return -ENOMEM;
2534         mutex_init(&vc4_hdmi->mutex);
2535         spin_lock_init(&vc4_hdmi->hw_lock);
2536         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2537
2538         dev_set_drvdata(dev, vc4_hdmi);
2539         encoder = &vc4_hdmi->encoder.base.base;
2540         vc4_hdmi->encoder.base.type = variant->encoder_type;
2541         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2542         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2543         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2544         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2545         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2546         vc4_hdmi->pdev = pdev;
2547         vc4_hdmi->variant = variant;
2548
2549         /*
2550          * Since we don't know the state of the controller and its
2551          * display (if any), let's assume it's always enabled.
2552          * vc4_hdmi_disable_scrambling() will thus run at boot, make
2553          * sure it's disabled, and avoid any inconsistency.
2554          */
2555         vc4_hdmi->scdc_enabled = true;
2556
2557         ret = variant->init_resources(vc4_hdmi);
2558         if (ret)
2559                 return ret;
2560
2561         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2562         if (!ddc_node) {
2563                 DRM_ERROR("Failed to find ddc node in device tree\n");
2564                 return -ENODEV;
2565         }
2566
2567         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2568         of_node_put(ddc_node);
2569         if (!vc4_hdmi->ddc) {
2570                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2571                 return -EPROBE_DEFER;
2572         }
2573
2574         /* Only use the GPIO HPD pin if present in the DT, otherwise
2575          * we'll use the HDMI core's register.
2576          */
2577         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2578         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2579                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2580                 goto err_put_ddc;
2581         }
2582
2583         vc4_hdmi->disable_wifi_frequencies =
2584                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2585
2586         if (variant->max_pixel_clock == 600000000) {
2587                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2588                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2589
2590                 if (max_rate < 550000000)
2591                         vc4_hdmi->disable_4kp60 = true;
2592         }
2593
2594         /*
2595          * If we boot without any cable connected to the HDMI connector,
2596          * the firmware will skip the HSM initialization and leave it
2597          * with a rate of 0, resulting in a bus lockup when we're
2598          * accessing the registers even if it's enabled.
2599          *
2600          * Let's put a sensible default at runtime_resume so that we
2601          * don't end up in this situation.
2602          */
2603         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2604         if (ret)
2605                 goto err_put_ddc;
2606
2607         /*
2608          * We need to have the device powered up at this point to call
2609          * our reset hook and for the CEC init.
2610          */
2611         ret = vc4_hdmi_runtime_resume(dev);
2612         if (ret)
2613                 goto err_put_ddc;
2614
2615         pm_runtime_get_noresume(dev);
2616         pm_runtime_set_active(dev);
2617         pm_runtime_enable(dev);
2618
2619         if (vc4_hdmi->variant->reset)
2620                 vc4_hdmi->variant->reset(vc4_hdmi);
2621
2622         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2623              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2624             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2625                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2626                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2627                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2628         }
2629
2630         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2631         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2632
2633         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2634         if (ret)
2635                 goto err_destroy_encoder;
2636
2637         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2638         if (ret)
2639                 goto err_destroy_conn;
2640
2641         ret = vc4_hdmi_cec_init(vc4_hdmi);
2642         if (ret)
2643                 goto err_free_hotplug;
2644
2645         ret = vc4_hdmi_audio_init(vc4_hdmi);
2646         if (ret)
2647                 goto err_free_cec;
2648
2649         vc4_debugfs_add_file(drm, variant->debugfs_name,
2650                              vc4_hdmi_debugfs_regs,
2651                              vc4_hdmi);
2652
2653         pm_runtime_put_sync(dev);
2654
2655         return 0;
2656
2657 err_free_cec:
2658         vc4_hdmi_cec_exit(vc4_hdmi);
2659 err_free_hotplug:
2660         vc4_hdmi_hotplug_exit(vc4_hdmi);
2661 err_destroy_conn:
2662         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2663 err_destroy_encoder:
2664         drm_encoder_cleanup(encoder);
2665         pm_runtime_put_sync(dev);
2666         pm_runtime_disable(dev);
2667 err_put_ddc:
2668         put_device(&vc4_hdmi->ddc->dev);
2669
2670         return ret;
2671 }
2672
2673 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2674                             void *data)
2675 {
2676         struct vc4_hdmi *vc4_hdmi;
2677
2678         /*
2679          * ASoC makes it a bit hard to retrieve a pointer to the
2680          * vc4_hdmi structure. Registering the card will overwrite our
2681          * device drvdata with a pointer to the snd_soc_card structure,
2682          * which can then be used to retrieve whatever drvdata we want
2683          * to associate.
2684          *
2685          * However, that doesn't fly in the case where we wouldn't
2686          * register an ASoC card (because of an old DT that is missing
2687          * the dmas properties for example), then the card isn't
2688          * registered and the device drvdata wouldn't be set.
2689          *
2690          * We can deal with both cases by making sure a snd_soc_card
2691          * pointer and a vc4_hdmi structure are pointing to the same
2692          * memory address, so we can treat them indistinctly without any
2693          * issue.
2694          */
2695         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2696         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2697         vc4_hdmi = dev_get_drvdata(dev);
2698
2699         kfree(vc4_hdmi->hdmi_regset.regs);
2700         kfree(vc4_hdmi->hd_regset.regs);
2701
2702         vc4_hdmi_cec_exit(vc4_hdmi);
2703         vc4_hdmi_hotplug_exit(vc4_hdmi);
2704         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2705         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2706
2707         pm_runtime_disable(dev);
2708
2709         put_device(&vc4_hdmi->ddc->dev);
2710 }
2711
2712 static const struct component_ops vc4_hdmi_ops = {
2713         .bind   = vc4_hdmi_bind,
2714         .unbind = vc4_hdmi_unbind,
2715 };
2716
2717 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2718 {
2719         return component_add(&pdev->dev, &vc4_hdmi_ops);
2720 }
2721
2722 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2723 {
2724         component_del(&pdev->dev, &vc4_hdmi_ops);
2725         return 0;
2726 }
2727
2728 static const struct vc4_hdmi_variant bcm2835_variant = {
2729         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2730         .debugfs_name           = "hdmi_regs",
2731         .card_name              = "vc4-hdmi",
2732         .max_pixel_clock        = 162000000,
2733         .registers              = vc4_hdmi_fields,
2734         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2735
2736         .init_resources         = vc4_hdmi_init_resources,
2737         .csc_setup              = vc4_hdmi_csc_setup,
2738         .reset                  = vc4_hdmi_reset,
2739         .set_timings            = vc4_hdmi_set_timings,
2740         .phy_init               = vc4_hdmi_phy_init,
2741         .phy_disable            = vc4_hdmi_phy_disable,
2742         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2743         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2744         .channel_map            = vc4_hdmi_channel_map,
2745         .supports_hdr           = false,
2746 };
2747
2748 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2749         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2750         .debugfs_name           = "hdmi0_regs",
2751         .card_name              = "vc4-hdmi-0",
2752         .max_pixel_clock        = 600000000,
2753         .registers              = vc5_hdmi_hdmi0_fields,
2754         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2755         .phy_lane_mapping       = {
2756                 PHY_LANE_0,
2757                 PHY_LANE_1,
2758                 PHY_LANE_2,
2759                 PHY_LANE_CK,
2760         },
2761         .unsupported_odd_h_timings      = true,
2762         .external_irq_controller        = true,
2763
2764         .init_resources         = vc5_hdmi_init_resources,
2765         .csc_setup              = vc5_hdmi_csc_setup,
2766         .reset                  = vc5_hdmi_reset,
2767         .set_timings            = vc5_hdmi_set_timings,
2768         .phy_init               = vc5_hdmi_phy_init,
2769         .phy_disable            = vc5_hdmi_phy_disable,
2770         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2771         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2772         .channel_map            = vc5_hdmi_channel_map,
2773         .supports_hdr           = true,
2774 };
2775
2776 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2777         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2778         .debugfs_name           = "hdmi1_regs",
2779         .card_name              = "vc4-hdmi-1",
2780         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2781         .registers              = vc5_hdmi_hdmi1_fields,
2782         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2783         .phy_lane_mapping       = {
2784                 PHY_LANE_1,
2785                 PHY_LANE_0,
2786                 PHY_LANE_CK,
2787                 PHY_LANE_2,
2788         },
2789         .unsupported_odd_h_timings      = true,
2790         .external_irq_controller        = true,
2791
2792         .init_resources         = vc5_hdmi_init_resources,
2793         .csc_setup              = vc5_hdmi_csc_setup,
2794         .reset                  = vc5_hdmi_reset,
2795         .set_timings            = vc5_hdmi_set_timings,
2796         .phy_init               = vc5_hdmi_phy_init,
2797         .phy_disable            = vc5_hdmi_phy_disable,
2798         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2799         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2800         .channel_map            = vc5_hdmi_channel_map,
2801         .supports_hdr           = true,
2802 };
2803
2804 static const struct of_device_id vc4_hdmi_dt_match[] = {
2805         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2806         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2807         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2808         {}
2809 };
2810
2811 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2812         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2813                            vc4_hdmi_runtime_resume,
2814                            NULL)
2815 };
2816
2817 struct platform_driver vc4_hdmi_driver = {
2818         .probe = vc4_hdmi_dev_probe,
2819         .remove = vc4_hdmi_dev_remove,
2820         .driver = {
2821                 .name = "vc4_hdmi",
2822                 .of_match_table = vc4_hdmi_dt_match,
2823                 .pm = &vc4_hdmi_pm_ops,
2824         },
2825 };