drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/gpio/consumer.h>
  42 #include <linux/i2c.h>
  43 #include <linux/of_address.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/of_platform.h>
  46 #include <linux/pm_runtime.h>
  47 #include <linux/rational.h>
  48 #include <linux/reset.h>
  49 #include <sound/dmaengine_pcm.h>
  50 #include <sound/hdmi-codec.h>
  51 #include <sound/pcm_drm_eld.h>
  52 #include <sound/pcm_params.h>
  53 #include <sound/soc.h>
  54 #include "media/cec.h"
  55 #include "vc4_drv.h"
  56 #include "vc4_hdmi.h"
  57 #include "vc4_hdmi_regs.h"
  58 #include "vc4_regs.h"
  59
  60 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  61 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  62 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  63 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  64 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  65 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  66
  67 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  68 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  69 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  70 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  71
  72 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  73 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  74 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  75 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  76 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  77 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  78
  79 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  80 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  81
  82 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  83
  84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  85 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  86
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  88 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  89
  90 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  91
  92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  93 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  94
  95 # define VC4_HD_M_SW_RST                        BIT(2)
  96 # define VC4_HD_M_ENABLE                        BIT(0)
  97
  98 #define HSM_MIN_CLOCK_FREQ      120000000
  99 #define CEC_CLOCK_FREQ 40000
 100
 101 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 102
 103 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 104 {
 105         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 106 }
 107
 108 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
 109                                        const struct drm_display_mode *mode)
 110 {
 111         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 112
 113         return !vc4_encoder->hdmi_monitor ||
 114                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 115 }
 116
 117 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 118 {
 119         struct drm_info_node *node = (struct drm_info_node *)m->private;
 120         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 121         struct drm_printer p = drm_seq_file_printer(m);
 122
 123         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 124         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 125
 126         return 0;
 127 }
 128
 129 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 130 {
 131         unsigned long flags;
 132
 133         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 134
 135         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 136         udelay(1);
 137         HDMI_WRITE(HDMI_M_CTL, 0);
 138
 139         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 140
 141         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 142                    VC4_HDMI_SW_RESET_HDMI |
 143                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 144
 145         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 146
 147         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 148 }
 149
 150 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 151 {
 152         unsigned long flags;
 153
 154         reset_control_reset(vc4_hdmi->reset);
 155
 156         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 157
 158         HDMI_WRITE(HDMI_DVP_CTL, 0);
 159
 160         HDMI_WRITE(HDMI_CLOCK_STOP,
 161                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 162
 163         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 164 }
 165
 166 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 167 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 168 {
 169         unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 170         unsigned long flags;
 171         u16 clk_cnt;
 172         u32 value;
 173
 174         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 175
 176         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 177         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 178
 179         /*
 180          * Set the clock divider: the hsm_clock rate and this divider
 181          * setting will give a 40 kHz CEC clock.
 182          */
 183         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 184         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 185         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 186
 187         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 188 }
 189 #else
 190 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 191 #endif
 192
 193 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 194
 195 static enum drm_connector_status
 196 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 197 {
 198         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 199         bool connected = false;
 200
 201         mutex_lock(&vc4_hdmi->mutex);
 202
 203         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 204
 205         if (vc4_hdmi->hpd_gpio) {
 206                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 207                         connected = true;
 208         } else {
 209                 if (vc4_hdmi->variant->hp_detect &&
 210                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 211                         connected = true;
 212         }
 213
 214         if (connected) {
 215                 if (connector->status != connector_status_connected) {
 216                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 217
 218                         if (edid) {
 219                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 220                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 221                                 kfree(edid);
 222                         }
 223                 }
 224
 225                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
 226                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 227                 mutex_unlock(&vc4_hdmi->mutex);
 228                 return connector_status_connected;
 229         }
 230
 231         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 232         pm_runtime_put(&vc4_hdmi->pdev->dev);
 233         mutex_unlock(&vc4_hdmi->mutex);
 234         return connector_status_disconnected;
 235 }
 236
 237 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 238 {
 239         drm_connector_unregister(connector);
 240         drm_connector_cleanup(connector);
 241 }
 242
 243 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 244 {
 245         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 246         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 247         int ret = 0;
 248         struct edid *edid;
 249
 250         mutex_lock(&vc4_hdmi->mutex);
 251
 252         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 253         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 254         if (!edid) {
 255                 ret = -ENODEV;
 256                 goto out;
 257         }
 258
 259         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 260
 261         drm_connector_update_edid_property(connector, edid);
 262         ret = drm_add_edid_modes(connector, edid);
 263         kfree(edid);
 264
 265         if (vc4_hdmi->disable_4kp60) {
 266                 struct drm_device *drm = connector->dev;
 267                 struct drm_display_mode *mode;
 268
 269                 list_for_each_entry(mode, &connector->probed_modes, head) {
 270                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 271                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 272                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 273                         }
 274                 }
 275         }
 276
 277 out:
 278         mutex_unlock(&vc4_hdmi->mutex);
 279
 280         return ret;
 281 }
 282
 283 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 284                                            struct drm_atomic_state *state)
 285 {
 286         struct drm_connector_state *old_state =
 287                 drm_atomic_get_old_connector_state(state, connector);
 288         struct drm_connector_state *new_state =
 289                 drm_atomic_get_new_connector_state(state, connector);
 290         struct drm_crtc *crtc = new_state->crtc;
 291
 292         if (!crtc)
 293                 return 0;
 294
 295         if (old_state->colorspace != new_state->colorspace ||
 296             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 297                 struct drm_crtc_state *crtc_state;
 298
 299                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 300                 if (IS_ERR(crtc_state))
 301                         return PTR_ERR(crtc_state);
 302
 303                 crtc_state->mode_changed = true;
 304         }
 305
 306         return 0;
 307 }
 308
 309 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 310 {
 311         struct vc4_hdmi_connector_state *old_state =
 312                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 313         struct vc4_hdmi_connector_state *new_state =
 314                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 315
 316         if (connector->state)
 317                 __drm_atomic_helper_connector_destroy_state(connector->state);
 318
 319         kfree(old_state);
 320         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 321
 322         if (!new_state)
 323                 return;
 324
 325         new_state->base.max_bpc = 8;
 326         new_state->base.max_requested_bpc = 8;
 327         drm_atomic_helper_connector_tv_reset(connector);
 328 }
 329
 330 static struct drm_connector_state *
 331 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 332 {
 333         struct drm_connector_state *conn_state = connector->state;
 334         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 335         struct vc4_hdmi_connector_state *new_state;
 336
 337         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 338         if (!new_state)
 339                 return NULL;
 340
 341         new_state->pixel_rate = vc4_state->pixel_rate;
 342         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 343
 344         return &new_state->base;
 345 }
 346
 347 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 348         .detect = vc4_hdmi_connector_detect,
 349         .fill_modes = drm_helper_probe_single_connector_modes,
 350         .destroy = vc4_hdmi_connector_destroy,
 351         .reset = vc4_hdmi_connector_reset,
 352         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 353         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 354 };
 355
 356 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 357         .get_modes = vc4_hdmi_connector_get_modes,
 358         .atomic_check = vc4_hdmi_connector_atomic_check,
 359 };
 360
 361 static int vc4_hdmi_connector_init(struct drm_device *dev,
 362                                    struct vc4_hdmi *vc4_hdmi)
 363 {
 364         struct drm_connector *connector = &vc4_hdmi->connector;
 365         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 366         int ret;
 367
 368         drm_connector_init_with_ddc(dev, connector,
 369                                     &vc4_hdmi_connector_funcs,
 370                                     DRM_MODE_CONNECTOR_HDMIA,
 371                                     vc4_hdmi->ddc);
 372         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 373
 374         /*
 375          * Some of the properties below require access to state, like bpc.
 376          * Allocate some default initial connector state with our reset helper.
 377          */
 378         if (connector->funcs->reset)
 379                 connector->funcs->reset(connector);
 380
 381         /* Create and attach TV margin props to this connector. */
 382         ret = drm_mode_create_tv_margin_properties(dev);
 383         if (ret)
 384                 return ret;
 385
 386         ret = drm_mode_create_hdmi_colorspace_property(connector);
 387         if (ret)
 388                 return ret;
 389
 390         drm_connector_attach_colorspace_property(connector);
 391         drm_connector_attach_tv_margin_properties(connector);
 392         drm_connector_attach_max_bpc_property(connector, 8, 12);
 393
 394         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 395                              DRM_CONNECTOR_POLL_DISCONNECT);
 396
 397         connector->interlace_allowed = 1;
 398         connector->doublescan_allowed = 0;
 399
 400         if (vc4_hdmi->variant->supports_hdr)
 401                 drm_connector_attach_hdr_output_metadata_property(connector);
 402
 403         drm_connector_attach_encoder(connector, encoder);
 404
 405         return 0;
 406 }
 407
 408 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 409                                 enum hdmi_infoframe_type type,
 410                                 bool poll)
 411 {
 412         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 413         u32 packet_id = type - 0x80;
 414         unsigned long flags;
 415
 416         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 417         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 418                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 419         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 420
 421         if (!poll)
 422                 return 0;
 423
 424         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 425                           BIT(packet_id)), 100);
 426 }
 427
 428 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 429                                      union hdmi_infoframe *frame)
 430 {
 431         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 432         u32 packet_id = frame->any.type - 0x80;
 433         const struct vc4_hdmi_register *ram_packet_start =
 434                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 435         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 436         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 437                                                        ram_packet_start->reg);
 438         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 439         unsigned long flags;
 440         ssize_t len, i;
 441         int ret;
 442
 443         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 444                     VC4_HDMI_RAM_PACKET_ENABLE),
 445                   "Packet RAM has to be on to store the packet.");
 446
 447         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 448         if (len < 0)
 449                 return;
 450
 451         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 452         if (ret) {
 453                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 454                 return;
 455         }
 456
 457         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 458
 459         for (i = 0; i < len; i += 7) {
 460                 writel(buffer[i + 0] << 0 |
 461                        buffer[i + 1] << 8 |
 462                        buffer[i + 2] << 16,
 463                        base + packet_reg);
 464                 packet_reg += 4;
 465
 466                 writel(buffer[i + 3] << 0 |
 467                        buffer[i + 4] << 8 |
 468                        buffer[i + 5] << 16 |
 469                        buffer[i + 6] << 24,
 470                        base + packet_reg);
 471                 packet_reg += 4;
 472         }
 473
 474         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 475                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 476
 477         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 478
 479         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 480                         BIT(packet_id)), 100);
 481         if (ret)
 482                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 483 }
 484
 485 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 486 {
 487         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 488         struct drm_connector *connector = &vc4_hdmi->connector;
 489         struct drm_connector_state *cstate = connector->state;
 490         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 491         union hdmi_infoframe frame;
 492         int ret;
 493
 494         lockdep_assert_held(&vc4_hdmi->mutex);
 495
 496         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 497                                                        connector, mode);
 498         if (ret < 0) {
 499                 DRM_ERROR("couldn't fill AVI infoframe\n");
 500                 return;
 501         }
 502
 503         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 504                                            connector, mode,
 505                                            vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
 506                                            HDMI_QUANTIZATION_RANGE_FULL :
 507                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 508         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 509         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 510
 511         vc4_hdmi_write_infoframe(encoder, &frame);
 512 }
 513
 514 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 515 {
 516         union hdmi_infoframe frame;
 517         int ret;
 518
 519         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 520         if (ret < 0) {
 521                 DRM_ERROR("couldn't fill SPD infoframe\n");
 522                 return;
 523         }
 524
 525         frame.spd.sdi = HDMI_SPD_SDI_PC;
 526
 527         vc4_hdmi_write_infoframe(encoder, &frame);
 528 }
 529
 530 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 531 {
 532         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 533         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 534         union hdmi_infoframe frame;
 535
 536         memcpy(&frame.audio, audio, sizeof(*audio));
 537         vc4_hdmi_write_infoframe(encoder, &frame);
 538 }
 539
 540 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 541 {
 542         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 543         struct drm_connector *connector = &vc4_hdmi->connector;
 544         struct drm_connector_state *conn_state = connector->state;
 545         union hdmi_infoframe frame;
 546
 547         lockdep_assert_held(&vc4_hdmi->mutex);
 548
 549         if (!vc4_hdmi->variant->supports_hdr)
 550                 return;
 551
 552         if (!conn_state->hdr_output_metadata)
 553                 return;
 554
 555         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 556                 return;
 557
 558         vc4_hdmi_write_infoframe(encoder, &frame);
 559 }
 560
 561 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 562 {
 563         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 564
 565         lockdep_assert_held(&vc4_hdmi->mutex);
 566
 567         vc4_hdmi_set_avi_infoframe(encoder);
 568         vc4_hdmi_set_spd_infoframe(encoder);
 569         /*
 570          * If audio was streaming, then we need to reenabled the audio
 571          * infoframe here during encoder_enable.
 572          */
 573         if (vc4_hdmi->audio.streaming)
 574                 vc4_hdmi_set_audio_infoframe(encoder);
 575
 576         vc4_hdmi_set_hdr_infoframe(encoder);
 577 }
 578
 579 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 580                                          struct drm_display_mode *mode)
 581 {
 582         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 583         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 584         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 585
 586         lockdep_assert_held(&vc4_hdmi->mutex);
 587
 588         if (!vc4_encoder->hdmi_monitor)
 589                 return false;
 590
 591         if (!display->hdmi.scdc.supported ||
 592             !display->hdmi.scdc.scrambling.supported)
 593                 return false;
 594
 595         return true;
 596 }
 597
 598 #define SCRAMBLING_POLLING_DELAY_MS     1000
 599
 600 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 601 {
 602         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 603         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 604         unsigned long flags;
 605
 606         lockdep_assert_held(&vc4_hdmi->mutex);
 607
 608         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 609                 return;
 610
 611         if (!vc4_hdmi_mode_needs_scrambling(mode))
 612                 return;
 613
 614         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 615         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 616
 617         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 618         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 619                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 620         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 621
 622         vc4_hdmi->scdc_enabled = true;
 623
 624         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 625                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 626 }
 627
 628 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 629 {
 630         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 631         unsigned long flags;
 632
 633         lockdep_assert_held(&vc4_hdmi->mutex);
 634
 635         if (!vc4_hdmi->scdc_enabled)
 636                 return;
 637
 638         vc4_hdmi->scdc_enabled = false;
 639
 640         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 641                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 642
 643         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 644         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 645                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 646         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 647
 648         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 649         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 650 }
 651
 652 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 653 {
 654         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 655                                                  struct vc4_hdmi,
 656                                                  scrambling_work);
 657
 658         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 659                 return;
 660
 661         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 662         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 663
 664         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 665                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 666 }
 667
 668 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 669                                                struct drm_atomic_state *state)
 670 {
 671         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 672         unsigned long flags;
 673
 674         mutex_lock(&vc4_hdmi->mutex);
 675
 676         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 677
 678         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 679
 680         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 681
 682         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 683
 684         mdelay(1);
 685
 686         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 687         HDMI_WRITE(HDMI_VID_CTL,
 688                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 689         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 690
 691         vc4_hdmi_disable_scrambling(encoder);
 692
 693         mutex_unlock(&vc4_hdmi->mutex);
 694 }
 695
 696 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 697                                                  struct drm_atomic_state *state)
 698 {
 699         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 700         unsigned long flags;
 701         int ret;
 702
 703         mutex_lock(&vc4_hdmi->mutex);
 704
 705         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 706         HDMI_WRITE(HDMI_VID_CTL,
 707                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 708         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 709
 710         if (vc4_hdmi->variant->phy_disable)
 711                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 712
 713         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 714         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 715
 716         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 717         if (ret < 0)
 718                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 719
 720         mutex_unlock(&vc4_hdmi->mutex);
 721 }
 722
 723 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 724 {
 725         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 726
 727         mutex_lock(&vc4_hdmi->mutex);
 728         vc4_hdmi->output_enabled = false;
 729         mutex_unlock(&vc4_hdmi->mutex);
 730 }
 731
 732 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 733                                struct drm_connector_state *state,
 734                                const struct drm_display_mode *mode)
 735 {
 736         unsigned long flags;
 737         u32 csc_ctl;
 738
 739         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 740
 741         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 742                                 VC4_HD_CSC_CTL_ORDER);
 743
 744         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
 745                 /* CEA VICs other than #1 requre limited range RGB
 746                  * output unless overridden by an AVI infoframe.
 747                  * Apply a colorspace conversion to squash 0-255 down
 748                  * to 16-235.  The matrix here is:
 749                  *
 750                  * [ 0      0      0.8594 16]
 751                  * [ 0      0.8594 0      16]
 752                  * [ 0.8594 0      0      16]
 753                  * [ 0      0      0       1]
 754                  */
 755                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 756                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 757                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 758                                          VC4_HD_CSC_CTL_MODE);
 759
 760                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 761                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 762                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 763                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 764                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 765                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 766         }
 767
 768         /* The RGB order applies even when CSC is disabled. */
 769         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 770
 771         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 772 }
 773
 774 /*
 775  * If we need to output Full Range RGB, then use the unity matrix
 776  *
 777  * [ 1      0      0      0]
 778  * [ 0      1      0      0]
 779  * [ 0      0      1      0]
 780  *
 781  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 782  */
 783 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
 784         { 0x2000, 0x0000, 0x0000, 0x0000 },
 785         { 0x0000, 0x2000, 0x0000, 0x0000 },
 786         { 0x0000, 0x0000, 0x2000, 0x0000 },
 787 };
 788
 789 /*
 790  * CEA VICs other than #1 require limited range RGB output unless
 791  * overridden by an AVI infoframe. Apply a colorspace conversion to
 792  * squash 0-255 down to 16-235. The matrix here is:
 793  *
 794  * [ 0.8594 0      0      16]
 795  * [ 0      0.8594 0      16]
 796  * [ 0      0      0.8594 16]
 797  *
 798  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 799  */
 800 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
 801         { 0x1b80, 0x0000, 0x0000, 0x0400 },
 802         { 0x0000, 0x1b80, 0x0000, 0x0400 },
 803         { 0x0000, 0x0000, 0x1b80, 0x0400 },
 804 };
 805
 806 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
 807                                     const u16 coeffs[3][4])
 808 {
 809         lockdep_assert_held(&vc4_hdmi->hw_lock);
 810
 811         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
 812         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
 813         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
 814         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
 815         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
 816         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
 817 }
 818
 819 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 820                                struct drm_connector_state *state,
 821                                const struct drm_display_mode *mode)
 822 {
 823         unsigned long flags;
 824         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 825                                                                VC5_MT_CP_CSC_CTL_MODE);
 826
 827         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 828
 829         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 830
 831         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
 832                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
 833         else
 834                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
 835
 836         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 837
 838         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 839 }
 840
 841 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 842                                  struct drm_connector_state *state,
 843                                  struct drm_display_mode *mode)
 844 {
 845         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 846         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 847         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 848         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 849         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 850                                    VC4_HDMI_VERTA_VSP) |
 851                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 852                                    VC4_HDMI_VERTA_VFP) |
 853                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 854         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 855                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 856                                    VC4_HDMI_VERTB_VBP));
 857         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 858                           VC4_SET_FIELD(mode->crtc_vtotal -
 859                                         mode->crtc_vsync_end -
 860                                         interlaced,
 861                                         VC4_HDMI_VERTB_VBP));
 862         unsigned long flags;
 863
 864         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 865
 866         HDMI_WRITE(HDMI_HORZA,
 867                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 868                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 869                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 870                                  VC4_HDMI_HORZA_HAP));
 871
 872         HDMI_WRITE(HDMI_HORZB,
 873                    VC4_SET_FIELD((mode->htotal -
 874                                   mode->hsync_end) * pixel_rep,
 875                                  VC4_HDMI_HORZB_HBP) |
 876                    VC4_SET_FIELD((mode->hsync_end -
 877                                   mode->hsync_start) * pixel_rep,
 878                                  VC4_HDMI_HORZB_HSP) |
 879                    VC4_SET_FIELD((mode->hsync_start -
 880                                   mode->hdisplay) * pixel_rep,
 881                                  VC4_HDMI_HORZB_HFP));
 882
 883         HDMI_WRITE(HDMI_VERTA0, verta);
 884         HDMI_WRITE(HDMI_VERTA1, verta);
 885
 886         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 887         HDMI_WRITE(HDMI_VERTB1, vertb);
 888
 889         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 890 }
 891
 892 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 893                                  struct drm_connector_state *state,
 894                                  struct drm_display_mode *mode)
 895 {
 896         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 897         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 898         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 899         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 900         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 901                                    VC5_HDMI_VERTA_VSP) |
 902                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 903                                    VC5_HDMI_VERTA_VFP) |
 904                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 905         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 906                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 907                                    VC4_HDMI_VERTB_VBP));
 908         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 909                           VC4_SET_FIELD(mode->crtc_vtotal -
 910                                         mode->crtc_vsync_end -
 911                                         interlaced,
 912                                         VC4_HDMI_VERTB_VBP));
 913         unsigned long flags;
 914         unsigned char gcp;
 915         bool gcp_en;
 916         u32 reg;
 917
 918         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 919
 920         HDMI_WRITE(HDMI_HORZA,
 921                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 922                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 923                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 924                                  VC5_HDMI_HORZA_HAP) |
 925                    VC4_SET_FIELD((mode->hsync_start -
 926                                   mode->hdisplay) * pixel_rep,
 927                                  VC5_HDMI_HORZA_HFP));
 928
 929         HDMI_WRITE(HDMI_HORZB,
 930                    VC4_SET_FIELD((mode->htotal -
 931                                   mode->hsync_end) * pixel_rep,
 932                                  VC5_HDMI_HORZB_HBP) |
 933                    VC4_SET_FIELD((mode->hsync_end -
 934                                   mode->hsync_start) * pixel_rep,
 935                                  VC5_HDMI_HORZB_HSP));
 936
 937         HDMI_WRITE(HDMI_VERTA0, verta);
 938         HDMI_WRITE(HDMI_VERTA1, verta);
 939
 940         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 941         HDMI_WRITE(HDMI_VERTB1, vertb);
 942
 943         switch (state->max_bpc) {
 944         case 12:
 945                 gcp = 6;
 946                 gcp_en = true;
 947                 break;
 948         case 10:
 949                 gcp = 5;
 950                 gcp_en = true;
 951                 break;
 952         case 8:
 953         default:
 954                 gcp = 4;
 955                 gcp_en = false;
 956                 break;
 957         }
 958
 959         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 960         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 961                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 962         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 963                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 964         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 965
 966         reg = HDMI_READ(HDMI_GCP_WORD_1);
 967         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 968         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 969         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 970
 971         reg = HDMI_READ(HDMI_GCP_CONFIG);
 972         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 973         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 974         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 975
 976         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 977
 978         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 979 }
 980
 981 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 982 {
 983         unsigned long flags;
 984         u32 drift;
 985         int ret;
 986
 987         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 988
 989         drift = HDMI_READ(HDMI_FIFO_CTL);
 990         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 991
 992         HDMI_WRITE(HDMI_FIFO_CTL,
 993                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 994         HDMI_WRITE(HDMI_FIFO_CTL,
 995                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 996
 997         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 998
 999         usleep_range(1000, 1100);
1000
1001         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1002
1003         HDMI_WRITE(HDMI_FIFO_CTL,
1004                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1005         HDMI_WRITE(HDMI_FIFO_CTL,
1006                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1007
1008         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1009
1010         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1011                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1012         WARN_ONCE(ret, "Timeout waiting for "
1013                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1014 }
1015
1016 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1017                                                 struct drm_atomic_state *state)
1018 {
1019         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1020         struct drm_connector *connector = &vc4_hdmi->connector;
1021         struct drm_connector_state *conn_state =
1022                 drm_atomic_get_new_connector_state(state, connector);
1023         struct vc4_hdmi_connector_state *vc4_conn_state =
1024                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1025         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1026         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
1027         unsigned long bvb_rate, hsm_rate;
1028         unsigned long flags;
1029         int ret;
1030
1031         mutex_lock(&vc4_hdmi->mutex);
1032
1033         /*
1034          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1035          * be faster than pixel clock, infinitesimally faster, tested in
1036          * simulation. Otherwise, exact value is unimportant for HDMI
1037          * operation." This conflicts with bcm2835's vc4 documentation, which
1038          * states HSM's clock has to be at least 108% of the pixel clock.
1039          *
1040          * Real life tests reveal that vc4's firmware statement holds up, and
1041          * users are able to use pixel clocks closer to HSM's, namely for
1042          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1043          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1044          * 162MHz.
1045          *
1046          * Additionally, the AXI clock needs to be at least 25% of
1047          * pixel clock, but HSM ends up being the limiting factor.
1048          */
1049         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1050         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1051         if (ret) {
1052                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1053                 goto out;
1054         }
1055
1056         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1057         if (ret < 0) {
1058                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1059                 goto out;
1060         }
1061
1062         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
1063         if (ret) {
1064                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1065                 goto err_put_runtime_pm;
1066         }
1067
1068         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1069         if (ret) {
1070                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1071                 goto err_put_runtime_pm;
1072         }
1073
1074
1075         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1076
1077         if (pixel_rate > 297000000)
1078                 bvb_rate = 300000000;
1079         else if (pixel_rate > 148500000)
1080                 bvb_rate = 150000000;
1081         else
1082                 bvb_rate = 75000000;
1083
1084         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1085         if (ret) {
1086                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1087                 goto err_disable_pixel_clock;
1088         }
1089
1090         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1091         if (ret) {
1092                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1093                 goto err_disable_pixel_clock;
1094         }
1095
1096         if (vc4_hdmi->variant->phy_init)
1097                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1098
1099         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1100
1101         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1102                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1103                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1104                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1105
1106         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1107
1108         if (vc4_hdmi->variant->set_timings)
1109                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1110
1111         mutex_unlock(&vc4_hdmi->mutex);
1112
1113         return;
1114
1115 err_disable_pixel_clock:
1116         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1117 err_put_runtime_pm:
1118         pm_runtime_put(&vc4_hdmi->pdev->dev);
1119 out:
1120         mutex_unlock(&vc4_hdmi->mutex);
1121         return;
1122 }
1123
1124 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1125                                              struct drm_atomic_state *state)
1126 {
1127         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1128         struct drm_connector *connector = &vc4_hdmi->connector;
1129         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1130         struct drm_connector_state *conn_state =
1131                 drm_atomic_get_new_connector_state(state, connector);
1132         unsigned long flags;
1133
1134         mutex_lock(&vc4_hdmi->mutex);
1135
1136         if (vc4_hdmi->variant->csc_setup)
1137                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1138
1139         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1140         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1141         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1142
1143         mutex_unlock(&vc4_hdmi->mutex);
1144 }
1145
1146 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1147                                               struct drm_atomic_state *state)
1148 {
1149         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1150         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1151         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1152         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1153         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1154         unsigned long flags;
1155         int ret;
1156
1157         mutex_lock(&vc4_hdmi->mutex);
1158
1159         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1160
1161         HDMI_WRITE(HDMI_VID_CTL,
1162                    VC4_HD_VID_CTL_ENABLE |
1163                    VC4_HD_VID_CTL_CLRRGB |
1164                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1165                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1166                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1167                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1168
1169         HDMI_WRITE(HDMI_VID_CTL,
1170                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1171
1172         if (vc4_encoder->hdmi_monitor) {
1173                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1174                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1175                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1176
1177                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1178
1179                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1180                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1181                 WARN_ONCE(ret, "Timeout waiting for "
1182                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1183         } else {
1184                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1185                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1186                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1187                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1188                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1189                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1190
1191                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1192
1193                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1194                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1195                 WARN_ONCE(ret, "Timeout waiting for "
1196                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1197         }
1198
1199         if (vc4_encoder->hdmi_monitor) {
1200                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1201
1202                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1203                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1204                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1205                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1206                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1207
1208                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1209                            VC4_HDMI_RAM_PACKET_ENABLE);
1210
1211                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1212
1213                 vc4_hdmi_set_infoframes(encoder);
1214         }
1215
1216         vc4_hdmi_recenter_fifo(vc4_hdmi);
1217         vc4_hdmi_enable_scrambling(encoder);
1218
1219         mutex_unlock(&vc4_hdmi->mutex);
1220 }
1221
1222 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1223 {
1224         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1225
1226         mutex_lock(&vc4_hdmi->mutex);
1227         vc4_hdmi->output_enabled = true;
1228         mutex_unlock(&vc4_hdmi->mutex);
1229 }
1230
1231 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1232                                              struct drm_crtc_state *crtc_state,
1233                                              struct drm_connector_state *conn_state)
1234 {
1235         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1236
1237         mutex_lock(&vc4_hdmi->mutex);
1238         drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1239                       &crtc_state->adjusted_mode);
1240         mutex_unlock(&vc4_hdmi->mutex);
1241 }
1242
1243 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1244 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1245
1246 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1247                                          struct drm_crtc_state *crtc_state,
1248                                          struct drm_connector_state *conn_state)
1249 {
1250         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1251         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1252         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1253         unsigned long long pixel_rate = mode->clock * 1000;
1254         unsigned long long tmds_rate;
1255
1256         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1257             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1258             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1259              (mode->hsync_end % 2) || (mode->htotal % 2)))
1260                 return -EINVAL;
1261
1262         /*
1263          * The 1440p@60 pixel rate is in the same range than the first
1264          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1265          * bandwidth). Slightly lower the frequency to bring it out of
1266          * the WiFi range.
1267          */
1268         tmds_rate = pixel_rate * 10;
1269         if (vc4_hdmi->disable_wifi_frequencies &&
1270             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1271              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1272                 mode->clock = 238560;
1273                 pixel_rate = mode->clock * 1000;
1274         }
1275
1276         if (conn_state->max_bpc == 12) {
1277                 pixel_rate = pixel_rate * 150;
1278                 do_div(pixel_rate, 100);
1279         } else if (conn_state->max_bpc == 10) {
1280                 pixel_rate = pixel_rate * 125;
1281                 do_div(pixel_rate, 100);
1282         }
1283
1284         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1285                 pixel_rate = pixel_rate * 2;
1286
1287         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1288                 return -EINVAL;
1289
1290         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1291                 return -EINVAL;
1292
1293         vc4_state->pixel_rate = pixel_rate;
1294
1295         return 0;
1296 }
1297
1298 static enum drm_mode_status
1299 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1300                             const struct drm_display_mode *mode)
1301 {
1302         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1303
1304         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1305             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1306             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1307              (mode->hsync_end % 2) || (mode->htotal % 2)))
1308                 return MODE_H_ILLEGAL;
1309
1310         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1311                 return MODE_CLOCK_HIGH;
1312
1313         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1314                 return MODE_CLOCK_HIGH;
1315
1316         return MODE_OK;
1317 }
1318
1319 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1320         .atomic_check = vc4_hdmi_encoder_atomic_check,
1321         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1322         .mode_valid = vc4_hdmi_encoder_mode_valid,
1323         .disable = vc4_hdmi_encoder_disable,
1324         .enable = vc4_hdmi_encoder_enable,
1325 };
1326
1327 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1328 {
1329         int i;
1330         u32 channel_map = 0;
1331
1332         for (i = 0; i < 8; i++) {
1333                 if (channel_mask & BIT(i))
1334                         channel_map |= i << (3 * i);
1335         }
1336         return channel_map;
1337 }
1338
1339 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1340 {
1341         int i;
1342         u32 channel_map = 0;
1343
1344         for (i = 0; i < 8; i++) {
1345                 if (channel_mask & BIT(i))
1346                         channel_map |= i << (4 * i);
1347         }
1348         return channel_map;
1349 }
1350
1351 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1352 {
1353         unsigned long flags;
1354         u32 hotplug;
1355
1356         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1357         hotplug = HDMI_READ(HDMI_HOTPLUG);
1358         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1359
1360         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1361 }
1362
1363 /* HDMI audio codec callbacks */
1364 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1365                                          unsigned int samplerate)
1366 {
1367         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1368         unsigned long flags;
1369         unsigned long n, m;
1370
1371         rational_best_approximation(hsm_clock, samplerate,
1372                                     VC4_HD_MAI_SMP_N_MASK >>
1373                                     VC4_HD_MAI_SMP_N_SHIFT,
1374                                     (VC4_HD_MAI_SMP_M_MASK >>
1375                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1376                                     &n, &m);
1377
1378         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1379         HDMI_WRITE(HDMI_MAI_SMP,
1380                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1381                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1382         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1383 }
1384
1385 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1386 {
1387         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1388         u32 n, cts;
1389         u64 tmp;
1390
1391         lockdep_assert_held(&vc4_hdmi->mutex);
1392         lockdep_assert_held(&vc4_hdmi->hw_lock);
1393
1394         n = 128 * samplerate / 1000;
1395         tmp = (u64)(mode->clock * 1000) * n;
1396         do_div(tmp, 128 * samplerate);
1397         cts = tmp;
1398
1399         HDMI_WRITE(HDMI_CRP_CFG,
1400                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1401                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1402
1403         /*
1404          * We could get slightly more accurate clocks in some cases by
1405          * providing a CTS_1 value.  The two CTS values are alternated
1406          * between based on the period fields
1407          */
1408         HDMI_WRITE(HDMI_CTS_0, cts);
1409         HDMI_WRITE(HDMI_CTS_1, cts);
1410 }
1411
1412 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1413 {
1414         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1415
1416         return snd_soc_card_get_drvdata(card);
1417 }
1418
1419 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1420 {
1421         lockdep_assert_held(&vc4_hdmi->mutex);
1422
1423         /*
1424          * If the controller is disabled, prevent any ALSA output.
1425          */
1426         if (!vc4_hdmi->output_enabled)
1427                 return false;
1428
1429         /*
1430          * If the encoder is currently in DVI mode, treat the codec DAI
1431          * as missing.
1432          */
1433         if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE))
1434                 return false;
1435
1436         return true;
1437 }
1438
1439 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1440 {
1441         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1442         unsigned long flags;
1443
1444         mutex_lock(&vc4_hdmi->mutex);
1445
1446         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1447                 mutex_unlock(&vc4_hdmi->mutex);
1448                 return -ENODEV;
1449         }
1450
1451         vc4_hdmi->audio.streaming = true;
1452
1453         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1454         HDMI_WRITE(HDMI_MAI_CTL,
1455                    VC4_HD_MAI_CTL_RESET |
1456                    VC4_HD_MAI_CTL_FLUSH |
1457                    VC4_HD_MAI_CTL_DLATE |
1458                    VC4_HD_MAI_CTL_ERRORE |
1459                    VC4_HD_MAI_CTL_ERRORF);
1460         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1461
1462         if (vc4_hdmi->variant->phy_rng_enable)
1463                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1464
1465         mutex_unlock(&vc4_hdmi->mutex);
1466
1467         return 0;
1468 }
1469
1470 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1471 {
1472         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1473         struct device *dev = &vc4_hdmi->pdev->dev;
1474         unsigned long flags;
1475         int ret;
1476
1477         lockdep_assert_held(&vc4_hdmi->mutex);
1478
1479         vc4_hdmi->audio.streaming = false;
1480         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1481         if (ret)
1482                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1483
1484         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1485
1486         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1487         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1488         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1489
1490         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1491 }
1492
1493 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1494 {
1495         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1496         unsigned long flags;
1497
1498         mutex_lock(&vc4_hdmi->mutex);
1499
1500         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1501
1502         HDMI_WRITE(HDMI_MAI_CTL,
1503                    VC4_HD_MAI_CTL_DLATE |
1504                    VC4_HD_MAI_CTL_ERRORE |
1505                    VC4_HD_MAI_CTL_ERRORF);
1506
1507         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1508
1509         if (vc4_hdmi->variant->phy_rng_disable)
1510                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1511
1512         vc4_hdmi->audio.streaming = false;
1513         vc4_hdmi_audio_reset(vc4_hdmi);
1514
1515         mutex_unlock(&vc4_hdmi->mutex);
1516 }
1517
1518 static int sample_rate_to_mai_fmt(int samplerate)
1519 {
1520         switch (samplerate) {
1521         case 8000:
1522                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1523         case 11025:
1524                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1525         case 12000:
1526                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1527         case 16000:
1528                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1529         case 22050:
1530                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1531         case 24000:
1532                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1533         case 32000:
1534                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1535         case 44100:
1536                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1537         case 48000:
1538                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1539         case 64000:
1540                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1541         case 88200:
1542                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1543         case 96000:
1544                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1545         case 128000:
1546                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1547         case 176400:
1548                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1549         case 192000:
1550                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1551         default:
1552                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1553         }
1554 }
1555
1556 /* HDMI audio codec callbacks */
1557 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1558                                   struct hdmi_codec_daifmt *daifmt,
1559                                   struct hdmi_codec_params *params)
1560 {
1561         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1562         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1563         unsigned int sample_rate = params->sample_rate;
1564         unsigned int channels = params->channels;
1565         unsigned long flags;
1566         u32 audio_packet_config, channel_mask;
1567         u32 channel_map;
1568         u32 mai_audio_format;
1569         u32 mai_sample_rate;
1570
1571         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1572                 sample_rate, params->sample_width, channels);
1573
1574         mutex_lock(&vc4_hdmi->mutex);
1575
1576         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1577                 mutex_unlock(&vc4_hdmi->mutex);
1578                 return -EINVAL;
1579         }
1580
1581         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1582
1583         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1584         HDMI_WRITE(HDMI_MAI_CTL,
1585                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1586                    VC4_HD_MAI_CTL_WHOLSMP |
1587                    VC4_HD_MAI_CTL_CHALIGN |
1588                    VC4_HD_MAI_CTL_ENABLE);
1589
1590         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1591         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1592             params->channels == 8)
1593                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1594         else
1595                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1596         HDMI_WRITE(HDMI_MAI_FMT,
1597                    VC4_SET_FIELD(mai_sample_rate,
1598                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1599                    VC4_SET_FIELD(mai_audio_format,
1600                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1601
1602         /* The B frame identifier should match the value used by alsa-lib (8) */
1603         audio_packet_config =
1604                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1605                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1606                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1607
1608         channel_mask = GENMASK(channels - 1, 0);
1609         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1610                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1611
1612         /* Set the MAI threshold */
1613         HDMI_WRITE(HDMI_MAI_THR,
1614                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1615                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1616                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1617                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1618
1619         HDMI_WRITE(HDMI_MAI_CONFIG,
1620                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1621                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1622                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1623
1624         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1625         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1626         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1627
1628         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1629
1630         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1631
1632         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1633         vc4_hdmi_set_audio_infoframe(encoder);
1634
1635         mutex_unlock(&vc4_hdmi->mutex);
1636
1637         return 0;
1638 }
1639
1640 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1641         .name = "vc4-hdmi-cpu-dai-component",
1642 };
1643
1644 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1645 {
1646         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1647
1648         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1649
1650         return 0;
1651 }
1652
1653 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1654         .name = "vc4-hdmi-cpu-dai",
1655         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1656         .playback = {
1657                 .stream_name = "Playback",
1658                 .channels_min = 1,
1659                 .channels_max = 8,
1660                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1661                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1662                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1663                          SNDRV_PCM_RATE_192000,
1664                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1665         },
1666 };
1667
1668 static const struct snd_dmaengine_pcm_config pcm_conf = {
1669         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1670         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1671 };
1672
1673 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1674                                   uint8_t *buf, size_t len)
1675 {
1676         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1677         struct drm_connector *connector = &vc4_hdmi->connector;
1678
1679         mutex_lock(&vc4_hdmi->mutex);
1680         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1681         mutex_unlock(&vc4_hdmi->mutex);
1682
1683         return 0;
1684 }
1685
1686 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1687         .get_eld = vc4_hdmi_audio_get_eld,
1688         .prepare = vc4_hdmi_audio_prepare,
1689         .audio_shutdown = vc4_hdmi_audio_shutdown,
1690         .audio_startup = vc4_hdmi_audio_startup,
1691 };
1692
1693 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1694         .ops = &vc4_hdmi_codec_ops,
1695         .max_i2s_channels = 8,
1696         .i2s = 1,
1697 };
1698
1699 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1700 {
1701         const struct vc4_hdmi_register *mai_data =
1702                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1703         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1704         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1705         struct device *dev = &vc4_hdmi->pdev->dev;
1706         struct platform_device *codec_pdev;
1707         const __be32 *addr;
1708         int index;
1709         int ret;
1710
1711         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1712                 dev_warn(dev,
1713                          "'dmas' DT property is missing, no HDMI audio\n");
1714                 return 0;
1715         }
1716
1717         if (mai_data->reg != VC4_HD) {
1718                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1719                 return -EINVAL;
1720         }
1721
1722         /*
1723          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1724          * the bus address specified in the DT, because the physical address
1725          * (the one returned by platform_get_resource()) is not appropriate
1726          * for DMA transfers.
1727          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1728          */
1729         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1730         /* Before BCM2711, we don't have a named register range */
1731         if (index < 0)
1732                 index = 1;
1733
1734         addr = of_get_address(dev->of_node, index, NULL, NULL);
1735
1736         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1737         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1738         vc4_hdmi->audio.dma_data.maxburst = 2;
1739
1740         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1741         if (ret) {
1742                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1743                 return ret;
1744         }
1745
1746         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1747                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1748         if (ret) {
1749                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1750                 return ret;
1751         }
1752
1753         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1754                                                    PLATFORM_DEVID_AUTO,
1755                                                    &vc4_hdmi_codec_pdata,
1756                                                    sizeof(vc4_hdmi_codec_pdata));
1757         if (IS_ERR(codec_pdev)) {
1758                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1759                 return PTR_ERR(codec_pdev);
1760         }
1761         vc4_hdmi->audio.codec_pdev = codec_pdev;
1762
1763         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1764         dai_link->codecs        = &vc4_hdmi->audio.codec;
1765         dai_link->platforms     = &vc4_hdmi->audio.platform;
1766
1767         dai_link->num_cpus      = 1;
1768         dai_link->num_codecs    = 1;
1769         dai_link->num_platforms = 1;
1770
1771         dai_link->name = "MAI";
1772         dai_link->stream_name = "MAI PCM";
1773         dai_link->codecs->dai_name = "i2s-hifi";
1774         dai_link->cpus->dai_name = dev_name(dev);
1775         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1776         dai_link->platforms->name = dev_name(dev);
1777
1778         card->dai_link = dai_link;
1779         card->num_links = 1;
1780         card->name = vc4_hdmi->variant->card_name;
1781         card->driver_name = "vc4-hdmi";
1782         card->dev = dev;
1783         card->owner = THIS_MODULE;
1784
1785         /*
1786          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1787          * stores a pointer to the snd card object in dev->driver_data. This
1788          * means we cannot use it for something else. The hdmi back-pointer is
1789          * now stored in card->drvdata and should be retrieved with
1790          * snd_soc_card_get_drvdata() if needed.
1791          */
1792         snd_soc_card_set_drvdata(card, vc4_hdmi);
1793         ret = devm_snd_soc_register_card(dev, card);
1794         if (ret)
1795                 dev_err_probe(dev, ret, "Could not register sound card\n");
1796
1797         return ret;
1798
1799 }
1800
1801 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
1802 {
1803         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
1804         vc4_hdmi->audio.codec_pdev = NULL;
1805 }
1806
1807 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1808 {
1809         struct vc4_hdmi *vc4_hdmi = priv;
1810         struct drm_connector *connector = &vc4_hdmi->connector;
1811         struct drm_device *dev = connector->dev;
1812
1813         if (dev && dev->registered)
1814                 drm_connector_helper_hpd_irq_event(connector);
1815
1816         return IRQ_HANDLED;
1817 }
1818
1819 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1820 {
1821         struct drm_connector *connector = &vc4_hdmi->connector;
1822         struct platform_device *pdev = vc4_hdmi->pdev;
1823         int ret;
1824
1825         if (vc4_hdmi->variant->external_irq_controller) {
1826                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1827                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1828
1829                 ret = request_threaded_irq(hpd_con,
1830                                            NULL,
1831                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1832                                            "vc4 hdmi hpd connected", vc4_hdmi);
1833                 if (ret)
1834                         return ret;
1835
1836                 ret = request_threaded_irq(hpd_rm,
1837                                            NULL,
1838                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1839                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1840                 if (ret) {
1841                         free_irq(hpd_con, vc4_hdmi);
1842                         return ret;
1843                 }
1844
1845                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1846         }
1847
1848         return 0;
1849 }
1850
1851 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1852 {
1853         struct platform_device *pdev = vc4_hdmi->pdev;
1854
1855         if (vc4_hdmi->variant->external_irq_controller) {
1856                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1857                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1858         }
1859 }
1860
1861 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1862 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1863 {
1864         struct vc4_hdmi *vc4_hdmi = priv;
1865
1866         if (vc4_hdmi->cec_rx_msg.len)
1867                 cec_received_msg(vc4_hdmi->cec_adap,
1868                                  &vc4_hdmi->cec_rx_msg);
1869
1870         return IRQ_HANDLED;
1871 }
1872
1873 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1874 {
1875         struct vc4_hdmi *vc4_hdmi = priv;
1876
1877         if (vc4_hdmi->cec_tx_ok) {
1878                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1879                                   0, 0, 0, 0);
1880         } else {
1881                 /*
1882                  * This CEC implementation makes 1 retry, so if we
1883                  * get a NACK, then that means it made 2 attempts.
1884                  */
1885                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1886                                   0, 2, 0, 0);
1887         }
1888         return IRQ_HANDLED;
1889 }
1890
1891 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1892 {
1893         struct vc4_hdmi *vc4_hdmi = priv;
1894         irqreturn_t ret;
1895
1896         if (vc4_hdmi->cec_irq_was_rx)
1897                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1898         else
1899                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1900
1901         return ret;
1902 }
1903
1904 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1905 {
1906         struct drm_device *dev = vc4_hdmi->connector.dev;
1907         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1908         unsigned int i;
1909
1910         lockdep_assert_held(&vc4_hdmi->hw_lock);
1911
1912         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1913                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1914
1915         if (msg->len > 16) {
1916                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1917                 return;
1918         }
1919
1920         for (i = 0; i < msg->len; i += 4) {
1921                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1922
1923                 msg->msg[i] = val & 0xff;
1924                 msg->msg[i + 1] = (val >> 8) & 0xff;
1925                 msg->msg[i + 2] = (val >> 16) & 0xff;
1926                 msg->msg[i + 3] = (val >> 24) & 0xff;
1927         }
1928 }
1929
1930 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1931 {
1932         u32 cntrl1;
1933
1934         lockdep_assert_held(&vc4_hdmi->hw_lock);
1935
1936         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1937         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1938         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1939         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1940
1941         return IRQ_WAKE_THREAD;
1942 }
1943
1944 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1945 {
1946         struct vc4_hdmi *vc4_hdmi = priv;
1947         irqreturn_t ret;
1948
1949         spin_lock(&vc4_hdmi->hw_lock);
1950         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1951         spin_unlock(&vc4_hdmi->hw_lock);
1952
1953         return ret;
1954 }
1955
1956 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1957 {
1958         u32 cntrl1;
1959
1960         lockdep_assert_held(&vc4_hdmi->hw_lock);
1961
1962         vc4_hdmi->cec_rx_msg.len = 0;
1963         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1964         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1965         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1966         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1967         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1968
1969         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1970
1971         return IRQ_WAKE_THREAD;
1972 }
1973
1974 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1975 {
1976         struct vc4_hdmi *vc4_hdmi = priv;
1977         irqreturn_t ret;
1978
1979         spin_lock(&vc4_hdmi->hw_lock);
1980         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
1981         spin_unlock(&vc4_hdmi->hw_lock);
1982
1983         return ret;
1984 }
1985
1986 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1987 {
1988         struct vc4_hdmi *vc4_hdmi = priv;
1989         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1990         irqreturn_t ret;
1991         u32 cntrl5;
1992
1993         if (!(stat & VC4_HDMI_CPU_CEC))
1994                 return IRQ_NONE;
1995
1996         spin_lock(&vc4_hdmi->hw_lock);
1997         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1998         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1999         if (vc4_hdmi->cec_irq_was_rx)
2000                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2001         else
2002                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2003
2004         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2005         spin_unlock(&vc4_hdmi->hw_lock);
2006
2007         return ret;
2008 }
2009
2010 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2011 {
2012         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2013         /* clock period in microseconds */
2014         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2015         unsigned long flags;
2016         u32 val;
2017         int ret;
2018
2019         /*
2020          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2021          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2022          * .detect or .get_modes might call .adap_enable, which leads to this
2023          * function being called with that mutex held.
2024          *
2025          * Concurrency is not an issue for the moment since we don't share any
2026          * state with KMS, so we can ignore the lock for now, but we need to
2027          * keep it in mind if we were to change that assumption.
2028          */
2029
2030         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2031         if (ret)
2032                 return ret;
2033
2034         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2035
2036         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2037         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2038                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2039                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2040         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2041                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2042
2043         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2044                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2045         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2046         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2047                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2048                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2049                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2050                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2051                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2052         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2053                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2054                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2055                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2056                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2057         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2058                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2059                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2060                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2061                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2062
2063         if (!vc4_hdmi->variant->external_irq_controller)
2064                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2065
2066         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2067
2068         return 0;
2069 }
2070
2071 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2072 {
2073         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2074         unsigned long flags;
2075
2076         /*
2077          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2078          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2079          * .detect or .get_modes might call .adap_enable, which leads to this
2080          * function being called with that mutex held.
2081          *
2082          * Concurrency is not an issue for the moment since we don't share any
2083          * state with KMS, so we can ignore the lock for now, but we need to
2084          * keep it in mind if we were to change that assumption.
2085          */
2086
2087         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2088
2089         if (!vc4_hdmi->variant->external_irq_controller)
2090                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2091
2092         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2093                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2094
2095         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2096
2097         pm_runtime_put(&vc4_hdmi->pdev->dev);
2098
2099         return 0;
2100 }
2101
2102 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2103 {
2104         if (enable)
2105                 return vc4_hdmi_cec_enable(adap);
2106         else
2107                 return vc4_hdmi_cec_disable(adap);
2108 }
2109
2110 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2111 {
2112         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2113         unsigned long flags;
2114
2115         /*
2116          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2117          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2118          * .detect or .get_modes might call .adap_enable, which leads to this
2119          * function being called with that mutex held.
2120          *
2121          * Concurrency is not an issue for the moment since we don't share any
2122          * state with KMS, so we can ignore the lock for now, but we need to
2123          * keep it in mind if we were to change that assumption.
2124          */
2125
2126         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2127         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2128                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2129                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2130         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2131
2132         return 0;
2133 }
2134
2135 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2136                                       u32 signal_free_time, struct cec_msg *msg)
2137 {
2138         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2139         struct drm_device *dev = vc4_hdmi->connector.dev;
2140         unsigned long flags;
2141         u32 val;
2142         unsigned int i;
2143
2144         /*
2145          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2146          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2147          * .detect or .get_modes might call .adap_enable, which leads to this
2148          * function being called with that mutex held.
2149          *
2150          * Concurrency is not an issue for the moment since we don't share any
2151          * state with KMS, so we can ignore the lock for now, but we need to
2152          * keep it in mind if we were to change that assumption.
2153          */
2154
2155         if (msg->len > 16) {
2156                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2157                 return -ENOMEM;
2158         }
2159
2160         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2161
2162         for (i = 0; i < msg->len; i += 4)
2163                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2164                            (msg->msg[i]) |
2165                            (msg->msg[i + 1] << 8) |
2166                            (msg->msg[i + 2] << 16) |
2167                            (msg->msg[i + 3] << 24));
2168
2169         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2170         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2171         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2172         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2173         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2174         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2175
2176         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2177
2178         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2179
2180         return 0;
2181 }
2182
2183 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2184         .adap_enable = vc4_hdmi_cec_adap_enable,
2185         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2186         .adap_transmit = vc4_hdmi_cec_adap_transmit,
2187 };
2188
2189 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2190 {
2191         struct cec_connector_info conn_info;
2192         struct platform_device *pdev = vc4_hdmi->pdev;
2193         struct device *dev = &pdev->dev;
2194         unsigned long flags;
2195         u32 value;
2196         int ret;
2197
2198         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2199                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2200                 return 0;
2201         }
2202
2203         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2204                                                   vc4_hdmi, "vc4",
2205                                                   CEC_CAP_DEFAULTS |
2206                                                   CEC_CAP_CONNECTOR_INFO, 1);
2207         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2208         if (ret < 0)
2209                 return ret;
2210
2211         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2212         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2213
2214         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2215         value = HDMI_READ(HDMI_CEC_CNTRL_1);
2216         /* Set the logical address to Unregistered */
2217         value |= VC4_HDMI_CEC_ADDR_MASK;
2218         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
2219         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2220
2221         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
2222
2223         if (vc4_hdmi->variant->external_irq_controller) {
2224                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
2225                                            vc4_cec_irq_handler_rx_bare,
2226                                            vc4_cec_irq_handler_rx_thread, 0,
2227                                            "vc4 hdmi cec rx", vc4_hdmi);
2228                 if (ret)
2229                         goto err_delete_cec_adap;
2230
2231                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
2232                                            vc4_cec_irq_handler_tx_bare,
2233                                            vc4_cec_irq_handler_tx_thread, 0,
2234                                            "vc4 hdmi cec tx", vc4_hdmi);
2235                 if (ret)
2236                         goto err_remove_cec_rx_handler;
2237         } else {
2238                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2239                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2240                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2241
2242                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
2243                                            vc4_cec_irq_handler,
2244                                            vc4_cec_irq_handler_thread, 0,
2245                                            "vc4 hdmi cec", vc4_hdmi);
2246                 if (ret)
2247                         goto err_delete_cec_adap;
2248         }
2249
2250         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2251         if (ret < 0)
2252                 goto err_remove_handlers;
2253
2254         return 0;
2255
2256 err_remove_handlers:
2257         if (vc4_hdmi->variant->external_irq_controller)
2258                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2259         else
2260                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2261
2262 err_remove_cec_rx_handler:
2263         if (vc4_hdmi->variant->external_irq_controller)
2264                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2265
2266 err_delete_cec_adap:
2267         cec_delete_adapter(vc4_hdmi->cec_adap);
2268
2269         return ret;
2270 }
2271
2272 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
2273 {
2274         struct platform_device *pdev = vc4_hdmi->pdev;
2275
2276         if (vc4_hdmi->variant->external_irq_controller) {
2277                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2278                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2279         } else {
2280                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2281         }
2282
2283         cec_unregister_adapter(vc4_hdmi->cec_adap);
2284 }
2285 #else
2286 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2287 {
2288         return 0;
2289 }
2290
2291 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
2292
2293 #endif
2294
2295 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
2296                                  struct debugfs_regset32 *regset,
2297                                  enum vc4_hdmi_regs reg)
2298 {
2299         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2300         struct debugfs_reg32 *regs, *new_regs;
2301         unsigned int count = 0;
2302         unsigned int i;
2303
2304         regs = kcalloc(variant->num_registers, sizeof(*regs),
2305                        GFP_KERNEL);
2306         if (!regs)
2307                 return -ENOMEM;
2308
2309         for (i = 0; i < variant->num_registers; i++) {
2310                 const struct vc4_hdmi_register *field = &variant->registers[i];
2311
2312                 if (field->reg != reg)
2313                         continue;
2314
2315                 regs[count].name = field->name;
2316                 regs[count].offset = field->offset;
2317                 count++;
2318         }
2319
2320         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2321         if (!new_regs)
2322                 return -ENOMEM;
2323
2324         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2325         regset->regs = new_regs;
2326         regset->nregs = count;
2327
2328         return 0;
2329 }
2330
2331 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2332 {
2333         struct platform_device *pdev = vc4_hdmi->pdev;
2334         struct device *dev = &pdev->dev;
2335         int ret;
2336
2337         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2338         if (IS_ERR(vc4_hdmi->hdmicore_regs))
2339                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2340
2341         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2342         if (IS_ERR(vc4_hdmi->hd_regs))
2343                 return PTR_ERR(vc4_hdmi->hd_regs);
2344
2345         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2346         if (ret)
2347                 return ret;
2348
2349         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2350         if (ret)
2351                 return ret;
2352
2353         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2354         if (IS_ERR(vc4_hdmi->pixel_clock)) {
2355                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2356                 if (ret != -EPROBE_DEFER)
2357                         DRM_ERROR("Failed to get pixel clock\n");
2358                 return ret;
2359         }
2360
2361         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2362         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2363                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2364                 return PTR_ERR(vc4_hdmi->hsm_clock);
2365         }
2366         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2367         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2368
2369         return 0;
2370 }
2371
2372 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2373 {
2374         struct platform_device *pdev = vc4_hdmi->pdev;
2375         struct device *dev = &pdev->dev;
2376         struct resource *res;
2377
2378         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2379         if (!res)
2380                 return -ENODEV;
2381
2382         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2383                                                resource_size(res));
2384         if (!vc4_hdmi->hdmicore_regs)
2385                 return -ENOMEM;
2386
2387         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2388         if (!res)
2389                 return -ENODEV;
2390
2391         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2392         if (!vc4_hdmi->hd_regs)
2393                 return -ENOMEM;
2394
2395         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2396         if (!res)
2397                 return -ENODEV;
2398
2399         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2400         if (!vc4_hdmi->cec_regs)
2401                 return -ENOMEM;
2402
2403         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2404         if (!res)
2405                 return -ENODEV;
2406
2407         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2408         if (!vc4_hdmi->csc_regs)
2409                 return -ENOMEM;
2410
2411         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2412         if (!res)
2413                 return -ENODEV;
2414
2415         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2416         if (!vc4_hdmi->dvp_regs)
2417                 return -ENOMEM;
2418
2419         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2420         if (!res)
2421                 return -ENODEV;
2422
2423         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2424         if (!vc4_hdmi->phy_regs)
2425                 return -ENOMEM;
2426
2427         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2428         if (!res)
2429                 return -ENODEV;
2430
2431         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2432         if (!vc4_hdmi->ram_regs)
2433                 return -ENOMEM;
2434
2435         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2436         if (!res)
2437                 return -ENODEV;
2438
2439         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2440         if (!vc4_hdmi->rm_regs)
2441                 return -ENOMEM;
2442
2443         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2444         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2445                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2446                 return PTR_ERR(vc4_hdmi->hsm_clock);
2447         }
2448
2449         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2450         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2451                 DRM_ERROR("Failed to get pixel bvb clock\n");
2452                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2453         }
2454
2455         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2456         if (IS_ERR(vc4_hdmi->audio_clock)) {
2457                 DRM_ERROR("Failed to get audio clock\n");
2458                 return PTR_ERR(vc4_hdmi->audio_clock);
2459         }
2460
2461         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2462         if (IS_ERR(vc4_hdmi->cec_clock)) {
2463                 DRM_ERROR("Failed to get CEC clock\n");
2464                 return PTR_ERR(vc4_hdmi->cec_clock);
2465         }
2466
2467         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2468         if (IS_ERR(vc4_hdmi->reset)) {
2469                 DRM_ERROR("Failed to get HDMI reset line\n");
2470                 return PTR_ERR(vc4_hdmi->reset);
2471         }
2472
2473         return 0;
2474 }
2475
2476 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2477 {
2478         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2479
2480         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2481
2482         return 0;
2483 }
2484
2485 static int vc4_hdmi_runtime_resume(struct device *dev)
2486 {
2487         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2488         int ret;
2489
2490         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2491         if (ret)
2492                 return ret;
2493
2494         return 0;
2495 }
2496
2497 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2498 {
2499         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2500         struct platform_device *pdev = to_platform_device(dev);
2501         struct drm_device *drm = dev_get_drvdata(master);
2502         struct vc4_hdmi *vc4_hdmi;
2503         struct drm_encoder *encoder;
2504         struct device_node *ddc_node;
2505         int ret;
2506
2507         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2508         if (!vc4_hdmi)
2509                 return -ENOMEM;
2510         mutex_init(&vc4_hdmi->mutex);
2511         spin_lock_init(&vc4_hdmi->hw_lock);
2512         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2513
2514         dev_set_drvdata(dev, vc4_hdmi);
2515         encoder = &vc4_hdmi->encoder.base.base;
2516         vc4_hdmi->encoder.base.type = variant->encoder_type;
2517         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2518         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2519         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2520         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2521         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2522         vc4_hdmi->pdev = pdev;
2523         vc4_hdmi->variant = variant;
2524
2525         /*
2526          * Since we don't know the state of the controller and its
2527          * display (if any), let's assume it's always enabled.
2528          * vc4_hdmi_disable_scrambling() will thus run at boot, make
2529          * sure it's disabled, and avoid any inconsistency.
2530          */
2531         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
2532                 vc4_hdmi->scdc_enabled = true;
2533
2534         ret = variant->init_resources(vc4_hdmi);
2535         if (ret)
2536                 return ret;
2537
2538         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2539         if (!ddc_node) {
2540                 DRM_ERROR("Failed to find ddc node in device tree\n");
2541                 return -ENODEV;
2542         }
2543
2544         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2545         of_node_put(ddc_node);
2546         if (!vc4_hdmi->ddc) {
2547                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2548                 return -EPROBE_DEFER;
2549         }
2550
2551         /* Only use the GPIO HPD pin if present in the DT, otherwise
2552          * we'll use the HDMI core's register.
2553          */
2554         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2555         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2556                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2557                 goto err_put_ddc;
2558         }
2559
2560         vc4_hdmi->disable_wifi_frequencies =
2561                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2562
2563         if (variant->max_pixel_clock == 600000000) {
2564                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2565                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2566
2567                 if (max_rate < 550000000)
2568                         vc4_hdmi->disable_4kp60 = true;
2569         }
2570
2571         /*
2572          * If we boot without any cable connected to the HDMI connector,
2573          * the firmware will skip the HSM initialization and leave it
2574          * with a rate of 0, resulting in a bus lockup when we're
2575          * accessing the registers even if it's enabled.
2576          *
2577          * Let's put a sensible default at runtime_resume so that we
2578          * don't end up in this situation.
2579          */
2580         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2581         if (ret)
2582                 goto err_put_ddc;
2583
2584         /*
2585          * We need to have the device powered up at this point to call
2586          * our reset hook and for the CEC init.
2587          */
2588         ret = vc4_hdmi_runtime_resume(dev);
2589         if (ret)
2590                 goto err_put_ddc;
2591
2592         pm_runtime_get_noresume(dev);
2593         pm_runtime_set_active(dev);
2594         pm_runtime_enable(dev);
2595
2596         if (vc4_hdmi->variant->reset)
2597                 vc4_hdmi->variant->reset(vc4_hdmi);
2598
2599         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2600              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2601             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2602                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2603                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2604                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2605         }
2606
2607         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2608         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2609
2610         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2611         if (ret)
2612                 goto err_destroy_encoder;
2613
2614         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2615         if (ret)
2616                 goto err_destroy_conn;
2617
2618         ret = vc4_hdmi_cec_init(vc4_hdmi);
2619         if (ret)
2620                 goto err_free_hotplug;
2621
2622         ret = vc4_hdmi_audio_init(vc4_hdmi);
2623         if (ret)
2624                 goto err_free_cec;
2625
2626         vc4_debugfs_add_file(drm, variant->debugfs_name,
2627                              vc4_hdmi_debugfs_regs,
2628                              vc4_hdmi);
2629
2630         pm_runtime_put_sync(dev);
2631
2632         return 0;
2633
2634 err_free_cec:
2635         vc4_hdmi_cec_exit(vc4_hdmi);
2636 err_free_hotplug:
2637         vc4_hdmi_hotplug_exit(vc4_hdmi);
2638 err_destroy_conn:
2639         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2640 err_destroy_encoder:
2641         drm_encoder_cleanup(encoder);
2642         pm_runtime_put_sync(dev);
2643         pm_runtime_disable(dev);
2644 err_put_ddc:
2645         put_device(&vc4_hdmi->ddc->dev);
2646
2647         return ret;
2648 }
2649
2650 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2651                             void *data)
2652 {
2653         struct vc4_hdmi *vc4_hdmi;
2654
2655         /*
2656          * ASoC makes it a bit hard to retrieve a pointer to the
2657          * vc4_hdmi structure. Registering the card will overwrite our
2658          * device drvdata with a pointer to the snd_soc_card structure,
2659          * which can then be used to retrieve whatever drvdata we want
2660          * to associate.
2661          *
2662          * However, that doesn't fly in the case where we wouldn't
2663          * register an ASoC card (because of an old DT that is missing
2664          * the dmas properties for example), then the card isn't
2665          * registered and the device drvdata wouldn't be set.
2666          *
2667          * We can deal with both cases by making sure a snd_soc_card
2668          * pointer and a vc4_hdmi structure are pointing to the same
2669          * memory address, so we can treat them indistinctly without any
2670          * issue.
2671          */
2672         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2673         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2674         vc4_hdmi = dev_get_drvdata(dev);
2675
2676         kfree(vc4_hdmi->hdmi_regset.regs);
2677         kfree(vc4_hdmi->hd_regset.regs);
2678
2679         vc4_hdmi_audio_exit(vc4_hdmi);
2680         vc4_hdmi_cec_exit(vc4_hdmi);
2681         vc4_hdmi_hotplug_exit(vc4_hdmi);
2682         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2683         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2684
2685         pm_runtime_disable(dev);
2686
2687         put_device(&vc4_hdmi->ddc->dev);
2688 }
2689
2690 static const struct component_ops vc4_hdmi_ops = {
2691         .bind   = vc4_hdmi_bind,
2692         .unbind = vc4_hdmi_unbind,
2693 };
2694
2695 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2696 {
2697         return component_add(&pdev->dev, &vc4_hdmi_ops);
2698 }
2699
2700 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2701 {
2702         component_del(&pdev->dev, &vc4_hdmi_ops);
2703         return 0;
2704 }
2705
2706 static const struct vc4_hdmi_variant bcm2835_variant = {
2707         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2708         .debugfs_name           = "hdmi_regs",
2709         .card_name              = "vc4-hdmi",
2710         .max_pixel_clock        = 162000000,
2711         .registers              = vc4_hdmi_fields,
2712         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2713
2714         .init_resources         = vc4_hdmi_init_resources,
2715         .csc_setup              = vc4_hdmi_csc_setup,
2716         .reset                  = vc4_hdmi_reset,
2717         .set_timings            = vc4_hdmi_set_timings,
2718         .phy_init               = vc4_hdmi_phy_init,
2719         .phy_disable            = vc4_hdmi_phy_disable,
2720         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2721         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2722         .channel_map            = vc4_hdmi_channel_map,
2723         .supports_hdr           = false,
2724 };
2725
2726 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2727         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2728         .debugfs_name           = "hdmi0_regs",
2729         .card_name              = "vc4-hdmi-0",
2730         .max_pixel_clock        = 600000000,
2731         .registers              = vc5_hdmi_hdmi0_fields,
2732         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2733         .phy_lane_mapping       = {
2734                 PHY_LANE_0,
2735                 PHY_LANE_1,
2736                 PHY_LANE_2,
2737                 PHY_LANE_CK,
2738         },
2739         .unsupported_odd_h_timings      = true,
2740         .external_irq_controller        = true,
2741
2742         .init_resources         = vc5_hdmi_init_resources,
2743         .csc_setup              = vc5_hdmi_csc_setup,
2744         .reset                  = vc5_hdmi_reset,
2745         .set_timings            = vc5_hdmi_set_timings,
2746         .phy_init               = vc5_hdmi_phy_init,
2747         .phy_disable            = vc5_hdmi_phy_disable,
2748         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2749         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2750         .channel_map            = vc5_hdmi_channel_map,
2751         .supports_hdr           = true,
2752         .hp_detect              = vc5_hdmi_hp_detect,
2753 };
2754
2755 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2756         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2757         .debugfs_name           = "hdmi1_regs",
2758         .card_name              = "vc4-hdmi-1",
2759         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2760         .registers              = vc5_hdmi_hdmi1_fields,
2761         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2762         .phy_lane_mapping       = {
2763                 PHY_LANE_1,
2764                 PHY_LANE_0,
2765                 PHY_LANE_CK,
2766                 PHY_LANE_2,
2767         },
2768         .unsupported_odd_h_timings      = true,
2769         .external_irq_controller        = true,
2770
2771         .init_resources         = vc5_hdmi_init_resources,
2772         .csc_setup              = vc5_hdmi_csc_setup,
2773         .reset                  = vc5_hdmi_reset,
2774         .set_timings            = vc5_hdmi_set_timings,
2775         .phy_init               = vc5_hdmi_phy_init,
2776         .phy_disable            = vc5_hdmi_phy_disable,
2777         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2778         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2779         .channel_map            = vc5_hdmi_channel_map,
2780         .supports_hdr           = true,
2781         .hp_detect              = vc5_hdmi_hp_detect,
2782 };
2783
2784 static const struct of_device_id vc4_hdmi_dt_match[] = {
2785         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2786         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2787         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2788         {}
2789 };
2790
2791 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2792         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2793                            vc4_hdmi_runtime_resume,
2794                            NULL)
2795 };
2796
2797 struct platform_driver vc4_hdmi_driver = {
2798         .probe = vc4_hdmi_dev_probe,
2799         .remove = vc4_hdmi_dev_remove,
2800         .driver = {
2801                 .name = "vc4_hdmi",
2802                 .of_match_table = vc4_hdmi_dt_match,
2803                 .pm = &vc4_hdmi_pm_ops,
2804         },
2805 };