1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
10 * DOC: VC4 Falcon HDMI module
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
34 #include <drm/display/drm_hdmi_helper.h>
35 #include <drm/display/drm_scdc_helper.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_drv.h>
38 #include <drm/drm_probe_helper.h>
39 #include <drm/drm_simple_kms_helper.h>
40 #include <linux/clk.h>
41 #include <linux/component.h>
42 #include <linux/gpio/consumer.h>
43 #include <linux/i2c.h>
44 #include <linux/of_address.h>
45 #include <linux/of_platform.h>
46 #include <linux/pm_runtime.h>
47 #include <linux/rational.h>
48 #include <linux/reset.h>
49 #include <sound/dmaengine_pcm.h>
50 #include <sound/hdmi-codec.h>
51 #include <sound/pcm_drm_eld.h>
52 #include <sound/pcm_params.h>
53 #include <sound/soc.h>
54 #include "media/cec.h"
57 #include "vc4_hdmi_regs.h"
60 #define VC5_HDMI_HORZA_HFP_SHIFT 16
61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
62 #define VC5_HDMI_HORZA_VPOS BIT(15)
63 #define VC5_HDMI_HORZA_HPOS BIT(14)
64 #define VC5_HDMI_HORZA_HAP_SHIFT 0
65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
67 #define VC5_HDMI_HORZB_HBP_SHIFT 16
68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
69 #define VC5_HDMI_HORZB_HSP_SHIFT 0
70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
72 #define VC5_HDMI_VERTA_VSP_SHIFT 24
73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
74 #define VC5_HDMI_VERTA_VFP_SHIFT 16
75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
76 #define VC5_HDMI_VERTA_VAL_SHIFT 0
77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
100 # define VC4_HD_M_SW_RST BIT(2)
101 # define VC4_HD_M_ENABLE BIT(0)
103 #define HSM_MIN_CLOCK_FREQ 120000000
104 #define CEC_CLOCK_FREQ 40000
106 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
108 static const char * const output_format_str[] = {
109 [VC4_HDMI_OUTPUT_RGB] = "RGB",
110 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0",
111 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2",
112 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4",
115 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
117 if (fmt >= ARRAY_SIZE(output_format_str))
120 return output_format_str[fmt];
123 static unsigned long long
124 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
125 unsigned int bpc, enum vc4_hdmi_output_format fmt);
127 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder)
129 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
130 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
132 lockdep_assert_held(&vc4_hdmi->mutex);
134 if (!display->is_hdmi)
137 if (!display->hdmi.scdc.supported ||
138 !display->hdmi.scdc.scrambling.supported)
144 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
146 enum vc4_hdmi_output_format fmt)
148 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
150 return clock > HDMI_14_MAX_TMDS_CLK;
153 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
154 const struct drm_display_mode *mode)
156 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
158 return !display->is_hdmi ||
159 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
162 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
164 struct drm_info_node *node = (struct drm_info_node *)m->private;
165 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
166 struct drm_device *drm = vc4_hdmi->connector.dev;
167 struct drm_printer p = drm_seq_file_printer(m);
170 if (!drm_dev_enter(drm, &idx))
173 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
174 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
175 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
176 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
177 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
178 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
179 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
180 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
187 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
189 struct drm_device *drm = vc4_hdmi->connector.dev;
194 * We can be called by our bind callback, when the
195 * connector->dev pointer might not be initialised yet.
197 if (drm && !drm_dev_enter(drm, &idx))
200 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
202 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
204 HDMI_WRITE(HDMI_M_CTL, 0);
206 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
208 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
209 VC4_HDMI_SW_RESET_HDMI |
210 VC4_HDMI_SW_RESET_FORMAT_DETECT);
212 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
214 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
220 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
222 struct drm_device *drm = vc4_hdmi->connector.dev;
227 * We can be called by our bind callback, when the
228 * connector->dev pointer might not be initialised yet.
230 if (drm && !drm_dev_enter(drm, &idx))
233 reset_control_reset(vc4_hdmi->reset);
235 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
237 HDMI_WRITE(HDMI_DVP_CTL, 0);
239 HDMI_WRITE(HDMI_CLOCK_STOP,
240 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
242 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
248 #ifdef CONFIG_DRM_VC4_HDMI_CEC
249 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
251 struct drm_device *drm = vc4_hdmi->connector.dev;
252 unsigned long cec_rate;
259 * This function is called by our runtime_resume implementation
260 * and thus at bind time, when we haven't registered our
261 * connector yet and thus don't have a pointer to the DRM
264 if (drm && !drm_dev_enter(drm, &idx))
267 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
269 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
271 value = HDMI_READ(HDMI_CEC_CNTRL_1);
272 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
275 * Set the clock divider: the hsm_clock rate and this divider
276 * setting will give a 40 kHz CEC clock.
278 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
279 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
280 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
282 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
288 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
291 static int reset_pipe(struct drm_crtc *crtc,
292 struct drm_modeset_acquire_ctx *ctx)
294 struct drm_atomic_state *state;
295 struct drm_crtc_state *crtc_state;
298 state = drm_atomic_state_alloc(crtc->dev);
302 state->acquire_ctx = ctx;
304 crtc_state = drm_atomic_get_crtc_state(state, crtc);
305 if (IS_ERR(crtc_state)) {
306 ret = PTR_ERR(crtc_state);
310 crtc_state->connectors_changed = true;
312 ret = drm_atomic_commit(state);
314 drm_atomic_state_put(state);
319 static int vc4_hdmi_reset_link(struct drm_connector *connector,
320 struct drm_modeset_acquire_ctx *ctx)
322 struct drm_device *drm = connector->dev;
323 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
324 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
325 struct drm_connector_state *conn_state;
326 struct drm_crtc_state *crtc_state;
327 struct drm_crtc *crtc;
328 bool scrambling_needed;
335 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
339 conn_state = connector->state;
340 crtc = conn_state->crtc;
344 ret = drm_modeset_lock(&crtc->mutex, ctx);
348 crtc_state = crtc->state;
349 if (!crtc_state->active)
352 if (!vc4_hdmi_supports_scrambling(encoder))
355 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
356 vc4_hdmi->output_bpc,
357 vc4_hdmi->output_format);
358 if (!scrambling_needed)
361 if (conn_state->commit &&
362 !try_wait_for_completion(&conn_state->commit->hw_done))
365 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
367 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
371 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed)
375 * HDMI 2.0 says that one should not send scrambled data
376 * prior to configuring the sink scrambling, and that
377 * TMDS clock/data transmission should be suspended when
378 * changing the TMDS clock rate in the sink. So let's
379 * just do a full modeset here, even though some sinks
380 * would be perfectly happy if were to just reconfigure
381 * the SCDC settings on the fly.
383 return reset_pipe(crtc, ctx);
386 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
387 struct drm_modeset_acquire_ctx *ctx,
388 enum drm_connector_status status)
390 struct drm_connector *connector = &vc4_hdmi->connector;
394 * NOTE: This function should really be called with
395 * vc4_hdmi->mutex held, but doing so results in reentrancy
396 * issues since cec_s_phys_addr_from_edid might call
397 * .adap_enable, which leads to that funtion being called with
400 * A similar situation occurs with
401 * drm_atomic_helper_connector_hdmi_reset_link() that will call
402 * into our KMS hooks if the scrambling was enabled.
404 * Concurrency isn't an issue at the moment since we don't share
405 * any state with any of the other frameworks so we can ignore
409 if (status == connector_status_disconnected) {
410 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
414 edid = drm_get_edid(connector, vc4_hdmi->ddc);
418 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
421 vc4_hdmi_reset_link(connector, ctx);
424 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
425 struct drm_modeset_acquire_ctx *ctx,
428 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
429 enum drm_connector_status status = connector_status_disconnected;
432 * NOTE: This function should really take vc4_hdmi->mutex, but
433 * doing so results in reentrancy issues since
434 * vc4_hdmi_handle_hotplug() can call into other functions that
435 * would take the mutex while it's held here.
437 * Concurrency isn't an issue at the moment since we don't share
438 * any state with any of the other frameworks so we can ignore
442 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
444 if (vc4_hdmi->hpd_gpio) {
445 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
446 status = connector_status_connected;
448 if (vc4_hdmi->variant->hp_detect &&
449 vc4_hdmi->variant->hp_detect(vc4_hdmi))
450 status = connector_status_connected;
453 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
454 pm_runtime_put(&vc4_hdmi->pdev->dev);
459 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
461 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
466 * NOTE: This function should really take vc4_hdmi->mutex, but
467 * doing so results in reentrancy issues since
468 * cec_s_phys_addr_from_edid might call .adap_enable, which
469 * leads to that funtion being called with our mutex held.
471 * Concurrency isn't an issue at the moment since we don't share
472 * any state with any of the other frameworks so we can ignore
476 edid = drm_get_edid(connector, vc4_hdmi->ddc);
477 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
481 drm_connector_update_edid_property(connector, edid);
482 ret = drm_add_edid_modes(connector, edid);
485 if (vc4_hdmi->disable_4kp60) {
486 struct drm_device *drm = connector->dev;
487 const struct drm_display_mode *mode;
489 list_for_each_entry(mode, &connector->probed_modes, head) {
490 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
491 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
492 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
500 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
501 struct drm_atomic_state *state)
503 struct drm_connector_state *old_state =
504 drm_atomic_get_old_connector_state(state, connector);
505 struct drm_connector_state *new_state =
506 drm_atomic_get_new_connector_state(state, connector);
507 struct drm_crtc *crtc = new_state->crtc;
512 if (old_state->colorspace != new_state->colorspace ||
513 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
514 struct drm_crtc_state *crtc_state;
516 crtc_state = drm_atomic_get_crtc_state(state, crtc);
517 if (IS_ERR(crtc_state))
518 return PTR_ERR(crtc_state);
520 crtc_state->mode_changed = true;
526 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
528 struct vc4_hdmi_connector_state *old_state =
529 conn_state_to_vc4_hdmi_conn_state(connector->state);
530 struct vc4_hdmi_connector_state *new_state =
531 kzalloc(sizeof(*new_state), GFP_KERNEL);
533 if (connector->state)
534 __drm_atomic_helper_connector_destroy_state(connector->state);
537 __drm_atomic_helper_connector_reset(connector, &new_state->base);
542 new_state->base.max_bpc = 8;
543 new_state->base.max_requested_bpc = 8;
544 new_state->output_format = VC4_HDMI_OUTPUT_RGB;
545 drm_atomic_helper_connector_tv_reset(connector);
548 static struct drm_connector_state *
549 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
551 struct drm_connector_state *conn_state = connector->state;
552 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
553 struct vc4_hdmi_connector_state *new_state;
555 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
559 new_state->tmds_char_rate = vc4_state->tmds_char_rate;
560 new_state->output_bpc = vc4_state->output_bpc;
561 new_state->output_format = vc4_state->output_format;
562 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
564 return &new_state->base;
567 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
568 .fill_modes = drm_helper_probe_single_connector_modes,
569 .reset = vc4_hdmi_connector_reset,
570 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
571 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
574 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
575 .detect_ctx = vc4_hdmi_connector_detect_ctx,
576 .get_modes = vc4_hdmi_connector_get_modes,
577 .atomic_check = vc4_hdmi_connector_atomic_check,
580 static int vc4_hdmi_connector_init(struct drm_device *dev,
581 struct vc4_hdmi *vc4_hdmi)
583 struct drm_connector *connector = &vc4_hdmi->connector;
584 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
587 ret = drmm_connector_init(dev, connector,
588 &vc4_hdmi_connector_funcs,
589 DRM_MODE_CONNECTOR_HDMIA,
594 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
597 * Some of the properties below require access to state, like bpc.
598 * Allocate some default initial connector state with our reset helper.
600 if (connector->funcs->reset)
601 connector->funcs->reset(connector);
603 /* Create and attach TV margin props to this connector. */
604 ret = drm_mode_create_tv_margin_properties(dev);
608 ret = drm_mode_create_hdmi_colorspace_property(connector);
612 drm_connector_attach_colorspace_property(connector);
613 drm_connector_attach_tv_margin_properties(connector);
614 drm_connector_attach_max_bpc_property(connector, 8, 12);
616 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
617 DRM_CONNECTOR_POLL_DISCONNECT);
619 connector->interlace_allowed = 1;
620 connector->doublescan_allowed = 0;
621 connector->stereo_allowed = 1;
623 if (vc4_hdmi->variant->supports_hdr)
624 drm_connector_attach_hdr_output_metadata_property(connector);
626 drm_connector_attach_encoder(connector, encoder);
631 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
632 enum hdmi_infoframe_type type,
635 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
636 struct drm_device *drm = vc4_hdmi->connector.dev;
637 u32 packet_id = type - 0x80;
642 if (!drm_dev_enter(drm, &idx))
645 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
646 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
647 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
648 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
651 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
652 BIT(packet_id)), 100);
659 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
660 union hdmi_infoframe *frame)
662 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
663 struct drm_device *drm = vc4_hdmi->connector.dev;
664 u32 packet_id = frame->any.type - 0x80;
665 const struct vc4_hdmi_register *ram_packet_start =
666 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
667 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
668 u32 packet_reg_next = ram_packet_start->offset +
669 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
670 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
671 ram_packet_start->reg);
672 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
678 if (!drm_dev_enter(drm, &idx))
681 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
682 VC4_HDMI_RAM_PACKET_ENABLE),
683 "Packet RAM has to be on to store the packet.");
685 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
689 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
691 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
695 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
697 for (i = 0; i < len; i += 7) {
698 writel(buffer[i + 0] << 0 |
704 writel(buffer[i + 3] << 0 |
706 buffer[i + 5] << 16 |
713 * clear remainder of packet ram as it's included in the
714 * infoframe and triggers a checksum error on hdmi analyser
716 for (; packet_reg < packet_reg_next; packet_reg += 4)
717 writel(0, base + packet_reg);
719 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
720 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
722 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
724 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
725 BIT(packet_id)), 100);
727 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
733 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
734 enum vc4_hdmi_output_format fmt)
737 case VC4_HDMI_OUTPUT_RGB:
738 frame->colorspace = HDMI_COLORSPACE_RGB;
741 case VC4_HDMI_OUTPUT_YUV420:
742 frame->colorspace = HDMI_COLORSPACE_YUV420;
745 case VC4_HDMI_OUTPUT_YUV422:
746 frame->colorspace = HDMI_COLORSPACE_YUV422;
749 case VC4_HDMI_OUTPUT_YUV444:
750 frame->colorspace = HDMI_COLORSPACE_YUV444;
758 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
760 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
761 struct drm_connector *connector = &vc4_hdmi->connector;
762 struct drm_connector_state *cstate = connector->state;
763 struct vc4_hdmi_connector_state *vc4_state =
764 conn_state_to_vc4_hdmi_conn_state(cstate);
765 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
766 union hdmi_infoframe frame;
769 lockdep_assert_held(&vc4_hdmi->mutex);
771 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
774 DRM_ERROR("couldn't fill AVI infoframe\n");
778 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
780 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
781 HDMI_QUANTIZATION_RANGE_FULL :
782 HDMI_QUANTIZATION_RANGE_LIMITED);
783 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
784 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
785 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
787 vc4_hdmi_write_infoframe(encoder, &frame);
790 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
792 union hdmi_infoframe frame;
795 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
797 DRM_ERROR("couldn't fill SPD infoframe\n");
801 frame.spd.sdi = HDMI_SPD_SDI_PC;
803 vc4_hdmi_write_infoframe(encoder, &frame);
806 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
808 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
809 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
810 union hdmi_infoframe frame;
812 memcpy(&frame.audio, audio, sizeof(*audio));
814 if (vc4_hdmi->packet_ram_enabled)
815 vc4_hdmi_write_infoframe(encoder, &frame);
818 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
820 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
821 struct drm_connector *connector = &vc4_hdmi->connector;
822 struct drm_connector_state *conn_state = connector->state;
823 union hdmi_infoframe frame;
825 lockdep_assert_held(&vc4_hdmi->mutex);
827 if (!vc4_hdmi->variant->supports_hdr)
830 if (!conn_state->hdr_output_metadata)
833 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
836 vc4_hdmi_write_infoframe(encoder, &frame);
839 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
841 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
843 lockdep_assert_held(&vc4_hdmi->mutex);
845 vc4_hdmi_set_avi_infoframe(encoder);
846 vc4_hdmi_set_spd_infoframe(encoder);
848 * If audio was streaming, then we need to reenabled the audio
849 * infoframe here during encoder_enable.
851 if (vc4_hdmi->audio.streaming)
852 vc4_hdmi_set_audio_infoframe(encoder);
854 vc4_hdmi_set_hdr_infoframe(encoder);
857 #define SCRAMBLING_POLLING_DELAY_MS 1000
859 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
861 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
862 struct drm_device *drm = vc4_hdmi->connector.dev;
863 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
867 lockdep_assert_held(&vc4_hdmi->mutex);
869 if (!vc4_hdmi_supports_scrambling(encoder))
872 if (!vc4_hdmi_mode_needs_scrambling(mode,
873 vc4_hdmi->output_bpc,
874 vc4_hdmi->output_format))
877 if (!drm_dev_enter(drm, &idx))
880 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
881 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
883 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
884 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
885 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
886 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
890 vc4_hdmi->scdc_enabled = true;
892 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
893 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
896 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
898 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
899 struct drm_device *drm = vc4_hdmi->connector.dev;
903 lockdep_assert_held(&vc4_hdmi->mutex);
905 if (!vc4_hdmi->scdc_enabled)
908 vc4_hdmi->scdc_enabled = false;
910 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
911 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
913 if (!drm_dev_enter(drm, &idx))
916 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
917 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
918 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
919 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
921 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
922 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
927 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
929 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
933 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
936 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
937 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
939 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
940 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
943 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
944 struct drm_atomic_state *state)
946 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
947 struct drm_device *drm = vc4_hdmi->connector.dev;
951 mutex_lock(&vc4_hdmi->mutex);
953 vc4_hdmi->packet_ram_enabled = false;
955 if (!drm_dev_enter(drm, &idx))
958 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
960 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
962 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
964 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
968 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
969 HDMI_WRITE(HDMI_VID_CTL,
970 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
971 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
973 vc4_hdmi_disable_scrambling(encoder);
978 mutex_unlock(&vc4_hdmi->mutex);
981 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
982 struct drm_atomic_state *state)
984 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
985 struct drm_device *drm = vc4_hdmi->connector.dev;
990 mutex_lock(&vc4_hdmi->mutex);
992 if (!drm_dev_enter(drm, &idx))
995 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
996 HDMI_WRITE(HDMI_VID_CTL,
997 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
998 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1000 if (vc4_hdmi->variant->phy_disable)
1001 vc4_hdmi->variant->phy_disable(vc4_hdmi);
1003 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
1004 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1006 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1008 DRM_ERROR("Failed to release power domain: %d\n", ret);
1013 mutex_unlock(&vc4_hdmi->mutex);
1016 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1017 struct drm_connector_state *state,
1018 const struct drm_display_mode *mode)
1020 struct drm_device *drm = vc4_hdmi->connector.dev;
1021 unsigned long flags;
1025 if (!drm_dev_enter(drm, &idx))
1028 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1030 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1031 VC4_HD_CSC_CTL_ORDER);
1033 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
1034 /* CEA VICs other than #1 requre limited range RGB
1035 * output unless overridden by an AVI infoframe.
1036 * Apply a colorspace conversion to squash 0-255 down
1037 * to 16-235. The matrix here is:
1044 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1045 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1046 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1047 VC4_HD_CSC_CTL_MODE);
1049 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1050 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1051 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1052 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1053 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1054 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1057 /* The RGB order applies even when CSC is disabled. */
1058 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1060 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1066 * If we need to output Full Range RGB, then use the unity matrix
1072 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1074 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
1075 { 0x2000, 0x0000, 0x0000, 0x0000 },
1076 { 0x0000, 0x2000, 0x0000, 0x0000 },
1077 { 0x0000, 0x0000, 0x2000, 0x0000 },
1081 * CEA VICs other than #1 require limited range RGB output unless
1082 * overridden by an AVI infoframe. Apply a colorspace conversion to
1083 * squash 0-255 down to 16-235. The matrix here is:
1089 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1091 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
1092 { 0x1b80, 0x0000, 0x0000, 0x0400 },
1093 { 0x0000, 0x1b80, 0x0000, 0x0400 },
1094 { 0x0000, 0x0000, 0x1b80, 0x0400 },
1098 * Conversion between Full Range RGB and Full Range YUV422 using the
1102 * [ 0.181906 0.611804 0.061758 16 ]
1103 * [ -0.100268 -0.337232 0.437500 128 ]
1104 * [ 0.437500 -0.397386 -0.040114 128 ]
1106 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1108 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = {
1109 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1110 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1111 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1115 * Conversion between Full Range RGB and Full Range YUV444 using the
1118 * [ -0.100268 -0.337232 0.437500 128 ]
1119 * [ 0.437500 -0.397386 -0.040114 128 ]
1120 * [ 0.181906 0.611804 0.061758 16 ]
1122 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1124 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = {
1125 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1126 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1127 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1130 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1131 const u16 coeffs[3][4])
1133 lockdep_assert_held(&vc4_hdmi->hw_lock);
1135 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1136 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1137 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1138 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1139 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1140 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1143 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1144 struct drm_connector_state *state,
1145 const struct drm_display_mode *mode)
1147 struct drm_device *drm = vc4_hdmi->connector.dev;
1148 struct vc4_hdmi_connector_state *vc4_state =
1149 conn_state_to_vc4_hdmi_conn_state(state);
1150 unsigned long flags;
1152 u32 if_xbar = 0x543210;
1153 u32 csc_chan_ctl = 0;
1154 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1155 VC5_MT_CP_CSC_CTL_MODE);
1158 if (!drm_dev_enter(drm, &idx))
1161 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1163 switch (vc4_state->output_format) {
1164 case VC4_HDMI_OUTPUT_YUV444:
1165 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709);
1168 case VC4_HDMI_OUTPUT_YUV422:
1169 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1170 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1171 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1172 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1174 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1175 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1177 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1178 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1180 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709);
1183 case VC4_HDMI_OUTPUT_RGB:
1186 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
1187 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
1189 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
1196 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1197 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1198 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1199 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1201 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1206 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1207 struct drm_connector_state *state,
1208 const struct drm_display_mode *mode)
1210 struct drm_device *drm = vc4_hdmi->connector.dev;
1211 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1212 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1213 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1214 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1215 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1216 VC4_HDMI_VERTA_VSP) |
1217 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1218 VC4_HDMI_VERTA_VFP) |
1219 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1220 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1221 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1223 VC4_HDMI_VERTB_VBP));
1224 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1225 VC4_SET_FIELD(mode->crtc_vtotal -
1226 mode->crtc_vsync_end,
1227 VC4_HDMI_VERTB_VBP));
1228 unsigned long flags;
1232 if (!drm_dev_enter(drm, &idx))
1235 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1237 HDMI_WRITE(HDMI_HORZA,
1238 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1239 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1240 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1241 VC4_HDMI_HORZA_HAP));
1243 HDMI_WRITE(HDMI_HORZB,
1244 VC4_SET_FIELD((mode->htotal -
1245 mode->hsync_end) * pixel_rep,
1246 VC4_HDMI_HORZB_HBP) |
1247 VC4_SET_FIELD((mode->hsync_end -
1248 mode->hsync_start) * pixel_rep,
1249 VC4_HDMI_HORZB_HSP) |
1250 VC4_SET_FIELD((mode->hsync_start -
1251 mode->hdisplay) * pixel_rep,
1252 VC4_HDMI_HORZB_HFP));
1254 HDMI_WRITE(HDMI_VERTA0, verta);
1255 HDMI_WRITE(HDMI_VERTA1, verta);
1257 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1258 HDMI_WRITE(HDMI_VERTB1, vertb);
1260 reg = HDMI_READ(HDMI_MISC_CONTROL);
1261 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1262 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1263 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1265 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1270 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1271 struct drm_connector_state *state,
1272 const struct drm_display_mode *mode)
1274 struct drm_device *drm = vc4_hdmi->connector.dev;
1275 const struct vc4_hdmi_connector_state *vc4_state =
1276 conn_state_to_vc4_hdmi_conn_state(state);
1277 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1278 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1279 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1280 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1281 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1282 VC5_HDMI_VERTA_VSP) |
1283 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1284 VC5_HDMI_VERTA_VFP) |
1285 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1286 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1287 VC5_HDMI_VERTB_VSPO) |
1288 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
1289 VC4_HDMI_VERTB_VBP));
1290 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1291 VC4_SET_FIELD(mode->crtc_vtotal -
1292 mode->crtc_vsync_end - interlaced,
1293 VC4_HDMI_VERTB_VBP));
1294 unsigned long flags;
1300 if (!drm_dev_enter(drm, &idx))
1303 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1305 HDMI_WRITE(HDMI_HORZA,
1306 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1307 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1308 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1309 VC5_HDMI_HORZA_HAP) |
1310 VC4_SET_FIELD((mode->hsync_start -
1311 mode->hdisplay) * pixel_rep,
1312 VC5_HDMI_HORZA_HFP));
1314 HDMI_WRITE(HDMI_HORZB,
1315 VC4_SET_FIELD((mode->htotal -
1316 mode->hsync_end) * pixel_rep,
1317 VC5_HDMI_HORZB_HBP) |
1318 VC4_SET_FIELD((mode->hsync_end -
1319 mode->hsync_start) * pixel_rep,
1320 VC5_HDMI_HORZB_HSP));
1322 HDMI_WRITE(HDMI_VERTA0, verta);
1323 HDMI_WRITE(HDMI_VERTA1, verta);
1325 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1326 HDMI_WRITE(HDMI_VERTB1, vertb);
1328 switch (vc4_state->output_bpc) {
1345 * YCC422 is always 36-bit and not considered deep colour so
1346 * doesn't signal in GCP.
1348 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1353 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1354 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1355 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1356 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1357 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1358 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1360 reg = HDMI_READ(HDMI_GCP_WORD_1);
1361 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1362 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1363 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1365 reg = HDMI_READ(HDMI_GCP_CONFIG);
1366 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1367 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
1368 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1370 reg = HDMI_READ(HDMI_MISC_CONTROL);
1371 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1372 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1373 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1375 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1377 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1382 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1384 struct drm_device *drm = vc4_hdmi->connector.dev;
1385 unsigned long flags;
1390 if (!drm_dev_enter(drm, &idx))
1393 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1395 drift = HDMI_READ(HDMI_FIFO_CTL);
1396 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1398 HDMI_WRITE(HDMI_FIFO_CTL,
1399 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1400 HDMI_WRITE(HDMI_FIFO_CTL,
1401 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1403 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1405 usleep_range(1000, 1100);
1407 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1409 HDMI_WRITE(HDMI_FIFO_CTL,
1410 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1411 HDMI_WRITE(HDMI_FIFO_CTL,
1412 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1414 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1416 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1417 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1418 WARN_ONCE(ret, "Timeout waiting for "
1419 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1424 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1425 struct drm_atomic_state *state)
1427 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1428 struct drm_device *drm = vc4_hdmi->connector.dev;
1429 struct drm_connector *connector = &vc4_hdmi->connector;
1430 struct drm_connector_state *conn_state =
1431 drm_atomic_get_new_connector_state(state, connector);
1432 struct vc4_hdmi_connector_state *vc4_conn_state =
1433 conn_state_to_vc4_hdmi_conn_state(conn_state);
1434 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1435 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1436 unsigned long bvb_rate, hsm_rate;
1437 unsigned long flags;
1441 mutex_lock(&vc4_hdmi->mutex);
1443 if (!drm_dev_enter(drm, &idx))
1447 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1448 * be faster than pixel clock, infinitesimally faster, tested in
1449 * simulation. Otherwise, exact value is unimportant for HDMI
1450 * operation." This conflicts with bcm2835's vc4 documentation, which
1451 * states HSM's clock has to be at least 108% of the pixel clock.
1453 * Real life tests reveal that vc4's firmware statement holds up, and
1454 * users are able to use pixel clocks closer to HSM's, namely for
1455 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1456 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1459 * Additionally, the AXI clock needs to be at least 25% of
1460 * pixel clock, but HSM ends up being the limiting factor.
1462 hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101);
1463 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1465 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1469 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1471 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1475 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1477 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1478 goto err_put_runtime_pm;
1481 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1483 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1484 goto err_put_runtime_pm;
1488 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1490 if (tmds_char_rate > 297000000)
1491 bvb_rate = 300000000;
1492 else if (tmds_char_rate > 148500000)
1493 bvb_rate = 150000000;
1495 bvb_rate = 75000000;
1497 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1499 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1500 goto err_disable_pixel_clock;
1503 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1505 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1506 goto err_disable_pixel_clock;
1509 if (vc4_hdmi->variant->phy_init)
1510 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1512 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1514 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1515 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1516 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1517 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1519 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1521 if (vc4_hdmi->variant->set_timings)
1522 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1526 mutex_unlock(&vc4_hdmi->mutex);
1530 err_disable_pixel_clock:
1531 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1533 pm_runtime_put(&vc4_hdmi->pdev->dev);
1537 mutex_unlock(&vc4_hdmi->mutex);
1541 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1542 struct drm_atomic_state *state)
1544 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1545 struct drm_device *drm = vc4_hdmi->connector.dev;
1546 struct drm_connector *connector = &vc4_hdmi->connector;
1547 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1548 struct drm_connector_state *conn_state =
1549 drm_atomic_get_new_connector_state(state, connector);
1550 unsigned long flags;
1553 mutex_lock(&vc4_hdmi->mutex);
1555 if (!drm_dev_enter(drm, &idx))
1558 if (vc4_hdmi->variant->csc_setup)
1559 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1561 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1562 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1563 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1568 mutex_unlock(&vc4_hdmi->mutex);
1571 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1572 struct drm_atomic_state *state)
1574 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1575 struct drm_device *drm = vc4_hdmi->connector.dev;
1576 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1577 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1578 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1579 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1580 unsigned long flags;
1584 mutex_lock(&vc4_hdmi->mutex);
1586 if (!drm_dev_enter(drm, &idx))
1589 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1591 HDMI_WRITE(HDMI_VID_CTL,
1592 VC4_HD_VID_CTL_ENABLE |
1593 VC4_HD_VID_CTL_CLRRGB |
1594 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1595 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1596 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1597 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1599 HDMI_WRITE(HDMI_VID_CTL,
1600 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1602 if (display->is_hdmi) {
1603 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1604 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1605 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1607 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1609 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1610 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1611 WARN_ONCE(ret, "Timeout waiting for "
1612 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1614 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1615 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1616 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1617 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1618 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1619 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1621 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1623 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1624 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1625 WARN_ONCE(ret, "Timeout waiting for "
1626 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1629 if (display->is_hdmi) {
1630 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1632 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1633 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1635 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1636 VC4_HDMI_RAM_PACKET_ENABLE);
1638 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1639 vc4_hdmi->packet_ram_enabled = true;
1641 vc4_hdmi_set_infoframes(encoder);
1644 vc4_hdmi_recenter_fifo(vc4_hdmi);
1645 vc4_hdmi_enable_scrambling(encoder);
1650 mutex_unlock(&vc4_hdmi->mutex);
1653 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1654 struct drm_crtc_state *crtc_state,
1655 struct drm_connector_state *conn_state)
1657 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1658 struct vc4_hdmi_connector_state *vc4_state =
1659 conn_state_to_vc4_hdmi_conn_state(conn_state);
1661 mutex_lock(&vc4_hdmi->mutex);
1662 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1663 &crtc_state->adjusted_mode);
1664 vc4_hdmi->output_bpc = vc4_state->output_bpc;
1665 vc4_hdmi->output_format = vc4_state->output_format;
1666 mutex_unlock(&vc4_hdmi->mutex);
1670 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1671 const struct drm_display_info *info,
1672 const struct drm_display_mode *mode,
1673 unsigned int format, unsigned int bpc)
1675 struct drm_device *dev = vc4_hdmi->connector.dev;
1676 u8 vic = drm_match_cea_mode(mode);
1678 if (vic == 1 && bpc != 8) {
1679 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1683 if (!info->is_hdmi &&
1684 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1685 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1690 case VC4_HDMI_OUTPUT_RGB:
1691 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1693 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1696 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1697 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1701 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1702 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1706 drm_dbg(dev, "RGB format supported in that configuration.\n");
1710 case VC4_HDMI_OUTPUT_YUV422:
1711 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1713 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1714 drm_dbg(dev, "Sink doesn't support YUV422.\n");
1719 drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1723 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1727 case VC4_HDMI_OUTPUT_YUV444:
1728 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1730 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1731 drm_dbg(dev, "Sink doesn't support YUV444.\n");
1735 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1736 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1740 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1741 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1745 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1753 static enum drm_mode_status
1754 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1755 unsigned long long clock)
1757 const struct drm_connector *connector = &vc4_hdmi->connector;
1758 const struct drm_display_info *info = &connector->display_info;
1760 if (clock > vc4_hdmi->variant->max_pixel_clock)
1761 return MODE_CLOCK_HIGH;
1763 if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK)
1764 return MODE_CLOCK_HIGH;
1766 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1767 return MODE_CLOCK_HIGH;
1772 static unsigned long long
1773 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1775 enum vc4_hdmi_output_format fmt)
1777 unsigned long long clock = mode->clock * 1000ULL;
1779 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1782 if (fmt == VC4_HDMI_OUTPUT_YUV422)
1785 clock = clock * bpc;
1792 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1793 struct vc4_hdmi_connector_state *vc4_state,
1794 const struct drm_display_mode *mode,
1795 unsigned int bpc, unsigned int fmt)
1797 unsigned long long clock;
1799 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
1800 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
1803 vc4_state->tmds_char_rate = clock;
1809 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
1810 struct vc4_hdmi_connector_state *vc4_state,
1811 const struct drm_display_mode *mode,
1814 struct drm_device *dev = vc4_hdmi->connector.dev;
1815 const struct drm_connector *connector = &vc4_hdmi->connector;
1816 const struct drm_display_info *info = &connector->display_info;
1817 unsigned int format;
1819 drm_dbg(dev, "Trying with an RGB output\n");
1821 format = VC4_HDMI_OUTPUT_RGB;
1822 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1825 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1828 vc4_state->output_format = format;
1833 drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
1835 format = VC4_HDMI_OUTPUT_YUV422;
1836 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1839 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1842 vc4_state->output_format = format;
1847 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
1853 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
1854 struct vc4_hdmi_connector_state *vc4_state,
1855 const struct drm_display_mode *mode)
1857 struct drm_device *dev = vc4_hdmi->connector.dev;
1858 struct drm_connector_state *conn_state = &vc4_state->base;
1859 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
1863 for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
1864 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
1866 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
1871 vc4_state->output_bpc = bpc;
1874 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
1875 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1876 vc4_state->output_bpc,
1877 vc4_hdmi_output_fmt_str(vc4_state->output_format),
1878 vc4_state->tmds_char_rate);
1886 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1887 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1889 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1890 struct drm_crtc_state *crtc_state,
1891 struct drm_connector_state *conn_state)
1893 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1894 struct drm_connector *connector = &vc4_hdmi->connector;
1895 struct drm_connector_state *old_conn_state =
1896 drm_atomic_get_old_connector_state(conn_state->state, connector);
1897 struct vc4_hdmi_connector_state *old_vc4_state =
1898 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
1899 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1900 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1901 unsigned long long tmds_char_rate = mode->clock * 1000;
1902 unsigned long long tmds_bit_rate;
1905 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1906 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1907 /* Only try to fixup DBLCLK modes to get 480i and 576i
1909 * A generic solution for all modes with odd horizontal
1910 * timing values seems impossible based on trying to
1911 * solve it for 1366x768 monitors.
1913 if ((mode->hsync_start - mode->hdisplay) & 1)
1914 mode->hsync_start--;
1915 if ((mode->hsync_end - mode->hsync_start) & 1)
1919 /* Now check whether we still have odd values remaining */
1920 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1921 (mode->hsync_end % 2) || (mode->htotal % 2))
1926 * The 1440p@60 pixel rate is in the same range than the first
1927 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1928 * bandwidth). Slightly lower the frequency to bring it out of
1931 tmds_bit_rate = tmds_char_rate * 10;
1932 if (vc4_hdmi->disable_wifi_frequencies &&
1933 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1934 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1935 mode->clock = 238560;
1936 tmds_char_rate = mode->clock * 1000;
1939 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
1943 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
1944 if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
1945 vc4_state->output_format != old_vc4_state->output_format)
1946 crtc_state->mode_changed = true;
1951 static enum drm_mode_status
1952 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1953 const struct drm_display_mode *mode)
1955 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1957 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1958 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1959 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1960 (mode->hsync_end % 2) || (mode->htotal % 2)))
1961 return MODE_H_ILLEGAL;
1963 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000);
1966 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1967 .atomic_check = vc4_hdmi_encoder_atomic_check,
1968 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1969 .mode_valid = vc4_hdmi_encoder_mode_valid,
1972 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1974 struct drm_device *drm = encoder->dev;
1975 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1976 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1979 ret = vc4_debugfs_add_file(drm->primary, variant->debugfs_name,
1980 vc4_hdmi_debugfs_regs,
1988 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
1989 .late_register = vc4_hdmi_late_register,
1992 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1995 u32 channel_map = 0;
1997 for (i = 0; i < 8; i++) {
1998 if (channel_mask & BIT(i))
1999 channel_map |= i << (3 * i);
2004 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2007 u32 channel_map = 0;
2009 for (i = 0; i < 8; i++) {
2010 if (channel_mask & BIT(i))
2011 channel_map |= i << (4 * i);
2016 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2018 struct drm_device *drm = vc4_hdmi->connector.dev;
2019 unsigned long flags;
2023 if (!drm_dev_enter(drm, &idx))
2026 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2027 hotplug = HDMI_READ(HDMI_HOTPLUG);
2028 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2032 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2035 /* HDMI audio codec callbacks */
2036 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2037 unsigned int samplerate)
2039 struct drm_device *drm = vc4_hdmi->connector.dev;
2041 unsigned long flags;
2045 if (!drm_dev_enter(drm, &idx))
2048 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2049 rational_best_approximation(hsm_clock, samplerate,
2050 VC4_HD_MAI_SMP_N_MASK >>
2051 VC4_HD_MAI_SMP_N_SHIFT,
2052 (VC4_HD_MAI_SMP_M_MASK >>
2053 VC4_HD_MAI_SMP_M_SHIFT) + 1,
2056 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2057 HDMI_WRITE(HDMI_MAI_SMP,
2058 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2059 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2060 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2065 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2067 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2071 lockdep_assert_held(&vc4_hdmi->mutex);
2072 lockdep_assert_held(&vc4_hdmi->hw_lock);
2074 n = 128 * samplerate / 1000;
2075 tmp = (u64)(mode->clock * 1000) * n;
2076 do_div(tmp, 128 * samplerate);
2079 HDMI_WRITE(HDMI_CRP_CFG,
2080 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2081 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2084 * We could get slightly more accurate clocks in some cases by
2085 * providing a CTS_1 value. The two CTS values are alternated
2086 * between based on the period fields
2088 HDMI_WRITE(HDMI_CTS_0, cts);
2089 HDMI_WRITE(HDMI_CTS_1, cts);
2092 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2094 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2096 return snd_soc_card_get_drvdata(card);
2099 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2101 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
2103 lockdep_assert_held(&vc4_hdmi->mutex);
2106 * If the encoder is currently in DVI mode, treat the codec DAI
2109 if (!display->is_hdmi)
2115 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2117 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2118 struct drm_device *drm = vc4_hdmi->connector.dev;
2119 unsigned long flags;
2123 mutex_lock(&vc4_hdmi->mutex);
2125 if (!drm_dev_enter(drm, &idx)) {
2130 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2135 vc4_hdmi->audio.streaming = true;
2137 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2138 HDMI_WRITE(HDMI_MAI_CTL,
2139 VC4_HD_MAI_CTL_RESET |
2140 VC4_HD_MAI_CTL_FLUSH |
2141 VC4_HD_MAI_CTL_DLATE |
2142 VC4_HD_MAI_CTL_ERRORE |
2143 VC4_HD_MAI_CTL_ERRORF);
2144 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2146 if (vc4_hdmi->variant->phy_rng_enable)
2147 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2152 mutex_unlock(&vc4_hdmi->mutex);
2157 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2159 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2160 struct device *dev = &vc4_hdmi->pdev->dev;
2161 unsigned long flags;
2164 lockdep_assert_held(&vc4_hdmi->mutex);
2166 vc4_hdmi->audio.streaming = false;
2167 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2169 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2171 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2173 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2174 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2175 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2177 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2180 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2182 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2183 struct drm_device *drm = vc4_hdmi->connector.dev;
2184 unsigned long flags;
2187 mutex_lock(&vc4_hdmi->mutex);
2189 if (!drm_dev_enter(drm, &idx))
2192 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2194 HDMI_WRITE(HDMI_MAI_CTL,
2195 VC4_HD_MAI_CTL_DLATE |
2196 VC4_HD_MAI_CTL_ERRORE |
2197 VC4_HD_MAI_CTL_ERRORF);
2199 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2201 if (vc4_hdmi->variant->phy_rng_disable)
2202 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2204 vc4_hdmi->audio.streaming = false;
2205 vc4_hdmi_audio_reset(vc4_hdmi);
2210 mutex_unlock(&vc4_hdmi->mutex);
2213 static int sample_rate_to_mai_fmt(int samplerate)
2215 switch (samplerate) {
2217 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2219 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2221 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2223 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2225 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2227 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2229 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2231 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2233 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2235 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2237 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2239 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2241 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2243 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2245 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2247 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2251 /* HDMI audio codec callbacks */
2252 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2253 struct hdmi_codec_daifmt *daifmt,
2254 struct hdmi_codec_params *params)
2256 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2257 struct drm_device *drm = vc4_hdmi->connector.dev;
2258 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2259 unsigned int sample_rate = params->sample_rate;
2260 unsigned int channels = params->channels;
2261 unsigned long flags;
2262 u32 audio_packet_config, channel_mask;
2264 u32 mai_audio_format;
2265 u32 mai_sample_rate;
2269 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2270 sample_rate, params->sample_width, channels);
2272 mutex_lock(&vc4_hdmi->mutex);
2274 if (!drm_dev_enter(drm, &idx)) {
2279 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2284 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2286 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2287 HDMI_WRITE(HDMI_MAI_CTL,
2288 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2289 VC4_HD_MAI_CTL_WHOLSMP |
2290 VC4_HD_MAI_CTL_CHALIGN |
2291 VC4_HD_MAI_CTL_ENABLE);
2293 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2294 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2295 params->channels == 8)
2296 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2298 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2299 HDMI_WRITE(HDMI_MAI_FMT,
2300 VC4_SET_FIELD(mai_sample_rate,
2301 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2302 VC4_SET_FIELD(mai_audio_format,
2303 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2305 /* The B frame identifier should match the value used by alsa-lib (8) */
2306 audio_packet_config =
2307 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2308 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2309 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2311 channel_mask = GENMASK(channels - 1, 0);
2312 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2313 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2315 /* Set the MAI threshold */
2316 HDMI_WRITE(HDMI_MAI_THR,
2317 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2318 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2319 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2320 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2322 HDMI_WRITE(HDMI_MAI_CONFIG,
2323 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2324 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2325 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2327 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2328 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2329 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2331 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2333 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2335 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
2336 vc4_hdmi_set_audio_infoframe(encoder);
2341 mutex_unlock(&vc4_hdmi->mutex);
2346 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2347 .name = "vc4-hdmi-cpu-dai-component",
2348 .legacy_dai_naming = 1,
2351 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2353 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2355 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2360 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2361 .name = "vc4-hdmi-cpu-dai",
2362 .probe = vc4_hdmi_audio_cpu_dai_probe,
2364 .stream_name = "Playback",
2367 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2368 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2369 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2370 SNDRV_PCM_RATE_192000,
2371 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2375 static const struct snd_dmaengine_pcm_config pcm_conf = {
2376 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2377 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2380 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2381 uint8_t *buf, size_t len)
2383 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2384 struct drm_connector *connector = &vc4_hdmi->connector;
2386 mutex_lock(&vc4_hdmi->mutex);
2387 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2388 mutex_unlock(&vc4_hdmi->mutex);
2393 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2394 .get_eld = vc4_hdmi_audio_get_eld,
2395 .prepare = vc4_hdmi_audio_prepare,
2396 .audio_shutdown = vc4_hdmi_audio_shutdown,
2397 .audio_startup = vc4_hdmi_audio_startup,
2400 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2401 .ops = &vc4_hdmi_codec_ops,
2402 .max_i2s_channels = 8,
2406 static void vc4_hdmi_audio_codec_release(void *ptr)
2408 struct vc4_hdmi *vc4_hdmi = ptr;
2410 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2411 vc4_hdmi->audio.codec_pdev = NULL;
2414 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2416 const struct vc4_hdmi_register *mai_data =
2417 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2418 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2419 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2420 struct device *dev = &vc4_hdmi->pdev->dev;
2421 struct platform_device *codec_pdev;
2427 * ASoC makes it a bit hard to retrieve a pointer to the
2428 * vc4_hdmi structure. Registering the card will overwrite our
2429 * device drvdata with a pointer to the snd_soc_card structure,
2430 * which can then be used to retrieve whatever drvdata we want
2433 * However, that doesn't fly in the case where we wouldn't
2434 * register an ASoC card (because of an old DT that is missing
2435 * the dmas properties for example), then the card isn't
2436 * registered and the device drvdata wouldn't be set.
2438 * We can deal with both cases by making sure a snd_soc_card
2439 * pointer and a vc4_hdmi structure are pointing to the same
2440 * memory address, so we can treat them indistinctly without any
2443 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2444 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2446 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2448 "'dmas' DT property is missing or empty, no HDMI audio\n");
2452 if (mai_data->reg != VC4_HD) {
2453 WARN_ONCE(true, "MAI isn't in the HD block\n");
2458 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2459 * the bus address specified in the DT, because the physical address
2460 * (the one returned by platform_get_resource()) is not appropriate
2461 * for DMA transfers.
2462 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2464 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2465 /* Before BCM2711, we don't have a named register range */
2469 addr = of_get_address(dev->of_node, index, NULL, NULL);
2471 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2472 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2473 vc4_hdmi->audio.dma_data.maxburst = 2;
2476 * NOTE: Strictly speaking, we should probably use a DRM-managed
2477 * registration there to avoid removing all the audio components
2478 * by the time the driver doesn't have any user anymore.
2480 * However, the ASoC core uses a number of devm_kzalloc calls
2481 * when registering, even when using non-device-managed
2482 * functions (such as in snd_soc_register_component()).
2484 * If we call snd_soc_unregister_component() in a DRM-managed
2485 * action, the device-managed actions have already been executed
2486 * and thus we would access memory that has been freed.
2488 * Using device-managed hooks here probably leaves us open to a
2489 * bunch of issues if userspace still has a handle on the ALSA
2490 * device when the device is removed. However, this is mitigated
2491 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2492 * path to prevent the access to the device resources if it
2493 * isn't there anymore.
2495 * Then, the vc4_hdmi structure is DRM-managed and thus only
2496 * freed whenever the last user has closed the DRM device file.
2497 * It should thus outlive ALSA in most situations.
2499 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2501 dev_err(dev, "Could not register PCM component: %d\n", ret);
2505 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2506 &vc4_hdmi_audio_cpu_dai_drv, 1);
2508 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2512 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2513 PLATFORM_DEVID_AUTO,
2514 &vc4_hdmi_codec_pdata,
2515 sizeof(vc4_hdmi_codec_pdata));
2516 if (IS_ERR(codec_pdev)) {
2517 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2518 return PTR_ERR(codec_pdev);
2520 vc4_hdmi->audio.codec_pdev = codec_pdev;
2522 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2526 dai_link->cpus = &vc4_hdmi->audio.cpu;
2527 dai_link->codecs = &vc4_hdmi->audio.codec;
2528 dai_link->platforms = &vc4_hdmi->audio.platform;
2530 dai_link->num_cpus = 1;
2531 dai_link->num_codecs = 1;
2532 dai_link->num_platforms = 1;
2534 dai_link->name = "MAI";
2535 dai_link->stream_name = "MAI PCM";
2536 dai_link->codecs->dai_name = "i2s-hifi";
2537 dai_link->cpus->dai_name = dev_name(dev);
2538 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2539 dai_link->platforms->name = dev_name(dev);
2541 card->dai_link = dai_link;
2542 card->num_links = 1;
2543 card->name = vc4_hdmi->variant->card_name;
2544 card->driver_name = "vc4-hdmi";
2546 card->owner = THIS_MODULE;
2549 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2550 * stores a pointer to the snd card object in dev->driver_data. This
2551 * means we cannot use it for something else. The hdmi back-pointer is
2552 * now stored in card->drvdata and should be retrieved with
2553 * snd_soc_card_get_drvdata() if needed.
2555 snd_soc_card_set_drvdata(card, vc4_hdmi);
2556 ret = devm_snd_soc_register_card(dev, card);
2558 dev_err_probe(dev, ret, "Could not register sound card\n");
2564 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2566 struct vc4_hdmi *vc4_hdmi = priv;
2567 struct drm_connector *connector = &vc4_hdmi->connector;
2568 struct drm_device *dev = connector->dev;
2570 if (dev && dev->registered)
2571 drm_connector_helper_hpd_irq_event(connector);
2576 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2578 struct drm_connector *connector = &vc4_hdmi->connector;
2579 struct platform_device *pdev = vc4_hdmi->pdev;
2582 if (vc4_hdmi->variant->external_irq_controller) {
2583 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2584 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2586 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2588 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2589 "vc4 hdmi hpd connected", vc4_hdmi);
2593 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2595 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2596 "vc4 hdmi hpd disconnected", vc4_hdmi);
2600 connector->polled = DRM_CONNECTOR_POLL_HPD;
2606 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2607 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2609 struct vc4_hdmi *vc4_hdmi = priv;
2611 if (vc4_hdmi->cec_rx_msg.len)
2612 cec_received_msg(vc4_hdmi->cec_adap,
2613 &vc4_hdmi->cec_rx_msg);
2618 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2620 struct vc4_hdmi *vc4_hdmi = priv;
2622 if (vc4_hdmi->cec_tx_ok) {
2623 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2627 * This CEC implementation makes 1 retry, so if we
2628 * get a NACK, then that means it made 2 attempts.
2630 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2636 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2638 struct vc4_hdmi *vc4_hdmi = priv;
2641 if (vc4_hdmi->cec_irq_was_rx)
2642 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2644 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2649 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2651 struct drm_device *dev = vc4_hdmi->connector.dev;
2652 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2655 lockdep_assert_held(&vc4_hdmi->hw_lock);
2657 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2658 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2660 if (msg->len > 16) {
2661 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2665 for (i = 0; i < msg->len; i += 4) {
2666 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2668 msg->msg[i] = val & 0xff;
2669 msg->msg[i + 1] = (val >> 8) & 0xff;
2670 msg->msg[i + 2] = (val >> 16) & 0xff;
2671 msg->msg[i + 3] = (val >> 24) & 0xff;
2675 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2680 * We don't need to protect the register access using
2681 * drm_dev_enter() there because the interrupt handler lifetime
2682 * is tied to the device itself, and not to the DRM device.
2684 * So when the device will be gone, one of the first thing we
2685 * will be doing will be to unregister the interrupt handler,
2686 * and then unregister the DRM device. drm_dev_enter() would
2687 * thus always succeed if we are here.
2690 lockdep_assert_held(&vc4_hdmi->hw_lock);
2692 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2693 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2694 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2695 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2697 return IRQ_WAKE_THREAD;
2700 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2702 struct vc4_hdmi *vc4_hdmi = priv;
2705 spin_lock(&vc4_hdmi->hw_lock);
2706 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2707 spin_unlock(&vc4_hdmi->hw_lock);
2712 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2716 lockdep_assert_held(&vc4_hdmi->hw_lock);
2719 * We don't need to protect the register access using
2720 * drm_dev_enter() there because the interrupt handler lifetime
2721 * is tied to the device itself, and not to the DRM device.
2723 * So when the device will be gone, one of the first thing we
2724 * will be doing will be to unregister the interrupt handler,
2725 * and then unregister the DRM device. drm_dev_enter() would
2726 * thus always succeed if we are here.
2729 vc4_hdmi->cec_rx_msg.len = 0;
2730 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2731 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2732 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2733 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2734 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2736 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2738 return IRQ_WAKE_THREAD;
2741 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2743 struct vc4_hdmi *vc4_hdmi = priv;
2746 spin_lock(&vc4_hdmi->hw_lock);
2747 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2748 spin_unlock(&vc4_hdmi->hw_lock);
2753 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2755 struct vc4_hdmi *vc4_hdmi = priv;
2756 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2761 * We don't need to protect the register access using
2762 * drm_dev_enter() there because the interrupt handler lifetime
2763 * is tied to the device itself, and not to the DRM device.
2765 * So when the device will be gone, one of the first thing we
2766 * will be doing will be to unregister the interrupt handler,
2767 * and then unregister the DRM device. drm_dev_enter() would
2768 * thus always succeed if we are here.
2771 if (!(stat & VC4_HDMI_CPU_CEC))
2774 spin_lock(&vc4_hdmi->hw_lock);
2775 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2776 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2777 if (vc4_hdmi->cec_irq_was_rx)
2778 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2780 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2782 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2783 spin_unlock(&vc4_hdmi->hw_lock);
2788 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2790 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2791 struct drm_device *drm = vc4_hdmi->connector.dev;
2792 /* clock period in microseconds */
2793 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2794 unsigned long flags;
2799 if (!drm_dev_enter(drm, &idx))
2801 * We can't return an error code, because the CEC
2802 * framework will emit WARN_ON messages at unbind
2807 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2813 mutex_lock(&vc4_hdmi->mutex);
2815 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2817 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2818 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2819 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2820 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2821 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2822 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2824 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2825 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2826 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2827 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2828 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2829 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2830 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2831 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2832 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2833 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2834 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2835 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2836 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2837 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2838 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2839 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2840 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2841 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2842 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2844 if (!vc4_hdmi->variant->external_irq_controller)
2845 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2847 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2849 mutex_unlock(&vc4_hdmi->mutex);
2855 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2857 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2858 struct drm_device *drm = vc4_hdmi->connector.dev;
2859 unsigned long flags;
2862 if (!drm_dev_enter(drm, &idx))
2864 * We can't return an error code, because the CEC
2865 * framework will emit WARN_ON messages at unbind
2870 mutex_lock(&vc4_hdmi->mutex);
2872 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2874 if (!vc4_hdmi->variant->external_irq_controller)
2875 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2877 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2878 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2880 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2882 mutex_unlock(&vc4_hdmi->mutex);
2884 pm_runtime_put(&vc4_hdmi->pdev->dev);
2891 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2894 return vc4_hdmi_cec_enable(adap);
2896 return vc4_hdmi_cec_disable(adap);
2899 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2901 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2902 struct drm_device *drm = vc4_hdmi->connector.dev;
2903 unsigned long flags;
2906 if (!drm_dev_enter(drm, &idx))
2908 * We can't return an error code, because the CEC
2909 * framework will emit WARN_ON messages at unbind
2914 mutex_lock(&vc4_hdmi->mutex);
2915 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2916 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2917 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2918 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2919 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2920 mutex_unlock(&vc4_hdmi->mutex);
2927 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2928 u32 signal_free_time, struct cec_msg *msg)
2930 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2931 struct drm_device *dev = vc4_hdmi->connector.dev;
2932 unsigned long flags;
2937 if (!drm_dev_enter(dev, &idx))
2940 if (msg->len > 16) {
2941 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2946 mutex_lock(&vc4_hdmi->mutex);
2948 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2950 for (i = 0; i < msg->len; i += 4)
2951 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2953 (msg->msg[i + 1] << 8) |
2954 (msg->msg[i + 2] << 16) |
2955 (msg->msg[i + 3] << 24));
2957 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2958 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2959 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2960 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2961 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2962 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2964 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2966 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2967 mutex_unlock(&vc4_hdmi->mutex);
2973 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2974 .adap_enable = vc4_hdmi_cec_adap_enable,
2975 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2976 .adap_transmit = vc4_hdmi_cec_adap_transmit,
2979 static void vc4_hdmi_cec_release(void *ptr)
2981 struct vc4_hdmi *vc4_hdmi = ptr;
2983 cec_unregister_adapter(vc4_hdmi->cec_adap);
2984 vc4_hdmi->cec_adap = NULL;
2987 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2989 struct cec_connector_info conn_info;
2990 struct platform_device *pdev = vc4_hdmi->pdev;
2991 struct device *dev = &pdev->dev;
2994 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2995 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2999 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3002 CEC_CAP_CONNECTOR_INFO, 1);
3003 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3007 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3008 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3010 if (vc4_hdmi->variant->external_irq_controller) {
3011 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3012 vc4_cec_irq_handler_rx_bare,
3013 vc4_cec_irq_handler_rx_thread, 0,
3014 "vc4 hdmi cec rx", vc4_hdmi);
3016 goto err_delete_cec_adap;
3018 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3019 vc4_cec_irq_handler_tx_bare,
3020 vc4_cec_irq_handler_tx_thread, 0,
3021 "vc4 hdmi cec tx", vc4_hdmi);
3023 goto err_delete_cec_adap;
3025 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3026 vc4_cec_irq_handler,
3027 vc4_cec_irq_handler_thread, 0,
3028 "vc4 hdmi cec", vc4_hdmi);
3030 goto err_delete_cec_adap;
3033 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3035 goto err_delete_cec_adap;
3038 * NOTE: Strictly speaking, we should probably use a DRM-managed
3039 * registration there to avoid removing the CEC adapter by the
3040 * time the DRM driver doesn't have any user anymore.
3042 * However, the CEC framework already cleans up the CEC adapter
3043 * only when the last user has closed its file descriptor, so we
3044 * don't need to handle it in DRM.
3046 * By the time the device-managed hook is executed, we will give
3047 * up our reference to the CEC adapter and therefore don't
3048 * really care when it's actually freed.
3050 * There's still a problematic sequence: if we unregister our
3051 * CEC adapter, but the userspace keeps a handle on the CEC
3052 * adapter but not the DRM device for some reason. In such a
3053 * case, our vc4_hdmi structure will be freed, but the
3054 * cec_adapter structure will have a dangling pointer to what
3055 * used to be our HDMI controller. If we get a CEC call at that
3056 * moment, we could end up with a use-after-free. Fortunately,
3057 * the CEC framework already handles this too, by calling
3058 * cec_is_registered() in cec_ioctl() and cec_poll().
3060 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3066 err_delete_cec_adap:
3067 cec_delete_adapter(vc4_hdmi->cec_adap);
3072 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3078 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3080 struct debugfs_reg32 *regs = ptr;
3085 static int vc4_hdmi_build_regset(struct drm_device *drm,
3086 struct vc4_hdmi *vc4_hdmi,
3087 struct debugfs_regset32 *regset,
3088 enum vc4_hdmi_regs reg)
3090 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3091 struct debugfs_reg32 *regs, *new_regs;
3092 unsigned int count = 0;
3096 regs = kcalloc(variant->num_registers, sizeof(*regs),
3101 for (i = 0; i < variant->num_registers; i++) {
3102 const struct vc4_hdmi_register *field = &variant->registers[i];
3104 if (field->reg != reg)
3107 regs[count].name = field->name;
3108 regs[count].offset = field->offset;
3112 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3116 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3117 regset->regs = new_regs;
3118 regset->nregs = count;
3120 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3127 static int vc4_hdmi_init_resources(struct drm_device *drm,
3128 struct vc4_hdmi *vc4_hdmi)
3130 struct platform_device *pdev = vc4_hdmi->pdev;
3131 struct device *dev = &pdev->dev;
3134 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3135 if (IS_ERR(vc4_hdmi->hdmicore_regs))
3136 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3138 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3139 if (IS_ERR(vc4_hdmi->hd_regs))
3140 return PTR_ERR(vc4_hdmi->hd_regs);
3142 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3146 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3150 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3151 if (IS_ERR(vc4_hdmi->pixel_clock)) {
3152 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3153 if (ret != -EPROBE_DEFER)
3154 DRM_ERROR("Failed to get pixel clock\n");
3158 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3159 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3160 DRM_ERROR("Failed to get HDMI state machine clock\n");
3161 return PTR_ERR(vc4_hdmi->hsm_clock);
3163 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3164 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3169 static int vc5_hdmi_init_resources(struct drm_device *drm,
3170 struct vc4_hdmi *vc4_hdmi)
3172 struct platform_device *pdev = vc4_hdmi->pdev;
3173 struct device *dev = &pdev->dev;
3174 struct resource *res;
3177 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3181 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3182 resource_size(res));
3183 if (!vc4_hdmi->hdmicore_regs)
3186 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3190 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3191 if (!vc4_hdmi->hd_regs)
3194 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3198 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3199 if (!vc4_hdmi->cec_regs)
3202 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3206 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3207 if (!vc4_hdmi->csc_regs)
3210 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3214 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3215 if (!vc4_hdmi->dvp_regs)
3218 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3222 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3223 if (!vc4_hdmi->phy_regs)
3226 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3230 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3231 if (!vc4_hdmi->ram_regs)
3234 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3238 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3239 if (!vc4_hdmi->rm_regs)
3242 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3243 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3244 DRM_ERROR("Failed to get HDMI state machine clock\n");
3245 return PTR_ERR(vc4_hdmi->hsm_clock);
3248 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3249 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3250 DRM_ERROR("Failed to get pixel bvb clock\n");
3251 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3254 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3255 if (IS_ERR(vc4_hdmi->audio_clock)) {
3256 DRM_ERROR("Failed to get audio clock\n");
3257 return PTR_ERR(vc4_hdmi->audio_clock);
3260 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3261 if (IS_ERR(vc4_hdmi->cec_clock)) {
3262 DRM_ERROR("Failed to get CEC clock\n");
3263 return PTR_ERR(vc4_hdmi->cec_clock);
3266 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3267 if (IS_ERR(vc4_hdmi->reset)) {
3268 DRM_ERROR("Failed to get HDMI reset line\n");
3269 return PTR_ERR(vc4_hdmi->reset);
3272 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3276 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3280 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3284 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3288 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3292 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3296 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3300 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3307 static int vc4_hdmi_runtime_suspend(struct device *dev)
3309 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3311 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3316 static int vc4_hdmi_runtime_resume(struct device *dev)
3318 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3319 unsigned long __maybe_unused flags;
3320 u32 __maybe_unused value;
3323 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3327 if (vc4_hdmi->variant->reset)
3328 vc4_hdmi->variant->reset(vc4_hdmi);
3330 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3331 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3332 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3333 /* Set the logical address to Unregistered */
3334 value |= VC4_HDMI_CEC_ADDR_MASK;
3335 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3336 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3338 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3340 if (!vc4_hdmi->variant->external_irq_controller) {
3341 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3342 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3343 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3350 static void vc4_hdmi_put_ddc_device(void *ptr)
3352 struct vc4_hdmi *vc4_hdmi = ptr;
3354 put_device(&vc4_hdmi->ddc->dev);
3357 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3359 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3360 struct platform_device *pdev = to_platform_device(dev);
3361 struct drm_device *drm = dev_get_drvdata(master);
3362 struct vc4_hdmi *vc4_hdmi;
3363 struct drm_encoder *encoder;
3364 struct device_node *ddc_node;
3367 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3371 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3375 spin_lock_init(&vc4_hdmi->hw_lock);
3376 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3378 dev_set_drvdata(dev, vc4_hdmi);
3379 encoder = &vc4_hdmi->encoder.base;
3380 vc4_hdmi->encoder.type = variant->encoder_type;
3381 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3382 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3383 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3384 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3385 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3386 vc4_hdmi->pdev = pdev;
3387 vc4_hdmi->variant = variant;
3390 * Since we don't know the state of the controller and its
3391 * display (if any), let's assume it's always enabled.
3392 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3393 * sure it's disabled, and avoid any inconsistency.
3395 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3396 vc4_hdmi->scdc_enabled = true;
3398 ret = variant->init_resources(drm, vc4_hdmi);
3402 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3404 DRM_ERROR("Failed to find ddc node in device tree\n");
3408 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3409 of_node_put(ddc_node);
3410 if (!vc4_hdmi->ddc) {
3411 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3412 return -EPROBE_DEFER;
3415 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3419 /* Only use the GPIO HPD pin if present in the DT, otherwise
3420 * we'll use the HDMI core's register.
3422 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3423 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3424 return PTR_ERR(vc4_hdmi->hpd_gpio);
3427 vc4_hdmi->disable_wifi_frequencies =
3428 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3430 if (variant->max_pixel_clock == 600000000) {
3431 struct vc4_dev *vc4 = to_vc4_dev(drm);
3432 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
3434 if (max_rate < 550000000)
3435 vc4_hdmi->disable_4kp60 = true;
3438 ret = devm_pm_runtime_enable(dev);
3443 * We need to have the device powered up at this point to call
3444 * our reset hook and for the CEC init.
3446 ret = pm_runtime_resume_and_get(dev);
3450 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3451 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3452 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3453 clk_prepare_enable(vc4_hdmi->pixel_clock);
3454 clk_prepare_enable(vc4_hdmi->hsm_clock);
3455 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3458 ret = drmm_encoder_init(drm, encoder,
3459 &vc4_hdmi_encoder_funcs,
3460 DRM_MODE_ENCODER_TMDS,
3463 goto err_put_runtime_pm;
3465 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3467 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3469 goto err_put_runtime_pm;
3471 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3473 goto err_put_runtime_pm;
3475 ret = vc4_hdmi_cec_init(vc4_hdmi);
3477 goto err_put_runtime_pm;
3479 ret = vc4_hdmi_audio_init(vc4_hdmi);
3481 goto err_put_runtime_pm;
3483 pm_runtime_put_sync(dev);
3488 pm_runtime_put_sync(dev);
3493 static const struct component_ops vc4_hdmi_ops = {
3494 .bind = vc4_hdmi_bind,
3497 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3499 return component_add(&pdev->dev, &vc4_hdmi_ops);
3502 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3504 component_del(&pdev->dev, &vc4_hdmi_ops);
3508 static const struct vc4_hdmi_variant bcm2835_variant = {
3509 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3510 .debugfs_name = "hdmi_regs",
3511 .card_name = "vc4-hdmi",
3512 .max_pixel_clock = 162000000,
3513 .registers = vc4_hdmi_fields,
3514 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3516 .init_resources = vc4_hdmi_init_resources,
3517 .csc_setup = vc4_hdmi_csc_setup,
3518 .reset = vc4_hdmi_reset,
3519 .set_timings = vc4_hdmi_set_timings,
3520 .phy_init = vc4_hdmi_phy_init,
3521 .phy_disable = vc4_hdmi_phy_disable,
3522 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3523 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3524 .channel_map = vc4_hdmi_channel_map,
3525 .supports_hdr = false,
3528 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3529 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3530 .debugfs_name = "hdmi0_regs",
3531 .card_name = "vc4-hdmi-0",
3532 .max_pixel_clock = 600000000,
3533 .registers = vc5_hdmi_hdmi0_fields,
3534 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3535 .phy_lane_mapping = {
3541 .unsupported_odd_h_timings = true,
3542 .external_irq_controller = true,
3544 .init_resources = vc5_hdmi_init_resources,
3545 .csc_setup = vc5_hdmi_csc_setup,
3546 .reset = vc5_hdmi_reset,
3547 .set_timings = vc5_hdmi_set_timings,
3548 .phy_init = vc5_hdmi_phy_init,
3549 .phy_disable = vc5_hdmi_phy_disable,
3550 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3551 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3552 .channel_map = vc5_hdmi_channel_map,
3553 .supports_hdr = true,
3554 .hp_detect = vc5_hdmi_hp_detect,
3557 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3558 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3559 .debugfs_name = "hdmi1_regs",
3560 .card_name = "vc4-hdmi-1",
3561 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3562 .registers = vc5_hdmi_hdmi1_fields,
3563 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3564 .phy_lane_mapping = {
3570 .unsupported_odd_h_timings = true,
3571 .external_irq_controller = true,
3573 .init_resources = vc5_hdmi_init_resources,
3574 .csc_setup = vc5_hdmi_csc_setup,
3575 .reset = vc5_hdmi_reset,
3576 .set_timings = vc5_hdmi_set_timings,
3577 .phy_init = vc5_hdmi_phy_init,
3578 .phy_disable = vc5_hdmi_phy_disable,
3579 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3580 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3581 .channel_map = vc5_hdmi_channel_map,
3582 .supports_hdr = true,
3583 .hp_detect = vc5_hdmi_hp_detect,
3586 static const struct of_device_id vc4_hdmi_dt_match[] = {
3587 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3588 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3589 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3593 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3594 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3595 vc4_hdmi_runtime_resume,
3599 struct platform_driver vc4_hdmi_driver = {
3600 .probe = vc4_hdmi_dev_probe,
3601 .remove = vc4_hdmi_dev_remove,
3604 .of_match_table = vc4_hdmi_dt_match,
3605 .pm = &vc4_hdmi_pm_ops,