1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
10 * DOC: VC4 Falcon HDMI module
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_probe_helper.h>
37 #include <drm/drm_simple_kms_helper.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <linux/clk.h>
40 #include <linux/component.h>
41 #include <linux/i2c.h>
42 #include <linux/of_address.h>
43 #include <linux/of_gpio.h>
44 #include <linux/of_platform.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/rational.h>
47 #include <linux/reset.h>
48 #include <sound/dmaengine_pcm.h>
49 #include <sound/hdmi-codec.h>
50 #include <sound/pcm_drm_eld.h>
51 #include <sound/pcm_params.h>
52 #include <sound/soc.h>
53 #include "media/cec.h"
56 #include "vc4_hdmi_regs.h"
59 #define VC5_HDMI_HORZA_HFP_SHIFT 16
60 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
61 #define VC5_HDMI_HORZA_VPOS BIT(15)
62 #define VC5_HDMI_HORZA_HPOS BIT(14)
63 #define VC5_HDMI_HORZA_HAP_SHIFT 0
64 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
66 #define VC5_HDMI_HORZB_HBP_SHIFT 16
67 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
68 #define VC5_HDMI_HORZB_HSP_SHIFT 0
69 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
71 #define VC5_HDMI_VERTA_VSP_SHIFT 24
72 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
73 #define VC5_HDMI_VERTA_VFP_SHIFT 16
74 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
75 #define VC5_HDMI_VERTA_VAL_SHIFT 0
76 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
78 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
79 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
94 # define VC4_HD_M_SW_RST BIT(2)
95 # define VC4_HD_M_ENABLE BIT(0)
97 #define HSM_MIN_CLOCK_FREQ 120000000
98 #define CEC_CLOCK_FREQ 40000
100 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
104 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
107 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
109 struct drm_info_node *node = (struct drm_info_node *)m->private;
110 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
111 struct drm_printer p = drm_seq_file_printer(m);
113 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
114 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
119 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
121 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
123 HDMI_WRITE(HDMI_M_CTL, 0);
125 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
127 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
128 VC4_HDMI_SW_RESET_HDMI |
129 VC4_HDMI_SW_RESET_FORMAT_DETECT);
131 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
134 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
136 reset_control_reset(vc4_hdmi->reset);
138 HDMI_WRITE(HDMI_DVP_CTL, 0);
140 HDMI_WRITE(HDMI_CLOCK_STOP,
141 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
144 #ifdef CONFIG_DRM_VC4_HDMI_CEC
145 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
150 value = HDMI_READ(HDMI_CEC_CNTRL_1);
151 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
154 * Set the clock divider: the hsm_clock rate and this divider
155 * setting will give a 40 kHz CEC clock.
157 clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
158 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
159 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
162 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
165 static enum drm_connector_status
166 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
168 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
169 bool connected = false;
171 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
173 if (vc4_hdmi->hpd_gpio &&
174 gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) {
176 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
181 if (connector->status != connector_status_connected) {
182 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
185 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
186 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
191 pm_runtime_put(&vc4_hdmi->pdev->dev);
192 return connector_status_connected;
195 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
196 pm_runtime_put(&vc4_hdmi->pdev->dev);
197 return connector_status_disconnected;
200 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
202 drm_connector_unregister(connector);
203 drm_connector_cleanup(connector);
206 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
208 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
209 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
213 edid = drm_get_edid(connector, vc4_hdmi->ddc);
214 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
218 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
220 drm_connector_update_edid_property(connector, edid);
221 ret = drm_add_edid_modes(connector, edid);
224 if (vc4_hdmi->disable_4kp60) {
225 struct drm_device *drm = connector->dev;
226 struct drm_display_mode *mode;
228 list_for_each_entry(mode, &connector->probed_modes, head) {
229 if (vc4_hdmi_mode_needs_scrambling(mode)) {
230 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
231 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
239 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
240 struct drm_atomic_state *state)
242 struct drm_connector_state *old_state =
243 drm_atomic_get_old_connector_state(state, connector);
244 struct drm_connector_state *new_state =
245 drm_atomic_get_new_connector_state(state, connector);
246 struct drm_crtc *crtc = new_state->crtc;
251 if (old_state->colorspace != new_state->colorspace ||
252 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
253 struct drm_crtc_state *crtc_state;
255 crtc_state = drm_atomic_get_crtc_state(state, crtc);
256 if (IS_ERR(crtc_state))
257 return PTR_ERR(crtc_state);
259 crtc_state->mode_changed = true;
265 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
267 struct vc4_hdmi_connector_state *old_state =
268 conn_state_to_vc4_hdmi_conn_state(connector->state);
269 struct vc4_hdmi_connector_state *new_state =
270 kzalloc(sizeof(*new_state), GFP_KERNEL);
272 if (connector->state)
273 __drm_atomic_helper_connector_destroy_state(connector->state);
276 __drm_atomic_helper_connector_reset(connector, &new_state->base);
281 new_state->base.max_bpc = 8;
282 new_state->base.max_requested_bpc = 8;
283 drm_atomic_helper_connector_tv_reset(connector);
286 static struct drm_connector_state *
287 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
289 struct drm_connector_state *conn_state = connector->state;
290 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
291 struct vc4_hdmi_connector_state *new_state;
293 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
297 new_state->pixel_rate = vc4_state->pixel_rate;
298 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
300 return &new_state->base;
303 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
304 .detect = vc4_hdmi_connector_detect,
305 .fill_modes = drm_helper_probe_single_connector_modes,
306 .destroy = vc4_hdmi_connector_destroy,
307 .reset = vc4_hdmi_connector_reset,
308 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
309 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
312 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
313 .get_modes = vc4_hdmi_connector_get_modes,
314 .atomic_check = vc4_hdmi_connector_atomic_check,
317 static int vc4_hdmi_connector_init(struct drm_device *dev,
318 struct vc4_hdmi *vc4_hdmi)
320 struct drm_connector *connector = &vc4_hdmi->connector;
321 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
324 drm_connector_init_with_ddc(dev, connector,
325 &vc4_hdmi_connector_funcs,
326 DRM_MODE_CONNECTOR_HDMIA,
328 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
331 * Some of the properties below require access to state, like bpc.
332 * Allocate some default initial connector state with our reset helper.
334 if (connector->funcs->reset)
335 connector->funcs->reset(connector);
337 /* Create and attach TV margin props to this connector. */
338 ret = drm_mode_create_tv_margin_properties(dev);
342 ret = drm_mode_create_hdmi_colorspace_property(connector);
346 drm_connector_attach_colorspace_property(connector);
347 drm_connector_attach_tv_margin_properties(connector);
348 drm_connector_attach_max_bpc_property(connector, 8, 12);
350 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
351 DRM_CONNECTOR_POLL_DISCONNECT);
353 connector->interlace_allowed = 1;
354 connector->doublescan_allowed = 0;
356 if (vc4_hdmi->variant->supports_hdr)
357 drm_connector_attach_hdr_output_metadata_property(connector);
359 drm_connector_attach_encoder(connector, encoder);
364 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
365 enum hdmi_infoframe_type type,
368 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
369 u32 packet_id = type - 0x80;
371 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
372 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
377 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
378 BIT(packet_id)), 100);
381 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
382 union hdmi_infoframe *frame)
384 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
385 u32 packet_id = frame->any.type - 0x80;
386 const struct vc4_hdmi_register *ram_packet_start =
387 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
388 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
389 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
390 ram_packet_start->reg);
391 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
395 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
396 VC4_HDMI_RAM_PACKET_ENABLE),
397 "Packet RAM has to be on to store the packet.");
399 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
403 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
405 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
409 for (i = 0; i < len; i += 7) {
410 writel(buffer[i + 0] << 0 |
416 writel(buffer[i + 3] << 0 |
418 buffer[i + 5] << 16 |
424 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
425 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
426 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
427 BIT(packet_id)), 100);
429 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
432 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
434 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
435 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
436 struct drm_connector *connector = &vc4_hdmi->connector;
437 struct drm_connector_state *cstate = connector->state;
438 struct drm_crtc *crtc = encoder->crtc;
439 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
440 union hdmi_infoframe frame;
443 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
446 DRM_ERROR("couldn't fill AVI infoframe\n");
450 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
452 vc4_encoder->limited_rgb_range ?
453 HDMI_QUANTIZATION_RANGE_LIMITED :
454 HDMI_QUANTIZATION_RANGE_FULL);
455 drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
456 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
458 vc4_hdmi_write_infoframe(encoder, &frame);
461 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
463 union hdmi_infoframe frame;
466 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
468 DRM_ERROR("couldn't fill SPD infoframe\n");
472 frame.spd.sdi = HDMI_SPD_SDI_PC;
474 vc4_hdmi_write_infoframe(encoder, &frame);
477 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
479 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
480 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
481 union hdmi_infoframe frame;
483 memcpy(&frame.audio, audio, sizeof(*audio));
484 vc4_hdmi_write_infoframe(encoder, &frame);
487 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
489 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
490 struct drm_connector *connector = &vc4_hdmi->connector;
491 struct drm_connector_state *conn_state = connector->state;
492 union hdmi_infoframe frame;
494 if (!vc4_hdmi->variant->supports_hdr)
497 if (!conn_state->hdr_output_metadata)
500 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
503 vc4_hdmi_write_infoframe(encoder, &frame);
506 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
508 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
510 vc4_hdmi_set_avi_infoframe(encoder);
511 vc4_hdmi_set_spd_infoframe(encoder);
513 * If audio was streaming, then we need to reenabled the audio
514 * infoframe here during encoder_enable.
516 if (vc4_hdmi->audio.streaming)
517 vc4_hdmi_set_audio_infoframe(encoder);
519 vc4_hdmi_set_hdr_infoframe(encoder);
522 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
523 struct drm_display_mode *mode)
525 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
526 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
527 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
529 if (!vc4_encoder->hdmi_monitor)
532 if (!display->hdmi.scdc.supported ||
533 !display->hdmi.scdc.scrambling.supported)
539 #define SCRAMBLING_POLLING_DELAY_MS 1000
541 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
543 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
544 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
546 if (!vc4_hdmi_supports_scrambling(encoder, mode))
549 if (!vc4_hdmi_mode_needs_scrambling(mode))
552 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
553 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
555 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
556 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
558 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
559 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
562 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
564 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
565 struct drm_crtc *crtc = encoder->crtc;
568 * At boot, encoder->crtc will be NULL. Since we don't know the
569 * state of the scrambler and in order to avoid any
570 * inconsistency, let's disable it all the time.
572 if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
575 if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
578 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
579 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
581 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
582 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
584 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
585 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
588 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
590 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
594 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
597 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
598 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
600 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
601 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
604 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
605 struct drm_atomic_state *state)
607 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
609 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
611 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
615 HDMI_WRITE(HDMI_VID_CTL,
616 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
617 vc4_hdmi_disable_scrambling(encoder);
620 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
621 struct drm_atomic_state *state)
623 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
626 HDMI_WRITE(HDMI_VID_CTL,
627 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
629 if (vc4_hdmi->variant->phy_disable)
630 vc4_hdmi->variant->phy_disable(vc4_hdmi);
632 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
633 clk_disable_unprepare(vc4_hdmi->pixel_clock);
635 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
637 DRM_ERROR("Failed to release power domain: %d\n", ret);
640 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
644 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
648 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
649 VC4_HD_CSC_CTL_ORDER);
652 /* CEA VICs other than #1 requre limited range RGB
653 * output unless overridden by an AVI infoframe.
654 * Apply a colorspace conversion to squash 0-255 down
655 * to 16-235. The matrix here is:
662 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
663 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
664 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
665 VC4_HD_CSC_CTL_MODE);
667 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
668 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
669 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
670 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
671 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
672 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
675 /* The RGB order applies even when CSC is disabled. */
676 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
679 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
683 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
686 /* CEA VICs other than #1 requre limited range RGB
687 * output unless overridden by an AVI infoframe.
688 * Apply a colorspace conversion to squash 0-255 down
689 * to 16-235. The matrix here is:
695 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
697 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
698 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
699 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
700 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
701 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
702 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
704 /* Still use the matrix for full range, but make it unity.
705 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
707 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
708 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
709 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
710 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
711 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
712 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
715 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
718 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
719 struct drm_connector_state *state,
720 struct drm_display_mode *mode)
722 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
723 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
724 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
725 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
726 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
727 VC4_HDMI_VERTA_VSP) |
728 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
729 VC4_HDMI_VERTA_VFP) |
730 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
731 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
732 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
733 VC4_HDMI_VERTB_VBP));
734 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
735 VC4_SET_FIELD(mode->crtc_vtotal -
736 mode->crtc_vsync_end -
738 VC4_HDMI_VERTB_VBP));
740 HDMI_WRITE(HDMI_HORZA,
741 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
742 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
743 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
744 VC4_HDMI_HORZA_HAP));
746 HDMI_WRITE(HDMI_HORZB,
747 VC4_SET_FIELD((mode->htotal -
748 mode->hsync_end) * pixel_rep,
749 VC4_HDMI_HORZB_HBP) |
750 VC4_SET_FIELD((mode->hsync_end -
751 mode->hsync_start) * pixel_rep,
752 VC4_HDMI_HORZB_HSP) |
753 VC4_SET_FIELD((mode->hsync_start -
754 mode->hdisplay) * pixel_rep,
755 VC4_HDMI_HORZB_HFP));
757 HDMI_WRITE(HDMI_VERTA0, verta);
758 HDMI_WRITE(HDMI_VERTA1, verta);
760 HDMI_WRITE(HDMI_VERTB0, vertb_even);
761 HDMI_WRITE(HDMI_VERTB1, vertb);
764 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
765 struct drm_connector_state *state,
766 struct drm_display_mode *mode)
768 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
769 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
770 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
771 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
772 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
773 VC5_HDMI_VERTA_VSP) |
774 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
775 VC5_HDMI_VERTA_VFP) |
776 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
777 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
778 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
779 VC4_HDMI_VERTB_VBP));
780 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
781 VC4_SET_FIELD(mode->crtc_vtotal -
782 mode->crtc_vsync_end -
784 VC4_HDMI_VERTB_VBP));
789 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
790 HDMI_WRITE(HDMI_HORZA,
791 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
792 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
793 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
794 VC5_HDMI_HORZA_HAP) |
795 VC4_SET_FIELD((mode->hsync_start -
796 mode->hdisplay) * pixel_rep,
797 VC5_HDMI_HORZA_HFP));
799 HDMI_WRITE(HDMI_HORZB,
800 VC4_SET_FIELD((mode->htotal -
801 mode->hsync_end) * pixel_rep,
802 VC5_HDMI_HORZB_HBP) |
803 VC4_SET_FIELD((mode->hsync_end -
804 mode->hsync_start) * pixel_rep,
805 VC5_HDMI_HORZB_HSP));
807 HDMI_WRITE(HDMI_VERTA0, verta);
808 HDMI_WRITE(HDMI_VERTA1, verta);
810 HDMI_WRITE(HDMI_VERTB0, vertb_even);
811 HDMI_WRITE(HDMI_VERTB1, vertb);
813 switch (state->max_bpc) {
829 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
830 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
831 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
832 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
833 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
834 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
836 reg = HDMI_READ(HDMI_GCP_WORD_1);
837 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
838 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
839 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
841 reg = HDMI_READ(HDMI_GCP_CONFIG);
842 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
843 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
844 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
846 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
849 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
854 drift = HDMI_READ(HDMI_FIFO_CTL);
855 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
857 HDMI_WRITE(HDMI_FIFO_CTL,
858 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
859 HDMI_WRITE(HDMI_FIFO_CTL,
860 drift | VC4_HDMI_FIFO_CTL_RECENTER);
861 usleep_range(1000, 1100);
862 HDMI_WRITE(HDMI_FIFO_CTL,
863 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
864 HDMI_WRITE(HDMI_FIFO_CTL,
865 drift | VC4_HDMI_FIFO_CTL_RECENTER);
867 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
868 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
869 WARN_ONCE(ret, "Timeout waiting for "
870 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
873 static struct drm_connector_state *
874 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
875 struct drm_atomic_state *state)
877 struct drm_connector_state *conn_state;
878 struct drm_connector *connector;
881 for_each_new_connector_in_state(state, connector, conn_state, i) {
882 if (conn_state->best_encoder == encoder)
889 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
890 struct drm_atomic_state *state)
892 struct drm_connector_state *conn_state =
893 vc4_hdmi_encoder_get_connector_state(encoder, state);
894 struct vc4_hdmi_connector_state *vc4_conn_state =
895 conn_state_to_vc4_hdmi_conn_state(conn_state);
896 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
897 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
898 unsigned long pixel_rate = vc4_conn_state->pixel_rate;
899 unsigned long bvb_rate, hsm_rate;
903 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
904 * be faster than pixel clock, infinitesimally faster, tested in
905 * simulation. Otherwise, exact value is unimportant for HDMI
906 * operation." This conflicts with bcm2835's vc4 documentation, which
907 * states HSM's clock has to be at least 108% of the pixel clock.
909 * Real life tests reveal that vc4's firmware statement holds up, and
910 * users are able to use pixel clocks closer to HSM's, namely for
911 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
912 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
915 * Additionally, the AXI clock needs to be at least 25% of
916 * pixel clock, but HSM ends up being the limiting factor.
918 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
919 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
921 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
925 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
927 DRM_ERROR("Failed to retain power domain: %d\n", ret);
931 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
933 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
934 goto err_put_runtime_pm;
937 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
939 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
940 goto err_put_runtime_pm;
944 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
946 if (pixel_rate > 297000000)
947 bvb_rate = 300000000;
948 else if (pixel_rate > 148500000)
949 bvb_rate = 150000000;
953 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
955 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
956 goto err_disable_pixel_clock;
959 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
961 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
962 goto err_disable_pixel_clock;
965 if (vc4_hdmi->variant->phy_init)
966 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
968 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
969 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
970 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
971 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
973 if (vc4_hdmi->variant->set_timings)
974 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
978 err_disable_pixel_clock:
979 clk_disable_unprepare(vc4_hdmi->pixel_clock);
981 pm_runtime_put(&vc4_hdmi->pdev->dev);
986 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
987 struct drm_atomic_state *state)
989 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
990 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
991 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
993 if (vc4_encoder->hdmi_monitor &&
994 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
995 if (vc4_hdmi->variant->csc_setup)
996 vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
998 vc4_encoder->limited_rgb_range = true;
1000 if (vc4_hdmi->variant->csc_setup)
1001 vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1003 vc4_encoder->limited_rgb_range = false;
1006 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1009 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1010 struct drm_atomic_state *state)
1012 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1013 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1014 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1015 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1016 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1019 HDMI_WRITE(HDMI_VID_CTL,
1020 VC4_HD_VID_CTL_ENABLE |
1021 VC4_HD_VID_CTL_CLRRGB |
1022 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1023 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1024 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1025 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1027 HDMI_WRITE(HDMI_VID_CTL,
1028 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1030 if (vc4_encoder->hdmi_monitor) {
1031 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1032 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1033 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1035 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1036 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1037 WARN_ONCE(ret, "Timeout waiting for "
1038 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1040 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1041 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1042 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1043 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1044 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1045 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1047 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1048 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1049 WARN_ONCE(ret, "Timeout waiting for "
1050 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1053 if (vc4_encoder->hdmi_monitor) {
1054 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1055 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1056 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1057 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1058 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1060 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1061 VC4_HDMI_RAM_PACKET_ENABLE);
1063 vc4_hdmi_set_infoframes(encoder);
1066 vc4_hdmi_recenter_fifo(vc4_hdmi);
1067 vc4_hdmi_enable_scrambling(encoder);
1070 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1074 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1075 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1077 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1078 struct drm_crtc_state *crtc_state,
1079 struct drm_connector_state *conn_state)
1081 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1082 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1083 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1084 unsigned long long pixel_rate = mode->clock * 1000;
1085 unsigned long long tmds_rate;
1087 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1088 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1089 (mode->hsync_end % 2) || (mode->htotal % 2)))
1093 * The 1440p@60 pixel rate is in the same range than the first
1094 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1095 * bandwidth). Slightly lower the frequency to bring it out of
1098 tmds_rate = pixel_rate * 10;
1099 if (vc4_hdmi->disable_wifi_frequencies &&
1100 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1101 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1102 mode->clock = 238560;
1103 pixel_rate = mode->clock * 1000;
1106 if (conn_state->max_bpc == 12) {
1107 pixel_rate = pixel_rate * 150;
1108 do_div(pixel_rate, 100);
1109 } else if (conn_state->max_bpc == 10) {
1110 pixel_rate = pixel_rate * 125;
1111 do_div(pixel_rate, 100);
1114 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1115 pixel_rate = pixel_rate * 2;
1117 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1120 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1123 vc4_state->pixel_rate = pixel_rate;
1128 static enum drm_mode_status
1129 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1130 const struct drm_display_mode *mode)
1132 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1134 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1135 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1136 (mode->hsync_end % 2) || (mode->htotal % 2)))
1137 return MODE_H_ILLEGAL;
1139 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1140 return MODE_CLOCK_HIGH;
1142 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1143 return MODE_CLOCK_HIGH;
1148 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1149 .atomic_check = vc4_hdmi_encoder_atomic_check,
1150 .mode_valid = vc4_hdmi_encoder_mode_valid,
1151 .disable = vc4_hdmi_encoder_disable,
1152 .enable = vc4_hdmi_encoder_enable,
1155 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1158 u32 channel_map = 0;
1160 for (i = 0; i < 8; i++) {
1161 if (channel_mask & BIT(i))
1162 channel_map |= i << (3 * i);
1167 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1170 u32 channel_map = 0;
1172 for (i = 0; i < 8; i++) {
1173 if (channel_mask & BIT(i))
1174 channel_map |= i << (4 * i);
1179 /* HDMI audio codec callbacks */
1180 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1181 unsigned int samplerate)
1183 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1186 rational_best_approximation(hsm_clock, samplerate,
1187 VC4_HD_MAI_SMP_N_MASK >>
1188 VC4_HD_MAI_SMP_N_SHIFT,
1189 (VC4_HD_MAI_SMP_M_MASK >>
1190 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1193 HDMI_WRITE(HDMI_MAI_SMP,
1194 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1195 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1198 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1200 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1201 struct drm_crtc *crtc = encoder->crtc;
1202 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1206 n = 128 * samplerate / 1000;
1207 tmp = (u64)(mode->clock * 1000) * n;
1208 do_div(tmp, 128 * samplerate);
1211 HDMI_WRITE(HDMI_CRP_CFG,
1212 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1213 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1216 * We could get slightly more accurate clocks in some cases by
1217 * providing a CTS_1 value. The two CTS values are alternated
1218 * between based on the period fields
1220 HDMI_WRITE(HDMI_CTS_0, cts);
1221 HDMI_WRITE(HDMI_CTS_1, cts);
1224 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1226 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1228 return snd_soc_card_get_drvdata(card);
1231 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1233 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1234 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1237 * If the HDMI encoder hasn't probed, or the encoder is
1238 * currently in DVI mode, treat the codec dai as missing.
1240 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1241 VC4_HDMI_RAM_PACKET_ENABLE))
1244 vc4_hdmi->audio.streaming = true;
1246 HDMI_WRITE(HDMI_MAI_CTL,
1247 VC4_HD_MAI_CTL_RESET |
1248 VC4_HD_MAI_CTL_FLUSH |
1249 VC4_HD_MAI_CTL_DLATE |
1250 VC4_HD_MAI_CTL_ERRORE |
1251 VC4_HD_MAI_CTL_ERRORF);
1253 if (vc4_hdmi->variant->phy_rng_enable)
1254 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1259 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1261 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1262 struct device *dev = &vc4_hdmi->pdev->dev;
1265 vc4_hdmi->audio.streaming = false;
1266 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1268 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1270 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1271 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1272 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1275 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1277 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1279 HDMI_WRITE(HDMI_MAI_CTL,
1280 VC4_HD_MAI_CTL_DLATE |
1281 VC4_HD_MAI_CTL_ERRORE |
1282 VC4_HD_MAI_CTL_ERRORF);
1284 if (vc4_hdmi->variant->phy_rng_disable)
1285 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1287 vc4_hdmi->audio.streaming = false;
1288 vc4_hdmi_audio_reset(vc4_hdmi);
1291 static int sample_rate_to_mai_fmt(int samplerate)
1293 switch (samplerate) {
1295 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1297 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1299 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1301 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1303 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1305 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1307 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1309 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1311 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1313 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1315 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1317 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1319 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1321 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1323 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1325 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1329 /* HDMI audio codec callbacks */
1330 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1331 struct hdmi_codec_daifmt *daifmt,
1332 struct hdmi_codec_params *params)
1334 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1335 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1336 unsigned int sample_rate = params->sample_rate;
1337 unsigned int channels = params->channels;
1338 u32 audio_packet_config, channel_mask;
1340 u32 mai_audio_format;
1341 u32 mai_sample_rate;
1343 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1344 sample_rate, params->sample_width, channels);
1346 HDMI_WRITE(HDMI_MAI_CTL,
1347 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1348 VC4_HD_MAI_CTL_WHOLSMP |
1349 VC4_HD_MAI_CTL_CHALIGN |
1350 VC4_HD_MAI_CTL_ENABLE);
1352 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1354 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1355 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1356 params->channels == 8)
1357 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1359 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1360 HDMI_WRITE(HDMI_MAI_FMT,
1361 VC4_SET_FIELD(mai_sample_rate,
1362 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1363 VC4_SET_FIELD(mai_audio_format,
1364 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1366 /* The B frame identifier should match the value used by alsa-lib (8) */
1367 audio_packet_config =
1368 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1369 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1370 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1372 channel_mask = GENMASK(channels - 1, 0);
1373 audio_packet_config |= VC4_SET_FIELD(channel_mask,
1374 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1376 /* Set the MAI threshold */
1377 HDMI_WRITE(HDMI_MAI_THR,
1378 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1379 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1380 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1381 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1383 HDMI_WRITE(HDMI_MAI_CONFIG,
1384 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1385 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1386 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1388 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1389 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1390 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1391 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1393 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
1394 vc4_hdmi_set_audio_infoframe(encoder);
1399 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1400 SND_SOC_DAPM_OUTPUT("TX"),
1403 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1404 { "TX", NULL, "Playback" },
1407 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1408 .name = "vc4-hdmi-cpu-dai-component",
1411 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1413 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1415 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1420 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1421 .name = "vc4-hdmi-cpu-dai",
1422 .probe = vc4_hdmi_audio_cpu_dai_probe,
1424 .stream_name = "Playback",
1427 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1428 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1429 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1430 SNDRV_PCM_RATE_192000,
1431 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1435 static const struct snd_dmaengine_pcm_config pcm_conf = {
1436 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1437 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1440 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1441 uint8_t *buf, size_t len)
1443 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1444 struct drm_connector *connector = &vc4_hdmi->connector;
1446 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1451 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1452 .get_eld = vc4_hdmi_audio_get_eld,
1453 .prepare = vc4_hdmi_audio_prepare,
1454 .audio_shutdown = vc4_hdmi_audio_shutdown,
1455 .audio_startup = vc4_hdmi_audio_startup,
1458 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1459 .ops = &vc4_hdmi_codec_ops,
1460 .max_i2s_channels = 8,
1464 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1466 const struct vc4_hdmi_register *mai_data =
1467 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1468 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1469 struct snd_soc_card *card = &vc4_hdmi->audio.card;
1470 struct device *dev = &vc4_hdmi->pdev->dev;
1471 struct platform_device *codec_pdev;
1476 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1478 "'dmas' DT property is missing, no HDMI audio\n");
1482 if (mai_data->reg != VC4_HD) {
1483 WARN_ONCE(true, "MAI isn't in the HD block\n");
1488 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1489 * the bus address specified in the DT, because the physical address
1490 * (the one returned by platform_get_resource()) is not appropriate
1491 * for DMA transfers.
1492 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1494 index = of_property_match_string(dev->of_node, "reg-names", "hd");
1495 /* Before BCM2711, we don't have a named register range */
1499 addr = of_get_address(dev->of_node, index, NULL, NULL);
1501 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1502 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1503 vc4_hdmi->audio.dma_data.maxburst = 2;
1505 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1507 dev_err(dev, "Could not register PCM component: %d\n", ret);
1511 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1512 &vc4_hdmi_audio_cpu_dai_drv, 1);
1514 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1518 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1519 PLATFORM_DEVID_AUTO,
1520 &vc4_hdmi_codec_pdata,
1521 sizeof(vc4_hdmi_codec_pdata));
1522 if (IS_ERR(codec_pdev)) {
1523 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1524 return PTR_ERR(codec_pdev);
1527 dai_link->cpus = &vc4_hdmi->audio.cpu;
1528 dai_link->codecs = &vc4_hdmi->audio.codec;
1529 dai_link->platforms = &vc4_hdmi->audio.platform;
1531 dai_link->num_cpus = 1;
1532 dai_link->num_codecs = 1;
1533 dai_link->num_platforms = 1;
1535 dai_link->name = "MAI";
1536 dai_link->stream_name = "MAI PCM";
1537 dai_link->codecs->dai_name = "i2s-hifi";
1538 dai_link->cpus->dai_name = dev_name(dev);
1539 dai_link->codecs->name = dev_name(&codec_pdev->dev);
1540 dai_link->platforms->name = dev_name(dev);
1542 card->dai_link = dai_link;
1543 card->num_links = 1;
1544 card->name = vc4_hdmi->variant->card_name;
1545 card->driver_name = "vc4-hdmi";
1547 card->owner = THIS_MODULE;
1550 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1551 * stores a pointer to the snd card object in dev->driver_data. This
1552 * means we cannot use it for something else. The hdmi back-pointer is
1553 * now stored in card->drvdata and should be retrieved with
1554 * snd_soc_card_get_drvdata() if needed.
1556 snd_soc_card_set_drvdata(card, vc4_hdmi);
1557 ret = devm_snd_soc_register_card(dev, card);
1559 dev_err_probe(dev, ret, "Could not register sound card\n");
1565 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1567 struct vc4_hdmi *vc4_hdmi = priv;
1568 struct drm_connector *connector = &vc4_hdmi->connector;
1569 struct drm_device *dev = connector->dev;
1571 if (dev && dev->registered)
1572 drm_connector_helper_hpd_irq_event(connector);
1577 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1579 struct drm_connector *connector = &vc4_hdmi->connector;
1580 struct platform_device *pdev = vc4_hdmi->pdev;
1583 if (vc4_hdmi->variant->external_irq_controller) {
1584 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1585 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1587 ret = request_threaded_irq(hpd_con,
1589 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1590 "vc4 hdmi hpd connected", vc4_hdmi);
1594 ret = request_threaded_irq(hpd_rm,
1596 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1597 "vc4 hdmi hpd disconnected", vc4_hdmi);
1599 free_irq(hpd_con, vc4_hdmi);
1603 connector->polled = DRM_CONNECTOR_POLL_HPD;
1609 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1611 struct platform_device *pdev = vc4_hdmi->pdev;
1613 if (vc4_hdmi->variant->external_irq_controller) {
1614 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1615 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1619 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1620 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1622 struct vc4_hdmi *vc4_hdmi = priv;
1624 if (vc4_hdmi->cec_rx_msg.len)
1625 cec_received_msg(vc4_hdmi->cec_adap,
1626 &vc4_hdmi->cec_rx_msg);
1631 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1633 struct vc4_hdmi *vc4_hdmi = priv;
1635 if (vc4_hdmi->cec_tx_ok) {
1636 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1640 * This CEC implementation makes 1 retry, so if we
1641 * get a NACK, then that means it made 2 attempts.
1643 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1649 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1651 struct vc4_hdmi *vc4_hdmi = priv;
1654 if (vc4_hdmi->cec_irq_was_rx)
1655 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1657 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1662 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1664 struct drm_device *dev = vc4_hdmi->connector.dev;
1665 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1668 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1669 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1671 if (msg->len > 16) {
1672 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1676 for (i = 0; i < msg->len; i += 4) {
1677 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1679 msg->msg[i] = val & 0xff;
1680 msg->msg[i + 1] = (val >> 8) & 0xff;
1681 msg->msg[i + 2] = (val >> 16) & 0xff;
1682 msg->msg[i + 3] = (val >> 24) & 0xff;
1686 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1688 struct vc4_hdmi *vc4_hdmi = priv;
1691 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1692 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1693 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1694 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1696 return IRQ_WAKE_THREAD;
1699 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1701 struct vc4_hdmi *vc4_hdmi = priv;
1704 vc4_hdmi->cec_rx_msg.len = 0;
1705 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1706 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1707 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1708 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1709 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1711 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1713 return IRQ_WAKE_THREAD;
1716 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1718 struct vc4_hdmi *vc4_hdmi = priv;
1719 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1723 if (!(stat & VC4_HDMI_CPU_CEC))
1726 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1727 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1728 if (vc4_hdmi->cec_irq_was_rx)
1729 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1731 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1733 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1737 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
1739 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1740 /* clock period in microseconds */
1741 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1745 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1749 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1750 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1751 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1752 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1753 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1754 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1756 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1757 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1758 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1759 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1760 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1761 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1762 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1763 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1764 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1765 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1766 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1767 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1768 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1769 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1770 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1771 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1772 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1773 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1774 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1776 if (!vc4_hdmi->variant->external_irq_controller)
1777 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1782 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
1784 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1786 if (!vc4_hdmi->variant->external_irq_controller)
1787 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1789 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
1790 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1792 pm_runtime_put(&vc4_hdmi->pdev->dev);
1797 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1800 return vc4_hdmi_cec_enable(adap);
1802 return vc4_hdmi_cec_disable(adap);
1805 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1807 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1809 HDMI_WRITE(HDMI_CEC_CNTRL_1,
1810 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1811 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1815 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1816 u32 signal_free_time, struct cec_msg *msg)
1818 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1819 struct drm_device *dev = vc4_hdmi->connector.dev;
1823 if (msg->len > 16) {
1824 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1828 for (i = 0; i < msg->len; i += 4)
1829 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1831 (msg->msg[i + 1] << 8) |
1832 (msg->msg[i + 2] << 16) |
1833 (msg->msg[i + 3] << 24));
1835 val = HDMI_READ(HDMI_CEC_CNTRL_1);
1836 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1837 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1838 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1839 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1840 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1842 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1846 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1847 .adap_enable = vc4_hdmi_cec_adap_enable,
1848 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1849 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1852 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1854 struct cec_connector_info conn_info;
1855 struct platform_device *pdev = vc4_hdmi->pdev;
1856 struct device *dev = &pdev->dev;
1860 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1861 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1865 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1868 CEC_CAP_CONNECTOR_INFO, 1);
1869 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1873 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1874 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1876 value = HDMI_READ(HDMI_CEC_CNTRL_1);
1877 /* Set the logical address to Unregistered */
1878 value |= VC4_HDMI_CEC_ADDR_MASK;
1879 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1881 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1883 if (vc4_hdmi->variant->external_irq_controller) {
1884 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
1885 vc4_cec_irq_handler_rx_bare,
1886 vc4_cec_irq_handler_rx_thread, 0,
1887 "vc4 hdmi cec rx", vc4_hdmi);
1889 goto err_delete_cec_adap;
1891 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
1892 vc4_cec_irq_handler_tx_bare,
1893 vc4_cec_irq_handler_tx_thread, 0,
1894 "vc4 hdmi cec tx", vc4_hdmi);
1896 goto err_remove_cec_rx_handler;
1898 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1900 ret = request_threaded_irq(platform_get_irq(pdev, 0),
1901 vc4_cec_irq_handler,
1902 vc4_cec_irq_handler_thread, 0,
1903 "vc4 hdmi cec", vc4_hdmi);
1905 goto err_delete_cec_adap;
1908 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1910 goto err_remove_handlers;
1914 err_remove_handlers:
1915 if (vc4_hdmi->variant->external_irq_controller)
1916 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1918 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1920 err_remove_cec_rx_handler:
1921 if (vc4_hdmi->variant->external_irq_controller)
1922 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1924 err_delete_cec_adap:
1925 cec_delete_adapter(vc4_hdmi->cec_adap);
1930 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1932 struct platform_device *pdev = vc4_hdmi->pdev;
1934 if (vc4_hdmi->variant->external_irq_controller) {
1935 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1936 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1938 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1941 cec_unregister_adapter(vc4_hdmi->cec_adap);
1944 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1949 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1953 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1954 struct debugfs_regset32 *regset,
1955 enum vc4_hdmi_regs reg)
1957 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1958 struct debugfs_reg32 *regs, *new_regs;
1959 unsigned int count = 0;
1962 regs = kcalloc(variant->num_registers, sizeof(*regs),
1967 for (i = 0; i < variant->num_registers; i++) {
1968 const struct vc4_hdmi_register *field = &variant->registers[i];
1970 if (field->reg != reg)
1973 regs[count].name = field->name;
1974 regs[count].offset = field->offset;
1978 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1982 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1983 regset->regs = new_regs;
1984 regset->nregs = count;
1989 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1991 struct platform_device *pdev = vc4_hdmi->pdev;
1992 struct device *dev = &pdev->dev;
1995 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1996 if (IS_ERR(vc4_hdmi->hdmicore_regs))
1997 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1999 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2000 if (IS_ERR(vc4_hdmi->hd_regs))
2001 return PTR_ERR(vc4_hdmi->hd_regs);
2003 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2007 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2011 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2012 if (IS_ERR(vc4_hdmi->pixel_clock)) {
2013 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2014 if (ret != -EPROBE_DEFER)
2015 DRM_ERROR("Failed to get pixel clock\n");
2019 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2020 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2021 DRM_ERROR("Failed to get HDMI state machine clock\n");
2022 return PTR_ERR(vc4_hdmi->hsm_clock);
2024 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2025 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2030 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2032 struct platform_device *pdev = vc4_hdmi->pdev;
2033 struct device *dev = &pdev->dev;
2034 struct resource *res;
2036 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2040 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2041 resource_size(res));
2042 if (!vc4_hdmi->hdmicore_regs)
2045 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2049 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2050 if (!vc4_hdmi->hd_regs)
2053 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2057 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2058 if (!vc4_hdmi->cec_regs)
2061 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2065 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2066 if (!vc4_hdmi->csc_regs)
2069 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2073 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2074 if (!vc4_hdmi->dvp_regs)
2077 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2081 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2082 if (!vc4_hdmi->phy_regs)
2085 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2089 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2090 if (!vc4_hdmi->ram_regs)
2093 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2097 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2098 if (!vc4_hdmi->rm_regs)
2101 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2102 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2103 DRM_ERROR("Failed to get HDMI state machine clock\n");
2104 return PTR_ERR(vc4_hdmi->hsm_clock);
2107 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2108 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2109 DRM_ERROR("Failed to get pixel bvb clock\n");
2110 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2113 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2114 if (IS_ERR(vc4_hdmi->audio_clock)) {
2115 DRM_ERROR("Failed to get audio clock\n");
2116 return PTR_ERR(vc4_hdmi->audio_clock);
2119 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2120 if (IS_ERR(vc4_hdmi->cec_clock)) {
2121 DRM_ERROR("Failed to get CEC clock\n");
2122 return PTR_ERR(vc4_hdmi->cec_clock);
2125 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2126 if (IS_ERR(vc4_hdmi->reset)) {
2127 DRM_ERROR("Failed to get HDMI reset line\n");
2128 return PTR_ERR(vc4_hdmi->reset);
2134 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2136 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2138 clk_disable_unprepare(vc4_hdmi->hsm_clock);
2143 static int vc4_hdmi_runtime_resume(struct device *dev)
2145 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2148 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2155 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2157 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2158 struct platform_device *pdev = to_platform_device(dev);
2159 struct drm_device *drm = dev_get_drvdata(master);
2160 struct vc4_hdmi *vc4_hdmi;
2161 struct drm_encoder *encoder;
2162 struct device_node *ddc_node;
2165 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2168 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2170 dev_set_drvdata(dev, vc4_hdmi);
2171 encoder = &vc4_hdmi->encoder.base.base;
2172 vc4_hdmi->encoder.base.type = variant->encoder_type;
2173 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2174 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2175 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2176 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2177 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2178 vc4_hdmi->pdev = pdev;
2179 vc4_hdmi->variant = variant;
2181 ret = variant->init_resources(vc4_hdmi);
2185 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2187 DRM_ERROR("Failed to find ddc node in device tree\n");
2191 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2192 of_node_put(ddc_node);
2193 if (!vc4_hdmi->ddc) {
2194 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2195 return -EPROBE_DEFER;
2198 /* Only use the GPIO HPD pin if present in the DT, otherwise
2199 * we'll use the HDMI core's register.
2201 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2202 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2203 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2207 vc4_hdmi->disable_wifi_frequencies =
2208 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2210 if (variant->max_pixel_clock == 600000000) {
2211 struct vc4_dev *vc4 = to_vc4_dev(drm);
2212 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2214 if (max_rate < 550000000)
2215 vc4_hdmi->disable_4kp60 = true;
2219 * If we boot without any cable connected to the HDMI connector,
2220 * the firmware will skip the HSM initialization and leave it
2221 * with a rate of 0, resulting in a bus lockup when we're
2222 * accessing the registers even if it's enabled.
2224 * Let's put a sensible default at runtime_resume so that we
2225 * don't end up in this situation.
2227 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2232 * We need to have the device powered up at this point to call
2233 * our reset hook and for the CEC init.
2235 ret = vc4_hdmi_runtime_resume(dev);
2239 pm_runtime_get_noresume(dev);
2240 pm_runtime_set_active(dev);
2241 pm_runtime_enable(dev);
2243 if (vc4_hdmi->variant->reset)
2244 vc4_hdmi->variant->reset(vc4_hdmi);
2246 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2247 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2248 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2249 clk_prepare_enable(vc4_hdmi->pixel_clock);
2250 clk_prepare_enable(vc4_hdmi->hsm_clock);
2251 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2254 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2255 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2257 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2259 goto err_destroy_encoder;
2261 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2263 goto err_destroy_conn;
2265 ret = vc4_hdmi_cec_init(vc4_hdmi);
2267 goto err_free_hotplug;
2269 ret = vc4_hdmi_audio_init(vc4_hdmi);
2273 vc4_debugfs_add_file(drm, variant->debugfs_name,
2274 vc4_hdmi_debugfs_regs,
2277 pm_runtime_put_sync(dev);
2282 vc4_hdmi_cec_exit(vc4_hdmi);
2284 vc4_hdmi_hotplug_exit(vc4_hdmi);
2286 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2287 err_destroy_encoder:
2288 drm_encoder_cleanup(encoder);
2289 pm_runtime_put_sync(dev);
2290 pm_runtime_disable(dev);
2292 put_device(&vc4_hdmi->ddc->dev);
2297 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2300 struct vc4_hdmi *vc4_hdmi;
2303 * ASoC makes it a bit hard to retrieve a pointer to the
2304 * vc4_hdmi structure. Registering the card will overwrite our
2305 * device drvdata with a pointer to the snd_soc_card structure,
2306 * which can then be used to retrieve whatever drvdata we want
2309 * However, that doesn't fly in the case where we wouldn't
2310 * register an ASoC card (because of an old DT that is missing
2311 * the dmas properties for example), then the card isn't
2312 * registered and the device drvdata wouldn't be set.
2314 * We can deal with both cases by making sure a snd_soc_card
2315 * pointer and a vc4_hdmi structure are pointing to the same
2316 * memory address, so we can treat them indistinctly without any
2319 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2320 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2321 vc4_hdmi = dev_get_drvdata(dev);
2323 kfree(vc4_hdmi->hdmi_regset.regs);
2324 kfree(vc4_hdmi->hd_regset.regs);
2326 vc4_hdmi_cec_exit(vc4_hdmi);
2327 vc4_hdmi_hotplug_exit(vc4_hdmi);
2328 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2329 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2331 pm_runtime_disable(dev);
2333 put_device(&vc4_hdmi->ddc->dev);
2336 static const struct component_ops vc4_hdmi_ops = {
2337 .bind = vc4_hdmi_bind,
2338 .unbind = vc4_hdmi_unbind,
2341 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2343 return component_add(&pdev->dev, &vc4_hdmi_ops);
2346 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2348 component_del(&pdev->dev, &vc4_hdmi_ops);
2352 static const struct vc4_hdmi_variant bcm2835_variant = {
2353 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2354 .debugfs_name = "hdmi_regs",
2355 .card_name = "vc4-hdmi",
2356 .max_pixel_clock = 162000000,
2357 .registers = vc4_hdmi_fields,
2358 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
2360 .init_resources = vc4_hdmi_init_resources,
2361 .csc_setup = vc4_hdmi_csc_setup,
2362 .reset = vc4_hdmi_reset,
2363 .set_timings = vc4_hdmi_set_timings,
2364 .phy_init = vc4_hdmi_phy_init,
2365 .phy_disable = vc4_hdmi_phy_disable,
2366 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
2367 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
2368 .channel_map = vc4_hdmi_channel_map,
2369 .supports_hdr = false,
2372 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2373 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2374 .debugfs_name = "hdmi0_regs",
2375 .card_name = "vc4-hdmi-0",
2376 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2377 .registers = vc5_hdmi_hdmi0_fields,
2378 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2379 .phy_lane_mapping = {
2385 .unsupported_odd_h_timings = true,
2386 .external_irq_controller = true,
2388 .init_resources = vc5_hdmi_init_resources,
2389 .csc_setup = vc5_hdmi_csc_setup,
2390 .reset = vc5_hdmi_reset,
2391 .set_timings = vc5_hdmi_set_timings,
2392 .phy_init = vc5_hdmi_phy_init,
2393 .phy_disable = vc5_hdmi_phy_disable,
2394 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2395 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2396 .channel_map = vc5_hdmi_channel_map,
2397 .supports_hdr = true,
2400 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2401 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
2402 .debugfs_name = "hdmi1_regs",
2403 .card_name = "vc4-hdmi-1",
2404 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2405 .registers = vc5_hdmi_hdmi1_fields,
2406 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2407 .phy_lane_mapping = {
2413 .unsupported_odd_h_timings = true,
2414 .external_irq_controller = true,
2416 .init_resources = vc5_hdmi_init_resources,
2417 .csc_setup = vc5_hdmi_csc_setup,
2418 .reset = vc5_hdmi_reset,
2419 .set_timings = vc5_hdmi_set_timings,
2420 .phy_init = vc5_hdmi_phy_init,
2421 .phy_disable = vc5_hdmi_phy_disable,
2422 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2423 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2424 .channel_map = vc5_hdmi_channel_map,
2425 .supports_hdr = true,
2428 static const struct of_device_id vc4_hdmi_dt_match[] = {
2429 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2430 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2431 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2435 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2436 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2437 vc4_hdmi_runtime_resume,
2441 struct platform_driver vc4_hdmi_driver = {
2442 .probe = vc4_hdmi_dev_probe,
2443 .remove = vc4_hdmi_dev_remove,
2446 .of_match_table = vc4_hdmi_dt_match,
2447 .pm = &vc4_hdmi_pm_ops,