1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Broadcom
8 #include <linux/delay.h>
9 #include <linux/refcount.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_debugfs.h>
14 #include <drm/drm_device.h>
15 #include <drm/drm_encoder.h>
16 #include <drm/drm_gem_cma_helper.h>
17 #include <drm/drm_mm.h>
18 #include <drm/drm_modeset_lock.h>
20 #include "uapi/drm/vc4_drm.h"
23 struct drm_gem_object;
25 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
28 enum vc4_kernel_bo_type {
29 /* Any kernel allocation (gem_create_object hook) before it
30 * gets another type set.
34 VC4_BO_TYPE_V3D_SHADER,
39 VC4_BO_TYPE_KERNEL_CACHE,
43 /* Performance monitor object. The perform lifetime is controlled by userspace
44 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
45 * request, and when this is the case, HW perf counters will be activated just
46 * before the submit_cl is submitted to the GPU and disabled when the job is
47 * done. This way, only events related to a specific job will be counted.
50 /* Tracks the number of users of the perfmon, when this counter reaches
51 * zero the perfmon is destroyed.
55 /* Number of counters activated in this perfmon instance
56 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
60 /* Events counted by the HW perf counters. */
61 u8 events[DRM_VC4_MAX_PERF_COUNTERS];
63 /* Storage for counter values. Counters are incremented by the HW
64 * perf counter values every time the perfmon is attached to a GPU job.
65 * This way, perfmon users don't have to retrieve the results after
66 * each job if they want to track events covering several submissions.
67 * Note that counter values can't be reset, but you can fake a reset by
68 * destroying the perfmon and creating a new one.
74 struct drm_device *dev;
76 struct vc4_hdmi *hdmi;
84 struct vc4_hang_state *hang_state;
86 /* The kernel-space BO cache. Tracks buffers that have been
87 * unreferenced by all other users (refcounts of 0!) but not
88 * yet freed, so we can do cheap allocations.
91 /* Array of list heads for entries in the BO cache,
92 * based on number of pages, so we can do O(1) lookups
93 * in the cache when allocating.
95 struct list_head *size_list;
96 uint32_t size_list_size;
98 /* List of all BOs in the cache, ordered by age, so we
99 * can do O(1) lookups when trying to free old
102 struct list_head time_list;
103 struct work_struct time_work;
104 struct timer_list time_timer;
114 /* Protects bo_cache and bo_labels. */
115 struct mutex bo_lock;
117 /* Purgeable BO pool. All BOs in this pool can have their memory
118 * reclaimed if the driver is unable to allocate new BOs. We also
119 * keep stats related to the purge mechanism here.
122 struct list_head list;
125 unsigned int purged_num;
130 uint64_t dma_fence_context;
132 /* Sequence number for the last job queued in bin_job_list.
133 * Starts at 0 (no jobs emitted).
137 /* Sequence number for the last completed job on the GPU.
138 * Starts at 0 (no jobs completed).
140 uint64_t finished_seqno;
142 /* List of all struct vc4_exec_info for jobs to be executed in
143 * the binner. The first job in the list is the one currently
144 * programmed into ct0ca for execution.
146 struct list_head bin_job_list;
148 /* List of all struct vc4_exec_info for jobs that have
149 * completed binning and are ready for rendering. The first
150 * job in the list is the one currently programmed into ct1ca
153 struct list_head render_job_list;
155 /* List of the finished vc4_exec_infos waiting to be freed by
158 struct list_head job_done_list;
159 /* Spinlock used to synchronize the job_list and seqno
160 * accesses between the IRQ handler and GEM ioctls.
163 wait_queue_head_t job_wait_queue;
164 struct work_struct job_done_work;
166 /* Used to track the active perfmon if any. Access to this field is
167 * protected by job_lock.
169 struct vc4_perfmon *active_perfmon;
171 /* List of struct vc4_seqno_cb for callbacks to be made from a
172 * workqueue when the given seqno is passed.
174 struct list_head seqno_cb_list;
176 /* The memory used for storing binner tile alloc, tile state,
177 * and overflow memory allocations. This is freed when V3D
180 struct vc4_bo *bin_bo;
182 /* Size of blocks allocated within bin_bo. */
183 uint32_t bin_alloc_size;
185 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
188 uint32_t bin_alloc_used;
190 /* Bitmask of the current bin_alloc used for overflow memory. */
191 uint32_t bin_alloc_overflow;
193 /* Incremented when an underrun error happened after an atomic commit.
194 * This is particularly useful to detect when a specific modeset is too
195 * demanding in term of memory or HVS bandwidth which is hard to guess
196 * at atomic check time.
200 struct work_struct overflow_mem_work;
204 /* Set to true when the load tracker is active. */
205 bool load_tracker_enabled;
207 /* Mutex controlling the power refcount. */
208 struct mutex power_lock;
211 struct timer_list timer;
212 struct work_struct reset_work;
215 struct semaphore async_modeset;
217 struct drm_modeset_lock ctm_state_lock;
218 struct drm_private_obj ctm_manager;
219 struct drm_private_obj load_tracker;
221 /* List of vc4_debugfs_info_entry for adding to debugfs once
222 * the minor is available (after drm_dev_register()).
224 struct list_head debugfs_list;
226 /* Mutex for binner bo allocation. */
227 struct mutex bin_bo_lock;
228 /* Reference count for our binner bo. */
229 struct kref bin_bo_kref;
232 static inline struct vc4_dev *
233 to_vc4_dev(struct drm_device *dev)
235 return (struct vc4_dev *)dev->dev_private;
239 struct drm_gem_cma_object base;
241 /* seqno of the last job to render using this BO. */
244 /* seqno of the last job to use the RCL to write to this BO.
246 * Note that this doesn't include binner overflow memory
249 uint64_t write_seqno;
253 /* List entry for the BO's position in either
254 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
256 struct list_head unref_head;
258 /* Time in jiffies when the BO was put in vc4->bo_cache. */
259 unsigned long free_time;
261 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
262 struct list_head size_head;
264 /* Struct for shader validation state, if created by
265 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
267 struct vc4_validated_shader_info *validated_shader;
269 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
270 * for user-allocated labels.
274 /* Count the number of active users. This is needed to determine
275 * whether we can move the BO to the purgeable list or not (when the BO
276 * is used by the GPU or the display engine we can't purge it).
280 /* Store purgeable/purged state here */
282 struct mutex madv_lock;
285 static inline struct vc4_bo *
286 to_vc4_bo(struct drm_gem_object *bo)
288 return (struct vc4_bo *)bo;
292 struct dma_fence base;
293 struct drm_device *dev;
294 /* vc4 seqno for signaled() test */
298 static inline struct vc4_fence *
299 to_vc4_fence(struct dma_fence *fence)
301 return (struct vc4_fence *)fence;
304 struct vc4_seqno_cb {
305 struct work_struct work;
307 void (*func)(struct vc4_seqno_cb *cb);
312 struct platform_device *pdev;
315 struct debugfs_regset32 regset;
319 struct platform_device *pdev;
323 /* Memory manager for CRTCs to allocate space in the display
324 * list. Units are dwords.
326 struct drm_mm dlist_mm;
327 /* Memory manager for the LBM memory used by HVS scaling. */
328 struct drm_mm lbm_mm;
331 struct drm_mm_node mitchell_netravali_filter;
332 struct debugfs_regset32 regset;
336 struct drm_plane base;
339 static inline struct vc4_plane *
340 to_vc4_plane(struct drm_plane *plane)
342 return (struct vc4_plane *)plane;
345 enum vc4_scaling_mode {
351 struct vc4_plane_state {
352 struct drm_plane_state base;
353 /* System memory copy of the display list for this element, computed
354 * at atomic_check time.
357 u32 dlist_size; /* Number of dwords allocated for the display list */
358 u32 dlist_count; /* Number of used dwords in the display list. */
360 /* Offset in the dlist to various words, for pageflip or
368 /* Offset where the plane's dlist was last stored in the
369 * hardware at vc4_crtc_atomic_flush() time.
371 u32 __iomem *hw_dlist;
373 /* Clipped coordinates of the plane on the display. */
374 int crtc_x, crtc_y, crtc_w, crtc_h;
375 /* Clipped area being scanned from in the FB. */
378 u32 src_w[2], src_h[2];
380 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
381 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
385 /* Offset to start scanning out from the start of the plane's
390 /* Our allocation in LBM for temporary storage during scaling. */
391 struct drm_mm_node lbm;
393 /* Set when the plane has per-pixel alpha content or does not cover
394 * the entire screen. This is a hint to the CRTC that it might need
395 * to enable background color fill.
399 /* Mark the dlist as initialized. Useful to avoid initializing it twice
400 * when async update is not possible.
402 bool dlist_initialized;
404 /* Load of this plane on the HVS block. The load is expressed in HVS
409 /* Memory bandwidth needed for this plane. This is expressed in
415 static inline struct vc4_plane_state *
416 to_vc4_plane_state(struct drm_plane_state *state)
418 return (struct vc4_plane_state *)state;
421 enum vc4_encoder_type {
422 VC4_ENCODER_TYPE_NONE,
423 VC4_ENCODER_TYPE_HDMI,
424 VC4_ENCODER_TYPE_VEC,
425 VC4_ENCODER_TYPE_DSI0,
426 VC4_ENCODER_TYPE_DSI1,
427 VC4_ENCODER_TYPE_SMI,
428 VC4_ENCODER_TYPE_DPI,
432 struct drm_encoder base;
433 enum vc4_encoder_type type;
437 static inline struct vc4_encoder *
438 to_vc4_encoder(struct drm_encoder *encoder)
440 return container_of(encoder, struct vc4_encoder, base);
443 struct vc4_crtc_data {
444 /* Which channel of the HVS this pixelvalve sources from. */
449 struct vc4_crtc_data base;
451 enum vc4_encoder_type encoder_types[4];
452 const char *debugfs_name;
457 struct drm_crtc base;
458 struct platform_device *pdev;
459 const struct vc4_crtc_data *data;
462 /* Timestamp at start of vblank irq - unaffected by lock delays. */
465 /* Which HVS channel we're using for our CRTC. */
471 /* Size in pixels of the COB memory allocated to this CRTC. */
474 struct drm_pending_vblank_event *event;
476 struct debugfs_regset32 regset;
479 static inline struct vc4_crtc *
480 to_vc4_crtc(struct drm_crtc *crtc)
482 return (struct vc4_crtc *)crtc;
485 static inline const struct vc4_crtc_data *
486 vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc)
491 static inline const struct vc4_pv_data *
492 vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc)
494 const struct vc4_crtc_data *data = vc4_crtc_to_vc4_crtc_data(crtc);
496 return container_of(data, struct vc4_pv_data, base);
499 struct vc4_crtc_state {
500 struct drm_crtc_state base;
501 /* Dlist area for this CRTC configuration. */
502 struct drm_mm_node mm;
514 static inline struct vc4_crtc_state *
515 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
517 return (struct vc4_crtc_state *)crtc_state;
520 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
521 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
522 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
523 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
525 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
527 struct vc4_exec_info {
528 /* Sequence number for this bin/render job. */
531 /* Latest write_seqno of any BO that binning depends on. */
532 uint64_t bin_dep_seqno;
534 struct dma_fence *fence;
536 /* Last current addresses the hardware was processing when the
537 * hangcheck timer checked on us.
539 uint32_t last_ct0ca, last_ct1ca;
541 /* Kernel-space copy of the ioctl arguments */
542 struct drm_vc4_submit_cl *args;
544 /* This is the array of BOs that were looked up at the start of exec.
545 * Command validation will use indices into this array.
547 struct drm_gem_cma_object **bo;
550 /* List of BOs that are being written by the RCL. Other than
551 * the binner temporary storage, this is all the BOs written
554 struct drm_gem_cma_object *rcl_write_bo[4];
555 uint32_t rcl_write_bo_count;
557 /* Pointers for our position in vc4->job_list */
558 struct list_head head;
560 /* List of other BOs used in the job that need to be released
561 * once the job is complete.
563 struct list_head unref_list;
565 /* Current unvalidated indices into @bo loaded by the non-hardware
566 * VC4_PACKET_GEM_HANDLES.
568 uint32_t bo_index[2];
570 /* This is the BO where we store the validated command lists, shader
571 * records, and uniforms.
573 struct drm_gem_cma_object *exec_bo;
576 * This tracks the per-shader-record state (packet 64) that
577 * determines the length of the shader record and the offset
578 * it's expected to be found at. It gets read in from the
581 struct vc4_shader_state {
583 /* Maximum vertex index referenced by any primitive using this
589 /** How many shader states the user declared they were using. */
590 uint32_t shader_state_size;
591 /** How many shader state records the validator has seen. */
592 uint32_t shader_state_count;
594 bool found_tile_binning_mode_config_packet;
595 bool found_start_tile_binning_packet;
596 bool found_increment_semaphore_packet;
598 uint8_t bin_tiles_x, bin_tiles_y;
599 /* Physical address of the start of the tile alloc array
600 * (where each tile's binned CL will start)
602 uint32_t tile_alloc_offset;
603 /* Bitmask of which binner slots are freed when this job completes. */
607 * Computed addresses pointing into exec_bo where we start the
608 * bin thread (ct0) and render thread (ct1).
610 uint32_t ct0ca, ct0ea;
611 uint32_t ct1ca, ct1ea;
613 /* Pointer to the unvalidated bin CL (if present). */
616 /* Pointers to the shader recs. These paddr gets incremented as CL
617 * packets are relocated in validate_gl_shader_state, and the vaddrs
618 * (u and v) get incremented and size decremented as the shader recs
619 * themselves are validated.
623 uint32_t shader_rec_p;
624 uint32_t shader_rec_size;
626 /* Pointers to the uniform data. These pointers are incremented, and
627 * size decremented, as each batch of uniforms is uploaded.
632 uint32_t uniforms_size;
634 /* Pointer to a performance monitor object if the user requested it,
637 struct vc4_perfmon *perfmon;
639 /* Whether the exec has taken a reference to the binner BO, which should
640 * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet.
645 /* Per-open file private data. Any driver-specific resource that has to be
646 * released when the DRM file is closed should be placed here.
657 static inline struct vc4_exec_info *
658 vc4_first_bin_job(struct vc4_dev *vc4)
660 return list_first_entry_or_null(&vc4->bin_job_list,
661 struct vc4_exec_info, head);
664 static inline struct vc4_exec_info *
665 vc4_first_render_job(struct vc4_dev *vc4)
667 return list_first_entry_or_null(&vc4->render_job_list,
668 struct vc4_exec_info, head);
671 static inline struct vc4_exec_info *
672 vc4_last_render_job(struct vc4_dev *vc4)
674 if (list_empty(&vc4->render_job_list))
676 return list_last_entry(&vc4->render_job_list,
677 struct vc4_exec_info, head);
681 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
684 * This will be used at draw time to relocate the reference to the texture
685 * contents in p0, and validate that the offset combined with
686 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
687 * Note that the hardware treats unprovided config parameters as 0, so not all
688 * of them need to be set up for every texure sample, and we'll store ~0 as
689 * the offset to mark the unused ones.
691 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
692 * Setup") for definitions of the texture parameters.
694 struct vc4_texture_sample_info {
696 uint32_t p_offset[4];
700 * struct vc4_validated_shader_info - information about validated shaders that
701 * needs to be used from command list validation.
703 * For a given shader, each time a shader state record references it, we need
704 * to verify that the shader doesn't read more uniforms than the shader state
705 * record's uniform BO pointer can provide, and we need to apply relocations
706 * and validate the shader state record's uniforms that define the texture
709 struct vc4_validated_shader_info {
710 uint32_t uniforms_size;
711 uint32_t uniforms_src_size;
712 uint32_t num_texture_samples;
713 struct vc4_texture_sample_info *texture_samples;
715 uint32_t num_uniform_addr_offsets;
716 uint32_t *uniform_addr_offsets;
722 * __wait_for - magic wait macro
724 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
725 * important that we check the condition again after having timed out, since the
726 * timeout could be due to preemption or similar and we've never had a chance to
727 * check the condition before the timeout.
729 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
730 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
731 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
735 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
737 /* Guarantee COND check prior to timeout */ \
744 ret__ = -ETIMEDOUT; \
747 usleep_range(wait__, wait__ * 2); \
748 if (wait__ < (Wmax)) \
754 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
756 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
759 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
760 void vc4_free_object(struct drm_gem_object *gem_obj);
761 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
762 bool from_cache, enum vc4_kernel_bo_type type);
763 int vc4_dumb_create(struct drm_file *file_priv,
764 struct drm_device *dev,
765 struct drm_mode_create_dumb *args);
766 struct dma_buf *vc4_prime_export(struct drm_gem_object *obj, int flags);
767 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
768 struct drm_file *file_priv);
769 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
770 struct drm_file *file_priv);
771 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
772 struct drm_file *file_priv);
773 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
774 struct drm_file *file_priv);
775 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
776 struct drm_file *file_priv);
777 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
778 struct drm_file *file_priv);
779 int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
780 struct drm_file *file_priv);
781 vm_fault_t vc4_fault(struct vm_fault *vmf);
782 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
783 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
784 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
785 struct dma_buf_attachment *attach,
786 struct sg_table *sgt);
787 void *vc4_prime_vmap(struct drm_gem_object *obj);
788 int vc4_bo_cache_init(struct drm_device *dev);
789 void vc4_bo_cache_destroy(struct drm_device *dev);
790 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
791 void vc4_bo_dec_usecnt(struct vc4_bo *bo);
792 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
793 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
796 extern struct platform_driver vc4_crtc_driver;
797 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
798 const struct drm_crtc_funcs *crtc_funcs,
799 const struct drm_crtc_helper_funcs *crtc_helper_funcs);
800 void vc4_crtc_destroy(struct drm_crtc *crtc);
801 int vc4_page_flip(struct drm_crtc *crtc,
802 struct drm_framebuffer *fb,
803 struct drm_pending_vblank_event *event,
805 struct drm_modeset_acquire_ctx *ctx);
806 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc);
807 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
808 struct drm_crtc_state *state);
809 void vc4_crtc_reset(struct drm_crtc *crtc);
810 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
811 void vc4_crtc_get_margins(struct drm_crtc_state *state,
812 unsigned int *right, unsigned int *left,
813 unsigned int *top, unsigned int *bottom);
816 void vc4_debugfs_init(struct drm_minor *minor);
817 #ifdef CONFIG_DEBUG_FS
818 void vc4_debugfs_add_file(struct drm_device *drm,
819 const char *filename,
820 int (*show)(struct seq_file*, void*),
822 void vc4_debugfs_add_regset32(struct drm_device *drm,
823 const char *filename,
824 struct debugfs_regset32 *regset);
826 static inline void vc4_debugfs_add_file(struct drm_device *drm,
827 const char *filename,
828 int (*show)(struct seq_file*, void*),
833 static inline void vc4_debugfs_add_regset32(struct drm_device *drm,
834 const char *filename,
835 struct debugfs_regset32 *regset)
841 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
844 extern struct platform_driver vc4_dpi_driver;
847 extern struct platform_driver vc4_dsi_driver;
850 extern const struct dma_fence_ops vc4_fence_ops;
853 void vc4_gem_init(struct drm_device *dev);
854 void vc4_gem_destroy(struct drm_device *dev);
855 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
856 struct drm_file *file_priv);
857 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
858 struct drm_file *file_priv);
859 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
860 struct drm_file *file_priv);
861 void vc4_submit_next_bin_job(struct drm_device *dev);
862 void vc4_submit_next_render_job(struct drm_device *dev);
863 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
864 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
865 uint64_t timeout_ns, bool interruptible);
866 void vc4_job_handle_completed(struct vc4_dev *vc4);
867 int vc4_queue_seqno_cb(struct drm_device *dev,
868 struct vc4_seqno_cb *cb, uint64_t seqno,
869 void (*func)(struct vc4_seqno_cb *cb));
870 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
871 struct drm_file *file_priv);
874 extern struct platform_driver vc4_hdmi_driver;
877 extern struct platform_driver vc4_vec_driver;
880 extern struct platform_driver vc4_txp_driver;
883 irqreturn_t vc4_irq(int irq, void *arg);
884 void vc4_irq_preinstall(struct drm_device *dev);
885 int vc4_irq_postinstall(struct drm_device *dev);
886 void vc4_irq_uninstall(struct drm_device *dev);
887 void vc4_irq_reset(struct drm_device *dev);
890 extern struct platform_driver vc4_hvs_driver;
891 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
892 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state);
893 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state);
894 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state);
895 void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc);
896 void vc4_hvs_dump_state(struct drm_device *dev);
897 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
898 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
901 int vc4_kms_load(struct drm_device *dev);
904 struct drm_plane *vc4_plane_init(struct drm_device *dev,
905 enum drm_plane_type type);
906 int vc4_plane_create_additional_planes(struct drm_device *dev);
907 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
908 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
909 void vc4_plane_async_set_fb(struct drm_plane *plane,
910 struct drm_framebuffer *fb);
913 extern struct platform_driver vc4_v3d_driver;
914 extern const struct of_device_id vc4_v3d_dt_match[];
915 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
916 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used);
917 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4);
918 int vc4_v3d_pm_get(struct vc4_dev *vc4);
919 void vc4_v3d_pm_put(struct vc4_dev *vc4);
923 vc4_validate_bin_cl(struct drm_device *dev,
926 struct vc4_exec_info *exec);
929 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
931 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
934 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
936 bool vc4_check_tex_size(struct vc4_exec_info *exec,
937 struct drm_gem_cma_object *fbo,
938 uint32_t offset, uint8_t tiling_format,
939 uint32_t width, uint32_t height, uint8_t cpp);
941 /* vc4_validate_shader.c */
942 struct vc4_validated_shader_info *
943 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
946 void vc4_perfmon_get(struct vc4_perfmon *perfmon);
947 void vc4_perfmon_put(struct vc4_perfmon *perfmon);
948 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
949 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
951 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
952 void vc4_perfmon_open_file(struct vc4_file *vc4file);
953 void vc4_perfmon_close_file(struct vc4_file *vc4file);
954 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
955 struct drm_file *file_priv);
956 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
957 struct drm_file *file_priv);
958 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
959 struct drm_file *file_priv);
961 #endif /* _VC4_DRV_H_ */