1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Broadcom
8 #include <linux/delay.h>
9 #include <linux/refcount.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_debugfs.h>
14 #include <drm/drm_device.h>
15 #include <drm/drm_encoder.h>
16 #include <drm/drm_gem_cma_helper.h>
17 #include <drm/drm_mm.h>
18 #include <drm/drm_modeset_lock.h>
20 #include "uapi/drm/vc4_drm.h"
23 struct drm_gem_object;
25 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
28 enum vc4_kernel_bo_type {
29 /* Any kernel allocation (gem_create_object hook) before it
30 * gets another type set.
34 VC4_BO_TYPE_V3D_SHADER,
39 VC4_BO_TYPE_KERNEL_CACHE,
43 /* Performance monitor object. The perform lifetime is controlled by userspace
44 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
45 * request, and when this is the case, HW perf counters will be activated just
46 * before the submit_cl is submitted to the GPU and disabled when the job is
47 * done. This way, only events related to a specific job will be counted.
50 /* Tracks the number of users of the perfmon, when this counter reaches
51 * zero the perfmon is destroyed.
55 /* Number of counters activated in this perfmon instance
56 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
60 /* Events counted by the HW perf counters. */
61 u8 events[DRM_VC4_MAX_PERF_COUNTERS];
63 /* Storage for counter values. Counters are incremented by the HW
64 * perf counter values every time the perfmon is attached to a GPU job.
65 * This way, perfmon users don't have to retrieve the results after
66 * each job if they want to track events covering several submissions.
67 * Note that counter values can't be reset, but you can fake a reset by
68 * destroying the perfmon and creating a new one.
74 struct drm_device *dev;
83 struct vc4_hang_state *hang_state;
85 /* The kernel-space BO cache. Tracks buffers that have been
86 * unreferenced by all other users (refcounts of 0!) but not
87 * yet freed, so we can do cheap allocations.
90 /* Array of list heads for entries in the BO cache,
91 * based on number of pages, so we can do O(1) lookups
92 * in the cache when allocating.
94 struct list_head *size_list;
95 uint32_t size_list_size;
97 /* List of all BOs in the cache, ordered by age, so we
98 * can do O(1) lookups when trying to free old
101 struct list_head time_list;
102 struct work_struct time_work;
103 struct timer_list time_timer;
113 /* Protects bo_cache and bo_labels. */
114 struct mutex bo_lock;
116 /* Purgeable BO pool. All BOs in this pool can have their memory
117 * reclaimed if the driver is unable to allocate new BOs. We also
118 * keep stats related to the purge mechanism here.
121 struct list_head list;
124 unsigned int purged_num;
129 uint64_t dma_fence_context;
131 /* Sequence number for the last job queued in bin_job_list.
132 * Starts at 0 (no jobs emitted).
136 /* Sequence number for the last completed job on the GPU.
137 * Starts at 0 (no jobs completed).
139 uint64_t finished_seqno;
141 /* List of all struct vc4_exec_info for jobs to be executed in
142 * the binner. The first job in the list is the one currently
143 * programmed into ct0ca for execution.
145 struct list_head bin_job_list;
147 /* List of all struct vc4_exec_info for jobs that have
148 * completed binning and are ready for rendering. The first
149 * job in the list is the one currently programmed into ct1ca
152 struct list_head render_job_list;
154 /* List of the finished vc4_exec_infos waiting to be freed by
157 struct list_head job_done_list;
158 /* Spinlock used to synchronize the job_list and seqno
159 * accesses between the IRQ handler and GEM ioctls.
162 wait_queue_head_t job_wait_queue;
163 struct work_struct job_done_work;
165 /* Used to track the active perfmon if any. Access to this field is
166 * protected by job_lock.
168 struct vc4_perfmon *active_perfmon;
170 /* List of struct vc4_seqno_cb for callbacks to be made from a
171 * workqueue when the given seqno is passed.
173 struct list_head seqno_cb_list;
175 /* The memory used for storing binner tile alloc, tile state,
176 * and overflow memory allocations. This is freed when V3D
179 struct vc4_bo *bin_bo;
181 /* Size of blocks allocated within bin_bo. */
182 uint32_t bin_alloc_size;
184 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
187 uint32_t bin_alloc_used;
189 /* Bitmask of the current bin_alloc used for overflow memory. */
190 uint32_t bin_alloc_overflow;
192 /* Incremented when an underrun error happened after an atomic commit.
193 * This is particularly useful to detect when a specific modeset is too
194 * demanding in term of memory or HVS bandwidth which is hard to guess
195 * at atomic check time.
199 struct work_struct overflow_mem_work;
203 /* Set to true when the load tracker is supported. */
204 bool load_tracker_available;
206 /* Set to true when the load tracker is active. */
207 bool load_tracker_enabled;
209 /* Mutex controlling the power refcount. */
210 struct mutex power_lock;
213 struct timer_list timer;
214 struct work_struct reset_work;
217 struct semaphore async_modeset;
219 struct drm_modeset_lock ctm_state_lock;
220 struct drm_private_obj ctm_manager;
221 struct drm_private_obj load_tracker;
223 /* List of vc4_debugfs_info_entry for adding to debugfs once
224 * the minor is available (after drm_dev_register()).
226 struct list_head debugfs_list;
228 /* Mutex for binner bo allocation. */
229 struct mutex bin_bo_lock;
230 /* Reference count for our binner bo. */
231 struct kref bin_bo_kref;
234 static inline struct vc4_dev *
235 to_vc4_dev(struct drm_device *dev)
237 return (struct vc4_dev *)dev->dev_private;
241 struct drm_gem_cma_object base;
243 /* seqno of the last job to render using this BO. */
246 /* seqno of the last job to use the RCL to write to this BO.
248 * Note that this doesn't include binner overflow memory
251 uint64_t write_seqno;
255 /* List entry for the BO's position in either
256 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
258 struct list_head unref_head;
260 /* Time in jiffies when the BO was put in vc4->bo_cache. */
261 unsigned long free_time;
263 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
264 struct list_head size_head;
266 /* Struct for shader validation state, if created by
267 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
269 struct vc4_validated_shader_info *validated_shader;
271 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
272 * for user-allocated labels.
276 /* Count the number of active users. This is needed to determine
277 * whether we can move the BO to the purgeable list or not (when the BO
278 * is used by the GPU or the display engine we can't purge it).
282 /* Store purgeable/purged state here */
284 struct mutex madv_lock;
287 static inline struct vc4_bo *
288 to_vc4_bo(struct drm_gem_object *bo)
290 return container_of(to_drm_gem_cma_obj(bo), struct vc4_bo, base);
294 struct dma_fence base;
295 struct drm_device *dev;
296 /* vc4 seqno for signaled() test */
300 static inline struct vc4_fence *
301 to_vc4_fence(struct dma_fence *fence)
303 return container_of(fence, struct vc4_fence, base);
306 struct vc4_seqno_cb {
307 struct work_struct work;
309 void (*func)(struct vc4_seqno_cb *cb);
314 struct platform_device *pdev;
317 struct debugfs_regset32 regset;
321 struct platform_device *pdev;
325 struct clk *core_clk;
327 /* Memory manager for CRTCs to allocate space in the display
328 * list. Units are dwords.
330 struct drm_mm dlist_mm;
331 /* Memory manager for the LBM memory used by HVS scaling. */
332 struct drm_mm lbm_mm;
335 struct drm_mm_node mitchell_netravali_filter;
337 struct debugfs_regset32 regset;
339 /* HVS version 5 flag, therefore requires updated dlist structures */
344 struct drm_plane base;
347 static inline struct vc4_plane *
348 to_vc4_plane(struct drm_plane *plane)
350 return container_of(plane, struct vc4_plane, base);
353 enum vc4_scaling_mode {
359 struct vc4_plane_state {
360 struct drm_plane_state base;
361 /* System memory copy of the display list for this element, computed
362 * at atomic_check time.
365 u32 dlist_size; /* Number of dwords allocated for the display list */
366 u32 dlist_count; /* Number of used dwords in the display list. */
368 /* Offset in the dlist to various words, for pageflip or
376 /* Offset where the plane's dlist was last stored in the
377 * hardware at vc4_crtc_atomic_flush() time.
379 u32 __iomem *hw_dlist;
381 /* Clipped coordinates of the plane on the display. */
382 int crtc_x, crtc_y, crtc_w, crtc_h;
383 /* Clipped area being scanned from in the FB. */
386 u32 src_w[2], src_h[2];
388 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
389 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
393 /* Offset to start scanning out from the start of the plane's
398 /* Our allocation in LBM for temporary storage during scaling. */
399 struct drm_mm_node lbm;
401 /* Set when the plane has per-pixel alpha content or does not cover
402 * the entire screen. This is a hint to the CRTC that it might need
403 * to enable background color fill.
407 /* Mark the dlist as initialized. Useful to avoid initializing it twice
408 * when async update is not possible.
410 bool dlist_initialized;
412 /* Load of this plane on the HVS block. The load is expressed in HVS
417 /* Memory bandwidth needed for this plane. This is expressed in
423 static inline struct vc4_plane_state *
424 to_vc4_plane_state(struct drm_plane_state *state)
426 return container_of(state, struct vc4_plane_state, base);
429 enum vc4_encoder_type {
430 VC4_ENCODER_TYPE_NONE,
431 VC4_ENCODER_TYPE_HDMI0,
432 VC4_ENCODER_TYPE_HDMI1,
433 VC4_ENCODER_TYPE_VEC,
434 VC4_ENCODER_TYPE_DSI0,
435 VC4_ENCODER_TYPE_DSI1,
436 VC4_ENCODER_TYPE_SMI,
437 VC4_ENCODER_TYPE_DPI,
441 struct drm_encoder base;
442 enum vc4_encoder_type type;
445 void (*pre_crtc_configure)(struct drm_encoder *encoder);
446 void (*pre_crtc_enable)(struct drm_encoder *encoder);
447 void (*post_crtc_enable)(struct drm_encoder *encoder);
449 void (*post_crtc_disable)(struct drm_encoder *encoder);
450 void (*post_crtc_powerdown)(struct drm_encoder *encoder);
453 static inline struct vc4_encoder *
454 to_vc4_encoder(struct drm_encoder *encoder)
456 return container_of(encoder, struct vc4_encoder, base);
459 struct vc4_crtc_data {
460 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */
461 unsigned int hvs_available_channels;
463 /* Which output of the HVS this pixelvalve sources from. */
468 struct vc4_crtc_data base;
470 /* Depth of the PixelValve FIFO in bytes */
471 unsigned int fifo_depth;
473 /* Number of pixels output per clock period */
476 enum vc4_encoder_type encoder_types[4];
477 const char *debugfs_name;
482 struct drm_crtc base;
483 struct platform_device *pdev;
484 const struct vc4_crtc_data *data;
487 /* Timestamp at start of vblank irq - unaffected by lock delays. */
494 struct drm_pending_vblank_event *event;
496 struct debugfs_regset32 regset;
499 static inline struct vc4_crtc *
500 to_vc4_crtc(struct drm_crtc *crtc)
502 return container_of(crtc, struct vc4_crtc, base);
505 static inline const struct vc4_crtc_data *
506 vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc)
511 static inline const struct vc4_pv_data *
512 vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc)
514 const struct vc4_crtc_data *data = vc4_crtc_to_vc4_crtc_data(crtc);
516 return container_of(data, struct vc4_pv_data, base);
519 struct vc4_crtc_state {
520 struct drm_crtc_state base;
521 /* Dlist area for this CRTC configuration. */
522 struct drm_mm_node mm;
525 unsigned int assigned_channel;
535 #define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1)
537 static inline struct vc4_crtc_state *
538 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
540 return container_of(crtc_state, struct vc4_crtc_state, base);
543 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
544 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
545 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
546 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
548 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
550 struct vc4_exec_info {
551 /* Sequence number for this bin/render job. */
554 /* Latest write_seqno of any BO that binning depends on. */
555 uint64_t bin_dep_seqno;
557 struct dma_fence *fence;
559 /* Last current addresses the hardware was processing when the
560 * hangcheck timer checked on us.
562 uint32_t last_ct0ca, last_ct1ca;
564 /* Kernel-space copy of the ioctl arguments */
565 struct drm_vc4_submit_cl *args;
567 /* This is the array of BOs that were looked up at the start of exec.
568 * Command validation will use indices into this array.
570 struct drm_gem_cma_object **bo;
573 /* List of BOs that are being written by the RCL. Other than
574 * the binner temporary storage, this is all the BOs written
577 struct drm_gem_cma_object *rcl_write_bo[4];
578 uint32_t rcl_write_bo_count;
580 /* Pointers for our position in vc4->job_list */
581 struct list_head head;
583 /* List of other BOs used in the job that need to be released
584 * once the job is complete.
586 struct list_head unref_list;
588 /* Current unvalidated indices into @bo loaded by the non-hardware
589 * VC4_PACKET_GEM_HANDLES.
591 uint32_t bo_index[2];
593 /* This is the BO where we store the validated command lists, shader
594 * records, and uniforms.
596 struct drm_gem_cma_object *exec_bo;
599 * This tracks the per-shader-record state (packet 64) that
600 * determines the length of the shader record and the offset
601 * it's expected to be found at. It gets read in from the
604 struct vc4_shader_state {
606 /* Maximum vertex index referenced by any primitive using this
612 /** How many shader states the user declared they were using. */
613 uint32_t shader_state_size;
614 /** How many shader state records the validator has seen. */
615 uint32_t shader_state_count;
617 bool found_tile_binning_mode_config_packet;
618 bool found_start_tile_binning_packet;
619 bool found_increment_semaphore_packet;
621 uint8_t bin_tiles_x, bin_tiles_y;
622 /* Physical address of the start of the tile alloc array
623 * (where each tile's binned CL will start)
625 uint32_t tile_alloc_offset;
626 /* Bitmask of which binner slots are freed when this job completes. */
630 * Computed addresses pointing into exec_bo where we start the
631 * bin thread (ct0) and render thread (ct1).
633 uint32_t ct0ca, ct0ea;
634 uint32_t ct1ca, ct1ea;
636 /* Pointer to the unvalidated bin CL (if present). */
639 /* Pointers to the shader recs. These paddr gets incremented as CL
640 * packets are relocated in validate_gl_shader_state, and the vaddrs
641 * (u and v) get incremented and size decremented as the shader recs
642 * themselves are validated.
646 uint32_t shader_rec_p;
647 uint32_t shader_rec_size;
649 /* Pointers to the uniform data. These pointers are incremented, and
650 * size decremented, as each batch of uniforms is uploaded.
655 uint32_t uniforms_size;
657 /* Pointer to a performance monitor object if the user requested it,
660 struct vc4_perfmon *perfmon;
662 /* Whether the exec has taken a reference to the binner BO, which should
663 * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet.
668 /* Per-open file private data. Any driver-specific resource that has to be
669 * released when the DRM file is closed should be placed here.
680 static inline struct vc4_exec_info *
681 vc4_first_bin_job(struct vc4_dev *vc4)
683 return list_first_entry_or_null(&vc4->bin_job_list,
684 struct vc4_exec_info, head);
687 static inline struct vc4_exec_info *
688 vc4_first_render_job(struct vc4_dev *vc4)
690 return list_first_entry_or_null(&vc4->render_job_list,
691 struct vc4_exec_info, head);
694 static inline struct vc4_exec_info *
695 vc4_last_render_job(struct vc4_dev *vc4)
697 if (list_empty(&vc4->render_job_list))
699 return list_last_entry(&vc4->render_job_list,
700 struct vc4_exec_info, head);
704 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
707 * This will be used at draw time to relocate the reference to the texture
708 * contents in p0, and validate that the offset combined with
709 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
710 * Note that the hardware treats unprovided config parameters as 0, so not all
711 * of them need to be set up for every texure sample, and we'll store ~0 as
712 * the offset to mark the unused ones.
714 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
715 * Setup") for definitions of the texture parameters.
717 struct vc4_texture_sample_info {
719 uint32_t p_offset[4];
723 * struct vc4_validated_shader_info - information about validated shaders that
724 * needs to be used from command list validation.
726 * For a given shader, each time a shader state record references it, we need
727 * to verify that the shader doesn't read more uniforms than the shader state
728 * record's uniform BO pointer can provide, and we need to apply relocations
729 * and validate the shader state record's uniforms that define the texture
732 struct vc4_validated_shader_info {
733 uint32_t uniforms_size;
734 uint32_t uniforms_src_size;
735 uint32_t num_texture_samples;
736 struct vc4_texture_sample_info *texture_samples;
738 uint32_t num_uniform_addr_offsets;
739 uint32_t *uniform_addr_offsets;
745 * __wait_for - magic wait macro
747 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
748 * important that we check the condition again after having timed out, since the
749 * timeout could be due to preemption or similar and we've never had a chance to
750 * check the condition before the timeout.
752 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
753 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
754 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
758 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
760 /* Guarantee COND check prior to timeout */ \
767 ret__ = -ETIMEDOUT; \
770 usleep_range(wait__, wait__ * 2); \
771 if (wait__ < (Wmax)) \
777 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
779 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
782 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
783 void vc4_free_object(struct drm_gem_object *gem_obj);
784 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
785 bool from_cache, enum vc4_kernel_bo_type type);
786 int vc4_dumb_create(struct drm_file *file_priv,
787 struct drm_device *dev,
788 struct drm_mode_create_dumb *args);
789 struct dma_buf *vc4_prime_export(struct drm_gem_object *obj, int flags);
790 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
791 struct drm_file *file_priv);
792 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
793 struct drm_file *file_priv);
794 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
795 struct drm_file *file_priv);
796 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
797 struct drm_file *file_priv);
798 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
799 struct drm_file *file_priv);
800 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
801 struct drm_file *file_priv);
802 int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
803 struct drm_file *file_priv);
804 vm_fault_t vc4_fault(struct vm_fault *vmf);
805 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
806 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
807 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
808 struct dma_buf_attachment *attach,
809 struct sg_table *sgt);
810 void *vc4_prime_vmap(struct drm_gem_object *obj);
811 int vc4_bo_cache_init(struct drm_device *dev);
812 void vc4_bo_cache_destroy(struct drm_device *dev);
813 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
814 void vc4_bo_dec_usecnt(struct vc4_bo *bo);
815 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
816 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
819 extern struct platform_driver vc4_crtc_driver;
820 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc);
821 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
822 const struct drm_crtc_funcs *crtc_funcs,
823 const struct drm_crtc_helper_funcs *crtc_helper_funcs);
824 void vc4_crtc_destroy(struct drm_crtc *crtc);
825 int vc4_page_flip(struct drm_crtc *crtc,
826 struct drm_framebuffer *fb,
827 struct drm_pending_vblank_event *event,
829 struct drm_modeset_acquire_ctx *ctx);
830 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc);
831 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
832 struct drm_crtc_state *state);
833 void vc4_crtc_reset(struct drm_crtc *crtc);
834 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
835 void vc4_crtc_get_margins(struct drm_crtc_state *state,
836 unsigned int *right, unsigned int *left,
837 unsigned int *top, unsigned int *bottom);
840 void vc4_debugfs_init(struct drm_minor *minor);
841 #ifdef CONFIG_DEBUG_FS
842 void vc4_debugfs_add_file(struct drm_device *drm,
843 const char *filename,
844 int (*show)(struct seq_file*, void*),
846 void vc4_debugfs_add_regset32(struct drm_device *drm,
847 const char *filename,
848 struct debugfs_regset32 *regset);
850 static inline void vc4_debugfs_add_file(struct drm_device *drm,
851 const char *filename,
852 int (*show)(struct seq_file*, void*),
857 static inline void vc4_debugfs_add_regset32(struct drm_device *drm,
858 const char *filename,
859 struct debugfs_regset32 *regset)
865 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
868 extern struct platform_driver vc4_dpi_driver;
871 extern struct platform_driver vc4_dsi_driver;
874 extern const struct dma_fence_ops vc4_fence_ops;
877 void vc4_gem_init(struct drm_device *dev);
878 void vc4_gem_destroy(struct drm_device *dev);
879 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
880 struct drm_file *file_priv);
881 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
882 struct drm_file *file_priv);
883 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
884 struct drm_file *file_priv);
885 void vc4_submit_next_bin_job(struct drm_device *dev);
886 void vc4_submit_next_render_job(struct drm_device *dev);
887 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
888 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
889 uint64_t timeout_ns, bool interruptible);
890 void vc4_job_handle_completed(struct vc4_dev *vc4);
891 int vc4_queue_seqno_cb(struct drm_device *dev,
892 struct vc4_seqno_cb *cb, uint64_t seqno,
893 void (*func)(struct vc4_seqno_cb *cb));
894 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
895 struct drm_file *file_priv);
898 extern struct platform_driver vc4_hdmi_driver;
901 extern struct platform_driver vc4_vec_driver;
904 extern struct platform_driver vc4_txp_driver;
907 irqreturn_t vc4_irq(int irq, void *arg);
908 void vc4_irq_preinstall(struct drm_device *dev);
909 int vc4_irq_postinstall(struct drm_device *dev);
910 void vc4_irq_uninstall(struct drm_device *dev);
911 void vc4_irq_reset(struct drm_device *dev);
914 extern struct platform_driver vc4_hvs_driver;
915 void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
916 int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
917 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
918 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state);
919 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state);
920 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state);
921 void vc4_hvs_dump_state(struct drm_device *dev);
922 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
923 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
926 int vc4_kms_load(struct drm_device *dev);
929 struct drm_plane *vc4_plane_init(struct drm_device *dev,
930 enum drm_plane_type type);
931 int vc4_plane_create_additional_planes(struct drm_device *dev);
932 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
933 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
934 void vc4_plane_async_set_fb(struct drm_plane *plane,
935 struct drm_framebuffer *fb);
938 extern struct platform_driver vc4_v3d_driver;
939 extern const struct of_device_id vc4_v3d_dt_match[];
940 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
941 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used);
942 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4);
943 int vc4_v3d_pm_get(struct vc4_dev *vc4);
944 void vc4_v3d_pm_put(struct vc4_dev *vc4);
948 vc4_validate_bin_cl(struct drm_device *dev,
951 struct vc4_exec_info *exec);
954 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
956 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
959 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
961 bool vc4_check_tex_size(struct vc4_exec_info *exec,
962 struct drm_gem_cma_object *fbo,
963 uint32_t offset, uint8_t tiling_format,
964 uint32_t width, uint32_t height, uint8_t cpp);
966 /* vc4_validate_shader.c */
967 struct vc4_validated_shader_info *
968 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
971 void vc4_perfmon_get(struct vc4_perfmon *perfmon);
972 void vc4_perfmon_put(struct vc4_perfmon *perfmon);
973 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
974 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
976 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
977 void vc4_perfmon_open_file(struct vc4_file *vc4file);
978 void vc4_perfmon_close_file(struct vc4_file *vc4file);
979 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
980 struct drm_file *file_priv);
981 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
982 struct drm_file *file_priv);
983 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
984 struct drm_file *file_priv);
986 #endif /* _VC4_DRV_H_ */