2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "drm_gem_cma_helper.h"
11 #include "drm_gem_cma_helper.h"
13 #include <linux/reservation.h>
14 #include <drm/drm_encoder.h>
17 struct drm_device *dev;
19 struct vc4_hdmi *hdmi;
26 struct drm_fbdev_cma *fbdev;
28 struct vc4_hang_state *hang_state;
30 /* The kernel-space BO cache. Tracks buffers that have been
31 * unreferenced by all other users (refcounts of 0!) but not
32 * yet freed, so we can do cheap allocations.
35 /* Array of list heads for entries in the BO cache,
36 * based on number of pages, so we can do O(1) lookups
37 * in the cache when allocating.
39 struct list_head *size_list;
40 uint32_t size_list_size;
42 /* List of all BOs in the cache, ordered by age, so we
43 * can do O(1) lookups when trying to free old
46 struct list_head time_list;
47 struct work_struct time_work;
48 struct timer_list time_timer;
58 /* Protects bo_cache and the BO stats. */
61 uint64_t dma_fence_context;
63 /* Sequence number for the last job queued in bin_job_list.
64 * Starts at 0 (no jobs emitted).
68 /* Sequence number for the last completed job on the GPU.
69 * Starts at 0 (no jobs completed).
71 uint64_t finished_seqno;
73 /* List of all struct vc4_exec_info for jobs to be executed in
74 * the binner. The first job in the list is the one currently
75 * programmed into ct0ca for execution.
77 struct list_head bin_job_list;
79 /* List of all struct vc4_exec_info for jobs that have
80 * completed binning and are ready for rendering. The first
81 * job in the list is the one currently programmed into ct1ca
84 struct list_head render_job_list;
86 /* List of the finished vc4_exec_infos waiting to be freed by
89 struct list_head job_done_list;
90 /* Spinlock used to synchronize the job_list and seqno
91 * accesses between the IRQ handler and GEM ioctls.
94 wait_queue_head_t job_wait_queue;
95 struct work_struct job_done_work;
97 /* List of struct vc4_seqno_cb for callbacks to be made from a
98 * workqueue when the given seqno is passed.
100 struct list_head seqno_cb_list;
102 /* The memory used for storing binner tile alloc, tile state,
103 * and overflow memory allocations. This is freed when V3D
106 struct vc4_bo *bin_bo;
108 /* Size of blocks allocated within bin_bo. */
109 uint32_t bin_alloc_size;
111 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
114 uint32_t bin_alloc_used;
116 /* Bitmask of the current bin_alloc used for overflow memory. */
117 uint32_t bin_alloc_overflow;
119 struct work_struct overflow_mem_work;
123 /* Mutex controlling the power refcount. */
124 struct mutex power_lock;
127 struct timer_list timer;
128 struct work_struct reset_work;
131 struct semaphore async_modeset;
134 static inline struct vc4_dev *
135 to_vc4_dev(struct drm_device *dev)
137 return (struct vc4_dev *)dev->dev_private;
141 struct drm_gem_cma_object base;
143 /* seqno of the last job to render using this BO. */
146 /* seqno of the last job to use the RCL to write to this BO.
148 * Note that this doesn't include binner overflow memory
151 uint64_t write_seqno;
153 /* List entry for the BO's position in either
154 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
156 struct list_head unref_head;
158 /* Time in jiffies when the BO was put in vc4->bo_cache. */
159 unsigned long free_time;
161 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
162 struct list_head size_head;
164 /* Struct for shader validation state, if created by
165 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
167 struct vc4_validated_shader_info *validated_shader;
169 /* normally (resv == &_resv) except for imported bo's */
170 struct reservation_object *resv;
171 struct reservation_object _resv;
174 static inline struct vc4_bo *
175 to_vc4_bo(struct drm_gem_object *bo)
177 return (struct vc4_bo *)bo;
181 struct dma_fence base;
182 struct drm_device *dev;
183 /* vc4 seqno for signaled() test */
187 static inline struct vc4_fence *
188 to_vc4_fence(struct dma_fence *fence)
190 return (struct vc4_fence *)fence;
193 struct vc4_seqno_cb {
194 struct work_struct work;
196 void (*func)(struct vc4_seqno_cb *cb);
201 struct platform_device *pdev;
207 struct platform_device *pdev;
211 /* Memory manager for CRTCs to allocate space in the display
212 * list. Units are dwords.
214 struct drm_mm dlist_mm;
215 /* Memory manager for the LBM memory used by HVS scaling. */
216 struct drm_mm lbm_mm;
219 struct drm_mm_node mitchell_netravali_filter;
223 struct drm_plane base;
226 static inline struct vc4_plane *
227 to_vc4_plane(struct drm_plane *plane)
229 return (struct vc4_plane *)plane;
232 enum vc4_encoder_type {
233 VC4_ENCODER_TYPE_NONE,
234 VC4_ENCODER_TYPE_HDMI,
235 VC4_ENCODER_TYPE_VEC,
236 VC4_ENCODER_TYPE_DSI0,
237 VC4_ENCODER_TYPE_DSI1,
238 VC4_ENCODER_TYPE_SMI,
239 VC4_ENCODER_TYPE_DPI,
243 struct drm_encoder base;
244 enum vc4_encoder_type type;
248 static inline struct vc4_encoder *
249 to_vc4_encoder(struct drm_encoder *encoder)
251 return container_of(encoder, struct vc4_encoder, base);
254 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
255 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
256 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
257 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
259 struct vc4_exec_info {
260 /* Sequence number for this bin/render job. */
263 /* Latest write_seqno of any BO that binning depends on. */
264 uint64_t bin_dep_seqno;
266 struct dma_fence *fence;
268 /* Last current addresses the hardware was processing when the
269 * hangcheck timer checked on us.
271 uint32_t last_ct0ca, last_ct1ca;
273 /* Kernel-space copy of the ioctl arguments */
274 struct drm_vc4_submit_cl *args;
276 /* This is the array of BOs that were looked up at the start of exec.
277 * Command validation will use indices into this array.
279 struct drm_gem_cma_object **bo;
282 /* List of BOs that are being written by the RCL. Other than
283 * the binner temporary storage, this is all the BOs written
286 struct drm_gem_cma_object *rcl_write_bo[4];
287 uint32_t rcl_write_bo_count;
289 /* Pointers for our position in vc4->job_list */
290 struct list_head head;
292 /* List of other BOs used in the job that need to be released
293 * once the job is complete.
295 struct list_head unref_list;
297 /* Current unvalidated indices into @bo loaded by the non-hardware
298 * VC4_PACKET_GEM_HANDLES.
300 uint32_t bo_index[2];
302 /* This is the BO where we store the validated command lists, shader
303 * records, and uniforms.
305 struct drm_gem_cma_object *exec_bo;
308 * This tracks the per-shader-record state (packet 64) that
309 * determines the length of the shader record and the offset
310 * it's expected to be found at. It gets read in from the
313 struct vc4_shader_state {
315 /* Maximum vertex index referenced by any primitive using this
321 /** How many shader states the user declared they were using. */
322 uint32_t shader_state_size;
323 /** How many shader state records the validator has seen. */
324 uint32_t shader_state_count;
326 bool found_tile_binning_mode_config_packet;
327 bool found_start_tile_binning_packet;
328 bool found_increment_semaphore_packet;
330 uint8_t bin_tiles_x, bin_tiles_y;
331 /* Physical address of the start of the tile alloc array
332 * (where each tile's binned CL will start)
334 uint32_t tile_alloc_offset;
335 /* Bitmask of which binner slots are freed when this job completes. */
339 * Computed addresses pointing into exec_bo where we start the
340 * bin thread (ct0) and render thread (ct1).
342 uint32_t ct0ca, ct0ea;
343 uint32_t ct1ca, ct1ea;
345 /* Pointer to the unvalidated bin CL (if present). */
348 /* Pointers to the shader recs. These paddr gets incremented as CL
349 * packets are relocated in validate_gl_shader_state, and the vaddrs
350 * (u and v) get incremented and size decremented as the shader recs
351 * themselves are validated.
355 uint32_t shader_rec_p;
356 uint32_t shader_rec_size;
358 /* Pointers to the uniform data. These pointers are incremented, and
359 * size decremented, as each batch of uniforms is uploaded.
364 uint32_t uniforms_size;
367 static inline struct vc4_exec_info *
368 vc4_first_bin_job(struct vc4_dev *vc4)
370 return list_first_entry_or_null(&vc4->bin_job_list,
371 struct vc4_exec_info, head);
374 static inline struct vc4_exec_info *
375 vc4_first_render_job(struct vc4_dev *vc4)
377 return list_first_entry_or_null(&vc4->render_job_list,
378 struct vc4_exec_info, head);
381 static inline struct vc4_exec_info *
382 vc4_last_render_job(struct vc4_dev *vc4)
384 if (list_empty(&vc4->render_job_list))
386 return list_last_entry(&vc4->render_job_list,
387 struct vc4_exec_info, head);
391 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
394 * This will be used at draw time to relocate the reference to the texture
395 * contents in p0, and validate that the offset combined with
396 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
397 * Note that the hardware treats unprovided config parameters as 0, so not all
398 * of them need to be set up for every texure sample, and we'll store ~0 as
399 * the offset to mark the unused ones.
401 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
402 * Setup") for definitions of the texture parameters.
404 struct vc4_texture_sample_info {
406 uint32_t p_offset[4];
410 * struct vc4_validated_shader_info - information about validated shaders that
411 * needs to be used from command list validation.
413 * For a given shader, each time a shader state record references it, we need
414 * to verify that the shader doesn't read more uniforms than the shader state
415 * record's uniform BO pointer can provide, and we need to apply relocations
416 * and validate the shader state record's uniforms that define the texture
419 struct vc4_validated_shader_info {
420 uint32_t uniforms_size;
421 uint32_t uniforms_src_size;
422 uint32_t num_texture_samples;
423 struct vc4_texture_sample_info *texture_samples;
425 uint32_t num_uniform_addr_offsets;
426 uint32_t *uniform_addr_offsets;
432 * _wait_for - magic (register) wait macro
434 * Does the right thing for modeset paths when run under kdgb or similar atomic
435 * contexts. Note that it's important that we check the condition again after
436 * having timed out, since the timeout could be due to preemption or similar and
437 * we've never had a chance to check the condition before the timeout.
439 #define _wait_for(COND, MS, W) ({ \
440 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
443 if (time_after(jiffies, timeout__)) { \
445 ret__ = -ETIMEDOUT; \
448 if (W && drm_can_sleep()) { \
457 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
460 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
461 void vc4_free_object(struct drm_gem_object *gem_obj);
462 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
464 int vc4_dumb_create(struct drm_file *file_priv,
465 struct drm_device *dev,
466 struct drm_mode_create_dumb *args);
467 struct dma_buf *vc4_prime_export(struct drm_device *dev,
468 struct drm_gem_object *obj, int flags);
469 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
470 struct drm_file *file_priv);
471 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
472 struct drm_file *file_priv);
473 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
474 struct drm_file *file_priv);
475 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
476 struct drm_file *file_priv);
477 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
478 struct reservation_object *vc4_prime_res_obj(struct drm_gem_object *obj);
479 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
480 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
481 struct dma_buf_attachment *attach,
482 struct sg_table *sgt);
483 void *vc4_prime_vmap(struct drm_gem_object *obj);
484 void vc4_bo_cache_init(struct drm_device *dev);
485 void vc4_bo_cache_destroy(struct drm_device *dev);
486 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
489 extern struct platform_driver vc4_crtc_driver;
490 bool vc4_event_pending(struct drm_crtc *crtc);
491 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
492 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
493 bool in_vblank_irq, int *vpos, int *hpos,
494 ktime_t *stime, ktime_t *etime,
495 const struct drm_display_mode *mode);
498 int vc4_debugfs_init(struct drm_minor *minor);
501 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
504 extern struct platform_driver vc4_dpi_driver;
505 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
508 extern struct platform_driver vc4_dsi_driver;
509 int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused);
512 extern const struct dma_fence_ops vc4_fence_ops;
515 void vc4_gem_init(struct drm_device *dev);
516 void vc4_gem_destroy(struct drm_device *dev);
517 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
518 struct drm_file *file_priv);
519 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
520 struct drm_file *file_priv);
521 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
522 struct drm_file *file_priv);
523 void vc4_submit_next_bin_job(struct drm_device *dev);
524 void vc4_submit_next_render_job(struct drm_device *dev);
525 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
526 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
527 uint64_t timeout_ns, bool interruptible);
528 void vc4_job_handle_completed(struct vc4_dev *vc4);
529 int vc4_queue_seqno_cb(struct drm_device *dev,
530 struct vc4_seqno_cb *cb, uint64_t seqno,
531 void (*func)(struct vc4_seqno_cb *cb));
534 extern struct platform_driver vc4_hdmi_driver;
535 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
538 extern struct platform_driver vc4_vec_driver;
539 int vc4_vec_debugfs_regs(struct seq_file *m, void *unused);
542 irqreturn_t vc4_irq(int irq, void *arg);
543 void vc4_irq_preinstall(struct drm_device *dev);
544 int vc4_irq_postinstall(struct drm_device *dev);
545 void vc4_irq_uninstall(struct drm_device *dev);
546 void vc4_irq_reset(struct drm_device *dev);
549 extern struct platform_driver vc4_hvs_driver;
550 void vc4_hvs_dump_state(struct drm_device *dev);
551 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
554 int vc4_kms_load(struct drm_device *dev);
557 struct drm_plane *vc4_plane_init(struct drm_device *dev,
558 enum drm_plane_type type);
559 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
560 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
561 void vc4_plane_async_set_fb(struct drm_plane *plane,
562 struct drm_framebuffer *fb);
565 extern struct platform_driver vc4_v3d_driver;
566 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
567 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
568 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
572 vc4_validate_bin_cl(struct drm_device *dev,
575 struct vc4_exec_info *exec);
578 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
580 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
583 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
585 bool vc4_check_tex_size(struct vc4_exec_info *exec,
586 struct drm_gem_cma_object *fbo,
587 uint32_t offset, uint8_t tiling_format,
588 uint32_t width, uint32_t height, uint8_t cpp);
590 /* vc4_validate_shader.c */
591 struct vc4_validated_shader_info *
592 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);