1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom
9 * In VC4, the Pixel Valve is what most closely corresponds to the
10 * DRM's concept of a CRTC. The PV generates video timings from the
11 * encoder's clock plus its configuration. It pulls scaled pixels from
12 * the HVS at that timing, and feeds it to the encoder.
14 * However, the DRM CRTC also collects the configuration of all the
15 * DRM planes attached to it. As a result, the CRTC is also
16 * responsible for writing the display list for the HVS channel that
19 * The 2835 has 3 different pixel valves. pv0 in the audio power
20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
21 * image domain can feed either HDMI or the SDTV controller. The
22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
23 * SDTV, etc.) according to which output type is chosen in the mux.
25 * For power management, the pixel valve's registers are all clocked
26 * by the AXI clock, while the timings and FIFOs make use of the
27 * output-specific clock. Since the encoders also directly consume
28 * the CPRMAN clocks, and know what timings they need, they are the
29 * ones that set the clock.
32 #include <linux/clk.h>
33 #include <linux/component.h>
34 #include <linux/of_device.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_fb_cma_helper.h>
40 #include <drm/drm_print.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/drm_vblank.h>
47 #define HVS_FIFO_LATENCY_PIX 6
49 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
50 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
52 static const struct debugfs_reg32 crtc_regs[] = {
53 VC4_REG32(PV_CONTROL),
54 VC4_REG32(PV_V_CONTROL),
55 VC4_REG32(PV_VSYNCD_EVEN),
60 VC4_REG32(PV_VERTA_EVEN),
61 VC4_REG32(PV_VERTB_EVEN),
63 VC4_REG32(PV_INTSTAT),
65 VC4_REG32(PV_HACT_ACT),
69 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
71 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
72 /* Top/base are supposed to be 4-pixel aligned, but the
73 * Raspberry Pi firmware fills the low bits (which are
74 * presumably ignored).
76 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
77 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
79 return top - base + 4;
82 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
85 ktime_t *stime, ktime_t *etime,
86 const struct drm_display_mode *mode)
88 struct drm_device *dev = crtc->dev;
89 struct vc4_dev *vc4 = to_vc4_dev(dev);
90 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
91 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
92 unsigned int cob_size;
98 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
100 /* Get optional system timestamp before query. */
102 *stime = ktime_get();
105 * Read vertical scanline which is currently composed for our
106 * pixelvalve by the HVS, and also the scaler status.
108 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
110 /* Get optional system timestamp after query. */
112 *etime = ktime_get();
114 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
116 /* Vertical position of hvs composed scanline. */
117 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
120 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
123 /* Use hpos to correct for field offset in interlaced mode. */
124 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
125 *hpos += mode->crtc_htotal / 2;
128 cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel);
129 /* This is the offset we need for translating hvs -> pv scanout pos. */
130 fifo_lines = cob_size / mode->crtc_hdisplay;
135 /* HVS more than fifo_lines into frame for compositing? */
136 if (*vpos > fifo_lines) {
138 * We are in active scanout and can get some meaningful results
139 * from HVS. The actual PV scanout can not trail behind more
140 * than fifo_lines as that is the fifo's capacity. Assume that
141 * in active scanout the HVS and PV work in lockstep wrt. HVS
142 * refilling the fifo and PV consuming from the fifo, ie.
143 * whenever the PV consumes and frees up a scanline in the
144 * fifo, the HVS will immediately refill it, therefore
145 * incrementing vpos. Therefore we choose HVS read position -
146 * fifo size in scanlines as a estimate of the real scanout
147 * position of the PV.
149 *vpos -= fifo_lines + 1;
155 * Less: This happens when we are in vblank and the HVS, after getting
156 * the VSTART restart signal from the PV, just started refilling its
157 * fifo with new lines from the top-most lines of the new framebuffers.
158 * The PV does not scan out in vblank, so does not remove lines from
159 * the fifo, so the fifo will be full quickly and the HVS has to pause.
160 * We can't get meaningful readings wrt. scanline position of the PV
161 * and need to make things up in a approximative but consistent way.
163 vblank_lines = mode->vtotal - mode->vdisplay;
167 * Assume the irq handler got called close to first
168 * line of vblank, so PV has about a full vblank
169 * scanlines to go, and as a base timestamp use the
170 * one taken at entry into vblank irq handler, so it
171 * is not affected by random delays due to lock
172 * contention on event_lock or vblank_time lock in
175 *vpos = -vblank_lines;
178 *stime = vc4_crtc->t_vblank;
180 *etime = vc4_crtc->t_vblank;
183 * If the HVS fifo is not yet full then we know for certain
184 * we are at the very beginning of vblank, as the hvs just
185 * started refilling, and the stime and etime timestamps
186 * truly correspond to start of vblank.
188 * Unfortunately there's no way to report this to upper levels
189 * and make it more useful.
193 * No clue where we are inside vblank. Return a vpos of zero,
194 * which will cause calling code to just return the etime
195 * timestamp uncorrected. At least this is no worse than the
204 void vc4_crtc_destroy(struct drm_crtc *crtc)
206 drm_crtc_cleanup(crtc);
209 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
211 const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
212 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
213 u32 fifo_len_bytes = pv_data->fifo_depth;
216 * Pixels are pulled from the HVS if the number of bytes is
217 * lower than the FIFO full level.
219 * The latency of the pixel fetch mechanism is 6 pixels, so we
220 * need to convert those 6 pixels in bytes, depending on the
221 * format, and then subtract that from the length of the FIFO
222 * to make sure we never end up in a situation where the FIFO
226 case PV_CONTROL_FORMAT_DSIV_16:
227 case PV_CONTROL_FORMAT_DSIC_16:
228 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
229 case PV_CONTROL_FORMAT_DSIV_18:
230 return fifo_len_bytes - 14;
231 case PV_CONTROL_FORMAT_24:
232 case PV_CONTROL_FORMAT_DSIV_24:
235 * For some reason, the pixelvalve4 doesn't work with
236 * the usual formula and will only work with 32.
238 if (crtc_data->hvs_output == 5)
241 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
245 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
248 u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
251 ret |= VC4_SET_FIELD((level >> 6),
252 PV5_CONTROL_FIFO_LEVEL_HIGH);
254 return ret | VC4_SET_FIELD(level & 0x3f,
255 PV_CONTROL_FIFO_LEVEL);
259 * Returns the encoder attached to the CRTC.
261 * VC4 can only scan out to one encoder at a time, while the DRM core
262 * allows drivers to push pixels to more than one encoder from the
265 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
267 struct drm_connector *connector;
268 struct drm_connector_list_iter conn_iter;
270 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
271 drm_for_each_connector_iter(connector, &conn_iter) {
272 if (connector->state->crtc == crtc) {
273 drm_connector_list_iter_end(&conn_iter);
274 return connector->encoder;
277 drm_connector_list_iter_end(&conn_iter);
282 static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
284 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
286 /* The PV needs to be disabled before it can be flushed */
287 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
288 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
291 static void vc4_crtc_config_pv(struct drm_crtc *crtc)
293 struct drm_device *dev = crtc->dev;
294 struct vc4_dev *vc4 = to_vc4_dev(dev);
295 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
296 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
297 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
298 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
299 struct drm_crtc_state *state = crtc->state;
300 struct drm_display_mode *mode = &state->adjusted_mode;
301 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
302 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
303 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
304 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
305 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
306 u8 ppc = pv_data->pixels_per_clock;
307 bool debug_dump_regs = false;
309 if (debug_dump_regs) {
310 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
311 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
312 drm_crtc_index(crtc));
313 drm_print_regset32(&p, &vc4_crtc->regset);
316 vc4_crtc_pixelvalve_reset(crtc);
319 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
321 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
325 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
327 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
331 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
333 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
336 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
338 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
341 CRTC_WRITE(PV_VERTA_EVEN,
342 VC4_SET_FIELD(mode->crtc_vtotal -
343 mode->crtc_vsync_end - 1,
345 VC4_SET_FIELD(mode->crtc_vsync_end -
346 mode->crtc_vsync_start,
348 CRTC_WRITE(PV_VERTB_EVEN,
349 VC4_SET_FIELD(mode->crtc_vsync_start -
352 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
354 /* We set up first field even mode for HDMI. VEC's
355 * NTSC mode would want first field odd instead, once
356 * we support it (to do so, set ODD_FIRST and put the
357 * delay in VSYNCD_EVEN instead).
359 CRTC_WRITE(PV_V_CONTROL,
360 PV_VCONTROL_CONTINUOUS |
361 (is_dsi ? PV_VCONTROL_DSI : 0) |
362 PV_VCONTROL_INTERLACE |
363 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
364 PV_VCONTROL_ODD_DELAY));
365 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
367 CRTC_WRITE(PV_V_CONTROL,
368 PV_VCONTROL_CONTINUOUS |
369 (is_dsi ? PV_VCONTROL_DSI : 0));
373 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
376 CRTC_WRITE(PV_MUX_CFG,
377 VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
378 PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
380 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
381 vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
382 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
383 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
384 PV_CONTROL_CLR_AT_START |
385 PV_CONTROL_TRIGGER_UNDERFLOW |
386 PV_CONTROL_WAIT_HSTART |
387 VC4_SET_FIELD(vc4_encoder->clock_select,
388 PV_CONTROL_CLK_SELECT));
390 if (debug_dump_regs) {
391 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
392 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
393 drm_crtc_index(crtc));
394 drm_print_regset32(&p, &vc4_crtc->regset);
398 static void require_hvs_enabled(struct drm_device *dev)
400 struct vc4_dev *vc4 = to_vc4_dev(dev);
402 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
403 SCALER_DISPCTRL_ENABLE);
406 static int vc4_crtc_disable(struct drm_crtc *crtc, unsigned int channel)
408 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
409 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
410 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
411 struct drm_device *dev = crtc->dev;
414 CRTC_WRITE(PV_V_CONTROL,
415 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
416 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
417 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
420 * This delay is needed to avoid to get a pixel stuck in an
421 * unflushable FIFO between the pixelvalve and the HDMI
422 * controllers on the BCM2711.
424 * Timing is fairly sensitive here, so mdelay is the safest
427 * If it was to be reworked, the stuck pixel happens on a
428 * BCM2711 when changing mode with a good probability, so a
429 * script that changes mode on a regular basis should trigger
430 * the bug after less than 10 attempts. It manifests itself with
431 * every pixels being shifted by one to the right, and thus the
432 * last pixel of a line actually being displayed as the first
433 * pixel on the next line.
437 if (vc4_encoder && vc4_encoder->post_crtc_disable)
438 vc4_encoder->post_crtc_disable(encoder);
440 vc4_crtc_pixelvalve_reset(crtc);
441 vc4_hvs_stop_channel(dev, channel);
443 if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
444 vc4_encoder->post_crtc_powerdown(encoder);
449 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
451 struct drm_device *drm = crtc->dev;
452 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
455 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
456 "brcm,bcm2711-pixelvalve2") ||
457 of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
458 "brcm,bcm2711-pixelvalve4")))
461 if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
464 if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
467 channel = vc4_hvs_get_fifo_from_output(drm, vc4_crtc->data->hvs_output);
471 return vc4_crtc_disable(crtc, channel);
474 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
475 struct drm_crtc_state *old_state)
477 struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);
478 struct drm_device *dev = crtc->dev;
480 require_hvs_enabled(dev);
482 /* Disable vblank irq handling before crtc is disabled. */
483 drm_crtc_vblank_off(crtc);
485 vc4_crtc_disable(crtc, old_vc4_state->assigned_channel);
488 * Make sure we issue a vblank event after disabling the CRTC if
489 * someone was waiting it.
491 if (crtc->state->event) {
494 spin_lock_irqsave(&dev->event_lock, flags);
495 drm_crtc_send_vblank_event(crtc, crtc->state->event);
496 crtc->state->event = NULL;
497 spin_unlock_irqrestore(&dev->event_lock, flags);
501 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
502 struct drm_crtc_state *old_state)
504 struct drm_device *dev = crtc->dev;
505 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
506 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
507 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
509 require_hvs_enabled(dev);
511 /* Enable vblank irq handling before crtc is started otherwise
512 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
514 drm_crtc_vblank_on(crtc);
516 vc4_hvs_atomic_enable(crtc, old_state);
518 if (vc4_encoder->pre_crtc_configure)
519 vc4_encoder->pre_crtc_configure(encoder);
521 vc4_crtc_config_pv(crtc);
523 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
525 if (vc4_encoder->pre_crtc_enable)
526 vc4_encoder->pre_crtc_enable(encoder);
528 /* When feeding the transposer block the pixelvalve is unneeded and
529 * should not be enabled.
531 CRTC_WRITE(PV_V_CONTROL,
532 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
534 if (vc4_encoder->post_crtc_enable)
535 vc4_encoder->post_crtc_enable(encoder);
538 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
539 const struct drm_display_mode *mode)
541 /* Do not allow doublescan modes from user space */
542 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
543 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
545 return MODE_NO_DBLESCAN;
551 void vc4_crtc_get_margins(struct drm_crtc_state *state,
552 unsigned int *left, unsigned int *right,
553 unsigned int *top, unsigned int *bottom)
555 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
556 struct drm_connector_state *conn_state;
557 struct drm_connector *conn;
560 *left = vc4_state->margins.left;
561 *right = vc4_state->margins.right;
562 *top = vc4_state->margins.top;
563 *bottom = vc4_state->margins.bottom;
565 /* We have to interate over all new connector states because
566 * vc4_crtc_get_margins() might be called before
567 * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
570 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
571 if (conn_state->crtc != state->crtc)
574 *left = conn_state->tv.margins.left;
575 *right = conn_state->tv.margins.right;
576 *top = conn_state->tv.margins.top;
577 *bottom = conn_state->tv.margins.bottom;
582 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
583 struct drm_crtc_state *state)
585 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
586 struct drm_connector *conn;
587 struct drm_connector_state *conn_state;
590 ret = vc4_hvs_atomic_check(crtc, state);
594 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
595 if (conn_state->crtc != crtc)
598 vc4_state->margins.left = conn_state->tv.margins.left;
599 vc4_state->margins.right = conn_state->tv.margins.right;
600 vc4_state->margins.top = conn_state->tv.margins.top;
601 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
608 static int vc4_enable_vblank(struct drm_crtc *crtc)
610 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
612 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
617 static void vc4_disable_vblank(struct drm_crtc *crtc)
619 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
621 CRTC_WRITE(PV_INTEN, 0);
624 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
626 struct drm_crtc *crtc = &vc4_crtc->base;
627 struct drm_device *dev = crtc->dev;
628 struct vc4_dev *vc4 = to_vc4_dev(dev);
629 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
630 u32 chan = vc4_state->assigned_channel;
633 spin_lock_irqsave(&dev->event_lock, flags);
634 if (vc4_crtc->event &&
635 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
636 vc4_state->feed_txp)) {
637 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
638 vc4_crtc->event = NULL;
639 drm_crtc_vblank_put(crtc);
641 /* Wait for the page flip to unmask the underrun to ensure that
642 * the display list was updated by the hardware. Before that
643 * happens, the HVS will be using the previous display list with
644 * the CRTC and encoder already reconfigured, leading to
645 * underruns. This can be seen when reconfiguring the CRTC.
647 vc4_hvs_unmask_underrun(dev, chan);
649 spin_unlock_irqrestore(&dev->event_lock, flags);
652 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
654 crtc->t_vblank = ktime_get();
655 drm_crtc_handle_vblank(&crtc->base);
656 vc4_crtc_handle_page_flip(crtc);
659 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
661 struct vc4_crtc *vc4_crtc = data;
662 u32 stat = CRTC_READ(PV_INTSTAT);
663 irqreturn_t ret = IRQ_NONE;
665 if (stat & PV_INT_VFP_START) {
666 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
667 vc4_crtc_handle_vblank(vc4_crtc);
674 struct vc4_async_flip_state {
675 struct drm_crtc *crtc;
676 struct drm_framebuffer *fb;
677 struct drm_framebuffer *old_fb;
678 struct drm_pending_vblank_event *event;
680 struct vc4_seqno_cb cb;
683 /* Called when the V3D execution for the BO being flipped to is done, so that
684 * we can actually update the plane's address to point to it.
687 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
689 struct vc4_async_flip_state *flip_state =
690 container_of(cb, struct vc4_async_flip_state, cb);
691 struct drm_crtc *crtc = flip_state->crtc;
692 struct drm_device *dev = crtc->dev;
693 struct vc4_dev *vc4 = to_vc4_dev(dev);
694 struct drm_plane *plane = crtc->primary;
696 vc4_plane_async_set_fb(plane, flip_state->fb);
697 if (flip_state->event) {
700 spin_lock_irqsave(&dev->event_lock, flags);
701 drm_crtc_send_vblank_event(crtc, flip_state->event);
702 spin_unlock_irqrestore(&dev->event_lock, flags);
705 drm_crtc_vblank_put(crtc);
706 drm_framebuffer_put(flip_state->fb);
708 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
709 * when the planes are updated through the async update path.
710 * FIXME: we should move to generic async-page-flip when it's
711 * available, so that we can get rid of this hand-made cleanup_fb()
714 if (flip_state->old_fb) {
715 struct drm_gem_cma_object *cma_bo;
718 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
719 bo = to_vc4_bo(&cma_bo->base);
720 vc4_bo_dec_usecnt(bo);
721 drm_framebuffer_put(flip_state->old_fb);
726 up(&vc4->async_modeset);
729 /* Implements async (non-vblank-synced) page flips.
731 * The page flip ioctl needs to return immediately, so we grab the
732 * modeset semaphore on the pipe, and queue the address update for
733 * when V3D is done with the BO being flipped to.
735 static int vc4_async_page_flip(struct drm_crtc *crtc,
736 struct drm_framebuffer *fb,
737 struct drm_pending_vblank_event *event,
740 struct drm_device *dev = crtc->dev;
741 struct vc4_dev *vc4 = to_vc4_dev(dev);
742 struct drm_plane *plane = crtc->primary;
744 struct vc4_async_flip_state *flip_state;
745 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
746 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
748 /* Increment the BO usecnt here, so that we never end up with an
749 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
750 * plane is later updated through the non-async path.
751 * FIXME: we should move to generic async-page-flip when it's
752 * available, so that we can get rid of this hand-made prepare_fb()
755 ret = vc4_bo_inc_usecnt(bo);
759 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
761 vc4_bo_dec_usecnt(bo);
765 drm_framebuffer_get(fb);
767 flip_state->crtc = crtc;
768 flip_state->event = event;
770 /* Make sure all other async modesetes have landed. */
771 ret = down_interruptible(&vc4->async_modeset);
773 drm_framebuffer_put(fb);
774 vc4_bo_dec_usecnt(bo);
779 /* Save the current FB before it's replaced by the new one in
780 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
781 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
783 * FIXME: we should move to generic async-page-flip when it's
784 * available, so that we can get rid of this hand-made cleanup_fb()
787 flip_state->old_fb = plane->state->fb;
788 if (flip_state->old_fb)
789 drm_framebuffer_get(flip_state->old_fb);
791 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
793 /* Immediately update the plane's legacy fb pointer, so that later
794 * modeset prep sees the state that will be present when the semaphore
797 drm_atomic_set_fb_for_plane(plane->state, fb);
799 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
800 vc4_async_page_flip_complete);
802 /* Driver takes ownership of state on successful async commit. */
806 int vc4_page_flip(struct drm_crtc *crtc,
807 struct drm_framebuffer *fb,
808 struct drm_pending_vblank_event *event,
810 struct drm_modeset_acquire_ctx *ctx)
812 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
813 return vc4_async_page_flip(crtc, fb, event, flags);
815 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
818 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
820 struct vc4_crtc_state *vc4_state, *old_vc4_state;
822 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
826 old_vc4_state = to_vc4_crtc_state(crtc->state);
827 vc4_state->feed_txp = old_vc4_state->feed_txp;
828 vc4_state->margins = old_vc4_state->margins;
829 vc4_state->assigned_channel = old_vc4_state->assigned_channel;
831 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
832 return &vc4_state->base;
835 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
836 struct drm_crtc_state *state)
838 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
839 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
841 if (drm_mm_node_allocated(&vc4_state->mm)) {
844 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
845 drm_mm_remove_node(&vc4_state->mm);
846 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
850 drm_atomic_helper_crtc_destroy_state(crtc, state);
853 void vc4_crtc_reset(struct drm_crtc *crtc)
855 struct vc4_crtc_state *vc4_crtc_state;
858 vc4_crtc_destroy_state(crtc, crtc->state);
860 vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL);
861 if (!vc4_crtc_state) {
866 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
867 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);
870 static const struct drm_crtc_funcs vc4_crtc_funcs = {
871 .set_config = drm_atomic_helper_set_config,
872 .destroy = vc4_crtc_destroy,
873 .page_flip = vc4_page_flip,
874 .set_property = NULL,
875 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
876 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
877 .reset = vc4_crtc_reset,
878 .atomic_duplicate_state = vc4_crtc_duplicate_state,
879 .atomic_destroy_state = vc4_crtc_destroy_state,
880 .gamma_set = drm_atomic_helper_legacy_gamma_set,
881 .enable_vblank = vc4_enable_vblank,
882 .disable_vblank = vc4_disable_vblank,
883 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
886 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
887 .mode_valid = vc4_crtc_mode_valid,
888 .atomic_check = vc4_crtc_atomic_check,
889 .atomic_flush = vc4_hvs_atomic_flush,
890 .atomic_enable = vc4_crtc_atomic_enable,
891 .atomic_disable = vc4_crtc_atomic_disable,
892 .get_scanout_position = vc4_crtc_get_scanout_position,
895 static const struct vc4_pv_data bcm2835_pv0_data = {
897 .hvs_available_channels = BIT(0),
900 .debugfs_name = "crtc0_regs",
902 .pixels_per_clock = 1,
904 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
905 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
909 static const struct vc4_pv_data bcm2835_pv1_data = {
911 .hvs_available_channels = BIT(2),
914 .debugfs_name = "crtc1_regs",
916 .pixels_per_clock = 1,
918 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
919 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
923 static const struct vc4_pv_data bcm2835_pv2_data = {
925 .hvs_available_channels = BIT(1),
928 .debugfs_name = "crtc2_regs",
930 .pixels_per_clock = 1,
932 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
933 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
937 static const struct vc4_pv_data bcm2711_pv0_data = {
939 .hvs_available_channels = BIT(0),
942 .debugfs_name = "crtc0_regs",
944 .pixels_per_clock = 1,
946 [0] = VC4_ENCODER_TYPE_DSI0,
947 [1] = VC4_ENCODER_TYPE_DPI,
951 static const struct vc4_pv_data bcm2711_pv1_data = {
953 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
956 .debugfs_name = "crtc1_regs",
958 .pixels_per_clock = 1,
960 [0] = VC4_ENCODER_TYPE_DSI1,
961 [1] = VC4_ENCODER_TYPE_SMI,
965 static const struct vc4_pv_data bcm2711_pv2_data = {
967 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
970 .debugfs_name = "crtc2_regs",
972 .pixels_per_clock = 2,
974 [0] = VC4_ENCODER_TYPE_HDMI0,
978 static const struct vc4_pv_data bcm2711_pv3_data = {
980 .hvs_available_channels = BIT(1),
983 .debugfs_name = "crtc3_regs",
985 .pixels_per_clock = 1,
987 [0] = VC4_ENCODER_TYPE_VEC,
991 static const struct vc4_pv_data bcm2711_pv4_data = {
993 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
996 .debugfs_name = "crtc4_regs",
998 .pixels_per_clock = 2,
1000 [0] = VC4_ENCODER_TYPE_HDMI1,
1004 static const struct of_device_id vc4_crtc_dt_match[] = {
1005 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1006 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1007 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1008 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1009 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1010 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1011 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1012 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1016 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1017 struct drm_crtc *crtc)
1019 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1020 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
1021 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
1022 struct drm_encoder *encoder;
1024 drm_for_each_encoder(encoder, drm) {
1025 struct vc4_encoder *vc4_encoder;
1028 vc4_encoder = to_vc4_encoder(encoder);
1029 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
1030 if (vc4_encoder->type == encoder_types[i]) {
1031 vc4_encoder->clock_select = i;
1032 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1039 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
1040 const struct drm_crtc_funcs *crtc_funcs,
1041 const struct drm_crtc_helper_funcs *crtc_helper_funcs)
1043 struct vc4_dev *vc4 = to_vc4_dev(drm);
1044 struct drm_crtc *crtc = &vc4_crtc->base;
1045 struct drm_plane *primary_plane;
1048 /* For now, we create just the primary and the legacy cursor
1049 * planes. We should be able to stack more planes on easily,
1050 * but to do that we would need to compute the bandwidth
1051 * requirement of the plane configuration, and reject ones
1052 * that will take too much.
1054 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1055 if (IS_ERR(primary_plane)) {
1056 dev_err(drm->dev, "failed to construct primary plane\n");
1057 return PTR_ERR(primary_plane);
1060 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1062 drm_crtc_helper_add(crtc, crtc_helper_funcs);
1064 if (!vc4->hvs->hvs5) {
1065 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1067 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1069 /* We support CTM, but only for one CRTC at a time. It's therefore
1070 * implemented as private driver state in vc4_kms, not here.
1072 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1075 for (i = 0; i < crtc->gamma_size; i++) {
1076 vc4_crtc->lut_r[i] = i;
1077 vc4_crtc->lut_g[i] = i;
1078 vc4_crtc->lut_b[i] = i;
1084 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1086 struct platform_device *pdev = to_platform_device(dev);
1087 struct drm_device *drm = dev_get_drvdata(master);
1088 const struct vc4_pv_data *pv_data;
1089 struct vc4_crtc *vc4_crtc;
1090 struct drm_crtc *crtc;
1091 struct drm_plane *destroy_plane, *temp;
1094 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1097 crtc = &vc4_crtc->base;
1099 pv_data = of_device_get_match_data(dev);
1102 vc4_crtc->data = &pv_data->base;
1103 vc4_crtc->pdev = pdev;
1105 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1106 if (IS_ERR(vc4_crtc->regs))
1107 return PTR_ERR(vc4_crtc->regs);
1109 vc4_crtc->regset.base = vc4_crtc->regs;
1110 vc4_crtc->regset.regs = crtc_regs;
1111 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1113 ret = vc4_crtc_init(drm, vc4_crtc,
1114 &vc4_crtc_funcs, &vc4_crtc_helper_funcs);
1117 vc4_set_crtc_possible_masks(drm, crtc);
1119 CRTC_WRITE(PV_INTEN, 0);
1120 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1121 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1122 vc4_crtc_irq_handler,
1124 "vc4 crtc", vc4_crtc);
1126 goto err_destroy_planes;
1128 platform_set_drvdata(pdev, vc4_crtc);
1130 vc4_debugfs_add_regset32(drm, pv_data->debugfs_name,
1136 list_for_each_entry_safe(destroy_plane, temp,
1137 &drm->mode_config.plane_list, head) {
1138 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1139 destroy_plane->funcs->destroy(destroy_plane);
1145 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1148 struct platform_device *pdev = to_platform_device(dev);
1149 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1151 vc4_crtc_destroy(&vc4_crtc->base);
1153 CRTC_WRITE(PV_INTEN, 0);
1155 platform_set_drvdata(pdev, NULL);
1158 static const struct component_ops vc4_crtc_ops = {
1159 .bind = vc4_crtc_bind,
1160 .unbind = vc4_crtc_unbind,
1163 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1165 return component_add(&pdev->dev, &vc4_crtc_ops);
1168 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1170 component_del(&pdev->dev, &vc4_crtc_ops);
1174 struct platform_driver vc4_crtc_driver = {
1175 .probe = vc4_crtc_dev_probe,
1176 .remove = vc4_crtc_dev_remove,
1179 .of_match_table = vc4_crtc_dt_match,