drivers/gpu/drm/vc4/vc4_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 CRTC module
   8  *
   9  * In VC4, the Pixel Valve is what most closely corresponds to the
  10  * DRM's concept of a CRTC.  The PV generates video timings from the
  11  * encoder's clock plus its configuration.  It pulls scaled pixels from
  12  * the HVS at that timing, and feeds it to the encoder.
  13  *
  14  * However, the DRM CRTC also collects the configuration of all the
  15  * DRM planes attached to it.  As a result, the CRTC is also
  16  * responsible for writing the display list for the HVS channel that
  17  * the CRTC will use.
  18  *
  19  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  20  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  21  * image domain can feed either HDMI or the SDTV controller.  The
  22  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  23  * SDTV, etc.) according to which output type is chosen in the mux.
  24  *
  25  * For power management, the pixel valve's registers are all clocked
  26  * by the AXI clock, while the timings and FIFOs make use of the
  27  * output-specific clock.  Since the encoders also directly consume
  28  * the CPRMAN clocks, and know what timings they need, they are the
  29  * ones that set the clock.
  30  */
  31
  32 #include <linux/clk.h>
  33 #include <linux/component.h>
  34 #include <linux/of_device.h>
  35 #include <linux/pm_runtime.h>
  36
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_atomic_helper.h>
  39 #include <drm/drm_atomic_uapi.h>
  40 #include <drm/drm_fb_dma_helper.h>
  41 #include <drm/drm_framebuffer.h>
  42 #include <drm/drm_drv.h>
  43 #include <drm/drm_print.h>
  44 #include <drm/drm_probe_helper.h>
  45 #include <drm/drm_vblank.h>
  46
  47 #include "vc4_drv.h"
  48 #include "vc4_hdmi.h"
  49 #include "vc4_regs.h"
  50
  51 #define HVS_FIFO_LATENCY_PIX    6
  52
  53 #define CRTC_WRITE(offset, val)                                                         \
  54         do {                                                                            \
  55                 kunit_fail_current_test("Accessing a register in a unit test!\n");      \
  56                 writel(val, vc4_crtc->regs + (offset));                                 \
  57         } while (0)
  58
  59 #define CRTC_READ(offset)                                                               \
  60         ({                                                                              \
  61                 kunit_fail_current_test("Accessing a register in a unit test!\n");      \
  62                 readl(vc4_crtc->regs + (offset));                                       \
  63         })
  64
  65 static const struct debugfs_reg32 crtc_regs[] = {
  66         VC4_REG32(PV_CONTROL),
  67         VC4_REG32(PV_V_CONTROL),
  68         VC4_REG32(PV_VSYNCD_EVEN),
  69         VC4_REG32(PV_HORZA),
  70         VC4_REG32(PV_HORZB),
  71         VC4_REG32(PV_VERTA),
  72         VC4_REG32(PV_VERTB),
  73         VC4_REG32(PV_VERTA_EVEN),
  74         VC4_REG32(PV_VERTB_EVEN),
  75         VC4_REG32(PV_INTEN),
  76         VC4_REG32(PV_INTSTAT),
  77         VC4_REG32(PV_STAT),
  78         VC4_REG32(PV_HACT_ACT),
  79 };
  80
  81 static unsigned int
  82 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
  83 {
  84         struct vc4_hvs *hvs = vc4->hvs;
  85         u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
  86         /* Top/base are supposed to be 4-pixel aligned, but the
  87          * Raspberry Pi firmware fills the low bits (which are
  88          * presumably ignored).
  89          */
  90         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
  91         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
  92
  93         return top - base + 4;
  94 }
  95
  96 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
  97                                           bool in_vblank_irq,
  98                                           int *vpos, int *hpos,
  99                                           ktime_t *stime, ktime_t *etime,
 100                                           const struct drm_display_mode *mode)
 101 {
 102         struct drm_device *dev = crtc->dev;
 103         struct vc4_dev *vc4 = to_vc4_dev(dev);
 104         struct vc4_hvs *hvs = vc4->hvs;
 105         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 106         struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
 107         unsigned int cob_size;
 108         u32 val;
 109         int fifo_lines;
 110         int vblank_lines;
 111         bool ret = false;
 112
 113         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 114
 115         /* Get optional system timestamp before query. */
 116         if (stime)
 117                 *stime = ktime_get();
 118
 119         /*
 120          * Read vertical scanline which is currently composed for our
 121          * pixelvalve by the HVS, and also the scaler status.
 122          */
 123         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
 124
 125         /* Get optional system timestamp after query. */
 126         if (etime)
 127                 *etime = ktime_get();
 128
 129         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 130
 131         /* Vertical position of hvs composed scanline. */
 132         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 133         *hpos = 0;
 134
 135         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 136                 *vpos /= 2;
 137
 138                 /* Use hpos to correct for field offset in interlaced mode. */
 139                 if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2)
 140                         *hpos += mode->crtc_htotal / 2;
 141         }
 142
 143         cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel);
 144         /* This is the offset we need for translating hvs -> pv scanout pos. */
 145         fifo_lines = cob_size / mode->crtc_hdisplay;
 146
 147         if (fifo_lines > 0)
 148                 ret = true;
 149
 150         /* HVS more than fifo_lines into frame for compositing? */
 151         if (*vpos > fifo_lines) {
 152                 /*
 153                  * We are in active scanout and can get some meaningful results
 154                  * from HVS. The actual PV scanout can not trail behind more
 155                  * than fifo_lines as that is the fifo's capacity. Assume that
 156                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 157                  * refilling the fifo and PV consuming from the fifo, ie.
 158                  * whenever the PV consumes and frees up a scanline in the
 159                  * fifo, the HVS will immediately refill it, therefore
 160                  * incrementing vpos. Therefore we choose HVS read position -
 161                  * fifo size in scanlines as a estimate of the real scanout
 162                  * position of the PV.
 163                  */
 164                 *vpos -= fifo_lines + 1;
 165
 166                 return ret;
 167         }
 168
 169         /*
 170          * Less: This happens when we are in vblank and the HVS, after getting
 171          * the VSTART restart signal from the PV, just started refilling its
 172          * fifo with new lines from the top-most lines of the new framebuffers.
 173          * The PV does not scan out in vblank, so does not remove lines from
 174          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 175          * We can't get meaningful readings wrt. scanline position of the PV
 176          * and need to make things up in a approximative but consistent way.
 177          */
 178         vblank_lines = mode->vtotal - mode->vdisplay;
 179
 180         if (in_vblank_irq) {
 181                 /*
 182                  * Assume the irq handler got called close to first
 183                  * line of vblank, so PV has about a full vblank
 184                  * scanlines to go, and as a base timestamp use the
 185                  * one taken at entry into vblank irq handler, so it
 186                  * is not affected by random delays due to lock
 187                  * contention on event_lock or vblank_time lock in
 188                  * the core.
 189                  */
 190                 *vpos = -vblank_lines;
 191
 192                 if (stime)
 193                         *stime = vc4_crtc->t_vblank;
 194                 if (etime)
 195                         *etime = vc4_crtc->t_vblank;
 196
 197                 /*
 198                  * If the HVS fifo is not yet full then we know for certain
 199                  * we are at the very beginning of vblank, as the hvs just
 200                  * started refilling, and the stime and etime timestamps
 201                  * truly correspond to start of vblank.
 202                  *
 203                  * Unfortunately there's no way to report this to upper levels
 204                  * and make it more useful.
 205                  */
 206         } else {
 207                 /*
 208                  * No clue where we are inside vblank. Return a vpos of zero,
 209                  * which will cause calling code to just return the etime
 210                  * timestamp uncorrected. At least this is no worse than the
 211                  * standard fallback.
 212                  */
 213                 *vpos = 0;
 214         }
 215
 216         return ret;
 217 }
 218
 219 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
 220 {
 221         const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
 222         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 223         struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
 224         u32 fifo_len_bytes = pv_data->fifo_depth;
 225
 226         /*
 227          * Pixels are pulled from the HVS if the number of bytes is
 228          * lower than the FIFO full level.
 229          *
 230          * The latency of the pixel fetch mechanism is 6 pixels, so we
 231          * need to convert those 6 pixels in bytes, depending on the
 232          * format, and then subtract that from the length of the FIFO
 233          * to make sure we never end up in a situation where the FIFO
 234          * is full.
 235          */
 236         switch (format) {
 237         case PV_CONTROL_FORMAT_DSIV_16:
 238         case PV_CONTROL_FORMAT_DSIC_16:
 239                 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
 240         case PV_CONTROL_FORMAT_DSIV_18:
 241                 return fifo_len_bytes - 14;
 242         case PV_CONTROL_FORMAT_24:
 243         case PV_CONTROL_FORMAT_DSIV_24:
 244         default:
 245                 /*
 246                  * For some reason, the pixelvalve4 doesn't work with
 247                  * the usual formula and will only work with 32.
 248                  */
 249                 if (crtc_data->hvs_output == 5)
 250                         return 32;
 251
 252                 /*
 253                  * It looks like in some situations, we will overflow
 254                  * the PixelValve FIFO (with the bit 10 of PV stat being
 255                  * set) and stall the HVS / PV, eventually resulting in
 256                  * a page flip timeout.
 257                  *
 258                  * Displaying the video overlay during a playback with
 259                  * Kodi on an RPi3 seems to be a great solution with a
 260                  * failure rate around 50%.
 261                  *
 262                  * Removing 1 from the FIFO full level however
 263                  * seems to completely remove that issue.
 264                  */
 265                 if (!vc4->is_vc5)
 266                         return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
 267
 268                 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
 269         }
 270 }
 271
 272 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
 273                                              u32 format)
 274 {
 275         u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
 276         u32 ret = 0;
 277
 278         ret |= VC4_SET_FIELD((level >> 6),
 279                              PV5_CONTROL_FIFO_LEVEL_HIGH);
 280
 281         return ret | VC4_SET_FIELD(level & 0x3f,
 282                                    PV_CONTROL_FIFO_LEVEL);
 283 }
 284
 285 /*
 286  * Returns the encoder attached to the CRTC.
 287  *
 288  * VC4 can only scan out to one encoder at a time, while the DRM core
 289  * allows drivers to push pixels to more than one encoder from the
 290  * same CRTC.
 291  */
 292 struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
 293                                          struct drm_crtc_state *state)
 294 {
 295         struct drm_encoder *encoder;
 296
 297         WARN_ON(hweight32(state->encoder_mask) > 1);
 298
 299         drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask)
 300                 return encoder;
 301
 302         return NULL;
 303 }
 304
 305 static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
 306 {
 307         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 308         struct drm_device *dev = crtc->dev;
 309         int idx;
 310
 311         if (!drm_dev_enter(dev, &idx))
 312                 return;
 313
 314         /* The PV needs to be disabled before it can be flushed */
 315         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
 316         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
 317
 318         drm_dev_exit(idx);
 319 }
 320
 321 static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encoder,
 322                                struct drm_atomic_state *state)
 323 {
 324         struct drm_device *dev = crtc->dev;
 325         struct vc4_dev *vc4 = to_vc4_dev(dev);
 326         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 327         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 328         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 329         struct drm_crtc_state *crtc_state = crtc->state;
 330         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 331         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 332         bool is_hdmi = vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0 ||
 333                        vc4_encoder->type == VC4_ENCODER_TYPE_HDMI1;
 334         u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1;
 335         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 336                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 337         bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
 338         bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;
 339         u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 340         u8 ppc = pv_data->pixels_per_clock;
 341
 342         u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;
 343         u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;
 344         u16 vert_fp = mode->crtc_vsync_start - mode->crtc_vdisplay;
 345
 346         bool debug_dump_regs = false;
 347         int idx;
 348
 349         if (!drm_dev_enter(dev, &idx))
 350                 return;
 351
 352         if (debug_dump_regs) {
 353                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 354                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
 355                          drm_crtc_index(crtc));
 356                 drm_print_regset32(&p, &vc4_crtc->regset);
 357         }
 358
 359         vc4_crtc_pixelvalve_reset(crtc);
 360
 361         CRTC_WRITE(PV_HORZA,
 362                    VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
 363                                  PV_HORZA_HBP) |
 364                    VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
 365                                  PV_HORZA_HSYNC));
 366
 367         CRTC_WRITE(PV_HORZB,
 368                    VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
 369                                  PV_HORZB_HFP) |
 370                    VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
 371                                  PV_HORZB_HACTIVE));
 372
 373         if (interlace) {
 374                 bool odd_field_first = false;
 375                 u32 field_delay = mode->htotal * pixel_rep / (2 * ppc);
 376                 u16 vert_bp_even = vert_bp;
 377                 u16 vert_fp_even = vert_fp;
 378
 379                 if (is_vec) {
 380                         /* VEC (composite output) */
 381                         ++field_delay;
 382                         if (mode->htotal == 858) {
 383                                 /* 525-line mode (NTSC or PAL-M) */
 384                                 odd_field_first = true;
 385                         }
 386                 }
 387
 388                 if (odd_field_first)
 389                         ++vert_fp_even;
 390                 else
 391                         ++vert_bp;
 392
 393                 CRTC_WRITE(PV_VERTA_EVEN,
 394                            VC4_SET_FIELD(vert_bp_even, PV_VERTA_VBP) |
 395                            VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));
 396                 CRTC_WRITE(PV_VERTB_EVEN,
 397                            VC4_SET_FIELD(vert_fp_even, PV_VERTB_VFP) |
 398                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 399
 400                 /* We set up first field even mode for HDMI and VEC's PAL.
 401                  * For NTSC, we need first field odd.
 402                  */
 403                 CRTC_WRITE(PV_V_CONTROL,
 404                            PV_VCONTROL_CONTINUOUS |
 405                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 406                            PV_VCONTROL_INTERLACE |
 407                            (odd_field_first
 408                                    ? PV_VCONTROL_ODD_FIRST
 409                                    : VC4_SET_FIELD(field_delay,
 410                                                    PV_VCONTROL_ODD_DELAY)));
 411                 CRTC_WRITE(PV_VSYNCD_EVEN,
 412                            (odd_field_first ? field_delay : 0));
 413         } else {
 414                 CRTC_WRITE(PV_V_CONTROL,
 415                            PV_VCONTROL_CONTINUOUS |
 416                            (is_dsi ? PV_VCONTROL_DSI : 0));
 417                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 418         }
 419
 420         CRTC_WRITE(PV_VERTA,
 421                    VC4_SET_FIELD(vert_bp, PV_VERTA_VBP) |
 422                    VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));
 423         CRTC_WRITE(PV_VERTB,
 424                    VC4_SET_FIELD(vert_fp, PV_VERTB_VFP) |
 425                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 426
 427         if (is_dsi)
 428                 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 429
 430         if (vc4->is_vc5)
 431                 CRTC_WRITE(PV_MUX_CFG,
 432                            VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
 433                                          PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
 434
 435         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
 436                    vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
 437                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 438                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 439                    PV_CONTROL_CLR_AT_START |
 440                    PV_CONTROL_TRIGGER_UNDERFLOW |
 441                    PV_CONTROL_WAIT_HSTART |
 442                    VC4_SET_FIELD(vc4_encoder->clock_select,
 443                                  PV_CONTROL_CLK_SELECT));
 444
 445         if (debug_dump_regs) {
 446                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 447                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
 448                          drm_crtc_index(crtc));
 449                 drm_print_regset32(&p, &vc4_crtc->regset);
 450         }
 451
 452         drm_dev_exit(idx);
 453 }
 454
 455 static void require_hvs_enabled(struct drm_device *dev)
 456 {
 457         struct vc4_dev *vc4 = to_vc4_dev(dev);
 458         struct vc4_hvs *hvs = vc4->hvs;
 459
 460         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 461                      SCALER_DISPCTRL_ENABLE);
 462 }
 463
 464 static int vc4_crtc_disable(struct drm_crtc *crtc,
 465                             struct drm_encoder *encoder,
 466                             struct drm_atomic_state *state,
 467                             unsigned int channel)
 468 {
 469         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 470         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 471         struct drm_device *dev = crtc->dev;
 472         struct vc4_dev *vc4 = to_vc4_dev(dev);
 473         int idx, ret;
 474
 475         if (!drm_dev_enter(dev, &idx))
 476                 return -ENODEV;
 477
 478         CRTC_WRITE(PV_V_CONTROL,
 479                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 480         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 481         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 482
 483         /*
 484          * This delay is needed to avoid to get a pixel stuck in an
 485          * unflushable FIFO between the pixelvalve and the HDMI
 486          * controllers on the BCM2711.
 487          *
 488          * Timing is fairly sensitive here, so mdelay is the safest
 489          * approach.
 490          *
 491          * If it was to be reworked, the stuck pixel happens on a
 492          * BCM2711 when changing mode with a good probability, so a
 493          * script that changes mode on a regular basis should trigger
 494          * the bug after less than 10 attempts. It manifests itself with
 495          * every pixels being shifted by one to the right, and thus the
 496          * last pixel of a line actually being displayed as the first
 497          * pixel on the next line.
 498          */
 499         mdelay(20);
 500
 501         if (vc4_encoder && vc4_encoder->post_crtc_disable)
 502                 vc4_encoder->post_crtc_disable(encoder, state);
 503
 504         vc4_crtc_pixelvalve_reset(crtc);
 505         vc4_hvs_stop_channel(vc4->hvs, channel);
 506
 507         if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
 508                 vc4_encoder->post_crtc_powerdown(encoder, state);
 509
 510         drm_dev_exit(idx);
 511
 512         return 0;
 513 }
 514
 515 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
 516 {
 517         struct drm_device *drm = crtc->dev;
 518         struct vc4_dev *vc4 = to_vc4_dev(drm);
 519         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 520         enum vc4_encoder_type encoder_type;
 521         const struct vc4_pv_data *pv_data;
 522         struct drm_encoder *encoder;
 523         struct vc4_hdmi *vc4_hdmi;
 524         unsigned encoder_sel;
 525         int channel;
 526         int ret;
 527
 528         if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 529                                       "brcm,bcm2711-pixelvalve2") ||
 530               of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 531                                       "brcm,bcm2711-pixelvalve4")))
 532                 return 0;
 533
 534         if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
 535                 return 0;
 536
 537         if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
 538                 return 0;
 539
 540         channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);
 541         if (channel < 0)
 542                 return 0;
 543
 544         encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);
 545         if (WARN_ON(encoder_sel != 0))
 546                 return 0;
 547
 548         pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 549         encoder_type = pv_data->encoder_types[encoder_sel];
 550         encoder = vc4_find_encoder_by_type(drm, encoder_type);
 551         if (WARN_ON(!encoder))
 552                 return 0;
 553
 554         vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 555         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 556         if (ret)
 557                 return ret;
 558
 559         ret = vc4_crtc_disable(crtc, encoder, NULL, channel);
 560         if (ret)
 561                 return ret;
 562
 563         /*
 564          * post_crtc_powerdown will have called pm_runtime_put, so we
 565          * don't need it here otherwise we'll get the reference counting
 566          * wrong.
 567          */
 568
 569         return 0;
 570 }
 571
 572 void vc4_crtc_send_vblank(struct drm_crtc *crtc)
 573 {
 574         struct drm_device *dev = crtc->dev;
 575         unsigned long flags;
 576
 577         if (!crtc->state || !crtc->state->event)
 578                 return;
 579
 580         spin_lock_irqsave(&dev->event_lock, flags);
 581         drm_crtc_send_vblank_event(crtc, crtc->state->event);
 582         crtc->state->event = NULL;
 583         spin_unlock_irqrestore(&dev->event_lock, flags);
 584 }
 585
 586 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 587                                     struct drm_atomic_state *state)
 588 {
 589         struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
 590                                                                          crtc);
 591         struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);
 592         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, old_state);
 593         struct drm_device *dev = crtc->dev;
 594
 595         drm_dbg(dev, "Disabling CRTC %s (%u) connected to Encoder %s (%u)",
 596                 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
 597
 598         require_hvs_enabled(dev);
 599
 600         /* Disable vblank irq handling before crtc is disabled. */
 601         drm_crtc_vblank_off(crtc);
 602
 603         vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel);
 604
 605         /*
 606          * Make sure we issue a vblank event after disabling the CRTC if
 607          * someone was waiting it.
 608          */
 609         vc4_crtc_send_vblank(crtc);
 610 }
 611
 612 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 613                                    struct drm_atomic_state *state)
 614 {
 615         struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state,
 616                                                                          crtc);
 617         struct drm_device *dev = crtc->dev;
 618         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 619         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, new_state);
 620         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 621         int idx;
 622
 623         drm_dbg(dev, "Enabling CRTC %s (%u) connected to Encoder %s (%u)",
 624                 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
 625
 626         if (!drm_dev_enter(dev, &idx))
 627                 return;
 628
 629         require_hvs_enabled(dev);
 630
 631         /* Enable vblank irq handling before crtc is started otherwise
 632          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 633          */
 634         drm_crtc_vblank_on(crtc);
 635
 636         vc4_hvs_atomic_enable(crtc, state);
 637
 638         if (vc4_encoder->pre_crtc_configure)
 639                 vc4_encoder->pre_crtc_configure(encoder, state);
 640
 641         vc4_crtc_config_pv(crtc, encoder, state);
 642
 643         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
 644
 645         if (vc4_encoder->pre_crtc_enable)
 646                 vc4_encoder->pre_crtc_enable(encoder, state);
 647
 648         /* When feeding the transposer block the pixelvalve is unneeded and
 649          * should not be enabled.
 650          */
 651         CRTC_WRITE(PV_V_CONTROL,
 652                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 653
 654         if (vc4_encoder->post_crtc_enable)
 655                 vc4_encoder->post_crtc_enable(encoder, state);
 656
 657         drm_dev_exit(idx);
 658 }
 659
 660 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 661                                                 const struct drm_display_mode *mode)
 662 {
 663         /* Do not allow doublescan modes from user space */
 664         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 665                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 666                               crtc->base.id);
 667                 return MODE_NO_DBLESCAN;
 668         }
 669
 670         return MODE_OK;
 671 }
 672
 673 void vc4_crtc_get_margins(struct drm_crtc_state *state,
 674                           unsigned int *left, unsigned int *right,
 675                           unsigned int *top, unsigned int *bottom)
 676 {
 677         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 678         struct drm_connector_state *conn_state;
 679         struct drm_connector *conn;
 680         int i;
 681
 682         *left = vc4_state->margins.left;
 683         *right = vc4_state->margins.right;
 684         *top = vc4_state->margins.top;
 685         *bottom = vc4_state->margins.bottom;
 686
 687         /* We have to interate over all new connector states because
 688          * vc4_crtc_get_margins() might be called before
 689          * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
 690          * might be outdated.
 691          */
 692         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 693                 if (conn_state->crtc != state->crtc)
 694                         continue;
 695
 696                 *left = conn_state->tv.margins.left;
 697                 *right = conn_state->tv.margins.right;
 698                 *top = conn_state->tv.margins.top;
 699                 *bottom = conn_state->tv.margins.bottom;
 700                 break;
 701         }
 702 }
 703
 704 int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 705                           struct drm_atomic_state *state)
 706 {
 707         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 708                                                                           crtc);
 709         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 710         struct drm_connector *conn;
 711         struct drm_connector_state *conn_state;
 712         struct drm_encoder *encoder;
 713         int ret, i;
 714
 715         ret = vc4_hvs_atomic_check(crtc, state);
 716         if (ret)
 717                 return ret;
 718
 719         encoder = vc4_get_crtc_encoder(crtc, crtc_state);
 720         if (encoder) {
 721                 const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 722                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 723
 724                 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {
 725                         vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 8000,
 726                                                   mode->clock * 9 / 10) * 1000;
 727                 } else {
 728                         vc4_state->hvs_load = mode->clock * 1000;
 729                 }
 730         }
 731
 732         for_each_new_connector_in_state(state, conn, conn_state,
 733                                         i) {
 734                 if (conn_state->crtc != crtc)
 735                         continue;
 736
 737                 vc4_state->margins.left = conn_state->tv.margins.left;
 738                 vc4_state->margins.right = conn_state->tv.margins.right;
 739                 vc4_state->margins.top = conn_state->tv.margins.top;
 740                 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
 741                 break;
 742         }
 743
 744         return 0;
 745 }
 746
 747 static int vc4_enable_vblank(struct drm_crtc *crtc)
 748 {
 749         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 750         struct drm_device *dev = crtc->dev;
 751         int idx;
 752
 753         if (!drm_dev_enter(dev, &idx))
 754                 return -ENODEV;
 755
 756         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 757
 758         drm_dev_exit(idx);
 759
 760         return 0;
 761 }
 762
 763 static void vc4_disable_vblank(struct drm_crtc *crtc)
 764 {
 765         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 766         struct drm_device *dev = crtc->dev;
 767         int idx;
 768
 769         if (!drm_dev_enter(dev, &idx))
 770                 return;
 771
 772         CRTC_WRITE(PV_INTEN, 0);
 773
 774         drm_dev_exit(idx);
 775 }
 776
 777 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 778 {
 779         struct drm_crtc *crtc = &vc4_crtc->base;
 780         struct drm_device *dev = crtc->dev;
 781         struct vc4_dev *vc4 = to_vc4_dev(dev);
 782         struct vc4_hvs *hvs = vc4->hvs;
 783         u32 chan = vc4_crtc->current_hvs_channel;
 784         unsigned long flags;
 785
 786         spin_lock_irqsave(&dev->event_lock, flags);
 787         spin_lock(&vc4_crtc->irq_lock);
 788         if (vc4_crtc->event &&
 789             (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) ||
 790              vc4_crtc->feeds_txp)) {
 791                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 792                 vc4_crtc->event = NULL;
 793                 drm_crtc_vblank_put(crtc);
 794
 795                 /* Wait for the page flip to unmask the underrun to ensure that
 796                  * the display list was updated by the hardware. Before that
 797                  * happens, the HVS will be using the previous display list with
 798                  * the CRTC and encoder already reconfigured, leading to
 799                  * underruns. This can be seen when reconfiguring the CRTC.
 800                  */
 801                 vc4_hvs_unmask_underrun(hvs, chan);
 802         }
 803         spin_unlock(&vc4_crtc->irq_lock);
 804         spin_unlock_irqrestore(&dev->event_lock, flags);
 805 }
 806
 807 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 808 {
 809         crtc->t_vblank = ktime_get();
 810         drm_crtc_handle_vblank(&crtc->base);
 811         vc4_crtc_handle_page_flip(crtc);
 812 }
 813
 814 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 815 {
 816         struct vc4_crtc *vc4_crtc = data;
 817         u32 stat = CRTC_READ(PV_INTSTAT);
 818         irqreturn_t ret = IRQ_NONE;
 819
 820         if (stat & PV_INT_VFP_START) {
 821                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 822                 vc4_crtc_handle_vblank(vc4_crtc);
 823                 ret = IRQ_HANDLED;
 824         }
 825
 826         return ret;
 827 }
 828
 829 struct vc4_async_flip_state {
 830         struct drm_crtc *crtc;
 831         struct drm_framebuffer *fb;
 832         struct drm_framebuffer *old_fb;
 833         struct drm_pending_vblank_event *event;
 834
 835         union {
 836                 struct dma_fence_cb fence;
 837                 struct vc4_seqno_cb seqno;
 838         } cb;
 839 };
 840
 841 /* Called when the V3D execution for the BO being flipped to is done, so that
 842  * we can actually update the plane's address to point to it.
 843  */
 844 static void
 845 vc4_async_page_flip_complete(struct vc4_async_flip_state *flip_state)
 846 {
 847         struct drm_crtc *crtc = flip_state->crtc;
 848         struct drm_device *dev = crtc->dev;
 849         struct drm_plane *plane = crtc->primary;
 850
 851         vc4_plane_async_set_fb(plane, flip_state->fb);
 852         if (flip_state->event) {
 853                 unsigned long flags;
 854
 855                 spin_lock_irqsave(&dev->event_lock, flags);
 856                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 857                 spin_unlock_irqrestore(&dev->event_lock, flags);
 858         }
 859
 860         drm_crtc_vblank_put(crtc);
 861         drm_framebuffer_put(flip_state->fb);
 862
 863         if (flip_state->old_fb)
 864                 drm_framebuffer_put(flip_state->old_fb);
 865
 866         kfree(flip_state);
 867 }
 868
 869 static void vc4_async_page_flip_seqno_complete(struct vc4_seqno_cb *cb)
 870 {
 871         struct vc4_async_flip_state *flip_state =
 872                 container_of(cb, struct vc4_async_flip_state, cb.seqno);
 873         struct vc4_bo *bo = NULL;
 874
 875         if (flip_state->old_fb) {
 876                 struct drm_gem_dma_object *dma_bo =
 877                         drm_fb_dma_get_gem_obj(flip_state->old_fb, 0);
 878                 bo = to_vc4_bo(&dma_bo->base);
 879         }
 880
 881         vc4_async_page_flip_complete(flip_state);
 882
 883         /*
 884          * Decrement the BO usecnt in order to keep the inc/dec
 885          * calls balanced when the planes are updated through
 886          * the async update path.
 887          *
 888          * FIXME: we should move to generic async-page-flip when
 889          * it's available, so that we can get rid of this
 890          * hand-made cleanup_fb() logic.
 891          */
 892         if (bo)
 893                 vc4_bo_dec_usecnt(bo);
 894 }
 895
 896 static void vc4_async_page_flip_fence_complete(struct dma_fence *fence,
 897                                                struct dma_fence_cb *cb)
 898 {
 899         struct vc4_async_flip_state *flip_state =
 900                 container_of(cb, struct vc4_async_flip_state, cb.fence);
 901
 902         vc4_async_page_flip_complete(flip_state);
 903         dma_fence_put(fence);
 904 }
 905
 906 static int vc4_async_set_fence_cb(struct drm_device *dev,
 907                                   struct vc4_async_flip_state *flip_state)
 908 {
 909         struct drm_framebuffer *fb = flip_state->fb;
 910         struct drm_gem_dma_object *dma_bo = drm_fb_dma_get_gem_obj(fb, 0);
 911         struct vc4_dev *vc4 = to_vc4_dev(dev);
 912         struct dma_fence *fence;
 913         int ret;
 914
 915         if (!vc4->is_vc5) {
 916                 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base);
 917
 918                 return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,
 919                                           vc4_async_page_flip_seqno_complete);
 920         }
 921
 922         ret = dma_resv_get_singleton(dma_bo->base.resv, DMA_RESV_USAGE_READ, &fence);
 923         if (ret)
 924                 return ret;
 925
 926         /* If there's no fence, complete the page flip immediately */
 927         if (!fence) {
 928                 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
 929                 return 0;
 930         }
 931
 932         /* If the fence has already been completed, complete the page flip */
 933         if (dma_fence_add_callback(fence, &flip_state->cb.fence,
 934                                    vc4_async_page_flip_fence_complete))
 935                 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
 936
 937         return 0;
 938 }
 939
 940 static int
 941 vc4_async_page_flip_common(struct drm_crtc *crtc,
 942                            struct drm_framebuffer *fb,
 943                            struct drm_pending_vblank_event *event,
 944                            uint32_t flags)
 945 {
 946         struct drm_device *dev = crtc->dev;
 947         struct drm_plane *plane = crtc->primary;
 948         struct vc4_async_flip_state *flip_state;
 949
 950         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 951         if (!flip_state)
 952                 return -ENOMEM;
 953
 954         drm_framebuffer_get(fb);
 955         flip_state->fb = fb;
 956         flip_state->crtc = crtc;
 957         flip_state->event = event;
 958
 959         /* Save the current FB before it's replaced by the new one in
 960          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 961          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 962          * it consistent.
 963          * FIXME: we should move to generic async-page-flip when it's
 964          * available, so that we can get rid of this hand-made cleanup_fb()
 965          * logic.
 966          */
 967         flip_state->old_fb = plane->state->fb;
 968         if (flip_state->old_fb)
 969                 drm_framebuffer_get(flip_state->old_fb);
 970
 971         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 972
 973         /* Immediately update the plane's legacy fb pointer, so that later
 974          * modeset prep sees the state that will be present when the semaphore
 975          * is released.
 976          */
 977         drm_atomic_set_fb_for_plane(plane->state, fb);
 978
 979         vc4_async_set_fence_cb(dev, flip_state);
 980
 981         /* Driver takes ownership of state on successful async commit. */
 982         return 0;
 983 }
 984
 985 /* Implements async (non-vblank-synced) page flips.
 986  *
 987  * The page flip ioctl needs to return immediately, so we grab the
 988  * modeset semaphore on the pipe, and queue the address update for
 989  * when V3D is done with the BO being flipped to.
 990  */
 991 static int vc4_async_page_flip(struct drm_crtc *crtc,
 992                                struct drm_framebuffer *fb,
 993                                struct drm_pending_vblank_event *event,
 994                                uint32_t flags)
 995 {
 996         struct drm_device *dev = crtc->dev;
 997         struct vc4_dev *vc4 = to_vc4_dev(dev);
 998         struct drm_gem_dma_object *dma_bo = drm_fb_dma_get_gem_obj(fb, 0);
 999         struct vc4_bo *bo = to_vc4_bo(&dma_bo->base);
1000         int ret;
1001
1002         if (WARN_ON_ONCE(vc4->is_vc5))
1003                 return -ENODEV;
1004
1005         /*
1006          * Increment the BO usecnt here, so that we never end up with an
1007          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
1008          * plane is later updated through the non-async path.
1009          *
1010          * FIXME: we should move to generic async-page-flip when
1011          * it's available, so that we can get rid of this
1012          * hand-made prepare_fb() logic.
1013          */
1014         ret = vc4_bo_inc_usecnt(bo);
1015         if (ret)
1016                 return ret;
1017
1018         ret = vc4_async_page_flip_common(crtc, fb, event, flags);
1019         if (ret) {
1020                 vc4_bo_dec_usecnt(bo);
1021                 return ret;
1022         }
1023
1024         return 0;
1025 }
1026
1027 static int vc5_async_page_flip(struct drm_crtc *crtc,
1028                                struct drm_framebuffer *fb,
1029                                struct drm_pending_vblank_event *event,
1030                                uint32_t flags)
1031 {
1032         return vc4_async_page_flip_common(crtc, fb, event, flags);
1033 }
1034
1035 int vc4_page_flip(struct drm_crtc *crtc,
1036                   struct drm_framebuffer *fb,
1037                   struct drm_pending_vblank_event *event,
1038                   uint32_t flags,
1039                   struct drm_modeset_acquire_ctx *ctx)
1040 {
1041         if (flags & DRM_MODE_PAGE_FLIP_ASYNC) {
1042                 struct drm_device *dev = crtc->dev;
1043                 struct vc4_dev *vc4 = to_vc4_dev(dev);
1044
1045                 if (vc4->is_vc5)
1046                         return vc5_async_page_flip(crtc, fb, event, flags);
1047                 else
1048                         return vc4_async_page_flip(crtc, fb, event, flags);
1049         } else {
1050                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
1051         }
1052 }
1053
1054 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
1055 {
1056         struct vc4_crtc_state *vc4_state, *old_vc4_state;
1057
1058         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
1059         if (!vc4_state)
1060                 return NULL;
1061
1062         old_vc4_state = to_vc4_crtc_state(crtc->state);
1063         vc4_state->margins = old_vc4_state->margins;
1064         vc4_state->assigned_channel = old_vc4_state->assigned_channel;
1065
1066         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
1067         return &vc4_state->base;
1068 }
1069
1070 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
1071                             struct drm_crtc_state *state)
1072 {
1073         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
1074         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
1075
1076         if (drm_mm_node_allocated(&vc4_state->mm)) {
1077                 unsigned long flags;
1078
1079                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1080                 drm_mm_remove_node(&vc4_state->mm);
1081                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1082
1083         }
1084
1085         drm_atomic_helper_crtc_destroy_state(crtc, state);
1086 }
1087
1088 void vc4_crtc_reset(struct drm_crtc *crtc)
1089 {
1090         struct vc4_crtc_state *vc4_crtc_state;
1091
1092         if (crtc->state)
1093                 vc4_crtc_destroy_state(crtc, crtc->state);
1094
1095         vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL);
1096         if (!vc4_crtc_state) {
1097                 crtc->state = NULL;
1098                 return;
1099         }
1100
1101         vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
1102         __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);
1103 }
1104
1105 int vc4_crtc_late_register(struct drm_crtc *crtc)
1106 {
1107         struct drm_device *drm = crtc->dev;
1108         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1109         const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
1110
1111         vc4_debugfs_add_regset32(drm, crtc_data->debugfs_name,
1112                                  &vc4_crtc->regset);
1113
1114         return 0;
1115 }
1116
1117 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1118         .set_config = drm_atomic_helper_set_config,
1119         .page_flip = vc4_page_flip,
1120         .set_property = NULL,
1121         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1122         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1123         .reset = vc4_crtc_reset,
1124         .atomic_duplicate_state = vc4_crtc_duplicate_state,
1125         .atomic_destroy_state = vc4_crtc_destroy_state,
1126         .enable_vblank = vc4_enable_vblank,
1127         .disable_vblank = vc4_disable_vblank,
1128         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1129         .late_register = vc4_crtc_late_register,
1130 };
1131
1132 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1133         .mode_valid = vc4_crtc_mode_valid,
1134         .atomic_check = vc4_crtc_atomic_check,
1135         .atomic_begin = vc4_hvs_atomic_begin,
1136         .atomic_flush = vc4_hvs_atomic_flush,
1137         .atomic_enable = vc4_crtc_atomic_enable,
1138         .atomic_disable = vc4_crtc_atomic_disable,
1139         .get_scanout_position = vc4_crtc_get_scanout_position,
1140 };
1141
1142 const struct vc4_pv_data bcm2835_pv0_data = {
1143         .base = {
1144                 .name = "pixelvalve-0",
1145                 .debugfs_name = "crtc0_regs",
1146                 .hvs_available_channels = BIT(0),
1147                 .hvs_output = 0,
1148         },
1149         .fifo_depth = 64,
1150         .pixels_per_clock = 1,
1151         .encoder_types = {
1152                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1153                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1154         },
1155 };
1156
1157 const struct vc4_pv_data bcm2835_pv1_data = {
1158         .base = {
1159                 .name = "pixelvalve-1",
1160                 .debugfs_name = "crtc1_regs",
1161                 .hvs_available_channels = BIT(2),
1162                 .hvs_output = 2,
1163         },
1164         .fifo_depth = 64,
1165         .pixels_per_clock = 1,
1166         .encoder_types = {
1167                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1168                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1169         },
1170 };
1171
1172 const struct vc4_pv_data bcm2835_pv2_data = {
1173         .base = {
1174                 .name = "pixelvalve-2",
1175                 .debugfs_name = "crtc2_regs",
1176                 .hvs_available_channels = BIT(1),
1177                 .hvs_output = 1,
1178         },
1179         .fifo_depth = 64,
1180         .pixels_per_clock = 1,
1181         .encoder_types = {
1182                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
1183                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1184         },
1185 };
1186
1187 const struct vc4_pv_data bcm2711_pv0_data = {
1188         .base = {
1189                 .name = "pixelvalve-0",
1190                 .debugfs_name = "crtc0_regs",
1191                 .hvs_available_channels = BIT(0),
1192                 .hvs_output = 0,
1193         },
1194         .fifo_depth = 64,
1195         .pixels_per_clock = 1,
1196         .encoder_types = {
1197                 [0] = VC4_ENCODER_TYPE_DSI0,
1198                 [1] = VC4_ENCODER_TYPE_DPI,
1199         },
1200 };
1201
1202 const struct vc4_pv_data bcm2711_pv1_data = {
1203         .base = {
1204                 .name = "pixelvalve-1",
1205                 .debugfs_name = "crtc1_regs",
1206                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1207                 .hvs_output = 3,
1208         },
1209         .fifo_depth = 64,
1210         .pixels_per_clock = 1,
1211         .encoder_types = {
1212                 [0] = VC4_ENCODER_TYPE_DSI1,
1213                 [1] = VC4_ENCODER_TYPE_SMI,
1214         },
1215 };
1216
1217 const struct vc4_pv_data bcm2711_pv2_data = {
1218         .base = {
1219                 .name = "pixelvalve-2",
1220                 .debugfs_name = "crtc2_regs",
1221                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1222                 .hvs_output = 4,
1223         },
1224         .fifo_depth = 256,
1225         .pixels_per_clock = 2,
1226         .encoder_types = {
1227                 [0] = VC4_ENCODER_TYPE_HDMI0,
1228         },
1229 };
1230
1231 const struct vc4_pv_data bcm2711_pv3_data = {
1232         .base = {
1233                 .name = "pixelvalve-3",
1234                 .debugfs_name = "crtc3_regs",
1235                 .hvs_available_channels = BIT(1),
1236                 .hvs_output = 1,
1237         },
1238         .fifo_depth = 64,
1239         .pixels_per_clock = 1,
1240         .encoder_types = {
1241                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1242         },
1243 };
1244
1245 const struct vc4_pv_data bcm2711_pv4_data = {
1246         .base = {
1247                 .name = "pixelvalve-4",
1248                 .debugfs_name = "crtc4_regs",
1249                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1250                 .hvs_output = 5,
1251         },
1252         .fifo_depth = 64,
1253         .pixels_per_clock = 2,
1254         .encoder_types = {
1255                 [0] = VC4_ENCODER_TYPE_HDMI1,
1256         },
1257 };
1258
1259 static const struct of_device_id vc4_crtc_dt_match[] = {
1260         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1261         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1262         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1263         { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1264         { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1265         { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1266         { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1267         { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1268         {}
1269 };
1270
1271 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1272                                         struct drm_crtc *crtc)
1273 {
1274         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1275         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
1276         const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
1277         struct drm_encoder *encoder;
1278
1279         drm_for_each_encoder(encoder, drm) {
1280                 struct vc4_encoder *vc4_encoder;
1281                 int i;
1282
1283                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
1284                         continue;
1285
1286                 vc4_encoder = to_vc4_encoder(encoder);
1287                 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
1288                         if (vc4_encoder->type == encoder_types[i]) {
1289                                 vc4_encoder->clock_select = i;
1290                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1291                                 break;
1292                         }
1293                 }
1294         }
1295 }
1296
1297 /**
1298  * __vc4_crtc_init - Initializes a CRTC
1299  * @drm: DRM Device
1300  * @pdev: CRTC Platform Device
1301  * @vc4_crtc: CRTC Object to Initialize
1302  * @data: Configuration data associated with this CRTC
1303  * @primary_plane: Primary plane for CRTC
1304  * @crtc_funcs: Callbacks for the new CRTC
1305  * @crtc_helper_funcs: Helper Callbacks for the new CRTC
1306  * @feeds_txp: Is this CRTC connected to the TXP?
1307  *
1308  * Initializes our private CRTC structure. This function is mostly
1309  * relevant for KUnit testing, all other users should use
1310  * vc4_crtc_init() instead.
1311  *
1312  * Returns:
1313  * 0 on success, a negative error code on failure.
1314  */
1315 int __vc4_crtc_init(struct drm_device *drm,
1316                     struct platform_device *pdev,
1317                     struct vc4_crtc *vc4_crtc,
1318                     const struct vc4_crtc_data *data,
1319                     struct drm_plane *primary_plane,
1320                     const struct drm_crtc_funcs *crtc_funcs,
1321                     const struct drm_crtc_helper_funcs *crtc_helper_funcs,
1322                     bool feeds_txp)
1323 {
1324         struct vc4_dev *vc4 = to_vc4_dev(drm);
1325         struct drm_crtc *crtc = &vc4_crtc->base;
1326         unsigned int i;
1327         int ret;
1328
1329         vc4_crtc->data = data;
1330         vc4_crtc->pdev = pdev;
1331         vc4_crtc->feeds_txp = feeds_txp;
1332         spin_lock_init(&vc4_crtc->irq_lock);
1333         ret = drmm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1334                                          crtc_funcs, data->name);
1335         if (ret)
1336                 return ret;
1337
1338         drm_crtc_helper_add(crtc, crtc_helper_funcs);
1339
1340         if (!vc4->is_vc5) {
1341                 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1342
1343                 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1344
1345                 /* We support CTM, but only for one CRTC at a time. It's therefore
1346                  * implemented as private driver state in vc4_kms, not here.
1347                  */
1348                 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1349         }
1350
1351         for (i = 0; i < crtc->gamma_size; i++) {
1352                 vc4_crtc->lut_r[i] = i;
1353                 vc4_crtc->lut_g[i] = i;
1354                 vc4_crtc->lut_b[i] = i;
1355         }
1356
1357         return 0;
1358 }
1359
1360 int vc4_crtc_init(struct drm_device *drm, struct platform_device *pdev,
1361                   struct vc4_crtc *vc4_crtc,
1362                   const struct vc4_crtc_data *data,
1363                   const struct drm_crtc_funcs *crtc_funcs,
1364                   const struct drm_crtc_helper_funcs *crtc_helper_funcs,
1365                   bool feeds_txp)
1366 {
1367         struct drm_plane *primary_plane;
1368
1369         /* For now, we create just the primary and the legacy cursor
1370          * planes.  We should be able to stack more planes on easily,
1371          * but to do that we would need to compute the bandwidth
1372          * requirement of the plane configuration, and reject ones
1373          * that will take too much.
1374          */
1375         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY, 0);
1376         if (IS_ERR(primary_plane)) {
1377                 dev_err(drm->dev, "failed to construct primary plane\n");
1378                 return PTR_ERR(primary_plane);
1379         }
1380
1381         return __vc4_crtc_init(drm, pdev, vc4_crtc, data, primary_plane,
1382                                crtc_funcs, crtc_helper_funcs, feeds_txp);
1383 }
1384
1385 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1386 {
1387         struct platform_device *pdev = to_platform_device(dev);
1388         struct drm_device *drm = dev_get_drvdata(master);
1389         const struct vc4_pv_data *pv_data;
1390         struct vc4_crtc *vc4_crtc;
1391         struct drm_crtc *crtc;
1392         int ret;
1393
1394         vc4_crtc = drmm_kzalloc(drm, sizeof(*vc4_crtc), GFP_KERNEL);
1395         if (!vc4_crtc)
1396                 return -ENOMEM;
1397         crtc = &vc4_crtc->base;
1398
1399         pv_data = of_device_get_match_data(dev);
1400         if (!pv_data)
1401                 return -ENODEV;
1402
1403         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1404         if (IS_ERR(vc4_crtc->regs))
1405                 return PTR_ERR(vc4_crtc->regs);
1406
1407         vc4_crtc->regset.base = vc4_crtc->regs;
1408         vc4_crtc->regset.regs = crtc_regs;
1409         vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1410
1411         ret = vc4_crtc_init(drm, pdev, vc4_crtc, &pv_data->base,
1412                             &vc4_crtc_funcs, &vc4_crtc_helper_funcs,
1413                             false);
1414         if (ret)
1415                 return ret;
1416         vc4_set_crtc_possible_masks(drm, crtc);
1417
1418         CRTC_WRITE(PV_INTEN, 0);
1419         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1420         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1421                                vc4_crtc_irq_handler,
1422                                IRQF_SHARED,
1423                                "vc4 crtc", vc4_crtc);
1424         if (ret)
1425                 return ret;
1426
1427         platform_set_drvdata(pdev, vc4_crtc);
1428
1429         return 0;
1430 }
1431
1432 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1433                             void *data)
1434 {
1435         struct platform_device *pdev = to_platform_device(dev);
1436         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1437
1438         CRTC_WRITE(PV_INTEN, 0);
1439
1440         platform_set_drvdata(pdev, NULL);
1441 }
1442
1443 static const struct component_ops vc4_crtc_ops = {
1444         .bind   = vc4_crtc_bind,
1445         .unbind = vc4_crtc_unbind,
1446 };
1447
1448 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1449 {
1450         return component_add(&pdev->dev, &vc4_crtc_ops);
1451 }
1452
1453 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1454 {
1455         component_del(&pdev->dev, &vc4_crtc_ops);
1456         return 0;
1457 }
1458
1459 struct platform_driver vc4_crtc_driver = {
1460         .probe = vc4_crtc_dev_probe,
1461         .remove = vc4_crtc_dev_remove,
1462         .driver = {
1463                 .name = "vc4_crtc",
1464                 .of_match_table = vc4_crtc_dt_match,
1465         },
1466 };