drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * encoder's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, the CRTC is also
  19  * responsible for writing the display list for the HVS channel that
  20  * the CRTC will use.
  21  *
  22  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  23  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  24  * image domain can feed either HDMI or the SDTV controller.  The
  25  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  26  * SDTV, etc.) according to which output type is chosen in the mux.
  27  *
  28  * For power management, the pixel valve's registers are all clocked
  29  * by the AXI clock, while the timings and FIFOs make use of the
  30  * output-specific clock.  Since the encoders also directly consume
  31  * the CPRMAN clocks, and know what timings they need, they are the
  32  * ones that set the clock.
  33  */
  34
  35 #include <drm/drm_atomic.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_atomic_uapi.h>
  38 #include <drm/drm_probe_helper.h>
  39 #include <linux/clk.h>
  40 #include <drm/drm_fb_cma_helper.h>
  41 #include <linux/component.h>
  42 #include <linux/of_device.h>
  43 #include "vc4_drv.h"
  44 #include "vc4_regs.h"
  45
  46 struct vc4_crtc_state {
  47         struct drm_crtc_state base;
  48         /* Dlist area for this CRTC configuration. */
  49         struct drm_mm_node mm;
  50         bool feed_txp;
  51         bool txp_armed;
  52
  53         struct {
  54                 unsigned int left;
  55                 unsigned int right;
  56                 unsigned int top;
  57                 unsigned int bottom;
  58         } margins;
  59 };
  60
  61 static inline struct vc4_crtc_state *
  62 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  63 {
  64         return (struct vc4_crtc_state *)crtc_state;
  65 }
  66
  67 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  68 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  69
  70 #define CRTC_REG(reg) { reg, #reg }
  71 static const struct {
  72         u32 reg;
  73         const char *name;
  74 } crtc_regs[] = {
  75         CRTC_REG(PV_CONTROL),
  76         CRTC_REG(PV_V_CONTROL),
  77         CRTC_REG(PV_VSYNCD_EVEN),
  78         CRTC_REG(PV_HORZA),
  79         CRTC_REG(PV_HORZB),
  80         CRTC_REG(PV_VERTA),
  81         CRTC_REG(PV_VERTB),
  82         CRTC_REG(PV_VERTA_EVEN),
  83         CRTC_REG(PV_VERTB_EVEN),
  84         CRTC_REG(PV_INTEN),
  85         CRTC_REG(PV_INTSTAT),
  86         CRTC_REG(PV_STAT),
  87         CRTC_REG(PV_HACT_ACT),
  88 };
  89
  90 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
  91 {
  92         int i;
  93
  94         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
  95                 DRM_INFO("0x%04x (%s): 0x%08x\n",
  96                          crtc_regs[i].reg, crtc_regs[i].name,
  97                          CRTC_READ(crtc_regs[i].reg));
  98         }
  99 }
 100
 101 #ifdef CONFIG_DEBUG_FS
 102 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
 103 {
 104         struct drm_info_node *node = (struct drm_info_node *)m->private;
 105         struct drm_device *dev = node->minor->dev;
 106         int crtc_index = (uintptr_t)node->info_ent->data;
 107         struct drm_crtc *crtc;
 108         struct vc4_crtc *vc4_crtc;
 109         int i;
 110
 111         i = 0;
 112         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 113                 if (i == crtc_index)
 114                         break;
 115                 i++;
 116         }
 117         if (!crtc)
 118                 return 0;
 119         vc4_crtc = to_vc4_crtc(crtc);
 120
 121         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 122                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 123                            crtc_regs[i].name, crtc_regs[i].reg,
 124                            CRTC_READ(crtc_regs[i].reg));
 125         }
 126
 127         return 0;
 128 }
 129 #endif
 130
 131 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 132                              bool in_vblank_irq, int *vpos, int *hpos,
 133                              ktime_t *stime, ktime_t *etime,
 134                              const struct drm_display_mode *mode)
 135 {
 136         struct vc4_dev *vc4 = to_vc4_dev(dev);
 137         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
 138         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 139         u32 val;
 140         int fifo_lines;
 141         int vblank_lines;
 142         bool ret = false;
 143
 144         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 145
 146         /* Get optional system timestamp before query. */
 147         if (stime)
 148                 *stime = ktime_get();
 149
 150         /*
 151          * Read vertical scanline which is currently composed for our
 152          * pixelvalve by the HVS, and also the scaler status.
 153          */
 154         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 155
 156         /* Get optional system timestamp after query. */
 157         if (etime)
 158                 *etime = ktime_get();
 159
 160         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 161
 162         /* Vertical position of hvs composed scanline. */
 163         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 164         *hpos = 0;
 165
 166         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 167                 *vpos /= 2;
 168
 169                 /* Use hpos to correct for field offset in interlaced mode. */
 170                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 171                         *hpos += mode->crtc_htotal / 2;
 172         }
 173
 174         /* This is the offset we need for translating hvs -> pv scanout pos. */
 175         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 176
 177         if (fifo_lines > 0)
 178                 ret = true;
 179
 180         /* HVS more than fifo_lines into frame for compositing? */
 181         if (*vpos > fifo_lines) {
 182                 /*
 183                  * We are in active scanout and can get some meaningful results
 184                  * from HVS. The actual PV scanout can not trail behind more
 185                  * than fifo_lines as that is the fifo's capacity. Assume that
 186                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 187                  * refilling the fifo and PV consuming from the fifo, ie.
 188                  * whenever the PV consumes and frees up a scanline in the
 189                  * fifo, the HVS will immediately refill it, therefore
 190                  * incrementing vpos. Therefore we choose HVS read position -
 191                  * fifo size in scanlines as a estimate of the real scanout
 192                  * position of the PV.
 193                  */
 194                 *vpos -= fifo_lines + 1;
 195
 196                 return ret;
 197         }
 198
 199         /*
 200          * Less: This happens when we are in vblank and the HVS, after getting
 201          * the VSTART restart signal from the PV, just started refilling its
 202          * fifo with new lines from the top-most lines of the new framebuffers.
 203          * The PV does not scan out in vblank, so does not remove lines from
 204          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 205          * We can't get meaningful readings wrt. scanline position of the PV
 206          * and need to make things up in a approximative but consistent way.
 207          */
 208         vblank_lines = mode->vtotal - mode->vdisplay;
 209
 210         if (in_vblank_irq) {
 211                 /*
 212                  * Assume the irq handler got called close to first
 213                  * line of vblank, so PV has about a full vblank
 214                  * scanlines to go, and as a base timestamp use the
 215                  * one taken at entry into vblank irq handler, so it
 216                  * is not affected by random delays due to lock
 217                  * contention on event_lock or vblank_time lock in
 218                  * the core.
 219                  */
 220                 *vpos = -vblank_lines;
 221
 222                 if (stime)
 223                         *stime = vc4_crtc->t_vblank;
 224                 if (etime)
 225                         *etime = vc4_crtc->t_vblank;
 226
 227                 /*
 228                  * If the HVS fifo is not yet full then we know for certain
 229                  * we are at the very beginning of vblank, as the hvs just
 230                  * started refilling, and the stime and etime timestamps
 231                  * truly correspond to start of vblank.
 232                  *
 233                  * Unfortunately there's no way to report this to upper levels
 234                  * and make it more useful.
 235                  */
 236         } else {
 237                 /*
 238                  * No clue where we are inside vblank. Return a vpos of zero,
 239                  * which will cause calling code to just return the etime
 240                  * timestamp uncorrected. At least this is no worse than the
 241                  * standard fallback.
 242                  */
 243                 *vpos = 0;
 244         }
 245
 246         return ret;
 247 }
 248
 249 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 250 {
 251         drm_crtc_cleanup(crtc);
 252 }
 253
 254 static void
 255 vc4_crtc_lut_load(struct drm_crtc *crtc)
 256 {
 257         struct drm_device *dev = crtc->dev;
 258         struct vc4_dev *vc4 = to_vc4_dev(dev);
 259         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 260         u32 i;
 261
 262         /* The LUT memory is laid out with each HVS channel in order,
 263          * each of which takes 256 writes for R, 256 for G, then 256
 264          * for B.
 265          */
 266         HVS_WRITE(SCALER_GAMADDR,
 267                   SCALER_GAMADDR_AUTOINC |
 268                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 269
 270         for (i = 0; i < crtc->gamma_size; i++)
 271                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 272         for (i = 0; i < crtc->gamma_size; i++)
 273                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 274         for (i = 0; i < crtc->gamma_size; i++)
 275                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 276 }
 277
 278 static void
 279 vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
 280 {
 281         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 282         struct drm_color_lut *lut = crtc->state->gamma_lut->data;
 283         u32 length = drm_color_lut_size(crtc->state->gamma_lut);
 284         u32 i;
 285
 286         for (i = 0; i < length; i++) {
 287                 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
 288                 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
 289                 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
 290         }
 291
 292         vc4_crtc_lut_load(crtc);
 293 }
 294
 295 static u32 vc4_get_fifo_full_level(u32 format)
 296 {
 297         static const u32 fifo_len_bytes = 64;
 298         static const u32 hvs_latency_pix = 6;
 299
 300         switch (format) {
 301         case PV_CONTROL_FORMAT_DSIV_16:
 302         case PV_CONTROL_FORMAT_DSIC_16:
 303                 return fifo_len_bytes - 2 * hvs_latency_pix;
 304         case PV_CONTROL_FORMAT_DSIV_18:
 305                 return fifo_len_bytes - 14;
 306         case PV_CONTROL_FORMAT_24:
 307         case PV_CONTROL_FORMAT_DSIV_24:
 308         default:
 309                 return fifo_len_bytes - 3 * hvs_latency_pix;
 310         }
 311 }
 312
 313 /*
 314  * Returns the encoder attached to the CRTC.
 315  *
 316  * VC4 can only scan out to one encoder at a time, while the DRM core
 317  * allows drivers to push pixels to more than one encoder from the
 318  * same CRTC.
 319  */
 320 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 321 {
 322         struct drm_connector *connector;
 323         struct drm_connector_list_iter conn_iter;
 324
 325         drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 326         drm_for_each_connector_iter(connector, &conn_iter) {
 327                 if (connector->state->crtc == crtc) {
 328                         drm_connector_list_iter_end(&conn_iter);
 329                         return connector->encoder;
 330                 }
 331         }
 332         drm_connector_list_iter_end(&conn_iter);
 333
 334         return NULL;
 335 }
 336
 337 static void vc4_crtc_config_pv(struct drm_crtc *crtc)
 338 {
 339         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
 340         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 341         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 342         struct drm_crtc_state *state = crtc->state;
 343         struct drm_display_mode *mode = &state->adjusted_mode;
 344         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 345         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 346         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 347                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 348         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 349
 350         /* Reset the PV fifo. */
 351         CRTC_WRITE(PV_CONTROL, 0);
 352         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 353         CRTC_WRITE(PV_CONTROL, 0);
 354
 355         CRTC_WRITE(PV_HORZA,
 356                    VC4_SET_FIELD((mode->htotal -
 357                                   mode->hsync_end) * pixel_rep,
 358                                  PV_HORZA_HBP) |
 359                    VC4_SET_FIELD((mode->hsync_end -
 360                                   mode->hsync_start) * pixel_rep,
 361                                  PV_HORZA_HSYNC));
 362         CRTC_WRITE(PV_HORZB,
 363                    VC4_SET_FIELD((mode->hsync_start -
 364                                   mode->hdisplay) * pixel_rep,
 365                                  PV_HORZB_HFP) |
 366                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 367
 368         CRTC_WRITE(PV_VERTA,
 369                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 370                                  PV_VERTA_VBP) |
 371                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 372                                  PV_VERTA_VSYNC));
 373         CRTC_WRITE(PV_VERTB,
 374                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 375                                  PV_VERTB_VFP) |
 376                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 377
 378         if (interlace) {
 379                 CRTC_WRITE(PV_VERTA_EVEN,
 380                            VC4_SET_FIELD(mode->crtc_vtotal -
 381                                          mode->crtc_vsync_end - 1,
 382                                          PV_VERTA_VBP) |
 383                            VC4_SET_FIELD(mode->crtc_vsync_end -
 384                                          mode->crtc_vsync_start,
 385                                          PV_VERTA_VSYNC));
 386                 CRTC_WRITE(PV_VERTB_EVEN,
 387                            VC4_SET_FIELD(mode->crtc_vsync_start -
 388                                          mode->crtc_vdisplay,
 389                                          PV_VERTB_VFP) |
 390                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 391
 392                 /* We set up first field even mode for HDMI.  VEC's
 393                  * NTSC mode would want first field odd instead, once
 394                  * we support it (to do so, set ODD_FIRST and put the
 395                  * delay in VSYNCD_EVEN instead).
 396                  */
 397                 CRTC_WRITE(PV_V_CONTROL,
 398                            PV_VCONTROL_CONTINUOUS |
 399                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 400                            PV_VCONTROL_INTERLACE |
 401                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 402                                          PV_VCONTROL_ODD_DELAY));
 403                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 404         } else {
 405                 CRTC_WRITE(PV_V_CONTROL,
 406                            PV_VCONTROL_CONTINUOUS |
 407                            (is_dsi ? PV_VCONTROL_DSI : 0));
 408         }
 409
 410         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 411
 412         CRTC_WRITE(PV_CONTROL,
 413                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 414                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 415                                  PV_CONTROL_FIFO_LEVEL) |
 416                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 417                    PV_CONTROL_CLR_AT_START |
 418                    PV_CONTROL_TRIGGER_UNDERFLOW |
 419                    PV_CONTROL_WAIT_HSTART |
 420                    VC4_SET_FIELD(vc4_encoder->clock_select,
 421                                  PV_CONTROL_CLK_SELECT) |
 422                    PV_CONTROL_FIFO_CLR |
 423                    PV_CONTROL_EN);
 424 }
 425
 426 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 427 {
 428         struct drm_device *dev = crtc->dev;
 429         struct vc4_dev *vc4 = to_vc4_dev(dev);
 430         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 431         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 432         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 433         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 434         bool debug_dump_regs = false;
 435
 436         if (debug_dump_regs) {
 437                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 438                 vc4_crtc_dump_regs(vc4_crtc);
 439         }
 440
 441         if (vc4_crtc->channel == 2) {
 442                 u32 dispctrl;
 443                 u32 dsp3_mux;
 444
 445                 /*
 446                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 447                  * FIFO X'.
 448                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 449                  *
 450                  * DSP3 is connected to FIFO2 unless the transposer is
 451                  * enabled. In this case, FIFO 2 is directly accessed by the
 452                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 453                  * route.
 454                  */
 455                 if (vc4_state->feed_txp)
 456                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 457                 else
 458                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 459
 460                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 461                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 462                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 463         }
 464
 465         if (!vc4_state->feed_txp)
 466                 vc4_crtc_config_pv(crtc);
 467
 468         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 469                   SCALER_DISPBKGND_AUTOHS |
 470                   SCALER_DISPBKGND_GAMMA |
 471                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 472
 473         /* Reload the LUT, since the SRAMs would have been disabled if
 474          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 475          */
 476         vc4_crtc_lut_load(crtc);
 477
 478         if (debug_dump_regs) {
 479                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 480                 vc4_crtc_dump_regs(vc4_crtc);
 481         }
 482 }
 483
 484 static void require_hvs_enabled(struct drm_device *dev)
 485 {
 486         struct vc4_dev *vc4 = to_vc4_dev(dev);
 487
 488         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 489                      SCALER_DISPCTRL_ENABLE);
 490 }
 491
 492 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 493                                     struct drm_crtc_state *old_state)
 494 {
 495         struct drm_device *dev = crtc->dev;
 496         struct vc4_dev *vc4 = to_vc4_dev(dev);
 497         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 498         u32 chan = vc4_crtc->channel;
 499         int ret;
 500         require_hvs_enabled(dev);
 501
 502         /* Disable vblank irq handling before crtc is disabled. */
 503         drm_crtc_vblank_off(crtc);
 504
 505         CRTC_WRITE(PV_V_CONTROL,
 506                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 507         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 508         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 509
 510         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 511             SCALER_DISPCTRLX_ENABLE) {
 512                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 513                           SCALER_DISPCTRLX_RESET);
 514
 515                 /* While the docs say that reset is self-clearing, it
 516                  * seems it doesn't actually.
 517                  */
 518                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 519         }
 520
 521         /* Once we leave, the scaler should be disabled and its fifo empty. */
 522
 523         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 524
 525         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 526                                    SCALER_DISPSTATX_MODE) !=
 527                      SCALER_DISPSTATX_MODE_DISABLED);
 528
 529         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 530                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 531                      SCALER_DISPSTATX_EMPTY);
 532
 533         /*
 534          * Make sure we issue a vblank event after disabling the CRTC if
 535          * someone was waiting it.
 536          */
 537         if (crtc->state->event) {
 538                 unsigned long flags;
 539
 540                 spin_lock_irqsave(&dev->event_lock, flags);
 541                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 542                 crtc->state->event = NULL;
 543                 spin_unlock_irqrestore(&dev->event_lock, flags);
 544         }
 545 }
 546
 547 void vc4_crtc_txp_armed(struct drm_crtc_state *state)
 548 {
 549         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 550
 551         vc4_state->txp_armed = true;
 552 }
 553
 554 static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
 555 {
 556         struct drm_device *dev = crtc->dev;
 557         struct vc4_dev *vc4 = to_vc4_dev(dev);
 558         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 559         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 560
 561         if (crtc->state->event) {
 562                 unsigned long flags;
 563
 564                 crtc->state->event->pipe = drm_crtc_index(crtc);
 565
 566                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 567
 568                 spin_lock_irqsave(&dev->event_lock, flags);
 569
 570                 if (!vc4_state->feed_txp || vc4_state->txp_armed) {
 571                         vc4_crtc->event = crtc->state->event;
 572                         crtc->state->event = NULL;
 573                 }
 574
 575                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 576                           vc4_state->mm.start);
 577
 578                 spin_unlock_irqrestore(&dev->event_lock, flags);
 579         } else {
 580                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 581                           vc4_state->mm.start);
 582         }
 583 }
 584
 585 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 586                                    struct drm_crtc_state *old_state)
 587 {
 588         struct drm_device *dev = crtc->dev;
 589         struct vc4_dev *vc4 = to_vc4_dev(dev);
 590         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 591         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 592         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 593
 594         require_hvs_enabled(dev);
 595
 596         /* Enable vblank irq handling before crtc is started otherwise
 597          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 598          */
 599         drm_crtc_vblank_on(crtc);
 600         vc4_crtc_update_dlist(crtc);
 601
 602         /* Turn on the scaler, which will wait for vstart to start
 603          * compositing.
 604          * When feeding the transposer, we should operate in oneshot
 605          * mode.
 606          */
 607         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 608                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 609                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 610                   SCALER_DISPCTRLX_ENABLE |
 611                   (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
 612
 613         /* When feeding the transposer block the pixelvalve is unneeded and
 614          * should not be enabled.
 615          */
 616         if (!vc4_state->feed_txp)
 617                 CRTC_WRITE(PV_V_CONTROL,
 618                            CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 619 }
 620
 621 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 622                                                 const struct drm_display_mode *mode)
 623 {
 624         /* Do not allow doublescan modes from user space */
 625         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 626                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 627                               crtc->base.id);
 628                 return MODE_NO_DBLESCAN;
 629         }
 630
 631         return MODE_OK;
 632 }
 633
 634 void vc4_crtc_get_margins(struct drm_crtc_state *state,
 635                           unsigned int *left, unsigned int *right,
 636                           unsigned int *top, unsigned int *bottom)
 637 {
 638         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 639         struct drm_connector_state *conn_state;
 640         struct drm_connector *conn;
 641         int i;
 642
 643         *left = vc4_state->margins.left;
 644         *right = vc4_state->margins.right;
 645         *top = vc4_state->margins.top;
 646         *bottom = vc4_state->margins.bottom;
 647
 648         /* We have to interate over all new connector states because
 649          * vc4_crtc_get_margins() might be called before
 650          * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
 651          * might be outdated.
 652          */
 653         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 654                 if (conn_state->crtc != state->crtc)
 655                         continue;
 656
 657                 *left = conn_state->tv.margins.left;
 658                 *right = conn_state->tv.margins.right;
 659                 *top = conn_state->tv.margins.top;
 660                 *bottom = conn_state->tv.margins.bottom;
 661                 break;
 662         }
 663 }
 664
 665 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 666                                  struct drm_crtc_state *state)
 667 {
 668         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 669         struct drm_device *dev = crtc->dev;
 670         struct vc4_dev *vc4 = to_vc4_dev(dev);
 671         struct drm_plane *plane;
 672         unsigned long flags;
 673         const struct drm_plane_state *plane_state;
 674         struct drm_connector *conn;
 675         struct drm_connector_state *conn_state;
 676         u32 dlist_count = 0;
 677         int ret, i;
 678
 679         /* The pixelvalve can only feed one encoder (and encoders are
 680          * 1:1 with connectors.)
 681          */
 682         if (hweight32(state->connector_mask) > 1)
 683                 return -EINVAL;
 684
 685         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 686                 dlist_count += vc4_plane_dlist_size(plane_state);
 687
 688         dlist_count++; /* Account for SCALER_CTL0_END. */
 689
 690         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 691         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 692                                  dlist_count);
 693         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 694         if (ret)
 695                 return ret;
 696
 697         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 698                 if (conn_state->crtc != crtc)
 699                         continue;
 700
 701                 /* The writeback connector is implemented using the transposer
 702                  * block which is directly taking its data from the HVS FIFO.
 703                  */
 704                 if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) {
 705                         state->no_vblank = true;
 706                         vc4_state->feed_txp = true;
 707                 } else {
 708                         state->no_vblank = false;
 709                         vc4_state->feed_txp = false;
 710                 }
 711
 712                 vc4_state->margins.left = conn_state->tv.margins.left;
 713                 vc4_state->margins.right = conn_state->tv.margins.right;
 714                 vc4_state->margins.top = conn_state->tv.margins.top;
 715                 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
 716                 break;
 717         }
 718
 719         return 0;
 720 }
 721
 722 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 723                                   struct drm_crtc_state *old_state)
 724 {
 725         struct drm_device *dev = crtc->dev;
 726         struct vc4_dev *vc4 = to_vc4_dev(dev);
 727         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 728         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 729         struct drm_plane *plane;
 730         struct vc4_plane_state *vc4_plane_state;
 731         bool debug_dump_regs = false;
 732         bool enable_bg_fill = false;
 733         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 734         u32 __iomem *dlist_next = dlist_start;
 735
 736         if (debug_dump_regs) {
 737                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 738                 vc4_hvs_dump_state(dev);
 739         }
 740
 741         /* Copy all the active planes' dlist contents to the hardware dlist. */
 742         drm_atomic_crtc_for_each_plane(plane, crtc) {
 743                 /* Is this the first active plane? */
 744                 if (dlist_next == dlist_start) {
 745                         /* We need to enable background fill when a plane
 746                          * could be alpha blending from the background, i.e.
 747                          * where no other plane is underneath. It suffices to
 748                          * consider the first active plane here since we set
 749                          * needs_bg_fill such that either the first plane
 750                          * already needs it or all planes on top blend from
 751                          * the first or a lower plane.
 752                          */
 753                         vc4_plane_state = to_vc4_plane_state(plane->state);
 754                         enable_bg_fill = vc4_plane_state->needs_bg_fill;
 755                 }
 756
 757                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 758         }
 759
 760         writel(SCALER_CTL0_END, dlist_next);
 761         dlist_next++;
 762
 763         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 764
 765         if (enable_bg_fill)
 766                 /* This sets a black background color fill, as is the case
 767                  * with other DRM drivers.
 768                  */
 769                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 770                           HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
 771                           SCALER_DISPBKGND_FILL);
 772
 773         /* Only update DISPLIST if the CRTC was already running and is not
 774          * being disabled.
 775          * vc4_crtc_enable() takes care of updating the dlist just after
 776          * re-enabling VBLANK interrupts and before enabling the engine.
 777          * If the CRTC is being disabled, there's no point in updating this
 778          * information.
 779          */
 780         if (crtc->state->active && old_state->active)
 781                 vc4_crtc_update_dlist(crtc);
 782
 783         if (crtc->state->color_mgmt_changed) {
 784                 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
 785
 786                 if (crtc->state->gamma_lut) {
 787                         vc4_crtc_update_gamma_lut(crtc);
 788                         dispbkgndx |= SCALER_DISPBKGND_GAMMA;
 789                 } else {
 790                         /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
 791                          * in hardware, which is the same as a linear lut that
 792                          * DRM expects us to use in absence of a user lut.
 793                          */
 794                         dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
 795                 }
 796                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
 797         }
 798
 799         if (debug_dump_regs) {
 800                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 801                 vc4_hvs_dump_state(dev);
 802         }
 803 }
 804
 805 static int vc4_enable_vblank(struct drm_crtc *crtc)
 806 {
 807         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 808
 809         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 810
 811         return 0;
 812 }
 813
 814 static void vc4_disable_vblank(struct drm_crtc *crtc)
 815 {
 816         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 817
 818         CRTC_WRITE(PV_INTEN, 0);
 819 }
 820
 821 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 822 {
 823         struct drm_crtc *crtc = &vc4_crtc->base;
 824         struct drm_device *dev = crtc->dev;
 825         struct vc4_dev *vc4 = to_vc4_dev(dev);
 826         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 827         u32 chan = vc4_crtc->channel;
 828         unsigned long flags;
 829
 830         spin_lock_irqsave(&dev->event_lock, flags);
 831         if (vc4_crtc->event &&
 832             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
 833              vc4_state->feed_txp)) {
 834                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 835                 vc4_crtc->event = NULL;
 836                 drm_crtc_vblank_put(crtc);
 837         }
 838         spin_unlock_irqrestore(&dev->event_lock, flags);
 839 }
 840
 841 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 842 {
 843         crtc->t_vblank = ktime_get();
 844         drm_crtc_handle_vblank(&crtc->base);
 845         vc4_crtc_handle_page_flip(crtc);
 846 }
 847
 848 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 849 {
 850         struct vc4_crtc *vc4_crtc = data;
 851         u32 stat = CRTC_READ(PV_INTSTAT);
 852         irqreturn_t ret = IRQ_NONE;
 853
 854         if (stat & PV_INT_VFP_START) {
 855                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 856                 vc4_crtc_handle_vblank(vc4_crtc);
 857                 ret = IRQ_HANDLED;
 858         }
 859
 860         return ret;
 861 }
 862
 863 struct vc4_async_flip_state {
 864         struct drm_crtc *crtc;
 865         struct drm_framebuffer *fb;
 866         struct drm_framebuffer *old_fb;
 867         struct drm_pending_vblank_event *event;
 868
 869         struct vc4_seqno_cb cb;
 870 };
 871
 872 /* Called when the V3D execution for the BO being flipped to is done, so that
 873  * we can actually update the plane's address to point to it.
 874  */
 875 static void
 876 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 877 {
 878         struct vc4_async_flip_state *flip_state =
 879                 container_of(cb, struct vc4_async_flip_state, cb);
 880         struct drm_crtc *crtc = flip_state->crtc;
 881         struct drm_device *dev = crtc->dev;
 882         struct vc4_dev *vc4 = to_vc4_dev(dev);
 883         struct drm_plane *plane = crtc->primary;
 884
 885         vc4_plane_async_set_fb(plane, flip_state->fb);
 886         if (flip_state->event) {
 887                 unsigned long flags;
 888
 889                 spin_lock_irqsave(&dev->event_lock, flags);
 890                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 891                 spin_unlock_irqrestore(&dev->event_lock, flags);
 892         }
 893
 894         drm_crtc_vblank_put(crtc);
 895         drm_framebuffer_put(flip_state->fb);
 896
 897         /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
 898          * when the planes are updated through the async update path.
 899          * FIXME: we should move to generic async-page-flip when it's
 900          * available, so that we can get rid of this hand-made cleanup_fb()
 901          * logic.
 902          */
 903         if (flip_state->old_fb) {
 904                 struct drm_gem_cma_object *cma_bo;
 905                 struct vc4_bo *bo;
 906
 907                 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
 908                 bo = to_vc4_bo(&cma_bo->base);
 909                 vc4_bo_dec_usecnt(bo);
 910                 drm_framebuffer_put(flip_state->old_fb);
 911         }
 912
 913         kfree(flip_state);
 914
 915         up(&vc4->async_modeset);
 916 }
 917
 918 /* Implements async (non-vblank-synced) page flips.
 919  *
 920  * The page flip ioctl needs to return immediately, so we grab the
 921  * modeset semaphore on the pipe, and queue the address update for
 922  * when V3D is done with the BO being flipped to.
 923  */
 924 static int vc4_async_page_flip(struct drm_crtc *crtc,
 925                                struct drm_framebuffer *fb,
 926                                struct drm_pending_vblank_event *event,
 927                                uint32_t flags)
 928 {
 929         struct drm_device *dev = crtc->dev;
 930         struct vc4_dev *vc4 = to_vc4_dev(dev);
 931         struct drm_plane *plane = crtc->primary;
 932         int ret = 0;
 933         struct vc4_async_flip_state *flip_state;
 934         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 935         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 936
 937         /* Increment the BO usecnt here, so that we never end up with an
 938          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
 939          * plane is later updated through the non-async path.
 940          * FIXME: we should move to generic async-page-flip when it's
 941          * available, so that we can get rid of this hand-made prepare_fb()
 942          * logic.
 943          */
 944         ret = vc4_bo_inc_usecnt(bo);
 945         if (ret)
 946                 return ret;
 947
 948         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 949         if (!flip_state) {
 950                 vc4_bo_dec_usecnt(bo);
 951                 return -ENOMEM;
 952         }
 953
 954         drm_framebuffer_get(fb);
 955         flip_state->fb = fb;
 956         flip_state->crtc = crtc;
 957         flip_state->event = event;
 958
 959         /* Make sure all other async modesetes have landed. */
 960         ret = down_interruptible(&vc4->async_modeset);
 961         if (ret) {
 962                 drm_framebuffer_put(fb);
 963                 vc4_bo_dec_usecnt(bo);
 964                 kfree(flip_state);
 965                 return ret;
 966         }
 967
 968         /* Save the current FB before it's replaced by the new one in
 969          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 970          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 971          * it consistent.
 972          * FIXME: we should move to generic async-page-flip when it's
 973          * available, so that we can get rid of this hand-made cleanup_fb()
 974          * logic.
 975          */
 976         flip_state->old_fb = plane->state->fb;
 977         if (flip_state->old_fb)
 978                 drm_framebuffer_get(flip_state->old_fb);
 979
 980         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 981
 982         /* Immediately update the plane's legacy fb pointer, so that later
 983          * modeset prep sees the state that will be present when the semaphore
 984          * is released.
 985          */
 986         drm_atomic_set_fb_for_plane(plane->state, fb);
 987
 988         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 989                            vc4_async_page_flip_complete);
 990
 991         /* Driver takes ownership of state on successful async commit. */
 992         return 0;
 993 }
 994
 995 static int vc4_page_flip(struct drm_crtc *crtc,
 996                          struct drm_framebuffer *fb,
 997                          struct drm_pending_vblank_event *event,
 998                          uint32_t flags,
 999                          struct drm_modeset_acquire_ctx *ctx)
1000 {
1001         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
1002                 return vc4_async_page_flip(crtc, fb, event, flags);
1003         else
1004                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
1005 }
1006
1007 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
1008 {
1009         struct vc4_crtc_state *vc4_state, *old_vc4_state;
1010
1011         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
1012         if (!vc4_state)
1013                 return NULL;
1014
1015         old_vc4_state = to_vc4_crtc_state(crtc->state);
1016         vc4_state->feed_txp = old_vc4_state->feed_txp;
1017         vc4_state->margins = old_vc4_state->margins;
1018
1019         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
1020         return &vc4_state->base;
1021 }
1022
1023 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
1024                                    struct drm_crtc_state *state)
1025 {
1026         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
1027         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
1028
1029         if (vc4_state->mm.allocated) {
1030                 unsigned long flags;
1031
1032                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1033                 drm_mm_remove_node(&vc4_state->mm);
1034                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1035
1036         }
1037
1038         drm_atomic_helper_crtc_destroy_state(crtc, state);
1039 }
1040
1041 static void
1042 vc4_crtc_reset(struct drm_crtc *crtc)
1043 {
1044         if (crtc->state)
1045                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1046
1047         crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
1048         if (crtc->state)
1049                 crtc->state->crtc = crtc;
1050 }
1051
1052 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1053         .set_config = drm_atomic_helper_set_config,
1054         .destroy = vc4_crtc_destroy,
1055         .page_flip = vc4_page_flip,
1056         .set_property = NULL,
1057         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1058         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1059         .reset = vc4_crtc_reset,
1060         .atomic_duplicate_state = vc4_crtc_duplicate_state,
1061         .atomic_destroy_state = vc4_crtc_destroy_state,
1062         .gamma_set = drm_atomic_helper_legacy_gamma_set,
1063         .enable_vblank = vc4_enable_vblank,
1064         .disable_vblank = vc4_disable_vblank,
1065 };
1066
1067 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1068         .mode_set_nofb = vc4_crtc_mode_set_nofb,
1069         .mode_valid = vc4_crtc_mode_valid,
1070         .atomic_check = vc4_crtc_atomic_check,
1071         .atomic_flush = vc4_crtc_atomic_flush,
1072         .atomic_enable = vc4_crtc_atomic_enable,
1073         .atomic_disable = vc4_crtc_atomic_disable,
1074 };
1075
1076 static const struct vc4_crtc_data pv0_data = {
1077         .hvs_channel = 0,
1078         .encoder_types = {
1079                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1080                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1081         },
1082 };
1083
1084 static const struct vc4_crtc_data pv1_data = {
1085         .hvs_channel = 2,
1086         .encoder_types = {
1087                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1088                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1089         },
1090 };
1091
1092 static const struct vc4_crtc_data pv2_data = {
1093         .hvs_channel = 1,
1094         .encoder_types = {
1095                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
1096                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1097         },
1098 };
1099
1100 static const struct of_device_id vc4_crtc_dt_match[] = {
1101         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
1102         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
1103         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
1104         {}
1105 };
1106
1107 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1108                                         struct drm_crtc *crtc)
1109 {
1110         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1111         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1112         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1113         struct drm_encoder *encoder;
1114
1115         drm_for_each_encoder(encoder, drm) {
1116                 struct vc4_encoder *vc4_encoder;
1117                 int i;
1118
1119                 /* HVS FIFO2 can feed the TXP IP. */
1120                 if (crtc_data->hvs_channel == 2 &&
1121                     encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1122                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
1123                         continue;
1124                 }
1125
1126                 vc4_encoder = to_vc4_encoder(encoder);
1127                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1128                         if (vc4_encoder->type == encoder_types[i]) {
1129                                 vc4_encoder->clock_select = i;
1130                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1131                                 break;
1132                         }
1133                 }
1134         }
1135 }
1136
1137 static void
1138 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1139 {
1140         struct drm_device *drm = vc4_crtc->base.dev;
1141         struct vc4_dev *vc4 = to_vc4_dev(drm);
1142         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1143         /* Top/base are supposed to be 4-pixel aligned, but the
1144          * Raspberry Pi firmware fills the low bits (which are
1145          * presumably ignored).
1146          */
1147         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1148         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1149
1150         vc4_crtc->cob_size = top - base + 4;
1151 }
1152
1153 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1154 {
1155         struct platform_device *pdev = to_platform_device(dev);
1156         struct drm_device *drm = dev_get_drvdata(master);
1157         struct vc4_crtc *vc4_crtc;
1158         struct drm_crtc *crtc;
1159         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1160         const struct of_device_id *match;
1161         int ret, i;
1162
1163         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1164         if (!vc4_crtc)
1165                 return -ENOMEM;
1166         crtc = &vc4_crtc->base;
1167
1168         match = of_match_device(vc4_crtc_dt_match, dev);
1169         if (!match)
1170                 return -ENODEV;
1171         vc4_crtc->data = match->data;
1172
1173         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1174         if (IS_ERR(vc4_crtc->regs))
1175                 return PTR_ERR(vc4_crtc->regs);
1176
1177         /* For now, we create just the primary and the legacy cursor
1178          * planes.  We should be able to stack more planes on easily,
1179          * but to do that we would need to compute the bandwidth
1180          * requirement of the plane configuration, and reject ones
1181          * that will take too much.
1182          */
1183         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1184         if (IS_ERR(primary_plane)) {
1185                 dev_err(dev, "failed to construct primary plane\n");
1186                 ret = PTR_ERR(primary_plane);
1187                 goto err;
1188         }
1189
1190         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1191                                   &vc4_crtc_funcs, NULL);
1192         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1193         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1194         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1195         drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1196
1197         /* We support CTM, but only for one CRTC at a time. It's therefore
1198          * implemented as private driver state in vc4_kms, not here.
1199          */
1200         drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1201
1202         /* Set up some arbitrary number of planes.  We're not limited
1203          * by a set number of physical registers, just the space in
1204          * the HVS (16k) and how small an plane can be (28 bytes).
1205          * However, each plane we set up takes up some memory, and
1206          * increases the cost of looping over planes, which atomic
1207          * modesetting does quite a bit.  As a result, we pick a
1208          * modest number of planes to expose, that should hopefully
1209          * still cover any sane usecase.
1210          */
1211         for (i = 0; i < 8; i++) {
1212                 struct drm_plane *plane =
1213                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1214
1215                 if (IS_ERR(plane))
1216                         continue;
1217
1218                 plane->possible_crtcs = drm_crtc_mask(crtc);
1219         }
1220
1221         /* Set up the legacy cursor after overlay initialization,
1222          * since we overlay planes on the CRTC in the order they were
1223          * initialized.
1224          */
1225         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1226         if (!IS_ERR(cursor_plane)) {
1227                 cursor_plane->possible_crtcs = drm_crtc_mask(crtc);
1228                 crtc->cursor = cursor_plane;
1229         }
1230
1231         vc4_crtc_get_cob_allocation(vc4_crtc);
1232
1233         CRTC_WRITE(PV_INTEN, 0);
1234         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1235         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1236                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1237         if (ret)
1238                 goto err_destroy_planes;
1239
1240         vc4_set_crtc_possible_masks(drm, crtc);
1241
1242         for (i = 0; i < crtc->gamma_size; i++) {
1243                 vc4_crtc->lut_r[i] = i;
1244                 vc4_crtc->lut_g[i] = i;
1245                 vc4_crtc->lut_b[i] = i;
1246         }
1247
1248         platform_set_drvdata(pdev, vc4_crtc);
1249
1250         return 0;
1251
1252 err_destroy_planes:
1253         list_for_each_entry_safe(destroy_plane, temp,
1254                                  &drm->mode_config.plane_list, head) {
1255                 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1256                     destroy_plane->funcs->destroy(destroy_plane);
1257         }
1258 err:
1259         return ret;
1260 }
1261
1262 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1263                             void *data)
1264 {
1265         struct platform_device *pdev = to_platform_device(dev);
1266         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1267
1268         vc4_crtc_destroy(&vc4_crtc->base);
1269
1270         CRTC_WRITE(PV_INTEN, 0);
1271
1272         platform_set_drvdata(pdev, NULL);
1273 }
1274
1275 static const struct component_ops vc4_crtc_ops = {
1276         .bind   = vc4_crtc_bind,
1277         .unbind = vc4_crtc_unbind,
1278 };
1279
1280 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1281 {
1282         return component_add(&pdev->dev, &vc4_crtc_ops);
1283 }
1284
1285 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1286 {
1287         component_del(&pdev->dev, &vc4_crtc_ops);
1288         return 0;
1289 }
1290
1291 struct platform_driver vc4_crtc_driver = {
1292         .probe = vc4_crtc_dev_probe,
1293         .remove = vc4_crtc_dev_remove,
1294         .driver = {
1295                 .name = "vc4_crtc",
1296                 .of_match_table = vc4_crtc_dt_match,
1297         },
1298 };