drivers/gpu/drm/vc4/vc4_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 CRTC module
   8  *
   9  * In VC4, the Pixel Valve is what most closely corresponds to the
  10  * DRM's concept of a CRTC.  The PV generates video timings from the
  11  * encoder's clock plus its configuration.  It pulls scaled pixels from
  12  * the HVS at that timing, and feeds it to the encoder.
  13  *
  14  * However, the DRM CRTC also collects the configuration of all the
  15  * DRM planes attached to it.  As a result, the CRTC is also
  16  * responsible for writing the display list for the HVS channel that
  17  * the CRTC will use.
  18  *
  19  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  20  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  21  * image domain can feed either HDMI or the SDTV controller.  The
  22  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  23  * SDTV, etc.) according to which output type is chosen in the mux.
  24  *
  25  * For power management, the pixel valve's registers are all clocked
  26  * by the AXI clock, while the timings and FIFOs make use of the
  27  * output-specific clock.  Since the encoders also directly consume
  28  * the CPRMAN clocks, and know what timings they need, they are the
  29  * ones that set the clock.
  30  */
  31
  32 #include <linux/clk.h>
  33 #include <linux/component.h>
  34 #include <linux/of_device.h>
  35
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_atomic_uapi.h>
  39 #include <drm/drm_fb_cma_helper.h>
  40 #include <drm/drm_print.h>
  41 #include <drm/drm_probe_helper.h>
  42 #include <drm/drm_vblank.h>
  43
  44 #include "vc4_drv.h"
  45 #include "vc4_regs.h"
  46
  47 #define HVS_FIFO_LATENCY_PIX    6
  48
  49 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  50 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  51
  52 static const struct debugfs_reg32 crtc_regs[] = {
  53         VC4_REG32(PV_CONTROL),
  54         VC4_REG32(PV_V_CONTROL),
  55         VC4_REG32(PV_VSYNCD_EVEN),
  56         VC4_REG32(PV_HORZA),
  57         VC4_REG32(PV_HORZB),
  58         VC4_REG32(PV_VERTA),
  59         VC4_REG32(PV_VERTB),
  60         VC4_REG32(PV_VERTA_EVEN),
  61         VC4_REG32(PV_VERTB_EVEN),
  62         VC4_REG32(PV_INTEN),
  63         VC4_REG32(PV_INTSTAT),
  64         VC4_REG32(PV_STAT),
  65         VC4_REG32(PV_HACT_ACT),
  66 };
  67
  68 static unsigned int
  69 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
  70 {
  71         u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
  72         /* Top/base are supposed to be 4-pixel aligned, but the
  73          * Raspberry Pi firmware fills the low bits (which are
  74          * presumably ignored).
  75          */
  76         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
  77         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
  78
  79         return top - base + 4;
  80 }
  81
  82 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
  83                                           bool in_vblank_irq,
  84                                           int *vpos, int *hpos,
  85                                           ktime_t *stime, ktime_t *etime,
  86                                           const struct drm_display_mode *mode)
  87 {
  88         struct drm_device *dev = crtc->dev;
  89         struct vc4_dev *vc4 = to_vc4_dev(dev);
  90         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  91         struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
  92         unsigned int cob_size;
  93         u32 val;
  94         int fifo_lines;
  95         int vblank_lines;
  96         bool ret = false;
  97
  98         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
  99
 100         /* Get optional system timestamp before query. */
 101         if (stime)
 102                 *stime = ktime_get();
 103
 104         /*
 105          * Read vertical scanline which is currently composed for our
 106          * pixelvalve by the HVS, and also the scaler status.
 107          */
 108         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
 109
 110         /* Get optional system timestamp after query. */
 111         if (etime)
 112                 *etime = ktime_get();
 113
 114         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 115
 116         /* Vertical position of hvs composed scanline. */
 117         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 118         *hpos = 0;
 119
 120         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 121                 *vpos /= 2;
 122
 123                 /* Use hpos to correct for field offset in interlaced mode. */
 124                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 125                         *hpos += mode->crtc_htotal / 2;
 126         }
 127
 128         cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel);
 129         /* This is the offset we need for translating hvs -> pv scanout pos. */
 130         fifo_lines = cob_size / mode->crtc_hdisplay;
 131
 132         if (fifo_lines > 0)
 133                 ret = true;
 134
 135         /* HVS more than fifo_lines into frame for compositing? */
 136         if (*vpos > fifo_lines) {
 137                 /*
 138                  * We are in active scanout and can get some meaningful results
 139                  * from HVS. The actual PV scanout can not trail behind more
 140                  * than fifo_lines as that is the fifo's capacity. Assume that
 141                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 142                  * refilling the fifo and PV consuming from the fifo, ie.
 143                  * whenever the PV consumes and frees up a scanline in the
 144                  * fifo, the HVS will immediately refill it, therefore
 145                  * incrementing vpos. Therefore we choose HVS read position -
 146                  * fifo size in scanlines as a estimate of the real scanout
 147                  * position of the PV.
 148                  */
 149                 *vpos -= fifo_lines + 1;
 150
 151                 return ret;
 152         }
 153
 154         /*
 155          * Less: This happens when we are in vblank and the HVS, after getting
 156          * the VSTART restart signal from the PV, just started refilling its
 157          * fifo with new lines from the top-most lines of the new framebuffers.
 158          * The PV does not scan out in vblank, so does not remove lines from
 159          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 160          * We can't get meaningful readings wrt. scanline position of the PV
 161          * and need to make things up in a approximative but consistent way.
 162          */
 163         vblank_lines = mode->vtotal - mode->vdisplay;
 164
 165         if (in_vblank_irq) {
 166                 /*
 167                  * Assume the irq handler got called close to first
 168                  * line of vblank, so PV has about a full vblank
 169                  * scanlines to go, and as a base timestamp use the
 170                  * one taken at entry into vblank irq handler, so it
 171                  * is not affected by random delays due to lock
 172                  * contention on event_lock or vblank_time lock in
 173                  * the core.
 174                  */
 175                 *vpos = -vblank_lines;
 176
 177                 if (stime)
 178                         *stime = vc4_crtc->t_vblank;
 179                 if (etime)
 180                         *etime = vc4_crtc->t_vblank;
 181
 182                 /*
 183                  * If the HVS fifo is not yet full then we know for certain
 184                  * we are at the very beginning of vblank, as the hvs just
 185                  * started refilling, and the stime and etime timestamps
 186                  * truly correspond to start of vblank.
 187                  *
 188                  * Unfortunately there's no way to report this to upper levels
 189                  * and make it more useful.
 190                  */
 191         } else {
 192                 /*
 193                  * No clue where we are inside vblank. Return a vpos of zero,
 194                  * which will cause calling code to just return the etime
 195                  * timestamp uncorrected. At least this is no worse than the
 196                  * standard fallback.
 197                  */
 198                 *vpos = 0;
 199         }
 200
 201         return ret;
 202 }
 203
 204 void vc4_crtc_destroy(struct drm_crtc *crtc)
 205 {
 206         drm_crtc_cleanup(crtc);
 207 }
 208
 209 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
 210 {
 211         const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
 212         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 213         struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
 214         u32 fifo_len_bytes = pv_data->fifo_depth;
 215
 216         /*
 217          * Pixels are pulled from the HVS if the number of bytes is
 218          * lower than the FIFO full level.
 219          *
 220          * The latency of the pixel fetch mechanism is 6 pixels, so we
 221          * need to convert those 6 pixels in bytes, depending on the
 222          * format, and then subtract that from the length of the FIFO
 223          * to make sure we never end up in a situation where the FIFO
 224          * is full.
 225          */
 226         switch (format) {
 227         case PV_CONTROL_FORMAT_DSIV_16:
 228         case PV_CONTROL_FORMAT_DSIC_16:
 229                 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
 230         case PV_CONTROL_FORMAT_DSIV_18:
 231                 return fifo_len_bytes - 14;
 232         case PV_CONTROL_FORMAT_24:
 233         case PV_CONTROL_FORMAT_DSIV_24:
 234         default:
 235                 /*
 236                  * For some reason, the pixelvalve4 doesn't work with
 237                  * the usual formula and will only work with 32.
 238                  */
 239                 if (crtc_data->hvs_output == 5)
 240                         return 32;
 241
 242                 /*
 243                  * It looks like in some situations, we will overflow
 244                  * the PixelValve FIFO (with the bit 10 of PV stat being
 245                  * set) and stall the HVS / PV, eventually resulting in
 246                  * a page flip timeout.
 247                  *
 248                  * Displaying the video overlay during a playback with
 249                  * Kodi on an RPi3 seems to be a great solution with a
 250                  * failure rate around 50%.
 251                  *
 252                  * Removing 1 from the FIFO full level however
 253                  * seems to completely remove that issue.
 254                  */
 255                 if (!vc4->hvs->hvs5)
 256                         return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
 257
 258                 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
 259         }
 260 }
 261
 262 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
 263                                              u32 format)
 264 {
 265         u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
 266         u32 ret = 0;
 267
 268         ret |= VC4_SET_FIELD((level >> 6),
 269                              PV5_CONTROL_FIFO_LEVEL_HIGH);
 270
 271         return ret | VC4_SET_FIELD(level & 0x3f,
 272                                    PV_CONTROL_FIFO_LEVEL);
 273 }
 274
 275 /*
 276  * Returns the encoder attached to the CRTC.
 277  *
 278  * VC4 can only scan out to one encoder at a time, while the DRM core
 279  * allows drivers to push pixels to more than one encoder from the
 280  * same CRTC.
 281  */
 282 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
 283                                                 struct drm_atomic_state *state,
 284                                                 struct drm_connector_state *(*get_state)(struct drm_atomic_state *state,
 285                                                                                          struct drm_connector *connector))
 286 {
 287         struct drm_connector *connector;
 288         struct drm_connector_list_iter conn_iter;
 289
 290         drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 291         drm_for_each_connector_iter(connector, &conn_iter) {
 292                 struct drm_connector_state *conn_state = get_state(state, connector);
 293
 294                 if (!conn_state)
 295                         continue;
 296
 297                 if (conn_state->crtc == crtc) {
 298                         drm_connector_list_iter_end(&conn_iter);
 299                         return connector->encoder;
 300                 }
 301         }
 302         drm_connector_list_iter_end(&conn_iter);
 303
 304         return NULL;
 305 }
 306
 307 static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
 308 {
 309         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 310
 311         /* The PV needs to be disabled before it can be flushed */
 312         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
 313         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
 314 }
 315
 316 static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_atomic_state *state)
 317 {
 318         struct drm_device *dev = crtc->dev;
 319         struct vc4_dev *vc4 = to_vc4_dev(dev);
 320         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,
 321                                                            drm_atomic_get_new_connector_state);
 322         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 323         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 324         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 325         struct drm_crtc_state *crtc_state = crtc->state;
 326         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 327         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 328         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 329         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 330                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 331         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 332         u8 ppc = pv_data->pixels_per_clock;
 333         bool debug_dump_regs = false;
 334
 335         if (debug_dump_regs) {
 336                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 337                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
 338                          drm_crtc_index(crtc));
 339                 drm_print_regset32(&p, &vc4_crtc->regset);
 340         }
 341
 342         vc4_crtc_pixelvalve_reset(crtc);
 343
 344         CRTC_WRITE(PV_HORZA,
 345                    VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
 346                                  PV_HORZA_HBP) |
 347                    VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
 348                                  PV_HORZA_HSYNC));
 349
 350         CRTC_WRITE(PV_HORZB,
 351                    VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
 352                                  PV_HORZB_HFP) |
 353                    VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
 354                                  PV_HORZB_HACTIVE));
 355
 356         CRTC_WRITE(PV_VERTA,
 357                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 358                                  PV_VERTA_VBP) |
 359                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 360                                  PV_VERTA_VSYNC));
 361         CRTC_WRITE(PV_VERTB,
 362                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 363                                  PV_VERTB_VFP) |
 364                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 365
 366         if (interlace) {
 367                 CRTC_WRITE(PV_VERTA_EVEN,
 368                            VC4_SET_FIELD(mode->crtc_vtotal -
 369                                          mode->crtc_vsync_end - 1,
 370                                          PV_VERTA_VBP) |
 371                            VC4_SET_FIELD(mode->crtc_vsync_end -
 372                                          mode->crtc_vsync_start,
 373                                          PV_VERTA_VSYNC));
 374                 CRTC_WRITE(PV_VERTB_EVEN,
 375                            VC4_SET_FIELD(mode->crtc_vsync_start -
 376                                          mode->crtc_vdisplay,
 377                                          PV_VERTB_VFP) |
 378                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 379
 380                 /* We set up first field even mode for HDMI.  VEC's
 381                  * NTSC mode would want first field odd instead, once
 382                  * we support it (to do so, set ODD_FIRST and put the
 383                  * delay in VSYNCD_EVEN instead).
 384                  */
 385                 CRTC_WRITE(PV_V_CONTROL,
 386                            PV_VCONTROL_CONTINUOUS |
 387                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 388                            PV_VCONTROL_INTERLACE |
 389                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 390                                          PV_VCONTROL_ODD_DELAY));
 391                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 392         } else {
 393                 CRTC_WRITE(PV_V_CONTROL,
 394                            PV_VCONTROL_CONTINUOUS |
 395                            (is_dsi ? PV_VCONTROL_DSI : 0));
 396         }
 397
 398         if (is_dsi)
 399                 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 400
 401         if (vc4->hvs->hvs5)
 402                 CRTC_WRITE(PV_MUX_CFG,
 403                            VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
 404                                          PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
 405
 406         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
 407                    vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
 408                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 409                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 410                    PV_CONTROL_CLR_AT_START |
 411                    PV_CONTROL_TRIGGER_UNDERFLOW |
 412                    PV_CONTROL_WAIT_HSTART |
 413                    VC4_SET_FIELD(vc4_encoder->clock_select,
 414                                  PV_CONTROL_CLK_SELECT));
 415
 416         if (debug_dump_regs) {
 417                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 418                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
 419                          drm_crtc_index(crtc));
 420                 drm_print_regset32(&p, &vc4_crtc->regset);
 421         }
 422 }
 423
 424 static void require_hvs_enabled(struct drm_device *dev)
 425 {
 426         struct vc4_dev *vc4 = to_vc4_dev(dev);
 427
 428         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 429                      SCALER_DISPCTRL_ENABLE);
 430 }
 431
 432 static int vc4_crtc_disable(struct drm_crtc *crtc,
 433                             struct drm_encoder *encoder,
 434                             struct drm_atomic_state *state,
 435                             unsigned int channel)
 436 {
 437         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 438         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 439         struct drm_device *dev = crtc->dev;
 440         int ret;
 441
 442         CRTC_WRITE(PV_V_CONTROL,
 443                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 444         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 445         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 446
 447         /*
 448          * This delay is needed to avoid to get a pixel stuck in an
 449          * unflushable FIFO between the pixelvalve and the HDMI
 450          * controllers on the BCM2711.
 451          *
 452          * Timing is fairly sensitive here, so mdelay is the safest
 453          * approach.
 454          *
 455          * If it was to be reworked, the stuck pixel happens on a
 456          * BCM2711 when changing mode with a good probability, so a
 457          * script that changes mode on a regular basis should trigger
 458          * the bug after less than 10 attempts. It manifests itself with
 459          * every pixels being shifted by one to the right, and thus the
 460          * last pixel of a line actually being displayed as the first
 461          * pixel on the next line.
 462          */
 463         mdelay(20);
 464
 465         if (vc4_encoder && vc4_encoder->post_crtc_disable)
 466                 vc4_encoder->post_crtc_disable(encoder, state);
 467
 468         vc4_crtc_pixelvalve_reset(crtc);
 469         vc4_hvs_stop_channel(dev, channel);
 470
 471         if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
 472                 vc4_encoder->post_crtc_powerdown(encoder, state);
 473
 474         return 0;
 475 }
 476
 477 static struct drm_encoder *vc4_crtc_get_encoder_by_type(struct drm_crtc *crtc,
 478                                                         enum vc4_encoder_type type)
 479 {
 480         struct drm_encoder *encoder;
 481
 482         drm_for_each_encoder(encoder, crtc->dev) {
 483                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 484
 485                 if (vc4_encoder->type == type)
 486                         return encoder;
 487         }
 488
 489         return NULL;
 490 }
 491
 492 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
 493 {
 494         struct drm_device *drm = crtc->dev;
 495         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 496         enum vc4_encoder_type encoder_type;
 497         const struct vc4_pv_data *pv_data;
 498         struct drm_encoder *encoder;
 499         unsigned encoder_sel;
 500         int channel;
 501
 502         if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 503                                       "brcm,bcm2711-pixelvalve2") ||
 504               of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 505                                       "brcm,bcm2711-pixelvalve4")))
 506                 return 0;
 507
 508         if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
 509                 return 0;
 510
 511         if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
 512                 return 0;
 513
 514         channel = vc4_hvs_get_fifo_from_output(drm, vc4_crtc->data->hvs_output);
 515         if (channel < 0)
 516                 return 0;
 517
 518         encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);
 519         if (WARN_ON(encoder_sel != 0))
 520                 return 0;
 521
 522         pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 523         encoder_type = pv_data->encoder_types[encoder_sel];
 524         encoder = vc4_crtc_get_encoder_by_type(crtc, encoder_type);
 525         if (WARN_ON(!encoder))
 526                 return 0;
 527
 528         return vc4_crtc_disable(crtc, encoder, NULL, channel);
 529 }
 530
 531 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 532                                     struct drm_atomic_state *state)
 533 {
 534         struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
 535                                                                          crtc);
 536         struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);
 537         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,
 538                                                            drm_atomic_get_old_connector_state);
 539         struct drm_device *dev = crtc->dev;
 540
 541         require_hvs_enabled(dev);
 542
 543         /* Disable vblank irq handling before crtc is disabled. */
 544         drm_crtc_vblank_off(crtc);
 545
 546         vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel);
 547
 548         /*
 549          * Make sure we issue a vblank event after disabling the CRTC if
 550          * someone was waiting it.
 551          */
 552         if (crtc->state->event) {
 553                 unsigned long flags;
 554
 555                 spin_lock_irqsave(&dev->event_lock, flags);
 556                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 557                 crtc->state->event = NULL;
 558                 spin_unlock_irqrestore(&dev->event_lock, flags);
 559         }
 560 }
 561
 562 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 563                                    struct drm_atomic_state *state)
 564 {
 565         struct drm_device *dev = crtc->dev;
 566         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 567         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,
 568                                                            drm_atomic_get_new_connector_state);
 569         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 570
 571         require_hvs_enabled(dev);
 572
 573         /* Enable vblank irq handling before crtc is started otherwise
 574          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 575          */
 576         drm_crtc_vblank_on(crtc);
 577
 578         vc4_hvs_atomic_enable(crtc, state);
 579
 580         if (vc4_encoder->pre_crtc_configure)
 581                 vc4_encoder->pre_crtc_configure(encoder, state);
 582
 583         vc4_crtc_config_pv(crtc, state);
 584
 585         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
 586
 587         if (vc4_encoder->pre_crtc_enable)
 588                 vc4_encoder->pre_crtc_enable(encoder, state);
 589
 590         /* When feeding the transposer block the pixelvalve is unneeded and
 591          * should not be enabled.
 592          */
 593         CRTC_WRITE(PV_V_CONTROL,
 594                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 595
 596         if (vc4_encoder->post_crtc_enable)
 597                 vc4_encoder->post_crtc_enable(encoder, state);
 598 }
 599
 600 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 601                                                 const struct drm_display_mode *mode)
 602 {
 603         /* Do not allow doublescan modes from user space */
 604         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 605                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 606                               crtc->base.id);
 607                 return MODE_NO_DBLESCAN;
 608         }
 609
 610         return MODE_OK;
 611 }
 612
 613 void vc4_crtc_get_margins(struct drm_crtc_state *state,
 614                           unsigned int *left, unsigned int *right,
 615                           unsigned int *top, unsigned int *bottom)
 616 {
 617         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 618         struct drm_connector_state *conn_state;
 619         struct drm_connector *conn;
 620         int i;
 621
 622         *left = vc4_state->margins.left;
 623         *right = vc4_state->margins.right;
 624         *top = vc4_state->margins.top;
 625         *bottom = vc4_state->margins.bottom;
 626
 627         /* We have to interate over all new connector states because
 628          * vc4_crtc_get_margins() might be called before
 629          * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
 630          * might be outdated.
 631          */
 632         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 633                 if (conn_state->crtc != state->crtc)
 634                         continue;
 635
 636                 *left = conn_state->tv.margins.left;
 637                 *right = conn_state->tv.margins.right;
 638                 *top = conn_state->tv.margins.top;
 639                 *bottom = conn_state->tv.margins.bottom;
 640                 break;
 641         }
 642 }
 643
 644 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 645                                  struct drm_atomic_state *state)
 646 {
 647         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 648                                                                           crtc);
 649         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 650         struct drm_connector *conn;
 651         struct drm_connector_state *conn_state;
 652         int ret, i;
 653
 654         ret = vc4_hvs_atomic_check(crtc, state);
 655         if (ret)
 656                 return ret;
 657
 658         for_each_new_connector_in_state(state, conn, conn_state,
 659                                         i) {
 660                 if (conn_state->crtc != crtc)
 661                         continue;
 662
 663                 vc4_state->margins.left = conn_state->tv.margins.left;
 664                 vc4_state->margins.right = conn_state->tv.margins.right;
 665                 vc4_state->margins.top = conn_state->tv.margins.top;
 666                 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
 667                 break;
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int vc4_enable_vblank(struct drm_crtc *crtc)
 674 {
 675         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 676
 677         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 678
 679         return 0;
 680 }
 681
 682 static void vc4_disable_vblank(struct drm_crtc *crtc)
 683 {
 684         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 685
 686         CRTC_WRITE(PV_INTEN, 0);
 687 }
 688
 689 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 690 {
 691         struct drm_crtc *crtc = &vc4_crtc->base;
 692         struct drm_device *dev = crtc->dev;
 693         struct vc4_dev *vc4 = to_vc4_dev(dev);
 694         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 695         u32 chan = vc4_state->assigned_channel;
 696         unsigned long flags;
 697
 698         spin_lock_irqsave(&dev->event_lock, flags);
 699         if (vc4_crtc->event &&
 700             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
 701              vc4_state->feed_txp)) {
 702                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 703                 vc4_crtc->event = NULL;
 704                 drm_crtc_vblank_put(crtc);
 705
 706                 /* Wait for the page flip to unmask the underrun to ensure that
 707                  * the display list was updated by the hardware. Before that
 708                  * happens, the HVS will be using the previous display list with
 709                  * the CRTC and encoder already reconfigured, leading to
 710                  * underruns. This can be seen when reconfiguring the CRTC.
 711                  */
 712                 vc4_hvs_unmask_underrun(dev, chan);
 713         }
 714         spin_unlock_irqrestore(&dev->event_lock, flags);
 715 }
 716
 717 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 718 {
 719         crtc->t_vblank = ktime_get();
 720         drm_crtc_handle_vblank(&crtc->base);
 721         vc4_crtc_handle_page_flip(crtc);
 722 }
 723
 724 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 725 {
 726         struct vc4_crtc *vc4_crtc = data;
 727         u32 stat = CRTC_READ(PV_INTSTAT);
 728         irqreturn_t ret = IRQ_NONE;
 729
 730         if (stat & PV_INT_VFP_START) {
 731                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 732                 vc4_crtc_handle_vblank(vc4_crtc);
 733                 ret = IRQ_HANDLED;
 734         }
 735
 736         return ret;
 737 }
 738
 739 struct vc4_async_flip_state {
 740         struct drm_crtc *crtc;
 741         struct drm_framebuffer *fb;
 742         struct drm_framebuffer *old_fb;
 743         struct drm_pending_vblank_event *event;
 744
 745         struct vc4_seqno_cb cb;
 746 };
 747
 748 /* Called when the V3D execution for the BO being flipped to is done, so that
 749  * we can actually update the plane's address to point to it.
 750  */
 751 static void
 752 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 753 {
 754         struct vc4_async_flip_state *flip_state =
 755                 container_of(cb, struct vc4_async_flip_state, cb);
 756         struct drm_crtc *crtc = flip_state->crtc;
 757         struct drm_device *dev = crtc->dev;
 758         struct drm_plane *plane = crtc->primary;
 759
 760         vc4_plane_async_set_fb(plane, flip_state->fb);
 761         if (flip_state->event) {
 762                 unsigned long flags;
 763
 764                 spin_lock_irqsave(&dev->event_lock, flags);
 765                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 766                 spin_unlock_irqrestore(&dev->event_lock, flags);
 767         }
 768
 769         drm_crtc_vblank_put(crtc);
 770         drm_framebuffer_put(flip_state->fb);
 771
 772         /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
 773          * when the planes are updated through the async update path.
 774          * FIXME: we should move to generic async-page-flip when it's
 775          * available, so that we can get rid of this hand-made cleanup_fb()
 776          * logic.
 777          */
 778         if (flip_state->old_fb) {
 779                 struct drm_gem_cma_object *cma_bo;
 780                 struct vc4_bo *bo;
 781
 782                 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
 783                 bo = to_vc4_bo(&cma_bo->base);
 784                 vc4_bo_dec_usecnt(bo);
 785                 drm_framebuffer_put(flip_state->old_fb);
 786         }
 787
 788         kfree(flip_state);
 789 }
 790
 791 /* Implements async (non-vblank-synced) page flips.
 792  *
 793  * The page flip ioctl needs to return immediately, so we grab the
 794  * modeset semaphore on the pipe, and queue the address update for
 795  * when V3D is done with the BO being flipped to.
 796  */
 797 static int vc4_async_page_flip(struct drm_crtc *crtc,
 798                                struct drm_framebuffer *fb,
 799                                struct drm_pending_vblank_event *event,
 800                                uint32_t flags)
 801 {
 802         struct drm_device *dev = crtc->dev;
 803         struct drm_plane *plane = crtc->primary;
 804         int ret = 0;
 805         struct vc4_async_flip_state *flip_state;
 806         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 807         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 808
 809         /* Increment the BO usecnt here, so that we never end up with an
 810          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
 811          * plane is later updated through the non-async path.
 812          * FIXME: we should move to generic async-page-flip when it's
 813          * available, so that we can get rid of this hand-made prepare_fb()
 814          * logic.
 815          */
 816         ret = vc4_bo_inc_usecnt(bo);
 817         if (ret)
 818                 return ret;
 819
 820         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 821         if (!flip_state) {
 822                 vc4_bo_dec_usecnt(bo);
 823                 return -ENOMEM;
 824         }
 825
 826         drm_framebuffer_get(fb);
 827         flip_state->fb = fb;
 828         flip_state->crtc = crtc;
 829         flip_state->event = event;
 830
 831         /* Save the current FB before it's replaced by the new one in
 832          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 833          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 834          * it consistent.
 835          * FIXME: we should move to generic async-page-flip when it's
 836          * available, so that we can get rid of this hand-made cleanup_fb()
 837          * logic.
 838          */
 839         flip_state->old_fb = plane->state->fb;
 840         if (flip_state->old_fb)
 841                 drm_framebuffer_get(flip_state->old_fb);
 842
 843         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 844
 845         /* Immediately update the plane's legacy fb pointer, so that later
 846          * modeset prep sees the state that will be present when the semaphore
 847          * is released.
 848          */
 849         drm_atomic_set_fb_for_plane(plane->state, fb);
 850
 851         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 852                            vc4_async_page_flip_complete);
 853
 854         /* Driver takes ownership of state on successful async commit. */
 855         return 0;
 856 }
 857
 858 int vc4_page_flip(struct drm_crtc *crtc,
 859                   struct drm_framebuffer *fb,
 860                   struct drm_pending_vblank_event *event,
 861                   uint32_t flags,
 862                   struct drm_modeset_acquire_ctx *ctx)
 863 {
 864         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 865                 return vc4_async_page_flip(crtc, fb, event, flags);
 866         else
 867                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
 868 }
 869
 870 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 871 {
 872         struct vc4_crtc_state *vc4_state, *old_vc4_state;
 873
 874         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 875         if (!vc4_state)
 876                 return NULL;
 877
 878         old_vc4_state = to_vc4_crtc_state(crtc->state);
 879         vc4_state->feed_txp = old_vc4_state->feed_txp;
 880         vc4_state->margins = old_vc4_state->margins;
 881         vc4_state->assigned_channel = old_vc4_state->assigned_channel;
 882
 883         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 884         return &vc4_state->base;
 885 }
 886
 887 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 888                             struct drm_crtc_state *state)
 889 {
 890         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 891         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 892
 893         if (drm_mm_node_allocated(&vc4_state->mm)) {
 894                 unsigned long flags;
 895
 896                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 897                 drm_mm_remove_node(&vc4_state->mm);
 898                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 899
 900         }
 901
 902         drm_atomic_helper_crtc_destroy_state(crtc, state);
 903 }
 904
 905 void vc4_crtc_reset(struct drm_crtc *crtc)
 906 {
 907         struct vc4_crtc_state *vc4_crtc_state;
 908
 909         if (crtc->state)
 910                 vc4_crtc_destroy_state(crtc, crtc->state);
 911
 912         vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL);
 913         if (!vc4_crtc_state) {
 914                 crtc->state = NULL;
 915                 return;
 916         }
 917
 918         vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
 919         __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);
 920 }
 921
 922 static const struct drm_crtc_funcs vc4_crtc_funcs = {
 923         .set_config = drm_atomic_helper_set_config,
 924         .destroy = vc4_crtc_destroy,
 925         .page_flip = vc4_page_flip,
 926         .set_property = NULL,
 927         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
 928         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
 929         .reset = vc4_crtc_reset,
 930         .atomic_duplicate_state = vc4_crtc_duplicate_state,
 931         .atomic_destroy_state = vc4_crtc_destroy_state,
 932         .enable_vblank = vc4_enable_vblank,
 933         .disable_vblank = vc4_disable_vblank,
 934         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
 935 };
 936
 937 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 938         .mode_valid = vc4_crtc_mode_valid,
 939         .atomic_check = vc4_crtc_atomic_check,
 940         .atomic_flush = vc4_hvs_atomic_flush,
 941         .atomic_enable = vc4_crtc_atomic_enable,
 942         .atomic_disable = vc4_crtc_atomic_disable,
 943         .get_scanout_position = vc4_crtc_get_scanout_position,
 944 };
 945
 946 static const struct vc4_pv_data bcm2835_pv0_data = {
 947         .base = {
 948                 .hvs_available_channels = BIT(0),
 949                 .hvs_output = 0,
 950         },
 951         .debugfs_name = "crtc0_regs",
 952         .fifo_depth = 64,
 953         .pixels_per_clock = 1,
 954         .encoder_types = {
 955                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
 956                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
 957         },
 958 };
 959
 960 static const struct vc4_pv_data bcm2835_pv1_data = {
 961         .base = {
 962                 .hvs_available_channels = BIT(2),
 963                 .hvs_output = 2,
 964         },
 965         .debugfs_name = "crtc1_regs",
 966         .fifo_depth = 64,
 967         .pixels_per_clock = 1,
 968         .encoder_types = {
 969                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
 970                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
 971         },
 972 };
 973
 974 static const struct vc4_pv_data bcm2835_pv2_data = {
 975         .base = {
 976                 .hvs_available_channels = BIT(1),
 977                 .hvs_output = 1,
 978         },
 979         .debugfs_name = "crtc2_regs",
 980         .fifo_depth = 64,
 981         .pixels_per_clock = 1,
 982         .encoder_types = {
 983                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
 984                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
 985         },
 986 };
 987
 988 static const struct vc4_pv_data bcm2711_pv0_data = {
 989         .base = {
 990                 .hvs_available_channels = BIT(0),
 991                 .hvs_output = 0,
 992         },
 993         .debugfs_name = "crtc0_regs",
 994         .fifo_depth = 64,
 995         .pixels_per_clock = 1,
 996         .encoder_types = {
 997                 [0] = VC4_ENCODER_TYPE_DSI0,
 998                 [1] = VC4_ENCODER_TYPE_DPI,
 999         },
1000 };
1001
1002 static const struct vc4_pv_data bcm2711_pv1_data = {
1003         .base = {
1004                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1005                 .hvs_output = 3,
1006         },
1007         .debugfs_name = "crtc1_regs",
1008         .fifo_depth = 64,
1009         .pixels_per_clock = 1,
1010         .encoder_types = {
1011                 [0] = VC4_ENCODER_TYPE_DSI1,
1012                 [1] = VC4_ENCODER_TYPE_SMI,
1013         },
1014 };
1015
1016 static const struct vc4_pv_data bcm2711_pv2_data = {
1017         .base = {
1018                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1019                 .hvs_output = 4,
1020         },
1021         .debugfs_name = "crtc2_regs",
1022         .fifo_depth = 256,
1023         .pixels_per_clock = 2,
1024         .encoder_types = {
1025                 [0] = VC4_ENCODER_TYPE_HDMI0,
1026         },
1027 };
1028
1029 static const struct vc4_pv_data bcm2711_pv3_data = {
1030         .base = {
1031                 .hvs_available_channels = BIT(1),
1032                 .hvs_output = 1,
1033         },
1034         .debugfs_name = "crtc3_regs",
1035         .fifo_depth = 64,
1036         .pixels_per_clock = 1,
1037         .encoder_types = {
1038                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1039         },
1040 };
1041
1042 static const struct vc4_pv_data bcm2711_pv4_data = {
1043         .base = {
1044                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1045                 .hvs_output = 5,
1046         },
1047         .debugfs_name = "crtc4_regs",
1048         .fifo_depth = 64,
1049         .pixels_per_clock = 2,
1050         .encoder_types = {
1051                 [0] = VC4_ENCODER_TYPE_HDMI1,
1052         },
1053 };
1054
1055 static const struct of_device_id vc4_crtc_dt_match[] = {
1056         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1057         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1058         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1059         { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1060         { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1061         { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1062         { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1063         { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1064         {}
1065 };
1066
1067 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1068                                         struct drm_crtc *crtc)
1069 {
1070         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1071         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
1072         const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
1073         struct drm_encoder *encoder;
1074
1075         drm_for_each_encoder(encoder, drm) {
1076                 struct vc4_encoder *vc4_encoder;
1077                 int i;
1078
1079                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
1080                         continue;
1081
1082                 vc4_encoder = to_vc4_encoder(encoder);
1083                 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
1084                         if (vc4_encoder->type == encoder_types[i]) {
1085                                 vc4_encoder->clock_select = i;
1086                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1087                                 break;
1088                         }
1089                 }
1090         }
1091 }
1092
1093 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
1094                   const struct drm_crtc_funcs *crtc_funcs,
1095                   const struct drm_crtc_helper_funcs *crtc_helper_funcs)
1096 {
1097         struct vc4_dev *vc4 = to_vc4_dev(drm);
1098         struct drm_crtc *crtc = &vc4_crtc->base;
1099         struct drm_plane *primary_plane;
1100         unsigned int i;
1101
1102         /* For now, we create just the primary and the legacy cursor
1103          * planes.  We should be able to stack more planes on easily,
1104          * but to do that we would need to compute the bandwidth
1105          * requirement of the plane configuration, and reject ones
1106          * that will take too much.
1107          */
1108         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1109         if (IS_ERR(primary_plane)) {
1110                 dev_err(drm->dev, "failed to construct primary plane\n");
1111                 return PTR_ERR(primary_plane);
1112         }
1113
1114         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1115                                   crtc_funcs, NULL);
1116         drm_crtc_helper_add(crtc, crtc_helper_funcs);
1117
1118         if (!vc4->hvs->hvs5) {
1119                 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1120
1121                 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1122
1123                 /* We support CTM, but only for one CRTC at a time. It's therefore
1124                  * implemented as private driver state in vc4_kms, not here.
1125                  */
1126                 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1127         }
1128
1129         for (i = 0; i < crtc->gamma_size; i++) {
1130                 vc4_crtc->lut_r[i] = i;
1131                 vc4_crtc->lut_g[i] = i;
1132                 vc4_crtc->lut_b[i] = i;
1133         }
1134
1135         return 0;
1136 }
1137
1138 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1139 {
1140         struct platform_device *pdev = to_platform_device(dev);
1141         struct drm_device *drm = dev_get_drvdata(master);
1142         const struct vc4_pv_data *pv_data;
1143         struct vc4_crtc *vc4_crtc;
1144         struct drm_crtc *crtc;
1145         struct drm_plane *destroy_plane, *temp;
1146         int ret;
1147
1148         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1149         if (!vc4_crtc)
1150                 return -ENOMEM;
1151         crtc = &vc4_crtc->base;
1152
1153         pv_data = of_device_get_match_data(dev);
1154         if (!pv_data)
1155                 return -ENODEV;
1156         vc4_crtc->data = &pv_data->base;
1157         vc4_crtc->pdev = pdev;
1158
1159         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1160         if (IS_ERR(vc4_crtc->regs))
1161                 return PTR_ERR(vc4_crtc->regs);
1162
1163         vc4_crtc->regset.base = vc4_crtc->regs;
1164         vc4_crtc->regset.regs = crtc_regs;
1165         vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1166
1167         ret = vc4_crtc_init(drm, vc4_crtc,
1168                             &vc4_crtc_funcs, &vc4_crtc_helper_funcs);
1169         if (ret)
1170                 return ret;
1171         vc4_set_crtc_possible_masks(drm, crtc);
1172
1173         CRTC_WRITE(PV_INTEN, 0);
1174         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1175         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1176                                vc4_crtc_irq_handler,
1177                                IRQF_SHARED,
1178                                "vc4 crtc", vc4_crtc);
1179         if (ret)
1180                 goto err_destroy_planes;
1181
1182         platform_set_drvdata(pdev, vc4_crtc);
1183
1184         vc4_debugfs_add_regset32(drm, pv_data->debugfs_name,
1185                                  &vc4_crtc->regset);
1186
1187         return 0;
1188
1189 err_destroy_planes:
1190         list_for_each_entry_safe(destroy_plane, temp,
1191                                  &drm->mode_config.plane_list, head) {
1192                 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1193                     destroy_plane->funcs->destroy(destroy_plane);
1194         }
1195
1196         return ret;
1197 }
1198
1199 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1200                             void *data)
1201 {
1202         struct platform_device *pdev = to_platform_device(dev);
1203         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1204
1205         vc4_crtc_destroy(&vc4_crtc->base);
1206
1207         CRTC_WRITE(PV_INTEN, 0);
1208
1209         platform_set_drvdata(pdev, NULL);
1210 }
1211
1212 static const struct component_ops vc4_crtc_ops = {
1213         .bind   = vc4_crtc_bind,
1214         .unbind = vc4_crtc_unbind,
1215 };
1216
1217 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1218 {
1219         return component_add(&pdev->dev, &vc4_crtc_ops);
1220 }
1221
1222 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1223 {
1224         component_del(&pdev->dev, &vc4_crtc_ops);
1225         return 0;
1226 }
1227
1228 struct platform_driver vc4_crtc_driver = {
1229         .probe = vc4_crtc_dev_probe,
1230         .remove = vc4_crtc_dev_remove,
1231         .driver = {
1232                 .name = "vc4_crtc",
1233                 .of_match_table = vc4_crtc_dt_match,
1234         },
1235 };