drivers/gpu/drm/v3d/v3d_drv.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2014-2018 Broadcom */
   3
   4 /**
   5  * DOC: Broadcom V3D Graphics Driver
   6  *
   7  * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
   8  * For V3D 2.x support, see the VC4 driver.
   9  *
  10  * The V3D GPU includes a tiled render (composed of a bin and render
  11  * pipelines), the TFU (texture formatting unit), and the CSD (compute
  12  * shader dispatch).
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/reset.h>
  24
  25 #include <drm/drm_drv.h>
  26 #include <drm/drm_fb_cma_helper.h>
  27 #include <drm/drm_fb_helper.h>
  28 #include <uapi/drm/v3d_drm.h>
  29
  30 #include "v3d_drv.h"
  31 #include "v3d_regs.h"
  32
  33 #define DRIVER_NAME "v3d"
  34 #define DRIVER_DESC "Broadcom V3D graphics"
  35 #define DRIVER_DATE "20180419"
  36 #define DRIVER_MAJOR 1
  37 #define DRIVER_MINOR 0
  38 #define DRIVER_PATCHLEVEL 0
  39
  40 #ifdef CONFIG_PM
  41 static int v3d_runtime_suspend(struct device *dev)
  42 {
  43         struct drm_device *drm = dev_get_drvdata(dev);
  44         struct v3d_dev *v3d = to_v3d_dev(drm);
  45
  46         v3d_irq_disable(v3d);
  47
  48         clk_disable_unprepare(v3d->clk);
  49
  50         return 0;
  51 }
  52
  53 static int v3d_runtime_resume(struct device *dev)
  54 {
  55         struct drm_device *drm = dev_get_drvdata(dev);
  56         struct v3d_dev *v3d = to_v3d_dev(drm);
  57         int ret;
  58
  59         ret = clk_prepare_enable(v3d->clk);
  60         if (ret != 0)
  61                 return ret;
  62
  63         /* XXX: VPM base */
  64
  65         v3d_mmu_set_page_table(v3d);
  66         v3d_irq_enable(v3d);
  67
  68         return 0;
  69 }
  70 #endif
  71
  72 static const struct dev_pm_ops v3d_v3d_pm_ops = {
  73         SET_RUNTIME_PM_OPS(v3d_runtime_suspend, v3d_runtime_resume, NULL)
  74 };
  75
  76 static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
  77                                struct drm_file *file_priv)
  78 {
  79         struct v3d_dev *v3d = to_v3d_dev(dev);
  80         struct drm_v3d_get_param *args = data;
  81         int ret;
  82         static const u32 reg_map[] = {
  83                 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
  84                 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
  85                 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
  86                 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
  87                 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
  88                 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
  89                 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
  90         };
  91
  92         if (args->pad != 0)
  93                 return -EINVAL;
  94
  95         /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
  96          * to explicitly allow it in the "the register in our
  97          * parameter map" check.
  98          */
  99         if (args->param < ARRAY_SIZE(reg_map) &&
 100             (reg_map[args->param] ||
 101              args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
 102                 u32 offset = reg_map[args->param];
 103
 104                 if (args->value != 0)
 105                         return -EINVAL;
 106
 107                 ret = pm_runtime_get_sync(v3d->dev);
 108                 if (ret < 0)
 109                         return ret;
 110                 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
 111                     args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
 112                         args->value = V3D_CORE_READ(0, offset);
 113                 } else {
 114                         args->value = V3D_READ(offset);
 115                 }
 116                 pm_runtime_mark_last_busy(v3d->dev);
 117                 pm_runtime_put_autosuspend(v3d->dev);
 118                 return 0;
 119         }
 120
 121
 122         switch (args->param) {
 123         case DRM_V3D_PARAM_SUPPORTS_TFU:
 124                 args->value = 1;
 125                 return 0;
 126         case DRM_V3D_PARAM_SUPPORTS_CSD:
 127                 args->value = v3d_has_csd(v3d);
 128                 return 0;
 129         case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
 130                 args->value = 1;
 131                 return 0;
 132         default:
 133                 DRM_DEBUG("Unknown parameter %d\n", args->param);
 134                 return -EINVAL;
 135         }
 136 }
 137
 138 static int
 139 v3d_open(struct drm_device *dev, struct drm_file *file)
 140 {
 141         struct v3d_dev *v3d = to_v3d_dev(dev);
 142         struct v3d_file_priv *v3d_priv;
 143         struct drm_gpu_scheduler *sched;
 144         int i;
 145
 146         v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
 147         if (!v3d_priv)
 148                 return -ENOMEM;
 149
 150         v3d_priv->v3d = v3d;
 151
 152         for (i = 0; i < V3D_MAX_QUEUES; i++) {
 153                 sched = &v3d->queue[i].sched;
 154                 drm_sched_entity_init(&v3d_priv->sched_entity[i],
 155                                       DRM_SCHED_PRIORITY_NORMAL, &sched,
 156                                       1, NULL);
 157         }
 158
 159         file->driver_priv = v3d_priv;
 160
 161         return 0;
 162 }
 163
 164 static void
 165 v3d_postclose(struct drm_device *dev, struct drm_file *file)
 166 {
 167         struct v3d_file_priv *v3d_priv = file->driver_priv;
 168         enum v3d_queue q;
 169
 170         for (q = 0; q < V3D_MAX_QUEUES; q++) {
 171                 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
 172         }
 173
 174         kfree(v3d_priv);
 175 }
 176
 177 DEFINE_DRM_GEM_FOPS(v3d_drm_fops);
 178
 179 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
 180  * protection between clients.  Note that render nodes would be be
 181  * able to submit CLs that could access BOs from clients authenticated
 182  * with the master node.  The TFU doesn't use the GMP, so it would
 183  * need to stay DRM_AUTH until we do buffer size/offset validation.
 184  */
 185 static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
 186         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 187         DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
 188         DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
 189         DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
 190         DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
 191         DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
 192         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 193         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 194 };
 195
 196 static struct drm_driver v3d_drm_driver = {
 197         .driver_features = (DRIVER_GEM |
 198                             DRIVER_RENDER |
 199                             DRIVER_SYNCOBJ),
 200
 201         .open = v3d_open,
 202         .postclose = v3d_postclose,
 203
 204 #if defined(CONFIG_DEBUG_FS)
 205         .debugfs_init = v3d_debugfs_init,
 206 #endif
 207
 208         .gem_create_object = v3d_create_object,
 209         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 210         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 211         .gem_prime_import_sg_table = v3d_prime_import_sg_table,
 212         .gem_prime_mmap = drm_gem_prime_mmap,
 213
 214         .ioctls = v3d_drm_ioctls,
 215         .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
 216         .fops = &v3d_drm_fops,
 217
 218         .name = DRIVER_NAME,
 219         .desc = DRIVER_DESC,
 220         .date = DRIVER_DATE,
 221         .major = DRIVER_MAJOR,
 222         .minor = DRIVER_MINOR,
 223         .patchlevel = DRIVER_PATCHLEVEL,
 224 };
 225
 226 static const struct of_device_id v3d_of_match[] = {
 227         { .compatible = "brcm,7268-v3d" },
 228         { .compatible = "brcm,7278-v3d" },
 229         {},
 230 };
 231 MODULE_DEVICE_TABLE(of, v3d_of_match);
 232
 233 static int
 234 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
 235 {
 236         struct resource *res =
 237                 platform_get_resource_byname(v3d->pdev, IORESOURCE_MEM, name);
 238
 239         *regs = devm_ioremap_resource(v3d->dev, res);
 240         return PTR_ERR_OR_ZERO(*regs);
 241 }
 242
 243 static int v3d_platform_drm_probe(struct platform_device *pdev)
 244 {
 245         struct device *dev = &pdev->dev;
 246         struct drm_device *drm;
 247         struct v3d_dev *v3d;
 248         int ret;
 249         u32 mmu_debug;
 250         u32 ident1;
 251
 252
 253         v3d = kzalloc(sizeof(*v3d), GFP_KERNEL);
 254         if (!v3d)
 255                 return -ENOMEM;
 256         v3d->dev = dev;
 257         v3d->pdev = pdev;
 258         drm = &v3d->drm;
 259
 260         ret = map_regs(v3d, &v3d->hub_regs, "hub");
 261         if (ret)
 262                 goto dev_free;
 263
 264         ret = map_regs(v3d, &v3d->core_regs[0], "core0");
 265         if (ret)
 266                 goto dev_free;
 267
 268         mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
 269         dev->coherent_dma_mask =
 270                 DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
 271         v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
 272
 273         ident1 = V3D_READ(V3D_HUB_IDENT1);
 274         v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
 275                     V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
 276         v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
 277         WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
 278
 279         v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
 280         if (IS_ERR(v3d->reset)) {
 281                 ret = PTR_ERR(v3d->reset);
 282
 283                 if (ret == -EPROBE_DEFER)
 284                         goto dev_free;
 285
 286                 v3d->reset = NULL;
 287                 ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
 288                 if (ret) {
 289                         dev_err(dev,
 290                                 "Failed to get reset control or bridge regs\n");
 291                         goto dev_free;
 292                 }
 293         }
 294
 295         if (v3d->ver < 41) {
 296                 ret = map_regs(v3d, &v3d->gca_regs, "gca");
 297                 if (ret)
 298                         goto dev_free;
 299         }
 300
 301         v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
 302                                         GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
 303         if (!v3d->mmu_scratch) {
 304                 dev_err(dev, "Failed to allocate MMU scratch page\n");
 305                 ret = -ENOMEM;
 306                 goto dev_free;
 307         }
 308
 309         pm_runtime_use_autosuspend(dev);
 310         pm_runtime_set_autosuspend_delay(dev, 50);
 311         pm_runtime_enable(dev);
 312
 313         ret = drm_dev_init(&v3d->drm, &v3d_drm_driver, dev);
 314         if (ret)
 315                 goto dma_free;
 316
 317         platform_set_drvdata(pdev, drm);
 318         drm->dev_private = v3d;
 319
 320         ret = v3d_gem_init(drm);
 321         if (ret)
 322                 goto dev_destroy;
 323
 324         ret = v3d_irq_init(v3d);
 325         if (ret)
 326                 goto gem_destroy;
 327
 328         ret = drm_dev_register(drm, 0);
 329         if (ret)
 330                 goto irq_disable;
 331
 332         return 0;
 333
 334 irq_disable:
 335         v3d_irq_disable(v3d);
 336 gem_destroy:
 337         v3d_gem_destroy(drm);
 338 dev_destroy:
 339         drm_dev_put(drm);
 340 dma_free:
 341         dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
 342 dev_free:
 343         kfree(v3d);
 344         return ret;
 345 }
 346
 347 static int v3d_platform_drm_remove(struct platform_device *pdev)
 348 {
 349         struct drm_device *drm = platform_get_drvdata(pdev);
 350         struct v3d_dev *v3d = to_v3d_dev(drm);
 351
 352         drm_dev_unregister(drm);
 353
 354         v3d_gem_destroy(drm);
 355
 356         drm_dev_put(drm);
 357
 358         dma_free_wc(v3d->dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
 359
 360         return 0;
 361 }
 362
 363 static struct platform_driver v3d_platform_driver = {
 364         .probe          = v3d_platform_drm_probe,
 365         .remove         = v3d_platform_drm_remove,
 366         .driver         = {
 367                 .name   = "v3d",
 368                 .of_match_table = v3d_of_match,
 369         },
 370 };
 371
 372 static int __init v3d_drm_register(void)
 373 {
 374         return platform_driver_register(&v3d_platform_driver);
 375 }
 376
 377 static void __exit v3d_drm_unregister(void)
 378 {
 379         platform_driver_unregister(&v3d_platform_driver);
 380 }
 381
 382 module_init(v3d_drm_register);
 383 module_exit(v3d_drm_unregister);
 384
 385 MODULE_ALIAS("platform:v3d-drm");
 386 MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
 387 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
 388 MODULE_LICENSE("GPL v2");