drivers/gpu/drm/v3d/v3d_drv.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2014-2018 Broadcom */
   3
   4 /**
   5  * DOC: Broadcom V3D Graphics Driver
   6  *
   7  * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
   8  * For V3D 2.x support, see the VC4 driver.
   9  *
  10  * The V3D GPU includes a tiled render (composed of a bin and render
  11  * pipelines), the TFU (texture formatting unit), and the CSD (compute
  12  * shader dispatch).
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/sched/clock.h>
  23 #include <linux/reset.h>
  24
  25 #include <drm/drm_drv.h>
  26 #include <drm/drm_managed.h>
  27 #include <uapi/drm/v3d_drm.h>
  28
  29 #include "v3d_drv.h"
  30 #include "v3d_regs.h"
  31
  32 #define DRIVER_NAME "v3d"
  33 #define DRIVER_DESC "Broadcom V3D graphics"
  34 #define DRIVER_DATE "20180419"
  35 #define DRIVER_MAJOR 1
  36 #define DRIVER_MINOR 0
  37 #define DRIVER_PATCHLEVEL 0
  38
  39 static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
  40                                struct drm_file *file_priv)
  41 {
  42         struct v3d_dev *v3d = to_v3d_dev(dev);
  43         struct drm_v3d_get_param *args = data;
  44         static const u32 reg_map[] = {
  45                 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
  46                 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
  47                 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
  48                 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
  49                 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
  50                 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
  51                 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
  52         };
  53
  54         if (args->pad != 0)
  55                 return -EINVAL;
  56
  57         /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
  58          * to explicitly allow it in the "the register in our
  59          * parameter map" check.
  60          */
  61         if (args->param < ARRAY_SIZE(reg_map) &&
  62             (reg_map[args->param] ||
  63              args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
  64                 u32 offset = reg_map[args->param];
  65
  66                 if (args->value != 0)
  67                         return -EINVAL;
  68
  69                 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
  70                     args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
  71                         args->value = V3D_CORE_READ(0, offset);
  72                 } else {
  73                         args->value = V3D_READ(offset);
  74                 }
  75                 return 0;
  76         }
  77
  78         switch (args->param) {
  79         case DRM_V3D_PARAM_SUPPORTS_TFU:
  80                 args->value = 1;
  81                 return 0;
  82         case DRM_V3D_PARAM_SUPPORTS_CSD:
  83                 args->value = v3d_has_csd(v3d);
  84                 return 0;
  85         case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
  86                 args->value = 1;
  87                 return 0;
  88         case DRM_V3D_PARAM_SUPPORTS_PERFMON:
  89                 args->value = (v3d->ver >= 40);
  90                 return 0;
  91         case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT:
  92                 args->value = 1;
  93                 return 0;
  94         case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE:
  95                 args->value = 1;
  96                 return 0;
  97         default:
  98                 DRM_DEBUG("Unknown parameter %d\n", args->param);
  99                 return -EINVAL;
 100         }
 101 }
 102
 103 static int
 104 v3d_open(struct drm_device *dev, struct drm_file *file)
 105 {
 106         struct v3d_dev *v3d = to_v3d_dev(dev);
 107         struct v3d_file_priv *v3d_priv;
 108         struct drm_gpu_scheduler *sched;
 109         int i;
 110
 111         v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
 112         if (!v3d_priv)
 113                 return -ENOMEM;
 114
 115         v3d_priv->v3d = v3d;
 116
 117         for (i = 0; i < V3D_MAX_QUEUES; i++) {
 118                 v3d_priv->enabled_ns[i] = 0;
 119                 v3d_priv->start_ns[i] = 0;
 120                 v3d_priv->jobs_sent[i] = 0;
 121
 122                 sched = &v3d->queue[i].sched;
 123                 drm_sched_entity_init(&v3d_priv->sched_entity[i],
 124                                       DRM_SCHED_PRIORITY_NORMAL, &sched,
 125                                       1, NULL);
 126         }
 127
 128         v3d_perfmon_open_file(v3d_priv);
 129         file->driver_priv = v3d_priv;
 130
 131         return 0;
 132 }
 133
 134 static void
 135 v3d_postclose(struct drm_device *dev, struct drm_file *file)
 136 {
 137         struct v3d_file_priv *v3d_priv = file->driver_priv;
 138         enum v3d_queue q;
 139
 140         for (q = 0; q < V3D_MAX_QUEUES; q++)
 141                 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
 142
 143         v3d_perfmon_close_file(v3d_priv);
 144         kfree(v3d_priv);
 145 }
 146
 147 static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file)
 148 {
 149         struct v3d_file_priv *file_priv = file->driver_priv;
 150         u64 timestamp = local_clock();
 151         enum v3d_queue queue;
 152
 153         for (queue = 0; queue < V3D_MAX_QUEUES; queue++) {
 154                 /* Note that, in case of a GPU reset, the time spent during an
 155                  * attempt of executing the job is not computed in the runtime.
 156                  */
 157                 drm_printf(p, "drm-engine-%s: \t%llu ns\n",
 158                            v3d_queue_to_string(queue),
 159                            file_priv->start_ns[queue] ? file_priv->enabled_ns[queue]
 160                                                       + timestamp - file_priv->start_ns[queue]
 161                                                       : file_priv->enabled_ns[queue]);
 162
 163                 /* Note that we only count jobs that completed. Therefore, jobs
 164                  * that were resubmitted due to a GPU reset are not computed.
 165                  */
 166                 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n",
 167                            v3d_queue_to_string(queue), file_priv->jobs_sent[queue]);
 168         }
 169 }
 170
 171 static const struct file_operations v3d_drm_fops = {
 172         .owner = THIS_MODULE,
 173         DRM_GEM_FOPS,
 174         .show_fdinfo = drm_show_fdinfo,
 175 };
 176
 177 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
 178  * protection between clients.  Note that render nodes would be
 179  * able to submit CLs that could access BOs from clients authenticated
 180  * with the master node.  The TFU doesn't use the GMP, so it would
 181  * need to stay DRM_AUTH until we do buffer size/offset validation.
 182  */
 183 static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
 184         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 185         DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
 186         DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
 187         DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
 188         DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
 189         DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
 190         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 191         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 192         DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW),
 193         DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW),
 194         DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW),
 195         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 196 };
 197
 198 static const struct drm_driver v3d_drm_driver = {
 199         .driver_features = (DRIVER_GEM |
 200                             DRIVER_RENDER |
 201                             DRIVER_SYNCOBJ),
 202
 203         .open = v3d_open,
 204         .postclose = v3d_postclose,
 205
 206 #if defined(CONFIG_DEBUG_FS)
 207         .debugfs_init = v3d_debugfs_init,
 208 #endif
 209
 210         .gem_create_object = v3d_create_object,
 211         .gem_prime_import_sg_table = v3d_prime_import_sg_table,
 212
 213         .ioctls = v3d_drm_ioctls,
 214         .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
 215         .fops = &v3d_drm_fops,
 216         .show_fdinfo = v3d_show_fdinfo,
 217
 218         .name = DRIVER_NAME,
 219         .desc = DRIVER_DESC,
 220         .date = DRIVER_DATE,
 221         .major = DRIVER_MAJOR,
 222         .minor = DRIVER_MINOR,
 223         .patchlevel = DRIVER_PATCHLEVEL,
 224 };
 225
 226 static const struct of_device_id v3d_of_match[] = {
 227         { .compatible = "brcm,2711-v3d" },
 228         { .compatible = "brcm,2712-v3d" },
 229         { .compatible = "brcm,7268-v3d" },
 230         { .compatible = "brcm,7278-v3d" },
 231         {},
 232 };
 233 MODULE_DEVICE_TABLE(of, v3d_of_match);
 234
 235 static int
 236 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
 237 {
 238         *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name);
 239         return PTR_ERR_OR_ZERO(*regs);
 240 }
 241
 242 static int v3d_platform_drm_probe(struct platform_device *pdev)
 243 {
 244         struct device *dev = &pdev->dev;
 245         struct drm_device *drm;
 246         struct v3d_dev *v3d;
 247         int ret;
 248         u32 mmu_debug;
 249         u32 ident1;
 250         u64 mask;
 251
 252         v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm);
 253         if (IS_ERR(v3d))
 254                 return PTR_ERR(v3d);
 255
 256         drm = &v3d->drm;
 257
 258         platform_set_drvdata(pdev, drm);
 259
 260         ret = map_regs(v3d, &v3d->hub_regs, "hub");
 261         if (ret)
 262                 return ret;
 263
 264         ret = map_regs(v3d, &v3d->core_regs[0], "core0");
 265         if (ret)
 266                 return ret;
 267
 268         mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
 269         mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
 270         ret = dma_set_mask_and_coherent(dev, mask);
 271         if (ret)
 272                 return ret;
 273
 274         v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
 275
 276         ident1 = V3D_READ(V3D_HUB_IDENT1);
 277         v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
 278                     V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
 279         v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
 280         WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
 281
 282         v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
 283         if (IS_ERR(v3d->reset)) {
 284                 ret = PTR_ERR(v3d->reset);
 285
 286                 if (ret == -EPROBE_DEFER)
 287                         return ret;
 288
 289                 v3d->reset = NULL;
 290                 ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
 291                 if (ret) {
 292                         dev_err(dev,
 293                                 "Failed to get reset control or bridge regs\n");
 294                         return ret;
 295                 }
 296         }
 297
 298         if (v3d->ver < 41) {
 299                 ret = map_regs(v3d, &v3d->gca_regs, "gca");
 300                 if (ret)
 301                         return ret;
 302         }
 303
 304         v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
 305                                         GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
 306         if (!v3d->mmu_scratch) {
 307                 dev_err(dev, "Failed to allocate MMU scratch page\n");
 308                 return -ENOMEM;
 309         }
 310
 311         ret = v3d_gem_init(drm);
 312         if (ret)
 313                 goto dma_free;
 314
 315         ret = v3d_irq_init(v3d);
 316         if (ret)
 317                 goto gem_destroy;
 318
 319         ret = drm_dev_register(drm, 0);
 320         if (ret)
 321                 goto irq_disable;
 322
 323         ret = v3d_sysfs_init(dev);
 324         if (ret)
 325                 goto drm_unregister;
 326
 327         return 0;
 328
 329 drm_unregister:
 330         drm_dev_unregister(drm);
 331 irq_disable:
 332         v3d_irq_disable(v3d);
 333 gem_destroy:
 334         v3d_gem_destroy(drm);
 335 dma_free:
 336         dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
 337         return ret;
 338 }
 339
 340 static void v3d_platform_drm_remove(struct platform_device *pdev)
 341 {
 342         struct drm_device *drm = platform_get_drvdata(pdev);
 343         struct v3d_dev *v3d = to_v3d_dev(drm);
 344         struct device *dev = &pdev->dev;
 345
 346         v3d_sysfs_destroy(dev);
 347
 348         drm_dev_unregister(drm);
 349
 350         v3d_gem_destroy(drm);
 351
 352         dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,
 353                     v3d->mmu_scratch_paddr);
 354 }
 355
 356 static struct platform_driver v3d_platform_driver = {
 357         .probe          = v3d_platform_drm_probe,
 358         .remove_new     = v3d_platform_drm_remove,
 359         .driver         = {
 360                 .name   = "v3d",
 361                 .of_match_table = v3d_of_match,
 362         },
 363 };
 364
 365 module_platform_driver(v3d_platform_driver);
 366
 367 MODULE_ALIAS("platform:v3d-drm");
 368 MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
 369 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
 370 MODULE_LICENSE("GPL v2");