drivers/gpu/drm/tidss/tidss_dispc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
   4  * Author: Jyri Sarha <jsarha@ti.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/delay.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/err.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/kernel.h>
  14 #include <linux/media-bus-format.h>
  15 #include <linux/module.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/of.h>
  18 #include <linux/of_graph.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regmap.h>
  23 #include <linux/sys_soc.h>
  24
  25 #include <drm/drm_blend.h>
  26 #include <drm/drm_fourcc.h>
  27 #include <drm/drm_fb_dma_helper.h>
  28 #include <drm/drm_framebuffer.h>
  29 #include <drm/drm_gem_dma_helper.h>
  30 #include <drm/drm_panel.h>
  31
  32 #include "tidss_crtc.h"
  33 #include "tidss_dispc.h"
  34 #include "tidss_drv.h"
  35 #include "tidss_irq.h"
  36 #include "tidss_plane.h"
  37
  38 #include "tidss_dispc_regs.h"
  39 #include "tidss_scale_coefs.h"
  40
  41 static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
  42         [DSS_REVISION_OFF] =                    0x00,
  43         [DSS_SYSCONFIG_OFF] =                   0x04,
  44         [DSS_SYSSTATUS_OFF] =                   0x08,
  45         [DISPC_IRQ_EOI_OFF] =                   0x20,
  46         [DISPC_IRQSTATUS_RAW_OFF] =             0x24,
  47         [DISPC_IRQSTATUS_OFF] =                 0x28,
  48         [DISPC_IRQENABLE_SET_OFF] =             0x2c,
  49         [DISPC_IRQENABLE_CLR_OFF] =             0x30,
  50
  51         [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] =    0x40,
  52         [DISPC_GLOBAL_BUFFER_OFF] =             0x44,
  53
  54         [DISPC_DBG_CONTROL_OFF] =               0x4c,
  55         [DISPC_DBG_STATUS_OFF] =                0x50,
  56
  57         [DISPC_CLKGATING_DISABLE_OFF] =         0x54,
  58 };
  59
  60 const struct dispc_features dispc_k2g_feats = {
  61         .min_pclk_khz = 4375,
  62
  63         .max_pclk_khz = {
  64                 [DISPC_VP_DPI] = 150000,
  65         },
  66
  67         /*
  68          * XXX According TRM the RGB input buffer width up to 2560 should
  69          *     work on 3 taps, but in practice it only works up to 1280.
  70          */
  71         .scaling = {
  72                 .in_width_max_5tap_rgb = 1280,
  73                 .in_width_max_3tap_rgb = 1280,
  74                 .in_width_max_5tap_yuv = 2560,
  75                 .in_width_max_3tap_yuv = 2560,
  76                 .upscale_limit = 16,
  77                 .downscale_limit_5tap = 4,
  78                 .downscale_limit_3tap = 2,
  79                 /*
  80                  * The max supported pixel inc value is 255. The value
  81                  * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
  82                  * The maximum bpp of all formats supported by the HW
  83                  * is 8. So the maximum supported xinc value is 32,
  84                  * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
  85                  */
  86                 .xinc_max = 32,
  87         },
  88
  89         .subrev = DISPC_K2G,
  90
  91         .common = "common",
  92
  93         .common_regs = tidss_k2g_common_regs,
  94
  95         .num_vps = 1,
  96         .vp_name = { "vp1" },
  97         .ovr_name = { "ovr1" },
  98         .vpclk_name =  { "vp1" },
  99         .vp_bus_type = { DISPC_VP_DPI },
 100
 101         .vp_feat = { .color = {
 102                         .has_ctm = true,
 103                         .gamma_size = 256,
 104                         .gamma_type = TIDSS_GAMMA_8BIT,
 105                 },
 106         },
 107
 108         .num_planes = 1,
 109         .vid_name = { "vid1" },
 110         .vid_lite = { false },
 111         .vid_order = { 0 },
 112 };
 113
 114 static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
 115         [DSS_REVISION_OFF] =                    0x4,
 116         [DSS_SYSCONFIG_OFF] =                   0x8,
 117         [DSS_SYSSTATUS_OFF] =                   0x20,
 118         [DISPC_IRQ_EOI_OFF] =                   0x24,
 119         [DISPC_IRQSTATUS_RAW_OFF] =             0x28,
 120         [DISPC_IRQSTATUS_OFF] =                 0x2c,
 121         [DISPC_IRQENABLE_SET_OFF] =             0x30,
 122         [DISPC_IRQENABLE_CLR_OFF] =             0x40,
 123         [DISPC_VID_IRQENABLE_OFF] =             0x44,
 124         [DISPC_VID_IRQSTATUS_OFF] =             0x58,
 125         [DISPC_VP_IRQENABLE_OFF] =              0x70,
 126         [DISPC_VP_IRQSTATUS_OFF] =              0x7c,
 127
 128         [WB_IRQENABLE_OFF] =                    0x88,
 129         [WB_IRQSTATUS_OFF] =                    0x8c,
 130
 131         [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] =    0x90,
 132         [DISPC_GLOBAL_OUTPUT_ENABLE_OFF] =      0x94,
 133         [DISPC_GLOBAL_BUFFER_OFF] =             0x98,
 134         [DSS_CBA_CFG_OFF] =                     0x9c,
 135         [DISPC_DBG_CONTROL_OFF] =               0xa0,
 136         [DISPC_DBG_STATUS_OFF] =                0xa4,
 137         [DISPC_CLKGATING_DISABLE_OFF] =         0xa8,
 138         [DISPC_SECURE_DISABLE_OFF] =            0xac,
 139 };
 140
 141 const struct dispc_features dispc_am65x_feats = {
 142         .max_pclk_khz = {
 143                 [DISPC_VP_DPI] = 165000,
 144                 [DISPC_VP_OLDI] = 165000,
 145         },
 146
 147         .scaling = {
 148                 .in_width_max_5tap_rgb = 1280,
 149                 .in_width_max_3tap_rgb = 2560,
 150                 .in_width_max_5tap_yuv = 2560,
 151                 .in_width_max_3tap_yuv = 4096,
 152                 .upscale_limit = 16,
 153                 .downscale_limit_5tap = 4,
 154                 .downscale_limit_3tap = 2,
 155                 /*
 156                  * The max supported pixel inc value is 255. The value
 157                  * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
 158                  * The maximum bpp of all formats supported by the HW
 159                  * is 8. So the maximum supported xinc value is 32,
 160                  * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
 161                  */
 162                 .xinc_max = 32,
 163         },
 164
 165         .subrev = DISPC_AM65X,
 166
 167         .common = "common",
 168         .common_regs = tidss_am65x_common_regs,
 169
 170         .num_vps = 2,
 171         .vp_name = { "vp1", "vp2" },
 172         .ovr_name = { "ovr1", "ovr2" },
 173         .vpclk_name =  { "vp1", "vp2" },
 174         .vp_bus_type = { DISPC_VP_OLDI, DISPC_VP_DPI },
 175
 176         .vp_feat = { .color = {
 177                         .has_ctm = true,
 178                         .gamma_size = 256,
 179                         .gamma_type = TIDSS_GAMMA_8BIT,
 180                 },
 181         },
 182
 183         .num_planes = 2,
 184         /* note: vid is plane_id 0 and vidl1 is plane_id 1 */
 185         .vid_name = { "vid", "vidl1" },
 186         .vid_lite = { false, true, },
 187         .vid_order = { 1, 0 },
 188 };
 189
 190 static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
 191         [DSS_REVISION_OFF] =                    0x4,
 192         [DSS_SYSCONFIG_OFF] =                   0x8,
 193         [DSS_SYSSTATUS_OFF] =                   0x20,
 194         [DISPC_IRQ_EOI_OFF] =                   0x80,
 195         [DISPC_IRQSTATUS_RAW_OFF] =             0x28,
 196         [DISPC_IRQSTATUS_OFF] =                 0x2c,
 197         [DISPC_IRQENABLE_SET_OFF] =             0x30,
 198         [DISPC_IRQENABLE_CLR_OFF] =             0x34,
 199         [DISPC_VID_IRQENABLE_OFF] =             0x38,
 200         [DISPC_VID_IRQSTATUS_OFF] =             0x48,
 201         [DISPC_VP_IRQENABLE_OFF] =              0x58,
 202         [DISPC_VP_IRQSTATUS_OFF] =              0x68,
 203
 204         [WB_IRQENABLE_OFF] =                    0x78,
 205         [WB_IRQSTATUS_OFF] =                    0x7c,
 206
 207         [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] =    0x98,
 208         [DISPC_GLOBAL_OUTPUT_ENABLE_OFF] =      0x9c,
 209         [DISPC_GLOBAL_BUFFER_OFF] =             0xa0,
 210         [DSS_CBA_CFG_OFF] =                     0xa4,
 211         [DISPC_DBG_CONTROL_OFF] =               0xa8,
 212         [DISPC_DBG_STATUS_OFF] =                0xac,
 213         [DISPC_CLKGATING_DISABLE_OFF] =         0xb0,
 214         [DISPC_SECURE_DISABLE_OFF] =            0x90,
 215
 216         [FBDC_REVISION_1_OFF] =                 0xb8,
 217         [FBDC_REVISION_2_OFF] =                 0xbc,
 218         [FBDC_REVISION_3_OFF] =                 0xc0,
 219         [FBDC_REVISION_4_OFF] =                 0xc4,
 220         [FBDC_REVISION_5_OFF] =                 0xc8,
 221         [FBDC_REVISION_6_OFF] =                 0xcc,
 222         [FBDC_COMMON_CONTROL_OFF] =             0xd0,
 223         [FBDC_CONSTANT_COLOR_0_OFF] =           0xd4,
 224         [FBDC_CONSTANT_COLOR_1_OFF] =           0xd8,
 225         [DISPC_CONNECTIONS_OFF] =               0xe4,
 226         [DISPC_MSS_VP1_OFF] =                   0xe8,
 227         [DISPC_MSS_VP3_OFF] =                   0xec,
 228 };
 229
 230 const struct dispc_features dispc_j721e_feats = {
 231         .max_pclk_khz = {
 232                 [DISPC_VP_DPI] = 170000,
 233                 [DISPC_VP_INTERNAL] = 600000,
 234         },
 235
 236         .scaling = {
 237                 .in_width_max_5tap_rgb = 2048,
 238                 .in_width_max_3tap_rgb = 4096,
 239                 .in_width_max_5tap_yuv = 4096,
 240                 .in_width_max_3tap_yuv = 4096,
 241                 .upscale_limit = 16,
 242                 .downscale_limit_5tap = 4,
 243                 .downscale_limit_3tap = 2,
 244                 /*
 245                  * The max supported pixel inc value is 255. The value
 246                  * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
 247                  * The maximum bpp of all formats supported by the HW
 248                  * is 8. So the maximum supported xinc value is 32,
 249                  * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
 250                  */
 251                 .xinc_max = 32,
 252         },
 253
 254         .subrev = DISPC_J721E,
 255
 256         .common = "common_m",
 257         .common_regs = tidss_j721e_common_regs,
 258
 259         .num_vps = 4,
 260         .vp_name = { "vp1", "vp2", "vp3", "vp4" },
 261         .ovr_name = { "ovr1", "ovr2", "ovr3", "ovr4" },
 262         .vpclk_name = { "vp1", "vp2", "vp3", "vp4" },
 263         /* Currently hard coded VP routing (see dispc_initial_config()) */
 264         .vp_bus_type =  { DISPC_VP_INTERNAL, DISPC_VP_DPI,
 265                           DISPC_VP_INTERNAL, DISPC_VP_DPI, },
 266         .vp_feat = { .color = {
 267                         .has_ctm = true,
 268                         .gamma_size = 1024,
 269                         .gamma_type = TIDSS_GAMMA_10BIT,
 270                 },
 271         },
 272         .num_planes = 4,
 273         .vid_name = { "vid1", "vidl1", "vid2", "vidl2" },
 274         .vid_lite = { 0, 1, 0, 1, },
 275         .vid_order = { 1, 3, 0, 2 },
 276 };
 277
 278 static const u16 *dispc_common_regmap;
 279
 280 struct dss_vp_data {
 281         u32 *gamma_table;
 282 };
 283
 284 struct dispc_device {
 285         struct tidss_device *tidss;
 286         struct device *dev;
 287
 288         void __iomem *base_common;
 289         void __iomem *base_vid[TIDSS_MAX_PLANES];
 290         void __iomem *base_ovr[TIDSS_MAX_PORTS];
 291         void __iomem *base_vp[TIDSS_MAX_PORTS];
 292
 293         struct regmap *oldi_io_ctrl;
 294
 295         struct clk *vp_clk[TIDSS_MAX_PORTS];
 296
 297         const struct dispc_features *feat;
 298
 299         struct clk *fclk;
 300
 301         bool is_enabled;
 302
 303         struct dss_vp_data vp_data[TIDSS_MAX_PORTS];
 304
 305         u32 *fourccs;
 306         u32 num_fourccs;
 307
 308         u32 memory_bandwidth_limit;
 309
 310         struct dispc_errata errata;
 311 };
 312
 313 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val)
 314 {
 315         iowrite32(val, dispc->base_common + reg);
 316 }
 317
 318 static u32 dispc_read(struct dispc_device *dispc, u16 reg)
 319 {
 320         return ioread32(dispc->base_common + reg);
 321 }
 322
 323 static
 324 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val)
 325 {
 326         void __iomem *base = dispc->base_vid[hw_plane];
 327
 328         iowrite32(val, base + reg);
 329 }
 330
 331 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg)
 332 {
 333         void __iomem *base = dispc->base_vid[hw_plane];
 334
 335         return ioread32(base + reg);
 336 }
 337
 338 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport,
 339                             u16 reg, u32 val)
 340 {
 341         void __iomem *base = dispc->base_ovr[hw_videoport];
 342
 343         iowrite32(val, base + reg);
 344 }
 345
 346 static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
 347 {
 348         void __iomem *base = dispc->base_ovr[hw_videoport];
 349
 350         return ioread32(base + reg);
 351 }
 352
 353 static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport,
 354                            u16 reg, u32 val)
 355 {
 356         void __iomem *base = dispc->base_vp[hw_videoport];
 357
 358         iowrite32(val, base + reg);
 359 }
 360
 361 static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
 362 {
 363         void __iomem *base = dispc->base_vp[hw_videoport];
 364
 365         return ioread32(base + reg);
 366 }
 367
 368 /*
 369  * TRM gives bitfields as start:end, where start is the higher bit
 370  * number. For example 7:0
 371  */
 372
 373 static u32 FLD_MASK(u32 start, u32 end)
 374 {
 375         return ((1 << (start - end + 1)) - 1) << end;
 376 }
 377
 378 static u32 FLD_VAL(u32 val, u32 start, u32 end)
 379 {
 380         return (val << end) & FLD_MASK(start, end);
 381 }
 382
 383 static u32 FLD_GET(u32 val, u32 start, u32 end)
 384 {
 385         return (val & FLD_MASK(start, end)) >> end;
 386 }
 387
 388 static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end)
 389 {
 390         return (orig & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end);
 391 }
 392
 393 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end)
 394 {
 395         return FLD_GET(dispc_read(dispc, idx), start, end);
 396 }
 397
 398 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val,
 399                         u32 start, u32 end)
 400 {
 401         dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val,
 402                                         start, end));
 403 }
 404
 405 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx,
 406                        u32 start, u32 end)
 407 {
 408         return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end);
 409 }
 410
 411 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx,
 412                             u32 val, u32 start, u32 end)
 413 {
 414         dispc_vid_write(dispc, hw_plane, idx,
 415                         FLD_MOD(dispc_vid_read(dispc, hw_plane, idx),
 416                                 val, start, end));
 417 }
 418
 419 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx,
 420                       u32 start, u32 end)
 421 {
 422         return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end);
 423 }
 424
 425 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val,
 426                            u32 start, u32 end)
 427 {
 428         dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx),
 429                                                val, start, end));
 430 }
 431
 432 __maybe_unused
 433 static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx,
 434                        u32 start, u32 end)
 435 {
 436         return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end);
 437 }
 438
 439 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx,
 440                             u32 val, u32 start, u32 end)
 441 {
 442         dispc_ovr_write(dispc, ovr, idx,
 443                         FLD_MOD(dispc_ovr_read(dispc, ovr, idx),
 444                                 val, start, end));
 445 }
 446
 447 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport)
 448 {
 449         dispc_irq_t vp_stat = 0;
 450
 451         if (stat & BIT(0))
 452                 vp_stat |= DSS_IRQ_VP_FRAME_DONE(hw_videoport);
 453         if (stat & BIT(1))
 454                 vp_stat |= DSS_IRQ_VP_VSYNC_EVEN(hw_videoport);
 455         if (stat & BIT(2))
 456                 vp_stat |= DSS_IRQ_VP_VSYNC_ODD(hw_videoport);
 457         if (stat & BIT(4))
 458                 vp_stat |= DSS_IRQ_VP_SYNC_LOST(hw_videoport);
 459
 460         return vp_stat;
 461 }
 462
 463 static u32 dispc_vp_irq_to_raw(dispc_irq_t vpstat, u32 hw_videoport)
 464 {
 465         u32 stat = 0;
 466
 467         if (vpstat & DSS_IRQ_VP_FRAME_DONE(hw_videoport))
 468                 stat |= BIT(0);
 469         if (vpstat & DSS_IRQ_VP_VSYNC_EVEN(hw_videoport))
 470                 stat |= BIT(1);
 471         if (vpstat & DSS_IRQ_VP_VSYNC_ODD(hw_videoport))
 472                 stat |= BIT(2);
 473         if (vpstat & DSS_IRQ_VP_SYNC_LOST(hw_videoport))
 474                 stat |= BIT(4);
 475
 476         return stat;
 477 }
 478
 479 static dispc_irq_t dispc_vid_irq_from_raw(u32 stat, u32 hw_plane)
 480 {
 481         dispc_irq_t vid_stat = 0;
 482
 483         if (stat & BIT(0))
 484                 vid_stat |= DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane);
 485
 486         return vid_stat;
 487 }
 488
 489 static u32 dispc_vid_irq_to_raw(dispc_irq_t vidstat, u32 hw_plane)
 490 {
 491         u32 stat = 0;
 492
 493         if (vidstat & DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane))
 494                 stat |= BIT(0);
 495
 496         return stat;
 497 }
 498
 499 static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc,
 500                                                u32 hw_videoport)
 501 {
 502         u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS);
 503
 504         return dispc_vp_irq_from_raw(stat, hw_videoport);
 505 }
 506
 507 static void dispc_k2g_vp_write_irqstatus(struct dispc_device *dispc,
 508                                          u32 hw_videoport, dispc_irq_t vpstat)
 509 {
 510         u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
 511
 512         dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat);
 513 }
 514
 515 static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc,
 516                                                 u32 hw_plane)
 517 {
 518         u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS);
 519
 520         return dispc_vid_irq_from_raw(stat, hw_plane);
 521 }
 522
 523 static void dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc,
 524                                           u32 hw_plane, dispc_irq_t vidstat)
 525 {
 526         u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
 527
 528         dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat);
 529 }
 530
 531 static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc,
 532                                                u32 hw_videoport)
 533 {
 534         u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE);
 535
 536         return dispc_vp_irq_from_raw(stat, hw_videoport);
 537 }
 538
 539 static void dispc_k2g_vp_set_irqenable(struct dispc_device *dispc,
 540                                        u32 hw_videoport, dispc_irq_t vpstat)
 541 {
 542         u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
 543
 544         dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat);
 545 }
 546
 547 static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc,
 548                                                 u32 hw_plane)
 549 {
 550         u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE);
 551
 552         return dispc_vid_irq_from_raw(stat, hw_plane);
 553 }
 554
 555 static void dispc_k2g_vid_set_irqenable(struct dispc_device *dispc,
 556                                         u32 hw_plane, dispc_irq_t vidstat)
 557 {
 558         u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
 559
 560         dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat);
 561 }
 562
 563 static void dispc_k2g_clear_irqstatus(struct dispc_device *dispc,
 564                                       dispc_irq_t mask)
 565 {
 566         dispc_k2g_vp_write_irqstatus(dispc, 0, mask);
 567         dispc_k2g_vid_write_irqstatus(dispc, 0, mask);
 568 }
 569
 570 static
 571 dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc)
 572 {
 573         dispc_irq_t stat = 0;
 574
 575         /* always clear the top level irqstatus */
 576         dispc_write(dispc, DISPC_IRQSTATUS,
 577                     dispc_read(dispc, DISPC_IRQSTATUS));
 578
 579         stat |= dispc_k2g_vp_read_irqstatus(dispc, 0);
 580         stat |= dispc_k2g_vid_read_irqstatus(dispc, 0);
 581
 582         dispc_k2g_clear_irqstatus(dispc, stat);
 583
 584         return stat;
 585 }
 586
 587 static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc)
 588 {
 589         dispc_irq_t stat = 0;
 590
 591         stat |= dispc_k2g_vp_read_irqenable(dispc, 0);
 592         stat |= dispc_k2g_vid_read_irqenable(dispc, 0);
 593
 594         return stat;
 595 }
 596
 597 static
 598 void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
 599 {
 600         dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc);
 601
 602         /* clear the irqstatus for newly enabled irqs */
 603         dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask);
 604
 605         dispc_k2g_vp_set_irqenable(dispc, 0, mask);
 606         dispc_k2g_vid_set_irqenable(dispc, 0, mask);
 607
 608         dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7));
 609
 610         /* flush posted write */
 611         dispc_k2g_read_irqenable(dispc);
 612 }
 613
 614 static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc,
 615                                               u32 hw_videoport)
 616 {
 617         u32 stat = dispc_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport));
 618
 619         return dispc_vp_irq_from_raw(stat, hw_videoport);
 620 }
 621
 622 static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc,
 623                                         u32 hw_videoport, dispc_irq_t vpstat)
 624 {
 625         u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
 626
 627         dispc_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat);
 628 }
 629
 630 static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc,
 631                                                u32 hw_plane)
 632 {
 633         u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane));
 634
 635         return dispc_vid_irq_from_raw(stat, hw_plane);
 636 }
 637
 638 static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc,
 639                                          u32 hw_plane, dispc_irq_t vidstat)
 640 {
 641         u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
 642
 643         dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat);
 644 }
 645
 646 static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc,
 647                                               u32 hw_videoport)
 648 {
 649         u32 stat = dispc_read(dispc, DISPC_VP_IRQENABLE(hw_videoport));
 650
 651         return dispc_vp_irq_from_raw(stat, hw_videoport);
 652 }
 653
 654 static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc,
 655                                       u32 hw_videoport, dispc_irq_t vpstat)
 656 {
 657         u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport);
 658
 659         dispc_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat);
 660 }
 661
 662 static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc,
 663                                                u32 hw_plane)
 664 {
 665         u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane));
 666
 667         return dispc_vid_irq_from_raw(stat, hw_plane);
 668 }
 669
 670 static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc,
 671                                        u32 hw_plane, dispc_irq_t vidstat)
 672 {
 673         u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane);
 674
 675         dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat);
 676 }
 677
 678 static
 679 void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask)
 680 {
 681         unsigned int i;
 682         u32 top_clear = 0;
 683
 684         for (i = 0; i < dispc->feat->num_vps; ++i) {
 685                 if (clearmask & DSS_IRQ_VP_MASK(i)) {
 686                         dispc_k3_vp_write_irqstatus(dispc, i, clearmask);
 687                         top_clear |= BIT(i);
 688                 }
 689         }
 690         for (i = 0; i < dispc->feat->num_planes; ++i) {
 691                 if (clearmask & DSS_IRQ_PLANE_MASK(i)) {
 692                         dispc_k3_vid_write_irqstatus(dispc, i, clearmask);
 693                         top_clear |= BIT(4 + i);
 694                 }
 695         }
 696         if (dispc->feat->subrev == DISPC_K2G)
 697                 return;
 698
 699         dispc_write(dispc, DISPC_IRQSTATUS, top_clear);
 700
 701         /* Flush posted writes */
 702         dispc_read(dispc, DISPC_IRQSTATUS);
 703 }
 704
 705 static
 706 dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc)
 707 {
 708         dispc_irq_t status = 0;
 709         unsigned int i;
 710
 711         for (i = 0; i < dispc->feat->num_vps; ++i)
 712                 status |= dispc_k3_vp_read_irqstatus(dispc, i);
 713
 714         for (i = 0; i < dispc->feat->num_planes; ++i)
 715                 status |= dispc_k3_vid_read_irqstatus(dispc, i);
 716
 717         dispc_k3_clear_irqstatus(dispc, status);
 718
 719         return status;
 720 }
 721
 722 static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc)
 723 {
 724         dispc_irq_t enable = 0;
 725         unsigned int i;
 726
 727         for (i = 0; i < dispc->feat->num_vps; ++i)
 728                 enable |= dispc_k3_vp_read_irqenable(dispc, i);
 729
 730         for (i = 0; i < dispc->feat->num_planes; ++i)
 731                 enable |= dispc_k3_vid_read_irqenable(dispc, i);
 732
 733         return enable;
 734 }
 735
 736 static void dispc_k3_set_irqenable(struct dispc_device *dispc,
 737                                    dispc_irq_t mask)
 738 {
 739         unsigned int i;
 740         u32 main_enable = 0, main_disable = 0;
 741         dispc_irq_t old_mask;
 742
 743         old_mask = dispc_k3_read_irqenable(dispc);
 744
 745         /* clear the irqstatus for newly enabled irqs */
 746         dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask);
 747
 748         for (i = 0; i < dispc->feat->num_vps; ++i) {
 749                 dispc_k3_vp_set_irqenable(dispc, i, mask);
 750                 if (mask & DSS_IRQ_VP_MASK(i))
 751                         main_enable |= BIT(i);          /* VP IRQ */
 752                 else
 753                         main_disable |= BIT(i);         /* VP IRQ */
 754         }
 755
 756         for (i = 0; i < dispc->feat->num_planes; ++i) {
 757                 dispc_k3_vid_set_irqenable(dispc, i, mask);
 758                 if (mask & DSS_IRQ_PLANE_MASK(i))
 759                         main_enable |= BIT(i + 4);      /* VID IRQ */
 760                 else
 761                         main_disable |= BIT(i + 4);     /* VID IRQ */
 762         }
 763
 764         if (main_enable)
 765                 dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable);
 766
 767         if (main_disable)
 768                 dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable);
 769
 770         /* Flush posted writes */
 771         dispc_read(dispc, DISPC_IRQENABLE_SET);
 772 }
 773
 774 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc)
 775 {
 776         switch (dispc->feat->subrev) {
 777         case DISPC_K2G:
 778                 return dispc_k2g_read_and_clear_irqstatus(dispc);
 779         case DISPC_AM65X:
 780         case DISPC_J721E:
 781                 return dispc_k3_read_and_clear_irqstatus(dispc);
 782         default:
 783                 WARN_ON(1);
 784                 return 0;
 785         }
 786 }
 787
 788 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
 789 {
 790         switch (dispc->feat->subrev) {
 791         case DISPC_K2G:
 792                 dispc_k2g_set_irqenable(dispc, mask);
 793                 break;
 794         case DISPC_AM65X:
 795         case DISPC_J721E:
 796                 dispc_k3_set_irqenable(dispc, mask);
 797                 break;
 798         default:
 799                 WARN_ON(1);
 800                 break;
 801         }
 802 }
 803
 804 enum dispc_oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 };
 805
 806 struct dispc_bus_format {
 807         u32 bus_fmt;
 808         u32 data_width;
 809         bool is_oldi_fmt;
 810         enum dispc_oldi_mode_reg_val oldi_mode_reg_val;
 811 };
 812
 813 static const struct dispc_bus_format dispc_bus_formats[] = {
 814         { MEDIA_BUS_FMT_RGB444_1X12,            12, false, 0 },
 815         { MEDIA_BUS_FMT_RGB565_1X16,            16, false, 0 },
 816         { MEDIA_BUS_FMT_RGB666_1X18,            18, false, 0 },
 817         { MEDIA_BUS_FMT_RGB888_1X24,            24, false, 0 },
 818         { MEDIA_BUS_FMT_RGB101010_1X30,         30, false, 0 },
 819         { MEDIA_BUS_FMT_RGB121212_1X36,         36, false, 0 },
 820         { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,      18, true, SPWG_18 },
 821         { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,      24, true, SPWG_24 },
 822         { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,     24, true, JEIDA_24 },
 823 };
 824
 825 static const
 826 struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc,
 827                                                u32 hw_videoport,
 828                                                u32 bus_fmt, u32 bus_flags)
 829 {
 830         unsigned int i;
 831
 832         for (i = 0; i < ARRAY_SIZE(dispc_bus_formats); ++i) {
 833                 if (dispc_bus_formats[i].bus_fmt == bus_fmt)
 834                         return &dispc_bus_formats[i];
 835         }
 836
 837         return NULL;
 838 }
 839
 840 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport,
 841                        const struct drm_crtc_state *state)
 842 {
 843         const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state);
 844         const struct dispc_bus_format *fmt;
 845
 846         fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
 847                                     tstate->bus_flags);
 848         if (!fmt) {
 849                 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n",
 850                         __func__, tstate->bus_format);
 851                 return -EINVAL;
 852         }
 853
 854         if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI &&
 855             fmt->is_oldi_fmt) {
 856                 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n",
 857                         __func__, dispc->feat->vp_name[hw_videoport]);
 858                 return -EINVAL;
 859         }
 860
 861         return 0;
 862 }
 863
 864 static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power)
 865 {
 866         u32 val = power ? 0 : OLDI_PWRDN_TX;
 867
 868         if (WARN_ON(!dispc->oldi_io_ctrl))
 869                 return;
 870
 871         regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL,
 872                            OLDI_PWRDN_TX, val);
 873         regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL,
 874                            OLDI_PWRDN_TX, val);
 875         regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL,
 876                            OLDI_PWRDN_TX, val);
 877         regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL,
 878                            OLDI_PWRDN_TX, val);
 879         regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL,
 880                            OLDI_PWRDN_TX, val);
 881 }
 882
 883 static void dispc_set_num_datalines(struct dispc_device *dispc,
 884                                     u32 hw_videoport, int num_lines)
 885 {
 886         int v;
 887
 888         switch (num_lines) {
 889         case 12:
 890                 v = 0; break;
 891         case 16:
 892                 v = 1; break;
 893         case 18:
 894                 v = 2; break;
 895         case 24:
 896                 v = 3; break;
 897         case 30:
 898                 v = 4; break;
 899         case 36:
 900                 v = 5; break;
 901         default:
 902                 WARN_ON(1);
 903                 v = 3;
 904         }
 905
 906         VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8);
 907 }
 908
 909 static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport,
 910                               const struct dispc_bus_format *fmt)
 911 {
 912         u32 oldi_cfg = 0;
 913         u32 oldi_reset_bit = BIT(5 + hw_videoport);
 914         int count = 0;
 915
 916         /*
 917          * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC
 918          * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0.
 919          */
 920
 921         if (fmt->data_width == 24)
 922                 oldi_cfg |= BIT(8); /* MSB */
 923         else if (fmt->data_width != 18)
 924                 dev_warn(dispc->dev, "%s: %d port width not supported\n",
 925                          __func__, fmt->data_width);
 926
 927         oldi_cfg |= BIT(7); /* DEPOL */
 928
 929         oldi_cfg = FLD_MOD(oldi_cfg, fmt->oldi_mode_reg_val, 3, 1);
 930
 931         oldi_cfg |= BIT(12); /* SOFTRST */
 932
 933         oldi_cfg |= BIT(0); /* ENABLE */
 934
 935         dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
 936
 937         while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) &&
 938                count < 10000)
 939                 count++;
 940
 941         if (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)))
 942                 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n",
 943                          __func__);
 944 }
 945
 946 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
 947                       const struct drm_crtc_state *state)
 948 {
 949         const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state);
 950         const struct dispc_bus_format *fmt;
 951
 952         fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
 953                                     tstate->bus_flags);
 954
 955         if (WARN_ON(!fmt))
 956                 return;
 957
 958         if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) {
 959                 dispc_oldi_tx_power(dispc, true);
 960
 961                 dispc_enable_oldi(dispc, hw_videoport, fmt);
 962         }
 963 }
 964
 965 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
 966                      const struct drm_crtc_state *state)
 967 {
 968         const struct drm_display_mode *mode = &state->adjusted_mode;
 969         const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state);
 970         bool align, onoff, rf, ieo, ipc, ihs, ivs;
 971         const struct dispc_bus_format *fmt;
 972         u32 hsw, hfp, hbp, vsw, vfp, vbp;
 973
 974         fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
 975                                     tstate->bus_flags);
 976
 977         if (WARN_ON(!fmt))
 978                 return;
 979
 980         dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width);
 981
 982         hfp = mode->hsync_start - mode->hdisplay;
 983         hsw = mode->hsync_end - mode->hsync_start;
 984         hbp = mode->htotal - mode->hsync_end;
 985
 986         vfp = mode->vsync_start - mode->vdisplay;
 987         vsw = mode->vsync_end - mode->vsync_start;
 988         vbp = mode->vtotal - mode->vsync_end;
 989
 990         dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
 991                        FLD_VAL(hsw - 1, 7, 0) |
 992                        FLD_VAL(hfp - 1, 19, 8) |
 993                        FLD_VAL(hbp - 1, 31, 20));
 994
 995         dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
 996                        FLD_VAL(vsw - 1, 7, 0) |
 997                        FLD_VAL(vfp, 19, 8) |
 998                        FLD_VAL(vbp, 31, 20));
 999
1000         ivs = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1001
1002         ihs = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1003
1004         ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW);
1005
1006         ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE);
1007
1008         /* always use the 'rf' setting */
1009         onoff = true;
1010
1011         rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE);
1012
1013         /* always use aligned syncs */
1014         align = true;
1015
1016         /* always use DE_HIGH for OLDI */
1017         if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI)
1018                 ieo = false;
1019
1020         dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ,
1021                        FLD_VAL(align, 18, 18) |
1022                        FLD_VAL(onoff, 17, 17) |
1023                        FLD_VAL(rf, 16, 16) |
1024                        FLD_VAL(ieo, 15, 15) |
1025                        FLD_VAL(ipc, 14, 14) |
1026                        FLD_VAL(ihs, 13, 13) |
1027                        FLD_VAL(ivs, 12, 12));
1028
1029         dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
1030                        FLD_VAL(mode->hdisplay - 1, 11, 0) |
1031                        FLD_VAL(mode->vdisplay - 1, 27, 16));
1032
1033         VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0);
1034 }
1035
1036 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport)
1037 {
1038         VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0);
1039 }
1040
1041 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport)
1042 {
1043         if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) {
1044                 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0);
1045
1046                 dispc_oldi_tx_power(dispc, false);
1047         }
1048 }
1049
1050 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport)
1051 {
1052         return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5);
1053 }
1054
1055 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport)
1056 {
1057         WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5));
1058         VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5);
1059 }
1060
1061 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN };
1062
1063 static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode)
1064 {
1065         u16 c12;
1066
1067         c12 = c8 << 4;
1068
1069         switch (mode) {
1070         case C8_TO_C12_REPLICATE:
1071                 /* Copy c8 4 MSB to 4 LSB for full scale c12 */
1072                 c12 |= c8 >> 4;
1073                 break;
1074         case C8_TO_C12_MAX:
1075                 c12 |= 0xF;
1076                 break;
1077         default:
1078         case C8_TO_C12_MIN:
1079                 break;
1080         }
1081
1082         return c12;
1083 }
1084
1085 static u64 argb8888_to_argb12121212(u32 argb8888, enum c8_to_c12_mode m)
1086 {
1087         u8 a, r, g, b;
1088         u64 v;
1089
1090         a = (argb8888 >> 24) & 0xff;
1091         r = (argb8888 >> 16) & 0xff;
1092         g = (argb8888 >> 8) & 0xff;
1093         b = (argb8888 >> 0) & 0xff;
1094
1095         v = ((u64)c8_to_c12(a, m) << 36) | ((u64)c8_to_c12(r, m) << 24) |
1096                 ((u64)c8_to_c12(g, m) << 12) | (u64)c8_to_c12(b, m);
1097
1098         return v;
1099 }
1100
1101 static void dispc_vp_set_default_color(struct dispc_device *dispc,
1102                                        u32 hw_videoport, u32 default_color)
1103 {
1104         u64 v;
1105
1106         v = argb8888_to_argb12121212(default_color, C8_TO_C12_REPLICATE);
1107
1108         dispc_ovr_write(dispc, hw_videoport,
1109                         DISPC_OVR_DEFAULT_COLOR, v & 0xffffffff);
1110         dispc_ovr_write(dispc, hw_videoport,
1111                         DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff);
1112 }
1113
1114 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
1115                                          u32 hw_videoport,
1116                                          const struct drm_display_mode *mode)
1117 {
1118         u32 hsw, hfp, hbp, vsw, vfp, vbp;
1119         enum dispc_vp_bus_type bus_type;
1120         int max_pclk;
1121
1122         bus_type = dispc->feat->vp_bus_type[hw_videoport];
1123
1124         max_pclk = dispc->feat->max_pclk_khz[bus_type];
1125
1126         if (WARN_ON(max_pclk == 0))
1127                 return MODE_BAD;
1128
1129         if (mode->clock < dispc->feat->min_pclk_khz)
1130                 return MODE_CLOCK_LOW;
1131
1132         if (mode->clock > max_pclk)
1133                 return MODE_CLOCK_HIGH;
1134
1135         if (mode->hdisplay > 4096)
1136                 return MODE_BAD;
1137
1138         if (mode->vdisplay > 4096)
1139                 return MODE_BAD;
1140
1141         /* TODO: add interlace support */
1142         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1143                 return MODE_NO_INTERLACE;
1144
1145         /*
1146          * Enforce the output width is divisible by 2. Actually this
1147          * is only needed in following cases:
1148          * - YUV output selected (BT656, BT1120)
1149          * - Dithering enabled
1150          * - TDM with TDMCycleFormat == 3
1151          * But for simplicity we enforce that always.
1152          */
1153         if ((mode->hdisplay % 2) != 0)
1154                 return MODE_BAD_HVALUE;
1155
1156         hfp = mode->hsync_start - mode->hdisplay;
1157         hsw = mode->hsync_end - mode->hsync_start;
1158         hbp = mode->htotal - mode->hsync_end;
1159
1160         vfp = mode->vsync_start - mode->vdisplay;
1161         vsw = mode->vsync_end - mode->vsync_start;
1162         vbp = mode->vtotal - mode->vsync_end;
1163
1164         if (hsw < 1 || hsw > 256 ||
1165             hfp < 1 || hfp > 4096 ||
1166             hbp < 1 || hbp > 4096)
1167                 return MODE_BAD_HVALUE;
1168
1169         if (vsw < 1 || vsw > 256 ||
1170             vfp > 4095 || vbp > 4095)
1171                 return MODE_BAD_VVALUE;
1172
1173         if (dispc->memory_bandwidth_limit) {
1174                 const unsigned int bpp = 4;
1175                 u64 bandwidth;
1176
1177                 bandwidth = 1000 * mode->clock;
1178                 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;
1179                 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);
1180
1181                 if (dispc->memory_bandwidth_limit < bandwidth)
1182                         return MODE_BAD;
1183         }
1184
1185         return MODE_OK;
1186 }
1187
1188 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport)
1189 {
1190         int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]);
1191
1192         if (ret)
1193                 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__,
1194                         ret);
1195
1196         return ret;
1197 }
1198
1199 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport)
1200 {
1201         clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
1202 }
1203
1204 /*
1205  * Calculate the percentage difference between the requested pixel clock rate
1206  * and the effective rate resulting from calculating the clock divider value.
1207  */
1208 static
1209 unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
1210 {
1211         int r = rate / 100, rr = real_rate / 100;
1212
1213         return (unsigned int)(abs(((rr - r) * 100) / r));
1214 }
1215
1216 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
1217                           unsigned long rate)
1218 {
1219         int r;
1220         unsigned long new_rate;
1221
1222         r = clk_set_rate(dispc->vp_clk[hw_videoport], rate);
1223         if (r) {
1224                 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n",
1225                         hw_videoport, rate);
1226                 return r;
1227         }
1228
1229         new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]);
1230
1231         if (dispc_pclk_diff(rate, new_rate) > 5)
1232                 dev_warn(dispc->dev,
1233                          "vp%d: Clock rate %lu differs over 5%% from requested %lu\n",
1234                          hw_videoport, new_rate, rate);
1235
1236         dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n",
1237                 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate);
1238
1239         return 0;
1240 }
1241
1242 /* OVR */
1243 static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc,
1244                                     u32 hw_plane, u32 hw_videoport,
1245                                     u32 x, u32 y, u32 layer)
1246 {
1247         /* On k2g there is only one plane and no need for ovr */
1248         dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION,
1249                         x | (y << 16));
1250 }
1251
1252 static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc,
1253                                       u32 hw_plane, u32 hw_videoport,
1254                                       u32 x, u32 y, u32 layer)
1255 {
1256         OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1257                         hw_plane, 4, 1);
1258         OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1259                         x, 17, 6);
1260         OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1261                         y, 30, 19);
1262 }
1263
1264 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc,
1265                                       u32 hw_plane, u32 hw_videoport,
1266                                       u32 x, u32 y, u32 layer)
1267 {
1268         OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1269                         hw_plane, 4, 1);
1270         OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1271                         x, 13, 0);
1272         OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1273                         y, 29, 16);
1274 }
1275
1276 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
1277                          u32 hw_videoport, u32 x, u32 y, u32 layer)
1278 {
1279         switch (dispc->feat->subrev) {
1280         case DISPC_K2G:
1281                 dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport,
1282                                         x, y, layer);
1283                 break;
1284         case DISPC_AM65X:
1285                 dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport,
1286                                           x, y, layer);
1287                 break;
1288         case DISPC_J721E:
1289                 dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport,
1290                                           x, y, layer);
1291                 break;
1292         default:
1293                 WARN_ON(1);
1294                 break;
1295         }
1296 }
1297
1298 void dispc_ovr_enable_layer(struct dispc_device *dispc,
1299                             u32 hw_videoport, u32 layer, bool enable)
1300 {
1301         if (dispc->feat->subrev == DISPC_K2G)
1302                 return;
1303
1304         OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1305                         !!enable, 0, 0);
1306 }
1307
1308 /* CSC */
1309 enum csc_ctm {
1310         CSC_RR, CSC_RG, CSC_RB,
1311         CSC_GR, CSC_GG, CSC_GB,
1312         CSC_BR, CSC_BG, CSC_BB,
1313 };
1314
1315 enum csc_yuv2rgb {
1316         CSC_RY, CSC_RCB, CSC_RCR,
1317         CSC_GY, CSC_GCB, CSC_GCR,
1318         CSC_BY, CSC_BCB, CSC_BCR,
1319 };
1320
1321 enum csc_rgb2yuv {
1322         CSC_YR,  CSC_YG,  CSC_YB,
1323         CSC_CBR, CSC_CBG, CSC_CBB,
1324         CSC_CRR, CSC_CRG, CSC_CRB,
1325 };
1326
1327 struct dispc_csc_coef {
1328         void (*to_regval)(const struct dispc_csc_coef *csc, u32 *regval);
1329         int m[9];
1330         int preoffset[3];
1331         int postoffset[3];
1332         enum { CLIP_LIMITED_RANGE = 0, CLIP_FULL_RANGE = 1, } cliping;
1333         const char *name;
1334 };
1335
1336 #define DISPC_CSC_REGVAL_LEN 8
1337
1338 static
1339 void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval)
1340 {
1341 #define OVAL(x, y) (FLD_VAL(x, 15, 3) | FLD_VAL(y, 31, 19))
1342         regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]);
1343         regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]);
1344         regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]);
1345 #undef OVAL
1346 }
1347
1348 #define CVAL(x, y) (FLD_VAL(x, 10, 0) | FLD_VAL(y, 26, 16))
1349 static
1350 void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regval)
1351 {
1352         regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]);
1353         regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]);
1354         regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]);
1355         regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]);
1356         regval[4] = CVAL(csc->m[CSC_BCB], 0);
1357
1358         dispc_csc_offset_regval(csc, regval);
1359 }
1360
1361 __maybe_unused static
1362 void dispc_csc_rgb2yuv_regval(const struct dispc_csc_coef *csc, u32 *regval)
1363 {
1364         regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]);
1365         regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]);
1366         regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]);
1367         regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]);
1368         regval[4] = CVAL(csc->m[CSC_CBB], 0);
1369
1370         dispc_csc_offset_regval(csc, regval);
1371 }
1372
1373 static void dispc_csc_cpr_regval(const struct dispc_csc_coef *csc,
1374                                  u32 *regval)
1375 {
1376         regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]);
1377         regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]);
1378         regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]);
1379         regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]);
1380         regval[4] = CVAL(csc->m[CSC_BB], 0);
1381
1382         dispc_csc_offset_regval(csc, regval);
1383 }
1384
1385 #undef CVAL
1386
1387 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,
1388                                     const struct dispc_csc_coef *csc)
1389 {
1390         static const u16 dispc_vid_csc_coef_reg[] = {
1391                 DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1),
1392                 DISPC_VID_CSC_COEF(2), DISPC_VID_CSC_COEF(3),
1393                 DISPC_VID_CSC_COEF(4), DISPC_VID_CSC_COEF(5),
1394                 DISPC_VID_CSC_COEF(6), /* K2G has no post offset support */
1395         };
1396         u32 regval[DISPC_CSC_REGVAL_LEN];
1397         unsigned int i;
1398
1399         csc->to_regval(csc, regval);
1400
1401         if (regval[7] != 0)
1402                 dev_warn(dispc->dev, "%s: No post offset support for %s\n",
1403                          __func__, csc->name);
1404
1405         for (i = 0; i < ARRAY_SIZE(dispc_vid_csc_coef_reg); i++)
1406                 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1407                                 regval[i]);
1408 }
1409
1410 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,
1411                                    const struct dispc_csc_coef *csc)
1412 {
1413         static const u16 dispc_vid_csc_coef_reg[DISPC_CSC_REGVAL_LEN] = {
1414                 DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1),
1415                 DISPC_VID_CSC_COEF(2), DISPC_VID_CSC_COEF(3),
1416                 DISPC_VID_CSC_COEF(4), DISPC_VID_CSC_COEF(5),
1417                 DISPC_VID_CSC_COEF(6), DISPC_VID_CSC_COEF7,
1418         };
1419         u32 regval[DISPC_CSC_REGVAL_LEN];
1420         unsigned int i;
1421
1422         csc->to_regval(csc, regval);
1423
1424         for (i = 0; i < ARRAY_SIZE(dispc_vid_csc_coef_reg); i++)
1425                 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1426                                 regval[i]);
1427 }
1428
1429 /* YUV -> RGB, ITU-R BT.601, full range */
1430 static const struct dispc_csc_coef csc_yuv2rgb_bt601_full = {
1431         dispc_csc_yuv2rgb_regval,
1432         { 256,   0,  358,       /* ry, rcb, rcr |1.000  0.000  1.402|*/
1433           256, -88, -182,       /* gy, gcb, gcr |1.000 -0.344 -0.714|*/
1434           256, 452,    0, },    /* by, bcb, bcr |1.000  1.772  0.000|*/
1435         {    0, -2048, -2048, },        /* full range */
1436         {    0,     0,     0, },
1437         CLIP_FULL_RANGE,
1438         "BT.601 Full",
1439 };
1440
1441 /* YUV -> RGB, ITU-R BT.601, limited range */
1442 static const struct dispc_csc_coef csc_yuv2rgb_bt601_lim = {
1443         dispc_csc_yuv2rgb_regval,
1444         { 298,    0,  409,      /* ry, rcb, rcr |1.164  0.000  1.596|*/
1445           298, -100, -208,      /* gy, gcb, gcr |1.164 -0.392 -0.813|*/
1446           298,  516,    0, },   /* by, bcb, bcr |1.164  2.017  0.000|*/
1447         { -256, -2048, -2048, },        /* limited range */
1448         {    0,     0,     0, },
1449         CLIP_FULL_RANGE,
1450         "BT.601 Limited",
1451 };
1452
1453 /* YUV -> RGB, ITU-R BT.709, full range */
1454 static const struct dispc_csc_coef csc_yuv2rgb_bt709_full = {
1455         dispc_csc_yuv2rgb_regval,
1456         { 256,    0,  402,      /* ry, rcb, rcr |1.000  0.000  1.570|*/
1457           256,  -48, -120,      /* gy, gcb, gcr |1.000 -0.187 -0.467|*/
1458           256,  475,    0, },   /* by, bcb, bcr |1.000  1.856  0.000|*/
1459         {    0, -2048, -2048, },        /* full range */
1460         {    0,     0,     0, },
1461         CLIP_FULL_RANGE,
1462         "BT.709 Full",
1463 };
1464
1465 /* YUV -> RGB, ITU-R BT.709, limited range */
1466 static const struct dispc_csc_coef csc_yuv2rgb_bt709_lim = {
1467         dispc_csc_yuv2rgb_regval,
1468         { 298,    0,  459,      /* ry, rcb, rcr |1.164  0.000  1.793|*/
1469           298,  -55, -136,      /* gy, gcb, gcr |1.164 -0.213 -0.533|*/
1470           298,  541,    0, },   /* by, bcb, bcr |1.164  2.112  0.000|*/
1471         { -256, -2048, -2048, },        /* limited range */
1472         {    0,     0,     0, },
1473         CLIP_FULL_RANGE,
1474         "BT.709 Limited",
1475 };
1476
1477 static const struct {
1478         enum drm_color_encoding encoding;
1479         enum drm_color_range range;
1480         const struct dispc_csc_coef *csc;
1481 } dispc_csc_table[] = {
1482         { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_FULL_RANGE,
1483           &csc_yuv2rgb_bt601_full, },
1484         { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_LIMITED_RANGE,
1485           &csc_yuv2rgb_bt601_lim, },
1486         { DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_FULL_RANGE,
1487           &csc_yuv2rgb_bt709_full, },
1488         { DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE,
1489           &csc_yuv2rgb_bt709_lim, },
1490 };
1491
1492 static const
1493 struct dispc_csc_coef *dispc_find_csc(enum drm_color_encoding encoding,
1494                                       enum drm_color_range range)
1495 {
1496         unsigned int i;
1497
1498         for (i = 0; i < ARRAY_SIZE(dispc_csc_table); i++) {
1499                 if (dispc_csc_table[i].encoding == encoding &&
1500                     dispc_csc_table[i].range == range) {
1501                         return dispc_csc_table[i].csc;
1502                 }
1503         }
1504         return NULL;
1505 }
1506
1507 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane,
1508                                 const struct drm_plane_state *state)
1509 {
1510         const struct dispc_csc_coef *coef;
1511
1512         coef = dispc_find_csc(state->color_encoding, state->color_range);
1513         if (!coef) {
1514                 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n",
1515                         __func__, state->color_encoding, state->color_range);
1516                 return;
1517         }
1518
1519         if (dispc->feat->subrev == DISPC_K2G)
1520                 dispc_k2g_vid_write_csc(dispc, hw_plane, coef);
1521         else
1522                 dispc_k3_vid_write_csc(dispc, hw_plane, coef);
1523 }
1524
1525 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane,
1526                                  bool enable)
1527 {
1528         VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9);
1529 }
1530
1531 /* SCALER */
1532
1533 static u32 dispc_calc_fir_inc(u32 in, u32 out)
1534 {
1535         return (u32)div_u64(0x200000ull * in, out);
1536 }
1537
1538 enum dispc_vid_fir_coef_set {
1539         DISPC_VID_FIR_COEF_HORIZ,
1540         DISPC_VID_FIR_COEF_HORIZ_UV,
1541         DISPC_VID_FIR_COEF_VERT,
1542         DISPC_VID_FIR_COEF_VERT_UV,
1543 };
1544
1545 static void dispc_vid_write_fir_coefs(struct dispc_device *dispc,
1546                                       u32 hw_plane,
1547                                       enum dispc_vid_fir_coef_set coef_set,
1548                                       const struct tidss_scale_coefs *coefs)
1549 {
1550         static const u16 c0_regs[] = {
1551                 [DISPC_VID_FIR_COEF_HORIZ] = DISPC_VID_FIR_COEFS_H0,
1552                 [DISPC_VID_FIR_COEF_HORIZ_UV] = DISPC_VID_FIR_COEFS_H0_C,
1553                 [DISPC_VID_FIR_COEF_VERT] = DISPC_VID_FIR_COEFS_V0,
1554                 [DISPC_VID_FIR_COEF_VERT_UV] = DISPC_VID_FIR_COEFS_V0_C,
1555         };
1556
1557         static const u16 c12_regs[] = {
1558                 [DISPC_VID_FIR_COEF_HORIZ] = DISPC_VID_FIR_COEFS_H12,
1559                 [DISPC_VID_FIR_COEF_HORIZ_UV] = DISPC_VID_FIR_COEFS_H12_C,
1560                 [DISPC_VID_FIR_COEF_VERT] = DISPC_VID_FIR_COEFS_V12,
1561                 [DISPC_VID_FIR_COEF_VERT_UV] = DISPC_VID_FIR_COEFS_V12_C,
1562         };
1563
1564         const u16 c0_base = c0_regs[coef_set];
1565         const u16 c12_base = c12_regs[coef_set];
1566         int phase;
1567
1568         if (!coefs) {
1569                 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__);
1570                 return;
1571         }
1572
1573         for (phase = 0; phase <= 8; ++phase) {
1574                 u16 reg = c0_base + phase * 4;
1575                 u16 c0 = coefs->c0[phase];
1576
1577                 dispc_vid_write(dispc, hw_plane, reg, c0);
1578         }
1579
1580         for (phase = 0; phase <= 15; ++phase) {
1581                 u16 reg = c12_base + phase * 4;
1582                 s16 c1, c2;
1583                 u32 c12;
1584
1585                 c1 = coefs->c1[phase];
1586                 c2 = coefs->c2[phase];
1587                 c12 = FLD_VAL(c1, 19, 10) | FLD_VAL(c2, 29, 20);
1588
1589                 dispc_vid_write(dispc, hw_plane, reg, c12);
1590         }
1591 }
1592
1593 static bool dispc_fourcc_is_yuv(u32 fourcc)
1594 {
1595         switch (fourcc) {
1596         case DRM_FORMAT_YUYV:
1597         case DRM_FORMAT_UYVY:
1598         case DRM_FORMAT_NV12:
1599                 return true;
1600         default:
1601                 return false;
1602         }
1603 }
1604
1605 struct dispc_scaling_params {
1606         int xinc, yinc;
1607         u32 in_w, in_h, in_w_uv, in_h_uv;
1608         u32 fir_xinc, fir_yinc, fir_xinc_uv, fir_yinc_uv;
1609         bool scale_x, scale_y;
1610         const struct tidss_scale_coefs *xcoef, *ycoef, *xcoef_uv, *ycoef_uv;
1611         bool five_taps;
1612 };
1613
1614 static int dispc_vid_calc_scaling(struct dispc_device *dispc,
1615                                   const struct drm_plane_state *state,
1616                                   struct dispc_scaling_params *sp,
1617                                   bool lite_plane)
1618 {
1619         const struct dispc_features_scaling *f = &dispc->feat->scaling;
1620         u32 fourcc = state->fb->format->format;
1621         u32 in_width_max_5tap = f->in_width_max_5tap_rgb;
1622         u32 in_width_max_3tap = f->in_width_max_3tap_rgb;
1623         u32 downscale_limit;
1624         u32 in_width_max;
1625
1626         memset(sp, 0, sizeof(*sp));
1627         sp->xinc = 1;
1628         sp->yinc = 1;
1629         sp->in_w = state->src_w >> 16;
1630         sp->in_w_uv = sp->in_w;
1631         sp->in_h = state->src_h >> 16;
1632         sp->in_h_uv = sp->in_h;
1633
1634         sp->scale_x = sp->in_w != state->crtc_w;
1635         sp->scale_y = sp->in_h != state->crtc_h;
1636
1637         if (dispc_fourcc_is_yuv(fourcc)) {
1638                 in_width_max_5tap = f->in_width_max_5tap_yuv;
1639                 in_width_max_3tap = f->in_width_max_3tap_yuv;
1640
1641                 sp->in_w_uv >>= 1;
1642                 sp->scale_x = true;
1643
1644                 if (fourcc == DRM_FORMAT_NV12) {
1645                         sp->in_h_uv >>= 1;
1646                         sp->scale_y = true;
1647                 }
1648         }
1649
1650         /* Skip the rest if no scaling is used */
1651         if ((!sp->scale_x && !sp->scale_y) || lite_plane)
1652                 return 0;
1653
1654         if (sp->in_w > in_width_max_5tap) {
1655                 sp->five_taps = false;
1656                 in_width_max = in_width_max_3tap;
1657                 downscale_limit = f->downscale_limit_3tap;
1658         } else {
1659                 sp->five_taps = true;
1660                 in_width_max = in_width_max_5tap;
1661                 downscale_limit = f->downscale_limit_5tap;
1662         }
1663
1664         if (sp->scale_x) {
1665                 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w);
1666
1667                 if (sp->fir_xinc < dispc_calc_fir_inc(1, f->upscale_limit)) {
1668                         dev_dbg(dispc->dev,
1669                                 "%s: X-scaling factor %u/%u > %u\n",
1670                                 __func__, state->crtc_w, state->src_w >> 16,
1671                                 f->upscale_limit);
1672                         return -EINVAL;
1673                 }
1674
1675                 if (sp->fir_xinc >= dispc_calc_fir_inc(downscale_limit, 1)) {
1676                         sp->xinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_w,
1677                                                              state->crtc_w),
1678                                                 downscale_limit);
1679
1680                         if (sp->xinc > f->xinc_max) {
1681                                 dev_dbg(dispc->dev,
1682                                         "%s: X-scaling factor %u/%u < 1/%u\n",
1683                                         __func__, state->crtc_w,
1684                                         state->src_w >> 16,
1685                                         downscale_limit * f->xinc_max);
1686                                 return -EINVAL;
1687                         }
1688
1689                         sp->in_w = (state->src_w >> 16) / sp->xinc;
1690                 }
1691
1692                 while (sp->in_w > in_width_max) {
1693                         sp->xinc++;
1694                         sp->in_w = (state->src_w >> 16) / sp->xinc;
1695                 }
1696
1697                 if (sp->xinc > f->xinc_max) {
1698                         dev_dbg(dispc->dev,
1699                                 "%s: Too wide input buffer %u > %u\n", __func__,
1700                                 state->src_w >> 16, in_width_max * f->xinc_max);
1701                         return -EINVAL;
1702                 }
1703
1704                 /*
1705                  * We need even line length for YUV formats. Decimation
1706                  * can lead to odd length, so we need to make it even
1707                  * again.
1708                  */
1709                 if (dispc_fourcc_is_yuv(fourcc))
1710                         sp->in_w &= ~1;
1711
1712                 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w);
1713         }
1714
1715         if (sp->scale_y) {
1716                 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, state->crtc_h);
1717
1718                 if (sp->fir_yinc < dispc_calc_fir_inc(1, f->upscale_limit)) {
1719                         dev_dbg(dispc->dev,
1720                                 "%s: Y-scaling factor %u/%u > %u\n",
1721                                 __func__, state->crtc_h, state->src_h >> 16,
1722                                 f->upscale_limit);
1723                         return -EINVAL;
1724                 }
1725
1726                 if (sp->fir_yinc >= dispc_calc_fir_inc(downscale_limit, 1)) {
1727                         sp->yinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_h,
1728                                                              state->crtc_h),
1729                                                 downscale_limit);
1730
1731                         sp->in_h /= sp->yinc;
1732                         sp->fir_yinc = dispc_calc_fir_inc(sp->in_h,
1733                                                           state->crtc_h);
1734                 }
1735         }
1736
1737         dev_dbg(dispc->dev,
1738                 "%s: %ux%u decim %ux%u -> %ux%u firinc %u.%03ux%u.%03u taps %u -> %ux%u\n",
1739                 __func__, state->src_w >> 16, state->src_h >> 16,
1740                 sp->xinc, sp->yinc, sp->in_w, sp->in_h,
1741                 sp->fir_xinc / 0x200000u,
1742                 ((sp->fir_xinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu,
1743                 sp->fir_yinc / 0x200000u,
1744                 ((sp->fir_yinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu,
1745                 sp->five_taps ? 5 : 3,
1746                 state->crtc_w, state->crtc_h);
1747
1748         if (dispc_fourcc_is_yuv(fourcc)) {
1749                 if (sp->scale_x) {
1750                         sp->in_w_uv /= sp->xinc;
1751                         sp->fir_xinc_uv = dispc_calc_fir_inc(sp->in_w_uv,
1752                                                              state->crtc_w);
1753                         sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev,
1754                                                              sp->fir_xinc_uv,
1755                                                              true);
1756                 }
1757                 if (sp->scale_y) {
1758                         sp->in_h_uv /= sp->yinc;
1759                         sp->fir_yinc_uv = dispc_calc_fir_inc(sp->in_h_uv,
1760                                                              state->crtc_h);
1761                         sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev,
1762                                                              sp->fir_yinc_uv,
1763                                                              sp->five_taps);
1764                 }
1765         }
1766
1767         if (sp->scale_x)
1768                 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc,
1769                                                   true);
1770
1771         if (sp->scale_y)
1772                 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc,
1773                                                   sp->five_taps);
1774
1775         return 0;
1776 }
1777
1778 static void dispc_vid_set_scaling(struct dispc_device *dispc,
1779                                   u32 hw_plane,
1780                                   struct dispc_scaling_params *sp,
1781                                   u32 fourcc)
1782 {
1783         /* HORIZONTAL RESIZE ENABLE */
1784         VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1785                         sp->scale_x, 7, 7);
1786
1787         /* VERTICAL RESIZE ENABLE */
1788         VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1789                         sp->scale_y, 8, 8);
1790
1791         /* Skip the rest if no scaling is used */
1792         if (!sp->scale_x && !sp->scale_y)
1793                 return;
1794
1795         /* VERTICAL 5-TAPS  */
1796         VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1797                         sp->five_taps, 21, 21);
1798
1799         if (dispc_fourcc_is_yuv(fourcc)) {
1800                 if (sp->scale_x) {
1801                         dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2,
1802                                         sp->fir_xinc_uv);
1803                         dispc_vid_write_fir_coefs(dispc, hw_plane,
1804                                                   DISPC_VID_FIR_COEF_HORIZ_UV,
1805                                                   sp->xcoef_uv);
1806                 }
1807                 if (sp->scale_y) {
1808                         dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2,
1809                                         sp->fir_yinc_uv);
1810                         dispc_vid_write_fir_coefs(dispc, hw_plane,
1811                                                   DISPC_VID_FIR_COEF_VERT_UV,
1812                                                   sp->ycoef_uv);
1813                 }
1814         }
1815
1816         if (sp->scale_x) {
1817                 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc);
1818                 dispc_vid_write_fir_coefs(dispc, hw_plane,
1819                                           DISPC_VID_FIR_COEF_HORIZ,
1820                                           sp->xcoef);
1821         }
1822
1823         if (sp->scale_y) {
1824                 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc);
1825                 dispc_vid_write_fir_coefs(dispc, hw_plane,
1826                                           DISPC_VID_FIR_COEF_VERT, sp->ycoef);
1827         }
1828 }
1829
1830 /* OTHER */
1831
1832 static const struct {
1833         u32 fourcc;
1834         u8 dss_code;
1835 } dispc_color_formats[] = {
1836         { DRM_FORMAT_ARGB4444, 0x0, },
1837         { DRM_FORMAT_ABGR4444, 0x1, },
1838         { DRM_FORMAT_RGBA4444, 0x2, },
1839
1840         { DRM_FORMAT_RGB565, 0x3, },
1841         { DRM_FORMAT_BGR565, 0x4, },
1842
1843         { DRM_FORMAT_ARGB1555, 0x5, },
1844         { DRM_FORMAT_ABGR1555, 0x6, },
1845
1846         { DRM_FORMAT_ARGB8888, 0x7, },
1847         { DRM_FORMAT_ABGR8888, 0x8, },
1848         { DRM_FORMAT_RGBA8888, 0x9, },
1849         { DRM_FORMAT_BGRA8888, 0xa, },
1850
1851         { DRM_FORMAT_RGB888, 0xb, },
1852         { DRM_FORMAT_BGR888, 0xc, },
1853
1854         { DRM_FORMAT_ARGB2101010, 0xe, },
1855         { DRM_FORMAT_ABGR2101010, 0xf, },
1856
1857         { DRM_FORMAT_XRGB4444, 0x20, },
1858         { DRM_FORMAT_XBGR4444, 0x21, },
1859         { DRM_FORMAT_RGBX4444, 0x22, },
1860
1861         { DRM_FORMAT_XRGB1555, 0x25, },
1862         { DRM_FORMAT_XBGR1555, 0x26, },
1863
1864         { DRM_FORMAT_XRGB8888, 0x27, },
1865         { DRM_FORMAT_XBGR8888, 0x28, },
1866         { DRM_FORMAT_RGBX8888, 0x29, },
1867         { DRM_FORMAT_BGRX8888, 0x2a, },
1868
1869         { DRM_FORMAT_XRGB2101010, 0x2e, },
1870         { DRM_FORMAT_XBGR2101010, 0x2f, },
1871
1872         { DRM_FORMAT_YUYV, 0x3e, },
1873         { DRM_FORMAT_UYVY, 0x3f, },
1874
1875         { DRM_FORMAT_NV12, 0x3d, },
1876 };
1877
1878 static void dispc_plane_set_pixel_format(struct dispc_device *dispc,
1879                                          u32 hw_plane, u32 fourcc)
1880 {
1881         unsigned int i;
1882
1883         for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) {
1884                 if (dispc_color_formats[i].fourcc == fourcc) {
1885                         VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1886                                         dispc_color_formats[i].dss_code,
1887                                         6, 1);
1888                         return;
1889                 }
1890         }
1891
1892         WARN_ON(1);
1893 }
1894
1895 const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len)
1896 {
1897         WARN_ON(!dispc->fourccs);
1898
1899         *len = dispc->num_fourccs;
1900
1901         return dispc->fourccs;
1902 }
1903
1904 static s32 pixinc(int pixels, u8 ps)
1905 {
1906         if (pixels == 1)
1907                 return 1;
1908         else if (pixels > 1)
1909                 return 1 + (pixels - 1) * ps;
1910         else if (pixels < 0)
1911                 return 1 - (-pixels + 1) * ps;
1912
1913         WARN_ON(1);
1914         return 0;
1915 }
1916
1917 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
1918                       const struct drm_plane_state *state,
1919                       u32 hw_videoport)
1920 {
1921         bool lite = dispc->feat->vid_lite[hw_plane];
1922         u32 fourcc = state->fb->format->format;
1923         bool need_scaling = state->src_w >> 16 != state->crtc_w ||
1924                 state->src_h >> 16 != state->crtc_h;
1925         struct dispc_scaling_params scaling;
1926         int ret;
1927
1928         if (dispc_fourcc_is_yuv(fourcc)) {
1929                 if (!dispc_find_csc(state->color_encoding,
1930                                     state->color_range)) {
1931                         dev_dbg(dispc->dev,
1932                                 "%s: Unsupported CSC (%u,%u) for HW plane %u\n",
1933                                 __func__, state->color_encoding,
1934                                 state->color_range, hw_plane);
1935                         return -EINVAL;
1936                 }
1937         }
1938
1939         if (need_scaling) {
1940                 if (lite) {
1941                         dev_dbg(dispc->dev,
1942                                 "%s: Lite plane %u can't scale %ux%u!=%ux%u\n",
1943                                 __func__, hw_plane,
1944                                 state->src_w >> 16, state->src_h >> 16,
1945                                 state->crtc_w, state->crtc_h);
1946                         return -EINVAL;
1947                 }
1948                 ret = dispc_vid_calc_scaling(dispc, state, &scaling, false);
1949                 if (ret)
1950                         return ret;
1951         }
1952
1953         return 0;
1954 }
1955
1956 static
1957 dma_addr_t dispc_plane_state_dma_addr(const struct drm_plane_state *state)
1958 {
1959         struct drm_framebuffer *fb = state->fb;
1960         struct drm_gem_dma_object *gem;
1961         u32 x = state->src_x >> 16;
1962         u32 y = state->src_y >> 16;
1963
1964         gem = drm_fb_dma_get_gem_obj(state->fb, 0);
1965
1966         return gem->dma_addr + fb->offsets[0] + x * fb->format->cpp[0] +
1967                 y * fb->pitches[0];
1968 }
1969
1970 static
1971 dma_addr_t dispc_plane_state_p_uv_addr(const struct drm_plane_state *state)
1972 {
1973         struct drm_framebuffer *fb = state->fb;
1974         struct drm_gem_dma_object *gem;
1975         u32 x = state->src_x >> 16;
1976         u32 y = state->src_y >> 16;
1977
1978         if (WARN_ON(state->fb->format->num_planes != 2))
1979                 return 0;
1980
1981         gem = drm_fb_dma_get_gem_obj(fb, 1);
1982
1983         return gem->dma_addr + fb->offsets[1] +
1984                 (x * fb->format->cpp[1] / fb->format->hsub) +
1985                 (y * fb->pitches[1] / fb->format->vsub);
1986 }
1987
1988 void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
1989                        const struct drm_plane_state *state,
1990                        u32 hw_videoport)
1991 {
1992         bool lite = dispc->feat->vid_lite[hw_plane];
1993         u32 fourcc = state->fb->format->format;
1994         u16 cpp = state->fb->format->cpp[0];
1995         u32 fb_width = state->fb->pitches[0] / cpp;
1996         dma_addr_t dma_addr = dispc_plane_state_dma_addr(state);
1997         struct dispc_scaling_params scale;
1998
1999         dispc_vid_calc_scaling(dispc, state, &scale, lite);
2000
2001         dispc_plane_set_pixel_format(dispc, hw_plane, fourcc);
2002
2003         dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);
2004         dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);
2005         dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);
2006         dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);
2007
2008         dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,
2009                         (scale.in_w - 1) | ((scale.in_h - 1) << 16));
2010
2011         /* For YUV422 format we use the macropixel size for pixel inc */
2012         if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY)
2013                 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2014                                 pixinc(scale.xinc, cpp * 2));
2015         else
2016                 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2017                                 pixinc(scale.xinc, cpp));
2018
2019         dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,
2020                         pixinc(1 + (scale.yinc * fb_width -
2021                                     scale.xinc * scale.in_w),
2022                                cpp));
2023
2024         if (state->fb->format->num_planes == 2) {
2025                 u16 cpp_uv = state->fb->format->cpp[1];
2026                 u32 fb_width_uv = state->fb->pitches[1] / cpp_uv;
2027                 dma_addr_t p_uv_addr = dispc_plane_state_p_uv_addr(state);
2028
2029                 dispc_vid_write(dispc, hw_plane,
2030                                 DISPC_VID_BA_UV_0, p_uv_addr & 0xffffffff);
2031                 dispc_vid_write(dispc, hw_plane,
2032                                 DISPC_VID_BA_UV_EXT_0, (u64)p_uv_addr >> 32);
2033                 dispc_vid_write(dispc, hw_plane,
2034                                 DISPC_VID_BA_UV_1, p_uv_addr & 0xffffffff);
2035                 dispc_vid_write(dispc, hw_plane,
2036                                 DISPC_VID_BA_UV_EXT_1, (u64)p_uv_addr >> 32);
2037
2038                 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV,
2039                                 pixinc(1 + (scale.yinc * fb_width_uv -
2040                                             scale.xinc * scale.in_w_uv),
2041                                        cpp_uv));
2042         }
2043
2044         if (!lite) {
2045                 dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE,
2046                                 (state->crtc_w - 1) |
2047                                 ((state->crtc_h - 1) << 16));
2048
2049                 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc);
2050         }
2051
2052         /* enable YUV->RGB color conversion */
2053         if (dispc_fourcc_is_yuv(fourcc)) {
2054                 dispc_vid_csc_setup(dispc, hw_plane, state);
2055                 dispc_vid_csc_enable(dispc, hw_plane, true);
2056         } else {
2057                 dispc_vid_csc_enable(dispc, hw_plane, false);
2058         }
2059
2060         dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA,
2061                         0xFF & (state->alpha >> 8));
2062
2063         if (state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
2064                 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
2065                                 28, 28);
2066         else
2067                 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
2068                                 28, 28);
2069 }
2070
2071 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable)
2072 {
2073         VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0);
2074 }
2075
2076 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane)
2077 {
2078         return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0);
2079 }
2080
2081 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc,
2082                                           u32 hw_plane, u32 low, u32 high)
2083 {
2084         dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD,
2085                         FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
2086 }
2087
2088 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc,
2089                                         u32 hw_plane, u32 low, u32 high)
2090 {
2091         dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD,
2092                         FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
2093 }
2094
2095 static void dispc_k2g_plane_init(struct dispc_device *dispc)
2096 {
2097         unsigned int hw_plane;
2098
2099         dev_dbg(dispc->dev, "%s()\n", __func__);
2100
2101         /* MFLAG_CTRL = ENABLED */
2102         REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
2103         /* MFLAG_START = MFLAGNORMALSTARTMODE */
2104         REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
2105
2106         for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
2107                 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
2108                 u32 thr_low, thr_high;
2109                 u32 mflag_low, mflag_high;
2110                 u32 preload;
2111
2112                 thr_high = size - 1;
2113                 thr_low = size / 2;
2114
2115                 mflag_high = size * 2 / 3;
2116                 mflag_low = size / 3;
2117
2118                 preload = thr_low;
2119
2120                 dev_dbg(dispc->dev,
2121                         "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n",
2122                         dispc->feat->vid_name[hw_plane],
2123                         size,
2124                         thr_high, thr_low,
2125                         mflag_high, mflag_low,
2126                         preload);
2127
2128                 dispc_vid_set_buf_threshold(dispc, hw_plane,
2129                                             thr_low, thr_high);
2130                 dispc_vid_set_mflag_threshold(dispc, hw_plane,
2131                                               mflag_low, mflag_high);
2132
2133                 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
2134
2135                 /*
2136                  * Prefetch up to fifo high-threshold value to minimize the
2137                  * possibility of underflows. Note that this means the PRELOAD
2138                  * register is ignored.
2139                  */
2140                 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
2141                                 19, 19);
2142         }
2143 }
2144
2145 static void dispc_k3_plane_init(struct dispc_device *dispc)
2146 {
2147         unsigned int hw_plane;
2148         u32 cba_lo_pri = 1;
2149         u32 cba_hi_pri = 0;
2150
2151         dev_dbg(dispc->dev, "%s()\n", __func__);
2152
2153         REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0);
2154         REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3);
2155
2156         /* MFLAG_CTRL = ENABLED */
2157         REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
2158         /* MFLAG_START = MFLAGNORMALSTARTMODE */
2159         REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
2160
2161         for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
2162                 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
2163                 u32 thr_low, thr_high;
2164                 u32 mflag_low, mflag_high;
2165                 u32 preload;
2166
2167                 thr_high = size - 1;
2168                 thr_low = size / 2;
2169
2170                 mflag_high = size * 2 / 3;
2171                 mflag_low = size / 3;
2172
2173                 preload = thr_low;
2174
2175                 dev_dbg(dispc->dev,
2176                         "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n",
2177                         dispc->feat->vid_name[hw_plane],
2178                         size,
2179                         thr_high, thr_low,
2180                         mflag_high, mflag_low,
2181                         preload);
2182
2183                 dispc_vid_set_buf_threshold(dispc, hw_plane,
2184                                             thr_low, thr_high);
2185                 dispc_vid_set_mflag_threshold(dispc, hw_plane,
2186                                               mflag_low, mflag_high);
2187
2188                 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
2189
2190                 /* Prefech up to PRELOAD value */
2191                 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
2192                                 19, 19);
2193         }
2194 }
2195
2196 static void dispc_plane_init(struct dispc_device *dispc)
2197 {
2198         switch (dispc->feat->subrev) {
2199         case DISPC_K2G:
2200                 dispc_k2g_plane_init(dispc);
2201                 break;
2202         case DISPC_AM65X:
2203         case DISPC_J721E:
2204                 dispc_k3_plane_init(dispc);
2205                 break;
2206         default:
2207                 WARN_ON(1);
2208         }
2209 }
2210
2211 static void dispc_vp_init(struct dispc_device *dispc)
2212 {
2213         unsigned int i;
2214
2215         dev_dbg(dispc->dev, "%s()\n", __func__);
2216
2217         /* Enable the gamma Shadow bit-field for all VPs*/
2218         for (i = 0; i < dispc->feat->num_vps; i++)
2219                 VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2);
2220 }
2221
2222 static void dispc_initial_config(struct dispc_device *dispc)
2223 {
2224         dispc_plane_init(dispc);
2225         dispc_vp_init(dispc);
2226
2227         /* Note: Hardcoded DPI routing on J721E for now */
2228         if (dispc->feat->subrev == DISPC_J721E) {
2229                 dispc_write(dispc, DISPC_CONNECTIONS,
2230                             FLD_VAL(2, 3, 0) |          /* VP1 to DPI0 */
2231                             FLD_VAL(8, 7, 4)            /* VP3 to DPI1 */
2232                         );
2233         }
2234 }
2235
2236 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc,
2237                                            u32 hw_videoport)
2238 {
2239         u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2240         u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2241         unsigned int i;
2242
2243         dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2244
2245         if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT))
2246                 return;
2247
2248         for (i = 0; i < hwlen; ++i) {
2249                 u32 v = table[i];
2250
2251                 v |= i << 24;
2252
2253                 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE,
2254                                v);
2255         }
2256 }
2257
2258 static void dispc_am65x_vp_write_gamma_table(struct dispc_device *dispc,
2259                                              u32 hw_videoport)
2260 {
2261         u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2262         u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2263         unsigned int i;
2264
2265         dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2266
2267         if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT))
2268                 return;
2269
2270         for (i = 0; i < hwlen; ++i) {
2271                 u32 v = table[i];
2272
2273                 v |= i << 24;
2274
2275                 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2276         }
2277 }
2278
2279 static void dispc_j721e_vp_write_gamma_table(struct dispc_device *dispc,
2280                                              u32 hw_videoport)
2281 {
2282         u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2283         u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2284         unsigned int i;
2285
2286         dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2287
2288         if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT))
2289                 return;
2290
2291         for (i = 0; i < hwlen; ++i) {
2292                 u32 v = table[i];
2293
2294                 if (i == 0)
2295                         v |= 1 << 31;
2296
2297                 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2298         }
2299 }
2300
2301 static void dispc_vp_write_gamma_table(struct dispc_device *dispc,
2302                                        u32 hw_videoport)
2303 {
2304         switch (dispc->feat->subrev) {
2305         case DISPC_K2G:
2306                 dispc_k2g_vp_write_gamma_table(dispc, hw_videoport);
2307                 break;
2308         case DISPC_AM65X:
2309                 dispc_am65x_vp_write_gamma_table(dispc, hw_videoport);
2310                 break;
2311         case DISPC_J721E:
2312                 dispc_j721e_vp_write_gamma_table(dispc, hw_videoport);
2313                 break;
2314         default:
2315                 WARN_ON(1);
2316                 break;
2317         }
2318 }
2319
2320 static const struct drm_color_lut dispc_vp_gamma_default_lut[] = {
2321         { .red = 0, .green = 0, .blue = 0, },
2322         { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },
2323 };
2324
2325 static void dispc_vp_set_gamma(struct dispc_device *dispc,
2326                                u32 hw_videoport,
2327                                const struct drm_color_lut *lut,
2328                                unsigned int length)
2329 {
2330         u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2331         u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2332         u32 hwbits;
2333         unsigned int i;
2334
2335         dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n",
2336                 __func__, hw_videoport, length, hwlen);
2337
2338         if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT)
2339                 hwbits = 10;
2340         else
2341                 hwbits = 8;
2342
2343         if (!lut || length < 2) {
2344                 lut = dispc_vp_gamma_default_lut;
2345                 length = ARRAY_SIZE(dispc_vp_gamma_default_lut);
2346         }
2347
2348         for (i = 0; i < length - 1; ++i) {
2349                 unsigned int first = i * (hwlen - 1) / (length - 1);
2350                 unsigned int last = (i + 1) * (hwlen - 1) / (length - 1);
2351                 unsigned int w = last - first;
2352                 u16 r, g, b;
2353                 unsigned int j;
2354
2355                 if (w == 0)
2356                         continue;
2357
2358                 for (j = 0; j <= w; j++) {
2359                         r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w;
2360                         g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w;
2361                         b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w;
2362
2363                         r >>= 16 - hwbits;
2364                         g >>= 16 - hwbits;
2365                         b >>= 16 - hwbits;
2366
2367                         table[first + j] = (r << (hwbits * 2)) |
2368                                 (g << hwbits) | b;
2369                 }
2370         }
2371
2372         dispc_vp_write_gamma_table(dispc, hw_videoport);
2373 }
2374
2375 static s16 dispc_S31_32_to_s2_8(s64 coef)
2376 {
2377         u64 sign_bit = 1ULL << 63;
2378         u64 cbits = (u64)coef;
2379         s16 ret;
2380
2381         if (cbits & sign_bit)
2382                 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x200);
2383         else
2384                 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x1FF);
2385
2386         return ret;
2387 }
2388
2389 static void dispc_k2g_cpr_from_ctm(const struct drm_color_ctm *ctm,
2390                                    struct dispc_csc_coef *cpr)
2391 {
2392         memset(cpr, 0, sizeof(*cpr));
2393
2394         cpr->to_regval = dispc_csc_cpr_regval;
2395         cpr->m[CSC_RR] = dispc_S31_32_to_s2_8(ctm->matrix[0]);
2396         cpr->m[CSC_RG] = dispc_S31_32_to_s2_8(ctm->matrix[1]);
2397         cpr->m[CSC_RB] = dispc_S31_32_to_s2_8(ctm->matrix[2]);
2398         cpr->m[CSC_GR] = dispc_S31_32_to_s2_8(ctm->matrix[3]);
2399         cpr->m[CSC_GG] = dispc_S31_32_to_s2_8(ctm->matrix[4]);
2400         cpr->m[CSC_GB] = dispc_S31_32_to_s2_8(ctm->matrix[5]);
2401         cpr->m[CSC_BR] = dispc_S31_32_to_s2_8(ctm->matrix[6]);
2402         cpr->m[CSC_BG] = dispc_S31_32_to_s2_8(ctm->matrix[7]);
2403         cpr->m[CSC_BB] = dispc_S31_32_to_s2_8(ctm->matrix[8]);
2404 }
2405
2406 #define CVAL(xR, xG, xB) (FLD_VAL(xR, 9, 0) | FLD_VAL(xG, 20, 11) |     \
2407                           FLD_VAL(xB, 31, 22))
2408
2409 static void dispc_k2g_vp_csc_cpr_regval(const struct dispc_csc_coef *csc,
2410                                         u32 *regval)
2411 {
2412         regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]);
2413         regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]);
2414         regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]);
2415 }
2416
2417 #undef CVAL
2418
2419 static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2420                                    const struct dispc_csc_coef *csc)
2421 {
2422         static const u16 dispc_vp_cpr_coef_reg[] = {
2423                 DISPC_VP_CSC_COEF0, DISPC_VP_CSC_COEF1, DISPC_VP_CSC_COEF2,
2424                 /* K2G CPR is packed to three registers. */
2425         };
2426         u32 regval[DISPC_CSC_REGVAL_LEN];
2427         unsigned int i;
2428
2429         dispc_k2g_vp_csc_cpr_regval(csc, regval);
2430
2431         for (i = 0; i < ARRAY_SIZE(dispc_vp_cpr_coef_reg); i++)
2432                 dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i],
2433                                regval[i]);
2434 }
2435
2436 static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2437                                  struct drm_color_ctm *ctm)
2438 {
2439         u32 cprenable = 0;
2440
2441         if (ctm) {
2442                 struct dispc_csc_coef cpr;
2443
2444                 dispc_k2g_cpr_from_ctm(ctm, &cpr);
2445                 dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr);
2446                 cprenable = 1;
2447         }
2448
2449         VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2450                        cprenable, 15, 15);
2451 }
2452
2453 static s16 dispc_S31_32_to_s3_8(s64 coef)
2454 {
2455         u64 sign_bit = 1ULL << 63;
2456         u64 cbits = (u64)coef;
2457         s16 ret;
2458
2459         if (cbits & sign_bit)
2460                 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x400);
2461         else
2462                 ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x3FF);
2463
2464         return ret;
2465 }
2466
2467 static void dispc_csc_from_ctm(const struct drm_color_ctm *ctm,
2468                                struct dispc_csc_coef *cpr)
2469 {
2470         memset(cpr, 0, sizeof(*cpr));
2471
2472         cpr->to_regval = dispc_csc_cpr_regval;
2473         cpr->m[CSC_RR] = dispc_S31_32_to_s3_8(ctm->matrix[0]);
2474         cpr->m[CSC_RG] = dispc_S31_32_to_s3_8(ctm->matrix[1]);
2475         cpr->m[CSC_RB] = dispc_S31_32_to_s3_8(ctm->matrix[2]);
2476         cpr->m[CSC_GR] = dispc_S31_32_to_s3_8(ctm->matrix[3]);
2477         cpr->m[CSC_GG] = dispc_S31_32_to_s3_8(ctm->matrix[4]);
2478         cpr->m[CSC_GB] = dispc_S31_32_to_s3_8(ctm->matrix[5]);
2479         cpr->m[CSC_BR] = dispc_S31_32_to_s3_8(ctm->matrix[6]);
2480         cpr->m[CSC_BG] = dispc_S31_32_to_s3_8(ctm->matrix[7]);
2481         cpr->m[CSC_BB] = dispc_S31_32_to_s3_8(ctm->matrix[8]);
2482 }
2483
2484 static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2485                                   const struct dispc_csc_coef *csc)
2486 {
2487         static const u16 dispc_vp_csc_coef_reg[DISPC_CSC_REGVAL_LEN] = {
2488                 DISPC_VP_CSC_COEF0, DISPC_VP_CSC_COEF1, DISPC_VP_CSC_COEF2,
2489                 DISPC_VP_CSC_COEF3, DISPC_VP_CSC_COEF4, DISPC_VP_CSC_COEF5,
2490                 DISPC_VP_CSC_COEF6, DISPC_VP_CSC_COEF7,
2491         };
2492         u32 regval[DISPC_CSC_REGVAL_LEN];
2493         unsigned int i;
2494
2495         csc->to_regval(csc, regval);
2496
2497         for (i = 0; i < ARRAY_SIZE(regval); i++)
2498                 dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i],
2499                                regval[i]);
2500 }
2501
2502 static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2503                                 struct drm_color_ctm *ctm)
2504 {
2505         u32 colorconvenable = 0;
2506
2507         if (ctm) {
2508                 struct dispc_csc_coef csc;
2509
2510                 dispc_csc_from_ctm(ctm, &csc);
2511                 dispc_k3_vp_write_csc(dispc, hw_videoport, &csc);
2512                 colorconvenable = 1;
2513         }
2514
2515         VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2516                        colorconvenable, 24, 24);
2517 }
2518
2519 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc,
2520                                     u32 hw_videoport,
2521                                     const struct drm_crtc_state *state,
2522                                     bool newmodeset)
2523 {
2524         struct drm_color_lut *lut = NULL;
2525         struct drm_color_ctm *ctm = NULL;
2526         unsigned int length = 0;
2527
2528         if (!(state->color_mgmt_changed || newmodeset))
2529                 return;
2530
2531         if (state->gamma_lut) {
2532                 lut = (struct drm_color_lut *)state->gamma_lut->data;
2533                 length = state->gamma_lut->length / sizeof(*lut);
2534         }
2535
2536         dispc_vp_set_gamma(dispc, hw_videoport, lut, length);
2537
2538         if (state->ctm)
2539                 ctm = (struct drm_color_ctm *)state->ctm->data;
2540
2541         if (dispc->feat->subrev == DISPC_K2G)
2542                 dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm);
2543         else
2544                 dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm);
2545 }
2546
2547 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport,
2548                     const struct drm_crtc_state *state, bool newmodeset)
2549 {
2550         dispc_vp_set_default_color(dispc, hw_videoport, 0);
2551         dispc_vp_set_color_mgmt(dispc, hw_videoport, state, newmodeset);
2552 }
2553
2554 int dispc_runtime_suspend(struct dispc_device *dispc)
2555 {
2556         dev_dbg(dispc->dev, "suspend\n");
2557
2558         dispc->is_enabled = false;
2559
2560         clk_disable_unprepare(dispc->fclk);
2561
2562         return 0;
2563 }
2564
2565 int dispc_runtime_resume(struct dispc_device *dispc)
2566 {
2567         dev_dbg(dispc->dev, "resume\n");
2568
2569         clk_prepare_enable(dispc->fclk);
2570
2571         if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) == 0)
2572                 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n");
2573
2574         dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n",
2575                 dispc_read(dispc, DSS_REVISION));
2576
2577         dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n",
2578                 REG_GET(dispc, DSS_SYSSTATUS, 1, 1),
2579                 REG_GET(dispc, DSS_SYSSTATUS, 2, 2),
2580                 REG_GET(dispc, DSS_SYSSTATUS, 3, 3));
2581
2582         if (dispc->feat->subrev == DISPC_AM65X)
2583                 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n",
2584                         REG_GET(dispc, DSS_SYSSTATUS, 5, 5),
2585                         REG_GET(dispc, DSS_SYSSTATUS, 6, 6),
2586                         REG_GET(dispc, DSS_SYSSTATUS, 7, 7));
2587
2588         dev_dbg(dispc->dev, "DISPC IDLE %d\n",
2589                 REG_GET(dispc, DSS_SYSSTATUS, 9, 9));
2590
2591         dispc_initial_config(dispc);
2592
2593         dispc->is_enabled = true;
2594
2595         tidss_irq_resume(dispc->tidss);
2596
2597         return 0;
2598 }
2599
2600 void dispc_remove(struct tidss_device *tidss)
2601 {
2602         dev_dbg(tidss->dev, "%s\n", __func__);
2603
2604         tidss->dispc = NULL;
2605 }
2606
2607 static int dispc_iomap_resource(struct platform_device *pdev, const char *name,
2608                                 void __iomem **base)
2609 {
2610         void __iomem *b;
2611
2612         b = devm_platform_ioremap_resource_byname(pdev, name);
2613         if (IS_ERR(b)) {
2614                 dev_err(&pdev->dev, "cannot ioremap resource '%s'\n", name);
2615                 return PTR_ERR(b);
2616         }
2617
2618         *base = b;
2619
2620         return 0;
2621 }
2622
2623 static int dispc_init_am65x_oldi_io_ctrl(struct device *dev,
2624                                          struct dispc_device *dispc)
2625 {
2626         dispc->oldi_io_ctrl =
2627                 syscon_regmap_lookup_by_phandle(dev->of_node,
2628                                                 "ti,am65x-oldi-io-ctrl");
2629         if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) {
2630                 dispc->oldi_io_ctrl = NULL;
2631         } else if (IS_ERR(dispc->oldi_io_ctrl)) {
2632                 dev_err(dev, "%s: syscon_regmap_lookup_by_phandle failed %ld\n",
2633                         __func__, PTR_ERR(dispc->oldi_io_ctrl));
2634                 return PTR_ERR(dispc->oldi_io_ctrl);
2635         }
2636         return 0;
2637 }
2638
2639 static void dispc_init_errata(struct dispc_device *dispc)
2640 {
2641         static const struct soc_device_attribute am65x_sr10_soc_devices[] = {
2642                 { .family = "AM65X", .revision = "SR1.0" },
2643                 { /* sentinel */ }
2644         };
2645
2646         if (soc_device_match(am65x_sr10_soc_devices)) {
2647                 dispc->errata.i2000 = true;
2648                 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n");
2649         }
2650 }
2651
2652 static void dispc_softreset(struct dispc_device *dispc)
2653 {
2654         u32 val;
2655         int ret = 0;
2656
2657         /* Soft reset */
2658         REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
2659         /* Wait for reset to complete */
2660         ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS,
2661                                  val, val & 1, 100, 5000);
2662         if (ret)
2663                 dev_warn(dispc->dev, "failed to reset dispc\n");
2664 }
2665
2666 int dispc_init(struct tidss_device *tidss)
2667 {
2668         struct device *dev = tidss->dev;
2669         struct platform_device *pdev = to_platform_device(dev);
2670         struct dispc_device *dispc;
2671         const struct dispc_features *feat;
2672         unsigned int i, num_fourccs;
2673         int r = 0;
2674
2675         dev_dbg(dev, "%s\n", __func__);
2676
2677         feat = tidss->feat;
2678
2679         if (feat->subrev != DISPC_K2G) {
2680                 r = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
2681                 if (r)
2682                         dev_warn(dev, "cannot set DMA masks to 48-bit\n");
2683         }
2684
2685         dma_set_max_seg_size(dev, UINT_MAX);
2686
2687         dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL);
2688         if (!dispc)
2689                 return -ENOMEM;
2690
2691         dispc->tidss = tidss;
2692         dispc->dev = dev;
2693         dispc->feat = feat;
2694
2695         dispc_init_errata(dispc);
2696
2697         dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats),
2698                                       sizeof(*dispc->fourccs), GFP_KERNEL);
2699         if (!dispc->fourccs)
2700                 return -ENOMEM;
2701
2702         num_fourccs = 0;
2703         for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) {
2704                 if (dispc->errata.i2000 &&
2705                     dispc_fourcc_is_yuv(dispc_color_formats[i].fourcc)) {
2706                         continue;
2707                 }
2708                 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc;
2709         }
2710
2711         dispc->num_fourccs = num_fourccs;
2712
2713         dispc_common_regmap = dispc->feat->common_regs;
2714
2715         r = dispc_iomap_resource(pdev, dispc->feat->common,
2716                                  &dispc->base_common);
2717         if (r)
2718                 return r;
2719
2720         for (i = 0; i < dispc->feat->num_planes; i++) {
2721                 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i],
2722                                          &dispc->base_vid[i]);
2723                 if (r)
2724                         return r;
2725         }
2726
2727         /* K2G display controller does not support soft reset */
2728         if (feat->subrev != DISPC_K2G)
2729                 dispc_softreset(dispc);
2730
2731         for (i = 0; i < dispc->feat->num_vps; i++) {
2732                 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size;
2733                 u32 *gamma_table;
2734                 struct clk *clk;
2735
2736                 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i],
2737                                          &dispc->base_ovr[i]);
2738                 if (r)
2739                         return r;
2740
2741                 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i],
2742                                          &dispc->base_vp[i]);
2743                 if (r)
2744                         return r;
2745
2746                 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]);
2747                 if (IS_ERR(clk)) {
2748                         dev_err(dev, "%s: Failed to get clk %s:%ld\n", __func__,
2749                                 dispc->feat->vpclk_name[i], PTR_ERR(clk));
2750                         return PTR_ERR(clk);
2751                 }
2752                 dispc->vp_clk[i] = clk;
2753
2754                 gamma_table = devm_kmalloc_array(dev, gamma_size,
2755                                                  sizeof(*gamma_table),
2756                                                  GFP_KERNEL);
2757                 if (!gamma_table)
2758                         return -ENOMEM;
2759                 dispc->vp_data[i].gamma_table = gamma_table;
2760         }
2761
2762         if (feat->subrev == DISPC_AM65X) {
2763                 r = dispc_init_am65x_oldi_io_ctrl(dev, dispc);
2764                 if (r)
2765                         return r;
2766         }
2767
2768         dispc->fclk = devm_clk_get(dev, "fck");
2769         if (IS_ERR(dispc->fclk)) {
2770                 dev_err(dev, "%s: Failed to get fclk: %ld\n",
2771                         __func__, PTR_ERR(dispc->fclk));
2772                 return PTR_ERR(dispc->fclk);
2773         }
2774         dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk));
2775
2776         of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth",
2777                              &dispc->memory_bandwidth_limit);
2778
2779         tidss->dispc = dispc;
2780
2781         return 0;
2782 }